1 /*******************************************************************************
2 * File Name: cycfg_peripherals.c
3 *
4 * Description:
5 * Peripheral Hardware Block configuration
6 * This file was automatically generated and should not be modified.
7 * Device Configurator: 2.0.0.1483
8 * Device Support Library (../../../psoc6pdl): 1.3.1.1499
9 *
10 ********************************************************************************
11 * Copyright 2017-2019 Cypress Semiconductor Corporation
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 ********************************************************************************/
26
27 #include "cycfg_peripherals.h"
28
29 const cy_stc_scb_uart_config_t CYBSP_UART_config =
30 {
31 .uartMode = CY_SCB_UART_STANDARD,
32 .enableMutliProcessorMode = false,
33 .smartCardRetryOnNack = false,
34 .irdaInvertRx = false,
35 .irdaEnableLowPowerReceiver = false,
36 .oversample = 8,
37 .enableMsbFirst = false,
38 .dataWidth = 8UL,
39 .parity = CY_SCB_UART_PARITY_NONE,
40 .stopBits = CY_SCB_UART_STOP_BITS_1,
41 .enableInputFilter = false,
42 .breakWidth = 11UL,
43 .dropOnFrameError = false,
44 .dropOnParityError = false,
45 .receiverAddress = 0x0UL,
46 .receiverAddressMask = 0x0UL,
47 .acceptAddrInFifo = false,
48 .enableCts = false,
49 .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
50 .rtsRxFifoLevel = 0UL,
51 .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
52 .rxFifoTriggerLevel = 0UL,
53 .rxFifoIntEnableMask = 0UL,
54 .txFifoTriggerLevel = 63UL,
55 .txFifoIntEnableMask = 0UL,
56 };
57 #if defined (CY_USING_HAL)
58 const cyhal_resource_inst_t CYBSP_UART_obj =
59 {
60 .type = CYHAL_RSC_SCB,
61 .block_num = 5U,
62 .channel_num = 0U,
63 };
64 #endif //defined (CY_USING_HAL)
65
66
init_cycfg_peripherals(void)67 void init_cycfg_peripherals(void)
68 {
69 Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
70 #if defined (CY_USING_HAL)
71 cyhal_hwmgr_reserve(&CYBSP_UART_obj);
72 #endif //defined (CY_USING_HAL)
73 }
74
