1 /*
2 ******************************************************************************
3 * @file ilps28qsw_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ILPS28QSW driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2023 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ilps28qsw_reg.h"
21
22 /**
23 * @defgroup ILPS28QSW
24 * @brief This file provides a set of functions needed to drive the
25 * ilps28qsw nano pressure sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ilps28qsw_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ilps28qsw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53 ret = ctx->read_reg(ctx->handle, reg, data, len);
54 return ret;
55 }
56
57 /**
58 * @brief Write generic device register
59 *
60 * @param ctx read / write interface definitions(ptr)
61 * @param reg register to write
62 * @param data pointer to data to write in register reg(ptr)
63 * @param len number of consecutive register to write
64 * @retval interface status (MANDATORY: return 0 -> no Error)
65 *
66 */
ilps28qsw_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)67 int32_t __weak ilps28qsw_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
68 uint8_t *data,
69 uint16_t len)
70 {
71 int32_t ret;
72 ret = ctx->write_reg(ctx->handle, reg, data, len);
73 return ret;
74 }
75
76 /**
77 * @}
78 *
79 */
80
81 /**
82 * @defgroup Private_functions
83 * @brief Section collect all the utility functions needed by APIs.
84 * @{
85 *
86 */
87
bytecpy(uint8_t * target,uint8_t * source)88 static void bytecpy(uint8_t *target, uint8_t *source)
89 {
90 if ((target != NULL) && (source != NULL))
91 {
92 *target = *source;
93 }
94 }
95
96 /**
97 * @}
98 *
99 */
100
101 /**
102 * @defgroup Sensitivity
103 * @brief These functions convert raw-data into engineering units.
104 * @{
105 *
106 */
107
ilps28qsw_from_fs1260_to_hPa(int32_t lsb)108 float_t ilps28qsw_from_fs1260_to_hPa(int32_t lsb)
109 {
110 return ((float_t)lsb / 1048576.0f); /* 4096.0f * 256 */
111 }
112
ilps28qsw_from_fs4000_to_hPa(int32_t lsb)113 float_t ilps28qsw_from_fs4000_to_hPa(int32_t lsb)
114 {
115 return ((float_t)lsb / 524288.0f); /* 2048.0f * 256 */
116 }
117
ilps28qsw_from_lsb_to_celsius(int16_t lsb)118 float_t ilps28qsw_from_lsb_to_celsius(int16_t lsb)
119 {
120 return ((float_t)lsb / 100.0f);
121 }
122
ilps28qsw_from_lsb_to_mv(int32_t lsb)123 float_t ilps28qsw_from_lsb_to_mv(int32_t lsb)
124 {
125 return ((float_t)lsb) / 426000.0f;
126 }
127
128 /**
129 * @}
130 *
131 */
132
133 /**
134 * @defgroup Basic functions
135 * @brief This section groups all the functions concerning device basic
136 * configuration.
137 * @{
138 *
139 */
140
141 /**
142 * @brief Device "Who am I".[get]
143 *
144 * @param ctx communication interface handler.(ptr)
145 * @param val ID values.(ptr)
146 * @retval interface status (MANDATORY: return 0 -> no Error)
147 *
148 */
ilps28qsw_id_get(stmdev_ctx_t * ctx,ilps28qsw_id_t * val)149 int32_t ilps28qsw_id_get(stmdev_ctx_t *ctx, ilps28qsw_id_t *val)
150 {
151 uint8_t reg;
152 int32_t ret;
153
154 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_WHO_AM_I, ®, 1);
155 val->whoami = reg;
156
157 return ret;
158 }
159
160 /**
161 * @brief Configures the bus operating mode.[set]
162 *
163 * @param ctx communication interface handler.(ptr)
164 * @param val configures the bus operating mode.(ptr)
165 * @retval interface status (MANDATORY: return 0 -> no Error)
166 *
167 */
ilps28qsw_bus_mode_set(stmdev_ctx_t * ctx,ilps28qsw_bus_mode_t * val)168 int32_t ilps28qsw_bus_mode_set(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val)
169 {
170 ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl;
171 int32_t ret;
172
173 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_I3C_IF_CTRL,
174 (uint8_t *)&i3c_if_ctrl, 1);
175 if (ret == 0)
176 {
177 i3c_if_ctrl.asf_on = (uint8_t)val->filter & 0x01U;
178 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_I3C_IF_CTRL,
179 (uint8_t *)&i3c_if_ctrl, 1);
180 }
181 return ret;
182 }
183
184 /**
185 * @brief Configures the bus operating mode.[set]
186 *
187 * @param ctx communication interface handler.(ptr)
188 * @param val configures the bus operating mode.(ptr)
189 * @retval interface status (MANDATORY: return 0 -> no Error)
190 *
191 */
ilps28qsw_bus_mode_get(stmdev_ctx_t * ctx,ilps28qsw_bus_mode_t * val)192 int32_t ilps28qsw_bus_mode_get(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val)
193 {
194 ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl;
195 int32_t ret;
196
197 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_I3C_IF_CTRL,
198 (uint8_t *)&i3c_if_ctrl, 1);
199 if (ret == 0)
200 {
201 switch (i3c_if_ctrl.asf_on)
202 {
203 case ILPS28QSW_AUTO:
204 val->filter = ILPS28QSW_AUTO;
205 break;
206 case ILPS28QSW_ALWAYS_ON:
207 val->filter = ILPS28QSW_ALWAYS_ON;
208 break;
209 default:
210 val->filter = ILPS28QSW_AUTO;
211 break;
212 }
213 }
214 return ret;
215 }
216
217 /**
218 * @brief Configures the bus operating mode.[get]
219 *
220 * @param ctx communication interface handler.(ptr)
221 * @param val configures the bus operating mode.(ptr)
222 * @retval interface status (MANDATORY: return 0 -> no Error)
223 *
224 */
ilps28qsw_init_set(stmdev_ctx_t * ctx,ilps28qsw_init_t val)225 int32_t ilps28qsw_init_set(stmdev_ctx_t *ctx, ilps28qsw_init_t val)
226 {
227 ilps28qsw_ctrl_reg2_t ctrl_reg2;
228 ilps28qsw_ctrl_reg3_t ctrl_reg3;
229 uint8_t reg[2];
230 int32_t ret;
231
232 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2, reg, 2);
233 if (ret == 0)
234 {
235 bytecpy((uint8_t *)&ctrl_reg2, ®[0]);
236 bytecpy((uint8_t *)&ctrl_reg3, ®[1]);
237
238 switch (val)
239 {
240 case ILPS28QSW_BOOT:
241 ctrl_reg2.boot = PROPERTY_ENABLE;
242 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2,
243 (uint8_t *)&ctrl_reg2, 1);
244 break;
245 case ILPS28QSW_RESET:
246 ctrl_reg2.swreset = PROPERTY_ENABLE;
247 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2,
248 (uint8_t *)&ctrl_reg2, 1);
249 break;
250 case ILPS28QSW_DRV_RDY:
251 ctrl_reg2.bdu = PROPERTY_ENABLE;
252 ctrl_reg3.if_add_inc = PROPERTY_ENABLE;
253 bytecpy(®[0], (uint8_t *)&ctrl_reg2);
254 bytecpy(®[1], (uint8_t *)&ctrl_reg3);
255 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, reg, 2);
256 break;
257 default:
258 ctrl_reg2.swreset = PROPERTY_ENABLE;
259 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2,
260 (uint8_t *)&ctrl_reg2, 1);
261 break;
262 }
263 }
264
265 return ret;
266 }
267
268 /**
269 * @brief Get the status of the device.[get]
270 *
271 * @param ctx communication interface handler.(ptr)
272 * @param val the status of the device.(ptr)
273 * @retval interface status (MANDATORY: return 0 -> no Error)
274 *
275 */
ilps28qsw_status_get(stmdev_ctx_t * ctx,ilps28qsw_stat_t * val)276 int32_t ilps28qsw_status_get(stmdev_ctx_t *ctx, ilps28qsw_stat_t *val)
277 {
278 ilps28qsw_interrupt_cfg_t interrupt_cfg;
279 ilps28qsw_int_source_t int_source;
280 ilps28qsw_ctrl_reg2_t ctrl_reg2;
281 ilps28qsw_status_t status;
282 int32_t ret;
283
284 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2,
285 (uint8_t *)&ctrl_reg2, 1);
286 if (ret == 0)
287 {
288 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE, (uint8_t *)&int_source, 1);
289 }
290 if (ret == 0)
291 {
292 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_STATUS, (uint8_t *)&status, 1);
293 }
294 if (ret == 0)
295 {
296 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
297 (uint8_t *)&interrupt_cfg, 1);
298 }
299 val->sw_reset = ctrl_reg2.swreset;
300 val->boot = int_source.boot_on;
301 val->drdy_pres = status.p_da;
302 val->drdy_temp = status.t_da;
303 val->ovr_pres = status.p_or;
304 val->ovr_temp = status.t_or;
305 val->end_meas = ~ctrl_reg2.oneshot;
306 val->ref_done = ~interrupt_cfg.autozero;
307
308 return ret;
309 }
310
311 /**
312 * @brief Electrical pin configuration.[set]
313 *
314 * @param ctx communication interface handler.(ptr)
315 * @param val the electrical settings for the configurable pins.(ptr)
316 * @retval interface status (MANDATORY: return 0 -> no Error)
317 *
318 */
ilps28qsw_pin_conf_set(stmdev_ctx_t * ctx,ilps28qsw_pin_conf_t * val)319 int32_t ilps28qsw_pin_conf_set(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val)
320 {
321 ilps28qsw_if_ctrl_t if_ctrl;
322 int32_t ret;
323
324 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
325
326 if (ret == 0)
327 {
328 if_ctrl.sda_pu_en = val->sda_pull_up;
329 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
330 }
331
332 return ret;
333 }
334
335 /**
336 * @brief Electrical pin configuration.[get]
337 *
338 * @param ctx communication interface handler.(ptr)
339 * @param val the electrical settings for the configurable pins.(ptr)
340 * @retval interface status (MANDATORY: return 0 -> no Error)
341 *
342 */
ilps28qsw_pin_conf_get(stmdev_ctx_t * ctx,ilps28qsw_pin_conf_t * val)343 int32_t ilps28qsw_pin_conf_get(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val)
344 {
345 ilps28qsw_if_ctrl_t if_ctrl;
346 int32_t ret;
347
348 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
349
350 val->sda_pull_up = if_ctrl.sda_pu_en;
351
352 return ret;
353 }
354
355 /**
356 * @brief Get the status of all the interrupt sources.[get]
357 *
358 * @param ctx communication interface handler.(ptr)
359 * @param val the status of all the interrupt sources.(ptr)
360 * @retval interface status (MANDATORY: return 0 -> no Error)
361 *
362 */
ilps28qsw_all_sources_get(stmdev_ctx_t * ctx,ilps28qsw_all_sources_t * val)363 int32_t ilps28qsw_all_sources_get(stmdev_ctx_t *ctx,
364 ilps28qsw_all_sources_t *val)
365 {
366 ilps28qsw_fifo_status2_t fifo_status2;
367 ilps28qsw_int_source_t int_source;
368 ilps28qsw_status_t status;
369 int32_t ret;
370
371 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_STATUS, (uint8_t *)&status, 1);
372 if (ret == 0)
373 {
374 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE,
375 (uint8_t *)&int_source, 1);
376 }
377 if (ret == 0)
378 {
379 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS2,
380 (uint8_t *)&fifo_status2, 1);
381 }
382
383 val->drdy_pres = status.p_da;
384 val->drdy_temp = status.t_da;
385 val->over_pres = int_source.ph;
386 val->under_pres = int_source.pl;
387 val->thrsld_pres = int_source.ia;
388 val->fifo_full = fifo_status2.fifo_full_ia;
389 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
390 val->fifo_th = fifo_status2.fifo_wtm_ia;
391
392 return ret;
393 }
394
395
396 /**
397 * @brief Sensor conversion parameters selection.[set]
398 *
399 * @param ctx communication interface handler.(ptr)
400 * @param val set the sensor conversion parameters.(ptr)
401 * @retval interface status (MANDATORY: return 0 -> no Error)
402 *
403 */
ilps28qsw_mode_set(stmdev_ctx_t * ctx,ilps28qsw_md_t * val)404 int32_t ilps28qsw_mode_set(stmdev_ctx_t *ctx, ilps28qsw_md_t *val)
405 {
406 ilps28qsw_ctrl_reg1_t ctrl_reg1;
407 ilps28qsw_ctrl_reg2_t ctrl_reg2;
408 ilps28qsw_ctrl_reg3_t ctrl_reg3;
409 ilps28qsw_fifo_ctrl_t fifo_ctrl;
410 uint8_t odr_save = 0, ah_qvar_en_save = 0;
411 uint8_t reg[3];
412 int32_t ret;
413
414 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3);
415
416 if (ret == 0)
417 {
418 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
419 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
420 bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
421
422 /* handle interleaved mode setting */
423 if (ctrl_reg1.odr != 0x0U)
424 {
425 /* power-down */
426 odr_save = ctrl_reg1.odr;
427 ctrl_reg1.odr = 0x0U;
428 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
429 }
430
431 if (ctrl_reg3.ah_qvar_en != 0U)
432 {
433 /* disable QVAR */
434 ah_qvar_en_save = ctrl_reg3.ah_qvar_en;
435 ctrl_reg3.ah_qvar_en = 0;
436 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
437 }
438
439 /* set interleaved mode (0 or 1) */
440 ctrl_reg3.ah_qvar_p_auto_en = val->interleaved_mode;
441 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
442
443 /* set FIFO interleaved mode (0 or 1) */
444 ret += ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
445 fifo_ctrl.ah_qvar_p_fifo_en = val->interleaved_mode;
446 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
447
448 if (ah_qvar_en_save != 0U)
449 {
450 /* restore ah_qvar_en back to previous setting */
451 ctrl_reg3.ah_qvar_en = ah_qvar_en_save;
452 }
453
454 if (odr_save != 0U)
455 {
456 /* restore odr back to previous setting */
457 ctrl_reg1.odr = odr_save;
458 }
459
460 ctrl_reg1.odr = (uint8_t)val->odr;
461 ctrl_reg1.avg = (uint8_t)val->avg;
462 ctrl_reg2.en_lpfp = (uint8_t)val->lpf & 0x01U;
463 ctrl_reg2.lfpf_cfg = ((uint8_t)val->lpf & 0x02U) >> 2;
464 ctrl_reg2.fs_mode = (uint8_t)val->fs;
465
466 bytecpy(®[0], (uint8_t *)&ctrl_reg1);
467 bytecpy(®[1], (uint8_t *)&ctrl_reg2);
468 bytecpy(®[2], (uint8_t *)&ctrl_reg3);
469 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3);
470 }
471
472 return ret;
473 }
474
475 /**
476 * @brief Sensor conversion parameters selection.[get]
477 *
478 * @param ctx communication interface handler.(ptr)
479 * @param val get the sensor conversion parameters.(ptr)
480 * @retval interface status (MANDATORY: return 0 -> no Error)
481 *
482 */
ilps28qsw_mode_get(stmdev_ctx_t * ctx,ilps28qsw_md_t * val)483 int32_t ilps28qsw_mode_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *val)
484 {
485 ilps28qsw_ctrl_reg1_t ctrl_reg1;
486 ilps28qsw_ctrl_reg2_t ctrl_reg2;
487 ilps28qsw_ctrl_reg3_t ctrl_reg3;
488 uint8_t reg[3];
489 int32_t ret;
490
491 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3);
492
493 if (ret == 0)
494 {
495 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
496 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
497 bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
498
499 switch (ctrl_reg2.fs_mode)
500 {
501 case ILPS28QSW_1260hPa:
502 val->fs = ILPS28QSW_1260hPa;
503 break;
504 case ILPS28QSW_4060hPa:
505 val->fs = ILPS28QSW_4060hPa;
506 break;
507 default:
508 val->fs = ILPS28QSW_1260hPa;
509 break;
510 }
511
512 switch (ctrl_reg1.odr)
513 {
514 case ILPS28QSW_ONE_SHOT:
515 val->odr = ILPS28QSW_ONE_SHOT;
516 break;
517 case ILPS28QSW_1Hz:
518 val->odr = ILPS28QSW_1Hz;
519 break;
520 case ILPS28QSW_4Hz:
521 val->odr = ILPS28QSW_4Hz;
522 break;
523 case ILPS28QSW_10Hz:
524 val->odr = ILPS28QSW_10Hz;
525 break;
526 case ILPS28QSW_25Hz:
527 val->odr = ILPS28QSW_25Hz;
528 break;
529 case ILPS28QSW_50Hz:
530 val->odr = ILPS28QSW_50Hz;
531 break;
532 case ILPS28QSW_75Hz:
533 val->odr = ILPS28QSW_75Hz;
534 break;
535 case ILPS28QSW_100Hz:
536 val->odr = ILPS28QSW_100Hz;
537 break;
538 case ILPS28QSW_200Hz:
539 val->odr = ILPS28QSW_200Hz;
540 break;
541 default:
542 val->odr = ILPS28QSW_ONE_SHOT;
543 break;
544 }
545
546 switch (ctrl_reg1.avg)
547 {
548 case ILPS28QSW_4_AVG:
549 val->avg = ILPS28QSW_4_AVG;
550 break;
551 case ILPS28QSW_8_AVG:
552 val->avg = ILPS28QSW_8_AVG;
553 break;
554 case ILPS28QSW_16_AVG:
555 val->avg = ILPS28QSW_16_AVG;
556 break;
557 case ILPS28QSW_32_AVG:
558 val->avg = ILPS28QSW_32_AVG;
559 break;
560 case ILPS28QSW_64_AVG:
561 val->avg = ILPS28QSW_64_AVG;
562 break;
563 case ILPS28QSW_128_AVG:
564 val->avg = ILPS28QSW_128_AVG;
565 break;
566 case ILPS28QSW_256_AVG:
567 val->avg = ILPS28QSW_256_AVG;
568 break;
569 case ILPS28QSW_512_AVG:
570 val->avg = ILPS28QSW_512_AVG;
571 break;
572 default:
573 val->avg = ILPS28QSW_4_AVG;
574 break;
575 }
576
577 switch ((ctrl_reg2.lfpf_cfg << 2) | ctrl_reg2.en_lpfp)
578 {
579 case ILPS28QSW_LPF_DISABLE:
580 val->lpf = ILPS28QSW_LPF_DISABLE;
581 break;
582 case ILPS28QSW_LPF_ODR_DIV_4:
583 val->lpf = ILPS28QSW_LPF_ODR_DIV_4;
584 break;
585 case ILPS28QSW_LPF_ODR_DIV_9:
586 val->lpf = ILPS28QSW_LPF_ODR_DIV_9;
587 break;
588 default:
589 val->lpf = ILPS28QSW_LPF_DISABLE;
590 break;
591 }
592
593 val->interleaved_mode = ctrl_reg3.ah_qvar_p_auto_en;
594 }
595 return ret;
596 }
597
598 /**
599 * @brief Software trigger for One-Shot.[get]
600 *
601 * @param ctx communication interface handler.(ptr)
602 * @param md the sensor conversion parameters.(ptr)
603 * @retval interface status (MANDATORY: return 0 -> no Error)
604 *
605 */
ilps28qsw_trigger_sw(stmdev_ctx_t * ctx,ilps28qsw_md_t * md)606 int32_t ilps28qsw_trigger_sw(stmdev_ctx_t *ctx, ilps28qsw_md_t *md)
607 {
608 ilps28qsw_ctrl_reg2_t ctrl_reg2;
609 int32_t ret = 0;
610
611 if (md->odr == ILPS28QSW_ONE_SHOT)
612 {
613 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
614 ctrl_reg2.oneshot = PROPERTY_ENABLE;
615 if (ret == 0)
616 {
617 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
618 }
619 }
620 return ret;
621 }
622
623 /**
624 * @brief AH/QVAR function enable.[set]
625 *
626 * @param ctx Read / write interface definitions
627 * @param val Change the value of ah_qvar_en in reg CTRL_REG3
628 * @retval Interface status (MANDATORY: return 0 -> no Error).
629 *
630 */
ilps28qsw_ah_qvar_en_set(stmdev_ctx_t * ctx,uint8_t val)631 int32_t ilps28qsw_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val)
632 {
633 ilps28qsw_ctrl_reg3_t ctrl_reg3;
634 int32_t ret;
635
636 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
637
638 if (ret == 0)
639 {
640 ctrl_reg3.ah_qvar_en = val;
641 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
642 }
643
644 return ret;
645 }
646
647 /**
648 * @brief AH/QVAR function enable.[get]
649 *
650 * @param ctx Read / write interface definitions
651 * @param val Return the value of ah_qvar_en in reg CTRL_REG3
652 * @retval Interface status (MANDATORY: return 0 -> no Error).
653 *
654 */
ilps28qsw_ah_qvar_en_get(stmdev_ctx_t * ctx,uint8_t * val)655 int32_t ilps28qsw_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val)
656 {
657 ilps28qsw_ctrl_reg3_t ctrl_reg3;
658 int32_t ret;
659
660 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
661 *val = ctrl_reg3.ah_qvar_en;
662
663 return ret;
664 }
665
666 /**
667 * @brief Software trigger for One-Shot.[get]
668 *
669 * @param ctx communication interface handler.(ptr)
670 * @param md the sensor conversion parameters.(ptr)
671 * @param data data retrived from the sensor.(ptr)
672 * @retval interface status (MANDATORY: return 0 -> no Error)
673 *
674 */
ilps28qsw_data_get(stmdev_ctx_t * ctx,ilps28qsw_md_t * md,ilps28qsw_data_t * data)675 int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md,
676 ilps28qsw_data_t *data)
677 {
678 uint8_t buff[5];
679 int32_t ret;
680
681 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 5);
682
683 /* pressure conversion */
684 data->pressure.raw = (int32_t)buff[2];
685 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[1];
686 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[0];
687 data->pressure.raw = data->pressure.raw * 256;
688
689 if (md->interleaved_mode == 1U)
690 {
691 if ((buff[0] & 0x1U) == 0U)
692 {
693 /* data is a pressure sample */
694 switch (md->fs)
695 {
696 case ILPS28QSW_1260hPa:
697 data->pressure.hpa = ilps28qsw_from_fs1260_to_hPa(data->pressure.raw);
698 break;
699 case ILPS28QSW_4060hPa:
700 data->pressure.hpa = ilps28qsw_from_fs4000_to_hPa(data->pressure.raw);
701 break;
702 default:
703 data->pressure.hpa = 0.0f;
704 break;
705 }
706 data->ah_qvar.lsb = 0;
707 }
708 else
709 {
710 /* data is a AH_QVAR sample */
711 data->ah_qvar.lsb = (data->pressure.raw / 256); /* shift 8bit left */
712 data->pressure.hpa = 0.0f;
713 }
714 }
715 else
716 {
717 switch (md->fs)
718 {
719 case ILPS28QSW_1260hPa:
720 data->pressure.hpa = ilps28qsw_from_fs1260_to_hPa(data->pressure.raw);
721 break;
722 case ILPS28QSW_4060hPa:
723 data->pressure.hpa = ilps28qsw_from_fs4000_to_hPa(data->pressure.raw);
724 break;
725 default:
726 data->pressure.hpa = 0.0f;
727 break;
728 }
729 data->ah_qvar.lsb = 0;
730 }
731
732 /* temperature conversion */
733 data->heat.raw = (int16_t)buff[4];
734 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[3];
735 data->heat.deg_c = ilps28qsw_from_lsb_to_celsius(data->heat.raw);
736
737 return ret;
738 }
739
740 /**
741 * @brief AH/QVAR data read.[get]
742 *
743 * @param ctx communication interface handler.(ptr)
744 * @param md the sensor conversion parameters.(ptr)
745 * @param data data retrived from the sensor.(ptr)
746 * @retval interface status (MANDATORY: return 0 -> no Error)
747 *
748 */
ilps28qsw_ah_qvar_data_get(stmdev_ctx_t * ctx,ilps28qsw_ah_qvar_data_t * data)749 int32_t ilps28qsw_ah_qvar_data_get(stmdev_ctx_t *ctx,
750 ilps28qsw_ah_qvar_data_t *data)
751 {
752 uint8_t buff[5];
753 int32_t ret;
754
755 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 3);
756
757 /* QVAR conversion */
758 data->raw = (int32_t)buff[2];
759 data->raw = (data->raw * 256) + (int32_t) buff[1];
760 data->raw = (data->raw * 256) + (int32_t) buff[0];
761 data->raw = (data->raw * 256);
762 data->lsb = (data->raw / 256); /* shift 8bit left */
763
764 data->mv = ilps28qsw_from_lsb_to_mv(data->lsb);
765
766 return ret;
767 }
768
769 /**
770 * @}
771 *
772 */
773
774 /**
775 * @defgroup FIFO functions
776 * @brief This section groups all the functions concerning the
777 * management of FIFO.
778 * @{
779 *
780 */
781
782 /**
783 * @brief FIFO operation mode selection.[set]
784 *
785 * @param ctx communication interface handler.(ptr)
786 * @param val set the FIFO operation mode.(ptr)
787 * @retval interface status (MANDATORY: return 0 -> no Error)
788 *
789 */
ilps28qsw_fifo_mode_set(stmdev_ctx_t * ctx,ilps28qsw_fifo_md_t * val)790 int32_t ilps28qsw_fifo_mode_set(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val)
791 {
792 ilps28qsw_fifo_ctrl_t fifo_ctrl;
793 ilps28qsw_fifo_wtm_t fifo_wtm;
794 uint8_t reg[2];
795 int32_t ret;
796
797 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2);
798 if (ret == 0)
799 {
800 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
801 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
802
803 fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U;
804 fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2;
805
806 if (val->watermark != 0x00U)
807 {
808 fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE;
809 }
810 else
811 {
812 fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE;
813 }
814
815 fifo_wtm.wtm = val->watermark;
816
817 bytecpy(®[0], (uint8_t *)&fifo_ctrl);
818 bytecpy(®[1], (uint8_t *)&fifo_wtm);
819
820 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2);
821 }
822 return ret;
823 }
824
825 /**
826 * @brief FIFO operation mode selection.[get]
827 *
828 * @param ctx communication interface handler.(ptr)
829 * @param val get the FIFO operation mode.(ptr)
830 * @retval interface status (MANDATORY: return 0 -> no Error)
831 *
832 */
ilps28qsw_fifo_mode_get(stmdev_ctx_t * ctx,ilps28qsw_fifo_md_t * val)833 int32_t ilps28qsw_fifo_mode_get(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val)
834 {
835 ilps28qsw_fifo_ctrl_t fifo_ctrl;
836 ilps28qsw_fifo_wtm_t fifo_wtm;
837 uint8_t reg[2];
838 int32_t ret;
839
840 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2);
841
842 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
843 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
844
845 switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode)
846 {
847 case ILPS28QSW_BYPASS:
848 val->operation = ILPS28QSW_BYPASS;
849 break;
850 case ILPS28QSW_FIFO:
851 val->operation = ILPS28QSW_FIFO;
852 break;
853 case ILPS28QSW_STREAM:
854 val->operation = ILPS28QSW_STREAM;
855 break;
856 case ILPS28QSW_STREAM_TO_FIFO:
857 val->operation = ILPS28QSW_STREAM_TO_FIFO;
858 break;
859 case ILPS28QSW_BYPASS_TO_STREAM:
860 val->operation = ILPS28QSW_BYPASS_TO_STREAM;
861 break;
862 case ILPS28QSW_BYPASS_TO_FIFO:
863 val->operation = ILPS28QSW_BYPASS_TO_FIFO;
864 break;
865 default:
866 val->operation = ILPS28QSW_BYPASS;
867 break;
868 }
869
870 val->watermark = fifo_wtm.wtm;
871
872 return ret;
873 }
874
875 /**
876 * @brief Get the number of samples stored in FIFO.[get]
877 *
878 * @param ctx communication interface handler.(ptr)
879 * @param md the sensor conversion parameters.(ptr)
880 * @param val number of samples stored in FIFO.(ptr)
881 * @retval interface status (MANDATORY: return 0 -> no Error)
882 *
883 */
ilps28qsw_fifo_level_get(stmdev_ctx_t * ctx,uint8_t * val)884 int32_t ilps28qsw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val)
885 {
886 ilps28qsw_fifo_status1_t fifo_status1;
887 int32_t ret;
888
889 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS1,
890 (uint8_t *)&fifo_status1, 1);
891
892 *val = fifo_status1.fss;
893
894 return ret;
895 }
896
897 /**
898 * @brief Software trigger for One-Shot.[get]
899 *
900 * @param ctx communication interface handler.(ptr)
901 * @param md the sensor conversion parameters.(ptr)
902 * @param fmd get the FIFO operation mode.(ptr)
903 * @param samp number of samples stored in FIFO.(ptr)
904 * @param data data retrived from FIFO.(ptr)
905 * @retval interface status (MANDATORY: return 0 -> no Error)
906 *
907 */
ilps28qsw_fifo_data_get(stmdev_ctx_t * ctx,uint8_t samp,ilps28qsw_md_t * md,ilps28qsw_fifo_data_t * data)908 int32_t ilps28qsw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp,
909 ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data)
910 {
911 uint8_t fifo_data[3];
912 uint8_t i;
913 int32_t ret = 0;
914
915 for (i = 0U; i < samp; i++)
916 {
917 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3);
918 data[i].raw = (int32_t)fifo_data[2];
919 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1];
920 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0];
921 data[i].raw = (data[i].raw * 256);
922
923 if (md->interleaved_mode == 1U)
924 {
925 if ((fifo_data[0] & 0x1U) == 0U)
926 {
927 /* data is a pressure sample */
928 switch (md->fs)
929 {
930 case ILPS28QSW_1260hPa:
931 data[i].hpa = ilps28qsw_from_fs1260_to_hPa(data[i].raw);
932 break;
933 case ILPS28QSW_4060hPa:
934 data[i].hpa = ilps28qsw_from_fs4000_to_hPa(data[i].raw);
935 break;
936 default:
937 data[i].hpa = 0.0f;
938 break;
939 }
940 data[i].lsb = 0;
941 }
942 else
943 {
944 /* data is a AH_QVAR sample */
945 data[i].lsb = (data[i].raw / 256); /* shift 8bit left */
946 data[i].hpa = 0.0f;
947 }
948 }
949 else
950 {
951 switch (md->fs)
952 {
953 case ILPS28QSW_1260hPa:
954 data[i].hpa = ilps28qsw_from_fs1260_to_hPa(data[i].raw);
955 break;
956 case ILPS28QSW_4060hPa:
957 data[i].hpa = ilps28qsw_from_fs4000_to_hPa(data[i].raw);
958 break;
959 default:
960 data[i].hpa = 0.0f;
961 break;
962 }
963 data[i].lsb = 0;
964 }
965
966 }
967
968 return ret;
969 }
970
971 /**
972 * @}
973 *
974 */
975
976 /**
977 * @defgroup Interrupt signals
978 * @brief This section groups all the functions concerning
979 * the management of interrupt signals.
980 * @{
981 *
982 */
983
984 /**
985 * @brief Interrupt pins hardware signal configuration.[set]
986 *
987 * @param ctx communication interface handler.(ptr)
988 * @param val the pins hardware signal settings.(ptr)
989 * @retval interface status (MANDATORY: return 0 -> no Error)
990 *
991 */
ilps28qsw_interrupt_mode_set(stmdev_ctx_t * ctx,ilps28qsw_int_mode_t * val)992 int32_t ilps28qsw_interrupt_mode_set(stmdev_ctx_t *ctx,
993 ilps28qsw_int_mode_t *val)
994 {
995 ilps28qsw_interrupt_cfg_t interrupt_cfg;
996 int32_t ret;
997
998 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
999 (uint8_t *)&interrupt_cfg, 1);
1000 if (ret == 0)
1001 {
1002 interrupt_cfg.lir = val->int_latched ;
1003 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1004 (uint8_t *)&interrupt_cfg, 1);
1005 }
1006 return ret;
1007 }
1008
1009 /**
1010 * @brief Interrupt pins hardware signal configuration.[get]
1011 *
1012 * @param ctx communication interface handler.(ptr)
1013 * @param val the pins hardware signal settings.(ptr)
1014 * @retval interface status (MANDATORY: return 0 -> no Error)
1015 *
1016 */
ilps28qsw_interrupt_mode_get(stmdev_ctx_t * ctx,ilps28qsw_int_mode_t * val)1017 int32_t ilps28qsw_interrupt_mode_get(stmdev_ctx_t *ctx,
1018 ilps28qsw_int_mode_t *val)
1019 {
1020 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1021 int32_t ret;
1022
1023 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1024 (uint8_t *)&interrupt_cfg, 1);
1025
1026 val->int_latched = interrupt_cfg.lir;
1027
1028 return ret;
1029 }
1030
1031 /**
1032 * @brief AH function disable
1033 *
1034 * @param ctx communication interface handler.(ptr)
1035 * @retval interface status (MANDATORY: return 0 -> no Error)
1036 *
1037 */
ilps28qsw_ah_qvar_disable(stmdev_ctx_t * ctx)1038 int32_t ilps28qsw_ah_qvar_disable(stmdev_ctx_t *ctx)
1039 {
1040 uint32_t val = 0;
1041 int32_t ret;
1042
1043 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_ANALOGIC_HUB_DISABLE, (uint8_t *)&val, 1);
1044
1045 return ret;
1046 }
1047
1048 /**
1049 * @}
1050 *
1051 */
1052
1053 /**
1054 * @defgroup Interrupt on threshold functions
1055 * @brief This section groups all the functions concerning
1056 * the wake up functionality.
1057 * @{
1058 *
1059 */
1060
1061 /**
1062 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1063 *
1064 * @param ctx communication interface handler.(ptr)
1065 * @param val parameters of configuration.(ptr)
1066 * @retval interface status (MANDATORY: return 0 -> no Error)
1067 *
1068 */
ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t * ctx,ilps28qsw_int_th_md_t * val)1069 int32_t ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t *ctx,
1070 ilps28qsw_int_th_md_t *val)
1071 {
1072 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1073 ilps28qsw_ths_p_l_t ths_p_l;
1074 ilps28qsw_ths_p_h_t ths_p_h;
1075 uint8_t reg[3];
1076 int32_t ret;
1077
1078 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3);
1079 if (ret == 0)
1080 {
1081 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1082 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1083 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1084
1085 interrupt_cfg.phe = val->over_th;
1086 interrupt_cfg.ple = val->under_th;
1087 ths_p_h.ths = (uint8_t)(val->threshold / 256U);
1088 ths_p_l.ths = (uint8_t)(val->threshold - (ths_p_h.ths * 256U));
1089
1090 bytecpy(®[0], (uint8_t *)&interrupt_cfg);
1091 bytecpy(®[1], (uint8_t *)&ths_p_l);
1092 bytecpy(®[2], (uint8_t *)&ths_p_h);
1093
1094 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3);
1095 }
1096 return ret;
1097 }
1098
1099 /**
1100 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1101 *
1102 * @param ctx communication interface handler.(ptr)
1103 * @param val parameters of configuration.(ptr)
1104 * @retval interface status (MANDATORY: return 0 -> no Error)
1105 *
1106 */
ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t * ctx,ilps28qsw_int_th_md_t * val)1107 int32_t ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t *ctx,
1108 ilps28qsw_int_th_md_t *val)
1109 {
1110 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1111 ilps28qsw_ths_p_l_t ths_p_l;
1112 ilps28qsw_ths_p_h_t ths_p_h;
1113 uint8_t reg[3];
1114 int32_t ret;
1115
1116 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3);
1117
1118 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1119 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1120 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1121
1122 val->over_th = interrupt_cfg.phe;
1123 val->under_th = interrupt_cfg.ple;
1124 val->threshold = ths_p_h.ths;
1125 val->threshold = (val->threshold * 256U) + ths_p_l.ths;
1126
1127 return ret;
1128 }
1129
1130 /**
1131 * @}
1132 *
1133 */
1134
1135 /**
1136 * @defgroup Reference value of pressure
1137 * @brief This section groups all the functions concerning
1138 * the wake up functionality.
1139 * @{
1140 *
1141 */
1142
1143 /**
1144 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1145 *
1146 * @param ctx communication interface handler.(ptr)
1147 * @param val parameters of configuration.(ptr)
1148 * @retval interface status (MANDATORY: return 0 -> no Error)
1149 *
1150 */
ilps28qsw_reference_mode_set(stmdev_ctx_t * ctx,ilps28qsw_ref_md_t * val)1151 int32_t ilps28qsw_reference_mode_set(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val)
1152 {
1153 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1154 int32_t ret;
1155
1156 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1157 (uint8_t *)&interrupt_cfg, 1);
1158 if (ret == 0)
1159 {
1160
1161 interrupt_cfg.autozero = val->get_ref;
1162 interrupt_cfg.autorefp = (uint8_t)val->apply_ref & 0x01U;
1163
1164 interrupt_cfg.reset_az = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1165 interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1166
1167 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1168 (uint8_t *)&interrupt_cfg, 1);
1169 }
1170 return ret;
1171 }
1172
1173 /**
1174 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1175 *
1176 * @param ctx communication interface handler.(ptr)
1177 * @param val parameters of configuration.(ptr)
1178 * @retval interface status (MANDATORY: return 0 -> no Error)
1179 *
1180 */
ilps28qsw_reference_mode_get(stmdev_ctx_t * ctx,ilps28qsw_ref_md_t * val)1181 int32_t ilps28qsw_reference_mode_get(stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val)
1182 {
1183 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1184 int32_t ret;
1185
1186 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1187 (uint8_t *)&interrupt_cfg, 1);
1188
1189 switch ((interrupt_cfg.reset_az << 1) |
1190 interrupt_cfg.autorefp)
1191 {
1192 case ILPS28QSW_OUT_AND_INTERRUPT:
1193 val->apply_ref = ILPS28QSW_OUT_AND_INTERRUPT;
1194 break;
1195 case ILPS28QSW_ONLY_INTERRUPT:
1196 val->apply_ref = ILPS28QSW_ONLY_INTERRUPT;
1197 break;
1198 default:
1199 val->apply_ref = ILPS28QSW_RST_REFS;
1200 break;
1201 }
1202 val->get_ref = interrupt_cfg.autozero;
1203
1204 return ret;
1205 }
1206
1207
1208 /**
1209 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1210 *
1211 * @param ctx communication interface handler.(ptr)
1212 * @param val parameters of configuration.(ptr)
1213 * @retval interface status (MANDATORY: return 0 -> no Error)
1214 *
1215 */
ilps28qsw_opc_set(stmdev_ctx_t * ctx,int16_t val)1216 int32_t ilps28qsw_opc_set(stmdev_ctx_t *ctx, int16_t val)
1217 {
1218 uint8_t reg[2];
1219 int32_t ret;
1220
1221 reg[1] = (uint8_t)(((uint16_t)val & 0xFF00U) / 256U);
1222 reg[0] = (uint8_t)((uint16_t)val & 0x00FFU);
1223
1224 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_RPDS_L, reg, 2);
1225
1226 return ret;
1227 }
1228
1229 /**
1230 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1231 *
1232 * @param ctx communication interface handler.(ptr)
1233 * @param val parameters of configuration.(ptr)
1234 * @retval interface status (MANDATORY: return 0 -> no Error)
1235 *
1236 */
ilps28qsw_opc_get(stmdev_ctx_t * ctx,int16_t * val)1237 int32_t ilps28qsw_opc_get(stmdev_ctx_t *ctx, int16_t *val)
1238 {
1239 uint8_t reg[2];
1240 int32_t ret;
1241
1242 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_RPDS_L, reg, 2);
1243
1244 *val = (int16_t)reg[1];
1245 *val = *val * 256 + (int16_t)reg[0];
1246
1247 return ret;
1248 }
1249
1250
1251 /**
1252 * @}
1253 *
1254 */
1255
1256 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1257
