1 /*
2 ******************************************************************************
3 * @file ilps28qsw_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ILPS28QSW driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ilps28qsw_reg.h"
21
22 /**
23 * @defgroup ILPS28QSW
24 * @brief This file provides a set of functions needed to drive the
25 * ilps28qsw nano pressure sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ilps28qsw_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ilps28qsw_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
ilps28qsw_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak ilps28qsw_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL)
80 {
81 return -1;
82 }
83
84 ret = ctx->write_reg(ctx->handle, reg, data, len);
85
86 return ret;
87 }
88
89 /**
90 * @}
91 *
92 */
93
94 /**
95 * @defgroup Private_functions
96 * @brief Section collect all the utility functions needed by APIs.
97 * @{
98 *
99 */
100
bytecpy(uint8_t * target,uint8_t * source)101 static void bytecpy(uint8_t *target, uint8_t *source)
102 {
103 if ((target != NULL) && (source != NULL))
104 {
105 *target = *source;
106 }
107 }
108
109 /**
110 * @}
111 *
112 */
113
114 /**
115 * @defgroup Sensitivity
116 * @brief These functions convert raw-data into engineering units.
117 * @{
118 *
119 */
120
ilps28qsw_from_fs1260_to_hPa(int32_t lsb)121 float_t ilps28qsw_from_fs1260_to_hPa(int32_t lsb)
122 {
123 return ((float_t)lsb / 1048576.0f); /* 4096.0f * 256 */
124 }
125
ilps28qsw_from_fs4060_to_hPa(int32_t lsb)126 float_t ilps28qsw_from_fs4060_to_hPa(int32_t lsb)
127 {
128 return ((float_t)lsb / 524288.0f); /* 2048.0f * 256 */
129 }
130
ilps28qsw_from_lsb_to_celsius(int16_t lsb)131 float_t ilps28qsw_from_lsb_to_celsius(int16_t lsb)
132 {
133 return ((float_t)lsb / 100.0f);
134 }
135
ilps28qsw_from_lsb_to_mv(int32_t lsb)136 float_t ilps28qsw_from_lsb_to_mv(int32_t lsb)
137 {
138 return ((float_t)lsb) / 426000.0f;
139 }
140
141 /**
142 * @}
143 *
144 */
145
146 /**
147 * @defgroup Basic functions
148 * @brief This section groups all the functions concerning device basic
149 * configuration.
150 * @{
151 *
152 */
153
154 /**
155 * @brief Device "Who am I".[get]
156 *
157 * @param ctx communication interface handler.(ptr)
158 * @param val ID values.(ptr)
159 * @retval interface status (MANDATORY: return 0 -> no Error)
160 *
161 */
ilps28qsw_id_get(const stmdev_ctx_t * ctx,ilps28qsw_id_t * val)162 int32_t ilps28qsw_id_get(const stmdev_ctx_t *ctx, ilps28qsw_id_t *val)
163 {
164 uint8_t reg;
165 int32_t ret;
166
167 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_WHO_AM_I, ®, 1);
168 val->whoami = reg;
169
170 return ret;
171 }
172
173 /**
174 * @brief Configures the bus operating mode.[set]
175 *
176 * @param ctx communication interface handler.(ptr)
177 * @param val configures the bus operating mode.(ptr)
178 * @retval interface status (MANDATORY: return 0 -> no Error)
179 *
180 */
ilps28qsw_bus_mode_set(const stmdev_ctx_t * ctx,ilps28qsw_bus_mode_t * val)181 int32_t ilps28qsw_bus_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val)
182 {
183 ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl;
184 int32_t ret;
185
186 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_I3C_IF_CTRL,
187 (uint8_t *)&i3c_if_ctrl, 1);
188 if (ret == 0)
189 {
190 i3c_if_ctrl.asf_on = (uint8_t)val->filter & 0x01U;
191 i3c_if_ctrl.I3C_Bus_Avb_Sel = (uint8_t)val->bus_avb_time & 0x03U;
192 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_I3C_IF_CTRL,
193 (uint8_t *)&i3c_if_ctrl, 1);
194 }
195
196 return ret;
197 }
198
199 /**
200 * @brief Configures the bus operating mode.[set]
201 *
202 * @param ctx communication interface handler.(ptr)
203 * @param val configures the bus operating mode.(ptr)
204 * @retval interface status (MANDATORY: return 0 -> no Error)
205 *
206 */
ilps28qsw_bus_mode_get(const stmdev_ctx_t * ctx,ilps28qsw_bus_mode_t * val)207 int32_t ilps28qsw_bus_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val)
208 {
209 ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl;
210 int32_t ret;
211
212 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_I3C_IF_CTRL, (uint8_t *)&i3c_if_ctrl, 1);
213 if (ret == 0)
214 {
215 switch (i3c_if_ctrl.asf_on)
216 {
217 case ILPS28QSW_AUTO:
218 val->filter = ILPS28QSW_AUTO;
219 break;
220 case ILPS28QSW_ALWAYS_ON:
221 val->filter = ILPS28QSW_ALWAYS_ON;
222 break;
223 default:
224 val->filter = ILPS28QSW_AUTO;
225 break;
226 }
227
228 switch (i3c_if_ctrl.I3C_Bus_Avb_Sel)
229 {
230 case ILPS28QSW_BUS_AVB_TIME_50us:
231 val->bus_avb_time = ILPS28QSW_BUS_AVB_TIME_50us;
232 break;
233 case ILPS28QSW_BUS_AVB_TIME_2us:
234 val->bus_avb_time = ILPS28QSW_BUS_AVB_TIME_2us;
235 break;
236 case ILPS28QSW_BUS_AVB_TIME_1ms:
237 val->bus_avb_time = ILPS28QSW_BUS_AVB_TIME_1ms;
238 break;
239 case ILPS28QSW_BUS_AVB_TIME_25ms:
240 val->bus_avb_time = ILPS28QSW_BUS_AVB_TIME_25ms;
241 break;
242 default:
243 val->bus_avb_time = ILPS28QSW_BUS_AVB_TIME_50us;
244 break;
245 }
246 }
247
248 return ret;
249 }
250
251 /**
252 * @brief Configures the bus operating mode.[get]
253 *
254 * @param ctx communication interface handler.(ptr)
255 * @param val configures the bus operating mode.(ptr)
256 * @retval interface status (MANDATORY: return 0 -> no Error)
257 *
258 */
ilps28qsw_init_set(const stmdev_ctx_t * ctx,ilps28qsw_init_t val)259 int32_t ilps28qsw_init_set(const stmdev_ctx_t *ctx, ilps28qsw_init_t val)
260 {
261 ilps28qsw_ctrl_reg2_t ctrl_reg2;
262 ilps28qsw_ctrl_reg3_t ctrl_reg3;
263 uint8_t reg[2];
264 int32_t ret;
265
266 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2, reg, 2);
267 if (ret == 0)
268 {
269 bytecpy((uint8_t *)&ctrl_reg2, ®[0]);
270 bytecpy((uint8_t *)&ctrl_reg3, ®[1]);
271
272 switch (val)
273 {
274 case ILPS28QSW_BOOT:
275 ctrl_reg2.boot = PROPERTY_ENABLE;
276 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2,
277 (uint8_t *)&ctrl_reg2, 1);
278 break;
279 case ILPS28QSW_RESET:
280 ctrl_reg2.swreset = PROPERTY_ENABLE;
281 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2,
282 (uint8_t *)&ctrl_reg2, 1);
283 break;
284 case ILPS28QSW_DRV_RDY:
285 ctrl_reg2.bdu = PROPERTY_ENABLE;
286 ctrl_reg3.if_add_inc = PROPERTY_ENABLE;
287 bytecpy(®[0], (uint8_t *)&ctrl_reg2);
288 bytecpy(®[1], (uint8_t *)&ctrl_reg3);
289 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, reg, 2);
290 break;
291 default:
292 ctrl_reg2.swreset = PROPERTY_ENABLE;
293 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2,
294 (uint8_t *)&ctrl_reg2, 1);
295 break;
296 }
297 }
298 return ret;
299 }
300
301 /**
302 * @brief Get the status of the device.[get]
303 *
304 * @param ctx communication interface handler.(ptr)
305 * @param val the status of the device.(ptr)
306 * @retval interface status (MANDATORY: return 0 -> no Error)
307 *
308 */
ilps28qsw_status_get(const stmdev_ctx_t * ctx,ilps28qsw_stat_t * val)309 int32_t ilps28qsw_status_get(const stmdev_ctx_t *ctx, ilps28qsw_stat_t *val)
310 {
311 ilps28qsw_interrupt_cfg_t interrupt_cfg;
312 ilps28qsw_int_source_t int_source;
313 ilps28qsw_ctrl_reg2_t ctrl_reg2;
314 ilps28qsw_status_t status;
315 int32_t ret;
316
317 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2,
318 (uint8_t *)&ctrl_reg2, 1);
319 if (ret == 0)
320 {
321 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE, (uint8_t *)&int_source, 1);
322 }
323 if (ret == 0)
324 {
325 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_STATUS, (uint8_t *)&status, 1);
326 }
327 if (ret == 0)
328 {
329 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
330 (uint8_t *)&interrupt_cfg, 1);
331 }
332 val->sw_reset = ctrl_reg2.swreset;
333 val->boot = int_source.boot_on;
334 val->drdy_pres = status.p_da;
335 val->drdy_temp = status.t_da;
336 val->ovr_pres = status.p_or;
337 val->ovr_temp = status.t_or;
338 val->end_meas = ~ctrl_reg2.oneshot;
339 val->ref_done = ~interrupt_cfg.autozero;
340
341 return ret;
342 }
343
344 /**
345 * @brief Electrical pin configuration.[set]
346 *
347 * @param ctx communication interface handler.(ptr)
348 * @param val the electrical settings for the configurable pins.(ptr)
349 * @retval interface status (MANDATORY: return 0 -> no Error)
350 *
351 */
ilps28qsw_pin_conf_set(const stmdev_ctx_t * ctx,ilps28qsw_pin_conf_t * val)352 int32_t ilps28qsw_pin_conf_set(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val)
353 {
354 ilps28qsw_if_ctrl_t if_ctrl;
355 int32_t ret;
356
357 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
358
359 if (ret == 0)
360 {
361 if_ctrl.sda_pu_en = val->sda_pull_up;
362 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
363 }
364
365 return ret;
366 }
367
368 /**
369 * @brief Electrical pin configuration.[get]
370 *
371 * @param ctx communication interface handler.(ptr)
372 * @param val the electrical settings for the configurable pins.(ptr)
373 * @retval interface status (MANDATORY: return 0 -> no Error)
374 *
375 */
ilps28qsw_pin_conf_get(const stmdev_ctx_t * ctx,ilps28qsw_pin_conf_t * val)376 int32_t ilps28qsw_pin_conf_get(const stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val)
377 {
378 ilps28qsw_if_ctrl_t if_ctrl;
379 int32_t ret;
380
381 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_IF_CTRL, (uint8_t *)&if_ctrl, 1);
382 val->sda_pull_up = if_ctrl.sda_pu_en;
383
384 return ret;
385 }
386
387 /**
388 * @brief Get the status of all the interrupt sources.[get]
389 *
390 * @param ctx communication interface handler.(ptr)
391 * @param val the status of all the interrupt sources.(ptr)
392 * @retval interface status (MANDATORY: return 0 -> no Error)
393 *
394 */
ilps28qsw_all_sources_get(const stmdev_ctx_t * ctx,ilps28qsw_all_sources_t * val)395 int32_t ilps28qsw_all_sources_get(const stmdev_ctx_t *ctx,
396 ilps28qsw_all_sources_t *val)
397 {
398 ilps28qsw_fifo_status2_t fifo_status2;
399 ilps28qsw_int_source_t int_source;
400 ilps28qsw_status_t status;
401 int32_t ret;
402
403 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_STATUS, (uint8_t *)&status, 1);
404 if (ret == 0)
405 {
406 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INT_SOURCE,
407 (uint8_t *)&int_source, 1);
408 }
409 if (ret == 0)
410 {
411 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS2,
412 (uint8_t *)&fifo_status2, 1);
413 }
414
415 val->drdy_pres = status.p_da;
416 val->drdy_temp = status.t_da;
417 val->over_pres = int_source.ph;
418 val->under_pres = int_source.pl;
419 val->thrsld_pres = int_source.ia;
420 val->fifo_full = fifo_status2.fifo_full_ia;
421 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
422 val->fifo_th = fifo_status2.fifo_wtm_ia;
423
424 return ret;
425 }
426
427
428 /**
429 * @brief Sensor conversion parameters selection.[set]
430 *
431 * @param ctx communication interface handler.(ptr)
432 * @param val set the sensor conversion parameters.(ptr)
433 * @retval interface status (MANDATORY: return 0 -> no Error)
434 *
435 */
ilps28qsw_mode_set(const stmdev_ctx_t * ctx,ilps28qsw_md_t * val)436 int32_t ilps28qsw_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val)
437 {
438 ilps28qsw_ctrl_reg1_t ctrl_reg1;
439 ilps28qsw_ctrl_reg2_t ctrl_reg2;
440 ilps28qsw_ctrl_reg3_t ctrl_reg3;
441 ilps28qsw_fifo_ctrl_t fifo_ctrl;
442 uint8_t odr_save = 0, ah_qvar_en_save = 0;
443 uint8_t reg[3];
444 int32_t ret;
445
446 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3);
447
448 if (ret == 0)
449 {
450 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
451 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
452 bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
453
454 /* handle interleaved mode setting */
455 if (ctrl_reg1.odr != 0x0U)
456 {
457 /* power-down */
458 odr_save = ctrl_reg1.odr;
459 ctrl_reg1.odr = 0x0U;
460 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
461 }
462
463 if (ctrl_reg3.ah_qvar_en != 0U)
464 {
465 /* disable QVAR */
466 ah_qvar_en_save = ctrl_reg3.ah_qvar_en;
467 ctrl_reg3.ah_qvar_en = 0;
468 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
469 }
470
471 /* set interleaved mode (0 or 1) */
472 ctrl_reg3.ah_qvar_p_auto_en = val->interleaved_mode;
473 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
474
475 /* set FIFO interleaved mode (0 or 1) */
476 ret += ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
477 fifo_ctrl.ah_qvar_p_fifo_en = val->interleaved_mode;
478 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
479
480 if (ah_qvar_en_save != 0U)
481 {
482 /* restore ah_qvar_en back to previous setting */
483 ctrl_reg3.ah_qvar_en = ah_qvar_en_save;
484 }
485
486 if (odr_save != 0U)
487 {
488 /* restore odr back to previous setting */
489 ctrl_reg1.odr = odr_save;
490 }
491
492 ctrl_reg1.odr = (uint8_t)val->odr;
493 ctrl_reg1.avg = (uint8_t)val->avg;
494 ctrl_reg2.en_lpfp = (uint8_t)val->lpf & 0x01U;
495 ctrl_reg2.lfpf_cfg = ((uint8_t)val->lpf & 0x02U) >> 1;
496 ctrl_reg2.fs_mode = (uint8_t)val->fs;
497
498 bytecpy(®[0], (uint8_t *)&ctrl_reg1);
499 bytecpy(®[1], (uint8_t *)&ctrl_reg2);
500 bytecpy(®[2], (uint8_t *)&ctrl_reg3);
501 ret += ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3);
502 }
503
504 return ret;
505 }
506
507 /**
508 * @brief Sensor conversion parameters selection.[get]
509 *
510 * @param ctx communication interface handler.(ptr)
511 * @param val get the sensor conversion parameters.(ptr)
512 * @retval interface status (MANDATORY: return 0 -> no Error)
513 *
514 */
ilps28qsw_mode_get(const stmdev_ctx_t * ctx,ilps28qsw_md_t * val)515 int32_t ilps28qsw_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *val)
516 {
517 ilps28qsw_ctrl_reg1_t ctrl_reg1;
518 ilps28qsw_ctrl_reg2_t ctrl_reg2;
519 ilps28qsw_ctrl_reg3_t ctrl_reg3;
520 uint8_t reg[3];
521 int32_t ret;
522
523 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG1, reg, 3);
524
525 if (ret == 0)
526 {
527 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
528 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
529 bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
530
531 switch (ctrl_reg2.fs_mode)
532 {
533 case ILPS28QSW_1260hPa:
534 val->fs = ILPS28QSW_1260hPa;
535 break;
536 case ILPS28QSW_4060hPa:
537 val->fs = ILPS28QSW_4060hPa;
538 break;
539 default:
540 val->fs = ILPS28QSW_1260hPa;
541 break;
542 }
543
544 switch (ctrl_reg1.odr)
545 {
546 case ILPS28QSW_ONE_SHOT:
547 val->odr = ILPS28QSW_ONE_SHOT;
548 break;
549 case ILPS28QSW_1Hz:
550 val->odr = ILPS28QSW_1Hz;
551 break;
552 case ILPS28QSW_4Hz:
553 val->odr = ILPS28QSW_4Hz;
554 break;
555 case ILPS28QSW_10Hz:
556 val->odr = ILPS28QSW_10Hz;
557 break;
558 case ILPS28QSW_25Hz:
559 val->odr = ILPS28QSW_25Hz;
560 break;
561 case ILPS28QSW_50Hz:
562 val->odr = ILPS28QSW_50Hz;
563 break;
564 case ILPS28QSW_75Hz:
565 val->odr = ILPS28QSW_75Hz;
566 break;
567 case ILPS28QSW_100Hz:
568 val->odr = ILPS28QSW_100Hz;
569 break;
570 case ILPS28QSW_200Hz:
571 val->odr = ILPS28QSW_200Hz;
572 break;
573 default:
574 val->odr = ILPS28QSW_ONE_SHOT;
575 break;
576 }
577
578 switch (ctrl_reg1.avg)
579 {
580 case ILPS28QSW_4_AVG:
581 val->avg = ILPS28QSW_4_AVG;
582 break;
583 case ILPS28QSW_8_AVG:
584 val->avg = ILPS28QSW_8_AVG;
585 break;
586 case ILPS28QSW_16_AVG:
587 val->avg = ILPS28QSW_16_AVG;
588 break;
589 case ILPS28QSW_32_AVG:
590 val->avg = ILPS28QSW_32_AVG;
591 break;
592 case ILPS28QSW_64_AVG:
593 val->avg = ILPS28QSW_64_AVG;
594 break;
595 case ILPS28QSW_128_AVG:
596 val->avg = ILPS28QSW_128_AVG;
597 break;
598 case ILPS28QSW_256_AVG:
599 val->avg = ILPS28QSW_256_AVG;
600 break;
601 case ILPS28QSW_512_AVG:
602 val->avg = ILPS28QSW_512_AVG;
603 break;
604 default:
605 val->avg = ILPS28QSW_4_AVG;
606 break;
607 }
608
609 switch ((ctrl_reg2.lfpf_cfg << 2) | ctrl_reg2.en_lpfp)
610 {
611 case ILPS28QSW_LPF_DISABLE:
612 val->lpf = ILPS28QSW_LPF_DISABLE;
613 break;
614 case ILPS28QSW_LPF_ODR_DIV_4:
615 val->lpf = ILPS28QSW_LPF_ODR_DIV_4;
616 break;
617 case ILPS28QSW_LPF_ODR_DIV_9:
618 val->lpf = ILPS28QSW_LPF_ODR_DIV_9;
619 break;
620 default:
621 val->lpf = ILPS28QSW_LPF_DISABLE;
622 break;
623 }
624
625 val->interleaved_mode = ctrl_reg3.ah_qvar_p_auto_en;
626 }
627 return ret;
628 }
629
630 /**
631 * @brief Software trigger for One-Shot.[get]
632 *
633 * @param ctx communication interface handler.(ptr)
634 * @param md the sensor conversion parameters.(ptr)
635 * @retval interface status (MANDATORY: return 0 -> no Error)
636 *
637 */
ilps28qsw_trigger_sw(const stmdev_ctx_t * ctx,ilps28qsw_md_t * md)638 int32_t ilps28qsw_trigger_sw(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md)
639 {
640 ilps28qsw_ctrl_reg2_t ctrl_reg2;
641 int32_t ret = 0;
642
643 if (md->odr == ILPS28QSW_ONE_SHOT)
644 {
645 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
646 ctrl_reg2.oneshot = PROPERTY_ENABLE;
647 if (ret == 0)
648 {
649 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
650 }
651 }
652 return ret;
653 }
654
655 /**
656 * @brief AH/QVAR function enable.[set]
657 *
658 * @param ctx Read / write interface definitions
659 * @param val Change the value of ah_qvar_en in reg CTRL_REG3
660 * @retval Interface status (MANDATORY: return 0 -> no Error).
661 *
662 */
ilps28qsw_ah_qvar_en_set(const stmdev_ctx_t * ctx,uint8_t val)663 int32_t ilps28qsw_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val)
664 {
665 ilps28qsw_ctrl_reg3_t ctrl_reg3;
666 int32_t ret;
667
668 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
669
670 if (ret == 0)
671 {
672 ctrl_reg3.ah_qvar_en = val;
673 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
674 }
675
676 return ret;
677 }
678
679 /**
680 * @brief AH/QVAR function enable.[get]
681 *
682 * @param ctx Read / write interface definitions
683 * @param val Return the value of ah_qvar_en in reg CTRL_REG3
684 * @retval Interface status (MANDATORY: return 0 -> no Error).
685 *
686 */
ilps28qsw_ah_qvar_en_get(const stmdev_ctx_t * ctx,uint8_t * val)687 int32_t ilps28qsw_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
688 {
689 ilps28qsw_ctrl_reg3_t ctrl_reg3;
690 int32_t ret;
691
692 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
693 *val = ctrl_reg3.ah_qvar_en;
694
695 return ret;
696 }
697
698 /**
699 * @brief Retrieve sensor data.[get]
700 *
701 * @param ctx communication interface handler.(ptr)
702 * @param md the sensor conversion parameters.(ptr)
703 * @param data data retrived from the sensor.(ptr)
704 * @retval interface status (MANDATORY: return 0 -> no Error)
705 *
706 */
ilps28qsw_data_get(const stmdev_ctx_t * ctx,ilps28qsw_md_t * md,ilps28qsw_data_t * data)707 int32_t ilps28qsw_data_get(const stmdev_ctx_t *ctx, ilps28qsw_md_t *md,
708 ilps28qsw_data_t *data)
709 {
710 uint8_t buff[5];
711 int32_t ret;
712
713 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 5);
714
715 /* pressure conversion */
716 data->pressure.raw = (int32_t)buff[2];
717 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[1];
718 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[0];
719 data->pressure.raw = data->pressure.raw * 256;
720
721 if (md->interleaved_mode == 1U)
722 {
723 if ((buff[0] & 0x1U) == 0U)
724 {
725 /* data is a pressure sample */
726 switch (md->fs)
727 {
728 case ILPS28QSW_1260hPa:
729 data->pressure.hpa = ilps28qsw_from_fs1260_to_hPa(data->pressure.raw);
730 break;
731 case ILPS28QSW_4060hPa:
732 data->pressure.hpa = ilps28qsw_from_fs4060_to_hPa(data->pressure.raw);
733 break;
734 default:
735 data->pressure.hpa = 0.0f;
736 break;
737 }
738 data->ah_qvar.lsb = 0;
739 }
740 else
741 {
742 /* data is a AH_QVAR sample */
743 data->ah_qvar.lsb = (data->pressure.raw / 256); /* shift 8bit left */
744 data->pressure.hpa = 0.0f;
745 }
746 }
747 else
748 {
749 switch (md->fs)
750 {
751 case ILPS28QSW_1260hPa:
752 data->pressure.hpa = ilps28qsw_from_fs1260_to_hPa(data->pressure.raw);
753 break;
754 case ILPS28QSW_4060hPa:
755 data->pressure.hpa = ilps28qsw_from_fs4060_to_hPa(data->pressure.raw);
756 break;
757 default:
758 data->pressure.hpa = 0.0f;
759 break;
760 }
761 data->ah_qvar.lsb = 0;
762 }
763
764 /* temperature conversion */
765 data->heat.raw = (int16_t)buff[4];
766 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[3];
767 data->heat.deg_c = ilps28qsw_from_lsb_to_celsius(data->heat.raw);
768
769 return ret;
770 }
771
772 /**
773 * @brief Pressure output value.[get]
774 *
775 * @param ctx read / write interface definitions
776 * @param buff buffer that stores data read
777 * @retval interface status (MANDATORY: return 0 -> no Error)
778 *
779 */
ilps28qsw_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)780 int32_t ilps28qsw_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
781 {
782 int32_t ret;
783 uint8_t reg[3];
784
785 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, reg, 3);
786 *buff = reg[2];
787 *buff = (*buff * 256U) + reg[1];
788 *buff = (*buff * 256U) + reg[0];
789 *buff *= 256U;
790
791 return ret;
792 }
793
794 /**
795 * @brief Temperature output value.[get]
796 *
797 * @param ctx read / write interface definitions
798 * @param buff buffer that stores data read
799 * @retval interface status (MANDATORY: return 0 -> no Error)
800 *
801 */
ilps28qsw_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)802 int32_t ilps28qsw_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff)
803 {
804 int32_t ret;
805 uint8_t reg[2];
806
807 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_TEMP_OUT_L, reg, 2);
808 *buff = (int16_t)reg[1];
809 *buff = (*buff * 256) + (int16_t)reg[0];
810
811 return ret;
812 }
813
814 /**
815 * @brief AH/QVAR data read.[get]
816 *
817 * @param ctx communication interface handler.(ptr)
818 * @param md the sensor conversion parameters.(ptr)
819 * @param data data retrived from the sensor.(ptr)
820 * @retval interface status (MANDATORY: return 0 -> no Error)
821 *
822 */
ilps28qsw_ah_qvar_data_get(const stmdev_ctx_t * ctx,ilps28qsw_ah_qvar_data_t * data)823 int32_t ilps28qsw_ah_qvar_data_get(const stmdev_ctx_t *ctx,
824 ilps28qsw_ah_qvar_data_t *data)
825 {
826 uint8_t buff[5];
827 int32_t ret;
828
829 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_PRESS_OUT_XL, buff, 3);
830
831 /* QVAR conversion */
832 data->raw = (int32_t)buff[2];
833 data->raw = (data->raw * 256) + (int32_t) buff[1];
834 data->raw = (data->raw * 256) + (int32_t) buff[0];
835 data->raw = (data->raw * 256);
836 data->lsb = (data->raw / 256); /* shift 8bit left */
837
838 data->mv = ilps28qsw_from_lsb_to_mv(data->lsb);
839
840 return ret;
841 }
842
843 /**
844 * @}
845 *
846 */
847
848 /**
849 * @defgroup FIFO functions
850 * @brief This section groups all the functions concerning the
851 * management of FIFO.
852 * @{
853 *
854 */
855
856 /**
857 * @brief FIFO operation mode selection.[set]
858 *
859 * @param ctx communication interface handler.(ptr)
860 * @param val set the FIFO operation mode.(ptr)
861 * @retval interface status (MANDATORY: return 0 -> no Error)
862 *
863 */
ilps28qsw_fifo_mode_set(const stmdev_ctx_t * ctx,ilps28qsw_fifo_md_t * val)864 int32_t ilps28qsw_fifo_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val)
865 {
866 ilps28qsw_fifo_ctrl_t fifo_ctrl;
867 ilps28qsw_fifo_wtm_t fifo_wtm;
868 uint8_t reg[2];
869 int32_t ret;
870
871 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2);
872 if (ret == 0)
873 {
874 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
875 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
876
877 fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U;
878 fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2;
879
880 if (val->watermark != 0x00U)
881 {
882 fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE;
883 }
884 else
885 {
886 fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE;
887 }
888
889 fifo_wtm.wtm = val->watermark;
890
891 bytecpy(®[0], (uint8_t *)&fifo_ctrl);
892 bytecpy(®[1], (uint8_t *)&fifo_wtm);
893
894 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2);
895 }
896 return ret;
897 }
898
899 /**
900 * @brief FIFO operation mode selection.[get]
901 *
902 * @param ctx communication interface handler.(ptr)
903 * @param val get the FIFO operation mode.(ptr)
904 * @retval interface status (MANDATORY: return 0 -> no Error)
905 *
906 */
ilps28qsw_fifo_mode_get(const stmdev_ctx_t * ctx,ilps28qsw_fifo_md_t * val)907 int32_t ilps28qsw_fifo_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val)
908 {
909 ilps28qsw_fifo_ctrl_t fifo_ctrl;
910 ilps28qsw_fifo_wtm_t fifo_wtm;
911 uint8_t reg[2];
912 int32_t ret;
913
914 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_CTRL, reg, 2);
915
916 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
917 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
918
919 switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode)
920 {
921 case ILPS28QSW_BYPASS:
922 val->operation = ILPS28QSW_BYPASS;
923 break;
924 case ILPS28QSW_FIFO:
925 val->operation = ILPS28QSW_FIFO;
926 break;
927 case ILPS28QSW_STREAM:
928 val->operation = ILPS28QSW_STREAM;
929 break;
930 case ILPS28QSW_STREAM_TO_FIFO:
931 val->operation = ILPS28QSW_STREAM_TO_FIFO;
932 break;
933 case ILPS28QSW_BYPASS_TO_STREAM:
934 val->operation = ILPS28QSW_BYPASS_TO_STREAM;
935 break;
936 case ILPS28QSW_BYPASS_TO_FIFO:
937 val->operation = ILPS28QSW_BYPASS_TO_FIFO;
938 break;
939 default:
940 val->operation = ILPS28QSW_BYPASS;
941 break;
942 }
943
944 val->watermark = fifo_wtm.wtm;
945
946 return ret;
947 }
948
949 /**
950 * @brief Get the number of samples stored in FIFO.[get]
951 *
952 * @param ctx communication interface handler.(ptr)
953 * @param md the sensor conversion parameters.(ptr)
954 * @param val number of samples stored in FIFO.(ptr)
955 * @retval interface status (MANDATORY: return 0 -> no Error)
956 *
957 */
ilps28qsw_fifo_level_get(const stmdev_ctx_t * ctx,uint8_t * val)958 int32_t ilps28qsw_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
959 {
960 ilps28qsw_fifo_status1_t fifo_status1;
961 int32_t ret;
962
963 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_STATUS1,
964 (uint8_t *)&fifo_status1, 1);
965
966 *val = fifo_status1.fss;
967
968 return ret;
969 }
970
971 /**
972 * @brief Software trigger for One-Shot.[get]
973 *
974 * @param ctx communication interface handler.(ptr)
975 * @param md the sensor conversion parameters.(ptr)
976 * @param fmd get the FIFO operation mode.(ptr)
977 * @param samp number of samples stored in FIFO.(ptr)
978 * @param data data retrived from FIFO.(ptr)
979 * @retval interface status (MANDATORY: return 0 -> no Error)
980 *
981 */
ilps28qsw_fifo_data_get(const stmdev_ctx_t * ctx,uint8_t samp,ilps28qsw_md_t * md,ilps28qsw_fifo_data_t * data)982 int32_t ilps28qsw_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp,
983 ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data)
984 {
985 uint8_t fifo_data[3];
986 uint8_t i;
987 int32_t ret = 0;
988
989 for (i = 0U; i < samp; i++)
990 {
991 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3);
992 data[i].raw = (int32_t)fifo_data[2];
993 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1];
994 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0];
995 data[i].raw = (data[i].raw * 256);
996
997 if (md->interleaved_mode == 1U)
998 {
999 if ((fifo_data[0] & 0x1U) == 0U)
1000 {
1001 /* data is a pressure sample */
1002 switch (md->fs)
1003 {
1004 case ILPS28QSW_1260hPa:
1005 data[i].hpa = ilps28qsw_from_fs1260_to_hPa(data[i].raw);
1006 break;
1007 case ILPS28QSW_4060hPa:
1008 data[i].hpa = ilps28qsw_from_fs4060_to_hPa(data[i].raw);
1009 break;
1010 default:
1011 data[i].hpa = 0.0f;
1012 break;
1013 }
1014 data[i].lsb = 0;
1015 }
1016 else
1017 {
1018 /* data is a AH_QVAR sample */
1019 data[i].lsb = (data[i].raw / 256); /* shift 8bit left */
1020 data[i].hpa = 0.0f;
1021 }
1022 }
1023 else
1024 {
1025 switch (md->fs)
1026 {
1027 case ILPS28QSW_1260hPa:
1028 data[i].hpa = ilps28qsw_from_fs1260_to_hPa(data[i].raw);
1029 break;
1030 case ILPS28QSW_4060hPa:
1031 data[i].hpa = ilps28qsw_from_fs4060_to_hPa(data[i].raw);
1032 break;
1033 default:
1034 data[i].hpa = 0.0f;
1035 break;
1036 }
1037 data[i].lsb = 0;
1038 }
1039 }
1040
1041 return ret;
1042 }
1043
1044 /**
1045 * @}
1046 *
1047 */
1048
1049 /**
1050 * @defgroup Interrupt signals
1051 * @brief This section groups all the functions concerning
1052 * the management of interrupt signals.
1053 * @{
1054 *
1055 */
1056
1057 /**
1058 * @brief Interrupt pins hardware signal configuration.[set]
1059 *
1060 * @param ctx communication interface handler.(ptr)
1061 * @param val the pins hardware signal settings.(ptr)
1062 * @retval interface status (MANDATORY: return 0 -> no Error)
1063 *
1064 */
ilps28qsw_interrupt_mode_set(const stmdev_ctx_t * ctx,ilps28qsw_int_mode_t * val)1065 int32_t ilps28qsw_interrupt_mode_set(const stmdev_ctx_t *ctx,
1066 ilps28qsw_int_mode_t *val)
1067 {
1068 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1069 int32_t ret;
1070
1071 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1072 (uint8_t *)&interrupt_cfg, 1);
1073 if (ret == 0)
1074 {
1075 interrupt_cfg.lir = val->int_latched ;
1076 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1077 (uint8_t *)&interrupt_cfg, 1);
1078 }
1079 return ret;
1080 }
1081
1082 /**
1083 * @brief Interrupt pins hardware signal configuration.[get]
1084 *
1085 * @param ctx communication interface handler.(ptr)
1086 * @param val the pins hardware signal settings.(ptr)
1087 * @retval interface status (MANDATORY: return 0 -> no Error)
1088 *
1089 */
ilps28qsw_interrupt_mode_get(const stmdev_ctx_t * ctx,ilps28qsw_int_mode_t * val)1090 int32_t ilps28qsw_interrupt_mode_get(const stmdev_ctx_t *ctx,
1091 ilps28qsw_int_mode_t *val)
1092 {
1093 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1094 int32_t ret;
1095
1096 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1097 (uint8_t *)&interrupt_cfg, 1);
1098 val->int_latched = interrupt_cfg.lir;
1099
1100 return ret;
1101 }
1102
1103 /**
1104 * @}
1105 *
1106 */
1107
1108 /**
1109 * @defgroup Interrupt on threshold functions
1110 * @brief This section groups all the functions concerning
1111 * the wake up functionality.
1112 * @{
1113 *
1114 */
1115
1116 /**
1117 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1118 *
1119 * @param ctx communication interface handler.(ptr)
1120 * @param val parameters of configuration.(ptr)
1121 * @retval interface status (MANDATORY: return 0 -> no Error)
1122 *
1123 */
ilps28qsw_int_on_threshold_mode_set(const stmdev_ctx_t * ctx,ilps28qsw_int_th_md_t * val)1124 int32_t ilps28qsw_int_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1125 ilps28qsw_int_th_md_t *val)
1126 {
1127 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1128 ilps28qsw_ths_p_l_t ths_p_l;
1129 ilps28qsw_ths_p_h_t ths_p_h;
1130 uint8_t reg[3];
1131 int32_t ret;
1132
1133 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3);
1134 if (ret == 0)
1135 {
1136 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1137 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1138 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1139
1140 interrupt_cfg.phe = val->over_th;
1141 interrupt_cfg.ple = val->under_th;
1142 ths_p_h.ths = (uint8_t)(val->threshold / 256U);
1143 ths_p_l.ths = (uint8_t)(val->threshold - (ths_p_h.ths * 256U));
1144
1145 bytecpy(®[0], (uint8_t *)&interrupt_cfg);
1146 bytecpy(®[1], (uint8_t *)&ths_p_l);
1147 bytecpy(®[2], (uint8_t *)&ths_p_h);
1148
1149 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3);
1150 }
1151 return ret;
1152 }
1153
1154 /**
1155 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1156 *
1157 * @param ctx communication interface handler.(ptr)
1158 * @param val parameters of configuration.(ptr)
1159 * @retval interface status (MANDATORY: return 0 -> no Error)
1160 *
1161 */
ilps28qsw_int_on_threshold_mode_get(const stmdev_ctx_t * ctx,ilps28qsw_int_th_md_t * val)1162 int32_t ilps28qsw_int_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1163 ilps28qsw_int_th_md_t *val)
1164 {
1165 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1166 ilps28qsw_ths_p_l_t ths_p_l;
1167 ilps28qsw_ths_p_h_t ths_p_h;
1168 uint8_t reg[3];
1169 int32_t ret;
1170
1171 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG, reg, 3);
1172
1173 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1174 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1175 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1176
1177 val->over_th = interrupt_cfg.phe;
1178 val->under_th = interrupt_cfg.ple;
1179 val->threshold = ths_p_h.ths;
1180 val->threshold = (val->threshold * 256U) + ths_p_l.ths;
1181
1182 return ret;
1183 }
1184
1185 /**
1186 * @}
1187 *
1188 */
1189
1190 /**
1191 * @defgroup Reference value of pressure
1192 * @brief This section groups all the functions concerning
1193 * the wake up functionality.
1194 * @{
1195 *
1196 */
1197
1198 /**
1199 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1200 *
1201 * @param ctx communication interface handler.(ptr)
1202 * @param val parameters of configuration.(ptr)
1203 * @retval interface status (MANDATORY: return 0 -> no Error)
1204 *
1205 */
ilps28qsw_reference_mode_set(const stmdev_ctx_t * ctx,ilps28qsw_ref_md_t * val)1206 int32_t ilps28qsw_reference_mode_set(const stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val)
1207 {
1208 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1209 int32_t ret;
1210
1211 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1212 (uint8_t *)&interrupt_cfg, 1);
1213 if (ret == 0)
1214 {
1215
1216 interrupt_cfg.autozero = val->get_ref;
1217 interrupt_cfg.autorefp = (uint8_t)val->apply_ref & 0x01U;
1218
1219 interrupt_cfg.reset_az = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1220 interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1221
1222 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1223 (uint8_t *)&interrupt_cfg, 1);
1224 }
1225 return ret;
1226 }
1227
1228 /**
1229 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1230 *
1231 * @param ctx communication interface handler.(ptr)
1232 * @param val parameters of configuration.(ptr)
1233 * @retval interface status (MANDATORY: return 0 -> no Error)
1234 *
1235 */
ilps28qsw_reference_mode_get(const stmdev_ctx_t * ctx,ilps28qsw_ref_md_t * val)1236 int32_t ilps28qsw_reference_mode_get(const stmdev_ctx_t *ctx, ilps28qsw_ref_md_t *val)
1237 {
1238 ilps28qsw_interrupt_cfg_t interrupt_cfg;
1239 int32_t ret;
1240
1241 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_INTERRUPT_CFG,
1242 (uint8_t *)&interrupt_cfg, 1);
1243
1244 switch ((interrupt_cfg.reset_az << 1) |
1245 interrupt_cfg.autorefp)
1246 {
1247 case ILPS28QSW_OUT_AND_INTERRUPT:
1248 val->apply_ref = ILPS28QSW_OUT_AND_INTERRUPT;
1249 break;
1250 case ILPS28QSW_ONLY_INTERRUPT:
1251 val->apply_ref = ILPS28QSW_ONLY_INTERRUPT;
1252 break;
1253 default:
1254 val->apply_ref = ILPS28QSW_RST_REFS;
1255 break;
1256 }
1257 val->get_ref = interrupt_cfg.autozero;
1258
1259 return ret;
1260 }
1261
1262 /**
1263 * @brief Reference Pressure LSB data .[get]
1264 *
1265 * @param ctx communication interface handler.(ptr)
1266 * @param val parameters of configuration.(ptr)
1267 * @retval interface status (MANDATORY: return 0 -> no Error)
1268 *
1269 */
ilps28qsw_refp_get(const stmdev_ctx_t * ctx,int16_t * val)1270 int32_t ilps28qsw_refp_get(const stmdev_ctx_t *ctx, int16_t *val)
1271 {
1272 uint8_t reg[2];
1273 int32_t ret;
1274
1275 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_REF_P_L, reg, 2);
1276
1277 *val = (int16_t)reg[1];
1278 *val = *val * 256 + (int16_t)reg[0];
1279
1280 return ret;
1281 }
1282
1283 /**
1284 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1285 *
1286 * @param ctx communication interface handler.(ptr)
1287 * @param val parameters of configuration.(ptr)
1288 * @retval interface status (MANDATORY: return 0 -> no Error)
1289 *
1290 */
ilps28qsw_opc_set(const stmdev_ctx_t * ctx,int16_t val)1291 int32_t ilps28qsw_opc_set(const stmdev_ctx_t *ctx, int16_t val)
1292 {
1293 uint8_t reg[2];
1294 int32_t ret;
1295
1296 reg[1] = (uint8_t)(((uint16_t)val & 0xFF00U) / 256U);
1297 reg[0] = (uint8_t)((uint16_t)val & 0x00FFU);
1298
1299 ret = ilps28qsw_write_reg(ctx, ILPS28QSW_RPDS_L, reg, 2);
1300
1301 return ret;
1302 }
1303
1304 /**
1305 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1306 *
1307 * @param ctx communication interface handler.(ptr)
1308 * @param val parameters of configuration.(ptr)
1309 * @retval interface status (MANDATORY: return 0 -> no Error)
1310 *
1311 */
ilps28qsw_opc_get(const stmdev_ctx_t * ctx,int16_t * val)1312 int32_t ilps28qsw_opc_get(const stmdev_ctx_t *ctx, int16_t *val)
1313 {
1314 uint8_t reg[2];
1315 int32_t ret;
1316
1317 ret = ilps28qsw_read_reg(ctx, ILPS28QSW_RPDS_L, reg, 2);
1318
1319 *val = (int16_t)reg[1];
1320 *val = *val * 256 + (int16_t)reg[0];
1321
1322 return ret;
1323 }
1324
1325
1326 /**
1327 * @}
1328 *
1329 */
1330
1331 /**
1332 * @}
1333 *
1334 */
1335
1336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1337
