1 /* 2 ****************************************************************************** 3 * @file ilps28qsw_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * ilps28qsw_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2023 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ILPS28QSW_REGS_H 23 #define ILPS28QSW_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ILPS28QSW 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup ILPS28QSW_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define ILPS28QSW_I2C_ADD 0xB9U 173 174 /** Device Identification (Who am I) **/ 175 #define ILPS28QSW_ID 0xB4U 176 177 /** 178 * @} 179 * 180 */ 181 182 #define ILPS28QSW_INTERRUPT_CFG 0x0BU 183 typedef struct 184 { 185 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 186 uint8_t phe : 1; 187 uint8_t ple : 1; 188 uint8_t lir : 1; 189 uint8_t not_used_01 : 1; 190 uint8_t reset_az : 1; 191 uint8_t autozero : 1; 192 uint8_t reset_arp : 1; 193 uint8_t autorefp : 1; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t autorefp : 1; 196 uint8_t reset_arp : 1; 197 uint8_t autozero : 1; 198 uint8_t reset_az : 1; 199 uint8_t not_used_01 : 1; 200 uint8_t lir : 1; 201 uint8_t ple : 1; 202 uint8_t phe : 1; 203 #endif /* DRV_BYTE_ORDER */ 204 } ilps28qsw_interrupt_cfg_t; 205 206 #define ILPS28QSW_THS_P_L 0x0CU 207 typedef struct 208 { 209 uint8_t ths : 8; 210 } ilps28qsw_ths_p_l_t; 211 212 #define ILPS28QSW_THS_P_H 0x0DU 213 typedef struct 214 { 215 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 216 uint8_t ths : 7; 217 uint8_t not_used_01 : 1; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t not_used_01 : 1; 220 uint8_t ths : 7; 221 #endif /* DRV_BYTE_ORDER */ 222 } ilps28qsw_ths_p_h_t; 223 224 #define ILPS28QSW_IF_CTRL 0x0EU 225 typedef struct 226 { 227 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 228 uint8_t not_used_01 : 4; 229 uint8_t sda_pu_en : 1; 230 uint8_t not_used_02 : 3; 231 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 232 uint8_t not_used_02 : 3; 233 uint8_t sda_pu_en : 1; 234 uint8_t not_used_01 : 4; 235 #endif /* DRV_BYTE_ORDER */ 236 } ilps28qsw_if_ctrl_t; 237 238 #define ILPS28QSW_WHO_AM_I 0x0FU 239 #define ILPS28QSW_CTRL_REG1 0x10U 240 typedef struct 241 { 242 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 243 uint8_t avg : 3; 244 uint8_t odr : 4; 245 uint8_t not_used_01 : 1; 246 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 247 uint8_t not_used_01 : 1; 248 uint8_t odr : 4; 249 uint8_t avg : 3; 250 #endif /* DRV_BYTE_ORDER */ 251 } ilps28qsw_ctrl_reg1_t; 252 253 #define ILPS28QSW_CTRL_REG2 0x11U 254 typedef struct 255 { 256 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 257 uint8_t oneshot : 1; 258 uint8_t not_used_01 : 1; 259 uint8_t swreset : 1; 260 uint8_t bdu : 1; 261 uint8_t en_lpfp : 1; 262 uint8_t lfpf_cfg : 1; 263 uint8_t fs_mode : 1; 264 uint8_t boot : 1; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t boot : 1; 267 uint8_t fs_mode : 1; 268 uint8_t lfpf_cfg : 1; 269 uint8_t en_lpfp : 1; 270 uint8_t bdu : 1; 271 uint8_t swreset : 1; 272 uint8_t not_used_01 : 1; 273 uint8_t oneshot : 1; 274 #endif /* DRV_BYTE_ORDER */ 275 } ilps28qsw_ctrl_reg2_t; 276 277 #define ILPS28QSW_CTRL_REG3 0x12U 278 typedef struct 279 { 280 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 281 uint8_t if_add_inc : 1; 282 uint8_t not_used_01 : 4; 283 uint8_t ah_qvar_p_auto_en : 1; 284 uint8_t not_used_02 : 1; 285 uint8_t ah_qvar_en : 1; 286 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 287 uint8_t ah_qvar_en : 1; 288 uint8_t not_used_02 : 1; 289 uint8_t ah_qvar_p_auto_en : 1; 290 uint8_t not_used_01 : 4; 291 uint8_t if_add_inc : 1; 292 #endif /* DRV_BYTE_ORDER */ 293 } ilps28qsw_ctrl_reg3_t; 294 295 #define ILPS28QSW_FIFO_CTRL 0x14U 296 typedef struct 297 { 298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 299 uint8_t f_mode : 2; 300 uint8_t trig_modes : 1; 301 uint8_t stop_on_wtm : 1; 302 uint8_t ah_qvar_p_fifo_en : 1; 303 uint8_t not_used_01 : 3; 304 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 305 uint8_t not_used_01 : 3; 306 uint8_t ah_qvar_p_fifo_en : 1; 307 uint8_t stop_on_wtm : 1; 308 uint8_t trig_modes : 1; 309 uint8_t f_mode : 2; 310 #endif /* DRV_BYTE_ORDER */ 311 } ilps28qsw_fifo_ctrl_t; 312 313 #define ILPS28QSW_FIFO_WTM 0x15U 314 typedef struct 315 { 316 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 317 uint8_t wtm : 7; 318 uint8_t not_used_01 : 1; 319 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 320 uint8_t not_used_01 : 1; 321 uint8_t wtm : 7; 322 #endif /* DRV_BYTE_ORDER */ 323 } ilps28qsw_fifo_wtm_t; 324 325 #define ILPS28QSW_REF_P_L 0x16U 326 typedef struct 327 { 328 uint8_t refp : 8; 329 } ilps28qsw_ref_p_l_t; 330 331 #define ILPS28QSW_REF_P_H 0x17U 332 typedef struct 333 { 334 uint8_t refp : 8; 335 } ilps28qsw_ref_p_h_t; 336 337 #define ILPS28QSW_I3C_IF_CTRL 0x19U 338 typedef struct 339 { 340 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 341 uint8_t not_used_02 : 5; 342 uint8_t asf_on : 1; 343 uint8_t not_used_01 : 2; 344 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 345 uint8_t not_used_01 : 2; 346 uint8_t asf_on : 1; 347 uint8_t not_used_02 : 5; 348 #endif /* DRV_BYTE_ORDER */ 349 } ilps28qsw_i3c_if_ctrl_t; 350 351 #define ILPS28QSW_RPDS_L 0x1AU 352 #define ILPS28QSW_RPDS_H 0x1BU 353 #define ILPS28QSW_INT_SOURCE 0x24U 354 typedef struct 355 { 356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 357 uint8_t ph : 1; 358 uint8_t pl : 1; 359 uint8_t ia : 1; 360 uint8_t not_used_01 : 4; 361 uint8_t boot_on : 1; 362 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 363 uint8_t boot_on : 1; 364 uint8_t not_used_01 : 4; 365 uint8_t ia : 1; 366 uint8_t pl : 1; 367 uint8_t ph : 1; 368 #endif /* DRV_BYTE_ORDER */ 369 } ilps28qsw_int_source_t; 370 371 #define ILPS28QSW_FIFO_STATUS1 0x25U 372 typedef struct 373 { 374 uint8_t fss : 8; 375 } ilps28qsw_fifo_status1_t; 376 377 #define ILPS28QSW_FIFO_STATUS2 0x26U 378 typedef struct 379 { 380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 381 uint8_t not_used_01 : 5; 382 uint8_t fifo_full_ia : 1; 383 uint8_t fifo_ovr_ia : 1; 384 uint8_t fifo_wtm_ia : 1; 385 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 386 uint8_t fifo_wtm_ia : 1; 387 uint8_t fifo_ovr_ia : 1; 388 uint8_t fifo_full_ia : 1; 389 uint8_t not_used_01 : 5; 390 #endif /* DRV_BYTE_ORDER */ 391 } ilps28qsw_fifo_status2_t; 392 393 #define ILPS28QSW_STATUS 0x27U 394 typedef struct 395 { 396 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 397 uint8_t p_da : 1; 398 uint8_t t_da : 1; 399 uint8_t not_used_01 : 2; 400 uint8_t p_or : 1; 401 uint8_t t_or : 1; 402 uint8_t not_used_02 : 2; 403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 404 uint8_t not_used_02 : 2; 405 uint8_t t_or : 1; 406 uint8_t p_or : 1; 407 uint8_t not_used_01 : 2; 408 uint8_t t_da : 1; 409 uint8_t p_da : 1; 410 #endif /* DRV_BYTE_ORDER */ 411 } ilps28qsw_status_t; 412 413 #define ILPS28QSW_PRESS_OUT_XL 0x28U 414 #define ILPS28QSW_PRESS_OUT_L 0x29U 415 #define ILPS28QSW_PRESS_OUT_H 0x2AU 416 #define ILPS28QSW_TEMP_OUT_L 0x2BU 417 #define ILPS28QSW_TEMP_OUT_H 0x2CU 418 #define ILPS28QSW_ANALOGIC_HUB_DISABLE 0x5FU 419 #define ILPS28QSW_FIFO_DATA_OUT_PRESS_XL 0x78U 420 #define ILPS28QSW_FIFO_DATA_OUT_PRESS_L 0x79U 421 #define ILPS28QSW_FIFO_DATA_OUT_PRESS_H 0x7AU 422 423 /** 424 * @defgroup ILPS28QSW_Register_Union 425 * @brief This union group all the registers that has a bitfield 426 * description. 427 * This union is useful but not need by the driver. 428 * 429 * REMOVING this union you are compliant with: 430 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 431 * 432 * @{ 433 * 434 */ 435 436 typedef union 437 { 438 ilps28qsw_interrupt_cfg_t interrupt_cfg; 439 ilps28qsw_ths_p_l_t ths_p_l; 440 ilps28qsw_ths_p_h_t ths_p_h; 441 ilps28qsw_if_ctrl_t if_ctrl; 442 ilps28qsw_ctrl_reg1_t ctrl_reg1; 443 ilps28qsw_ctrl_reg2_t ctrl_reg2; 444 ilps28qsw_ctrl_reg3_t ctrl_reg3; 445 ilps28qsw_fifo_ctrl_t fifo_ctrl; 446 ilps28qsw_fifo_wtm_t fifo_wtm; 447 ilps28qsw_ref_p_l_t ref_p_l; 448 ilps28qsw_ref_p_h_t ref_p_h; 449 ilps28qsw_i3c_if_ctrl_t i3c_if_ctrl; 450 ilps28qsw_int_source_t int_source; 451 ilps28qsw_fifo_status1_t fifo_status1; 452 ilps28qsw_fifo_status2_t fifo_status2; 453 ilps28qsw_status_t status; 454 bitwise_t bitwise; 455 uint8_t byte; 456 } ilps28qsw_reg_t; 457 458 #ifndef __weak 459 #define __weak __attribute__((weak)) 460 #endif /* __weak */ 461 462 /* 463 * These are the basic platform dependent I/O routines to read 464 * and write device registers connected on a standard bus. 465 * The driver keeps offering a default implementation based on function 466 * pointers to read/write routines for backward compatibility. 467 * The __weak directive allows the final application to overwrite 468 * them with a custom implementation. 469 */ 470 471 int32_t ilps28qsw_read_reg(stmdev_ctx_t *ctx, uint8_t reg, 472 uint8_t *data, uint16_t len); 473 int32_t ilps28qsw_write_reg(stmdev_ctx_t *ctx, uint8_t reg, 474 uint8_t *data, uint16_t len); 475 476 extern float_t ilps28qsw_from_fs1260_to_hPa(int32_t lsb); 477 extern float_t ilps28qsw_from_fs4000_to_hPa(int32_t lsb); 478 479 extern float_t ilps28qsw_from_lsb_to_celsius(int16_t lsb); 480 481 extern float_t ilps28qsw_from_lsb_to_mv(int32_t lsb); 482 483 typedef struct 484 { 485 uint8_t whoami; 486 } ilps28qsw_id_t; 487 int32_t ilps28qsw_id_get(stmdev_ctx_t *ctx, ilps28qsw_id_t *val); 488 489 typedef struct 490 { 491 enum 492 { 493 ILPS28QSW_AUTO = 0x00, /* anti-spike filters managed by protocol */ 494 ILPS28QSW_ALWAYS_ON = 0x01, /* anti-spike filters always on */ 495 } filter; 496 } ilps28qsw_bus_mode_t; 497 int32_t ilps28qsw_bus_mode_set(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); 498 int32_t ilps28qsw_bus_mode_get(stmdev_ctx_t *ctx, ilps28qsw_bus_mode_t *val); 499 500 typedef enum 501 { 502 ILPS28QSW_DRV_RDY = 0x00, /* Initialize the device for driver usage */ 503 ILPS28QSW_BOOT = 0x01, /* Restore calib. param. ( it takes 10ms ) */ 504 ILPS28QSW_RESET = 0x02, /* Reset configuration registers */ 505 } ilps28qsw_init_t; 506 int32_t ilps28qsw_init_set(stmdev_ctx_t *ctx, ilps28qsw_init_t val); 507 508 typedef struct 509 { 510 uint8_t sw_reset : 1; /* Restoring configuration registers. */ 511 uint8_t boot : 1; /* Restoring calibration parameters. */ 512 uint8_t drdy_pres : 1; /* Pressure data ready. */ 513 uint8_t drdy_temp : 1; /* Temperature data ready. */ 514 uint8_t ovr_pres : 1; /* Pressure data overrun. */ 515 uint8_t ovr_temp : 1; /* Temperature data overrun. */ 516 uint8_t end_meas : 1; /* Single measurement is finished. */ 517 uint8_t ref_done : 1; /* Auto-Zero value is set. */ 518 } ilps28qsw_stat_t; 519 int32_t ilps28qsw_status_get(stmdev_ctx_t *ctx, ilps28qsw_stat_t *val); 520 521 typedef struct 522 { 523 uint8_t sda_pull_up : 1; /* 1 = pull-up always disabled */ 524 uint8_t cs_pull_up : 1; /* 1 = pull-up always disabled */ 525 } ilps28qsw_pin_conf_t; 526 int32_t ilps28qsw_pin_conf_set(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); 527 int32_t ilps28qsw_pin_conf_get(stmdev_ctx_t *ctx, ilps28qsw_pin_conf_t *val); 528 529 typedef struct 530 { 531 uint8_t drdy_pres : 1; /* Pressure data ready */ 532 uint8_t drdy_temp : 1; /* Temperature data ready */ 533 uint8_t over_pres : 1; /* Over pressure event */ 534 uint8_t under_pres : 1; /* Under pressure event */ 535 uint8_t thrsld_pres : 1; /* Over/Under pressure event */ 536 uint8_t fifo_full : 1; /* FIFO full */ 537 uint8_t fifo_ovr : 1; /* FIFO overrun */ 538 uint8_t fifo_th : 1; /* FIFO threshold reached */ 539 } ilps28qsw_all_sources_t; 540 int32_t ilps28qsw_all_sources_get(stmdev_ctx_t *ctx, 541 ilps28qsw_all_sources_t *val); 542 543 typedef struct 544 { 545 enum 546 { 547 ILPS28QSW_1260hPa = 0x00, 548 ILPS28QSW_4060hPa = 0x01, 549 } fs; 550 enum 551 { 552 ILPS28QSW_ONE_SHOT = 0x00, /* Device in power down till software trigger */ 553 ILPS28QSW_1Hz = 0x01, 554 ILPS28QSW_4Hz = 0x02, 555 ILPS28QSW_10Hz = 0x03, 556 ILPS28QSW_25Hz = 0x04, 557 ILPS28QSW_50Hz = 0x05, 558 ILPS28QSW_75Hz = 0x06, 559 ILPS28QSW_100Hz = 0x07, 560 ILPS28QSW_200Hz = 0x08, 561 } odr; 562 enum 563 { 564 ILPS28QSW_4_AVG = 0, 565 ILPS28QSW_8_AVG = 1, 566 ILPS28QSW_16_AVG = 2, 567 ILPS28QSW_32_AVG = 3, 568 ILPS28QSW_64_AVG = 4, 569 ILPS28QSW_128_AVG = 5, 570 ILPS28QSW_256_AVG = 6, 571 ILPS28QSW_512_AVG = 7, 572 } avg; 573 enum 574 { 575 ILPS28QSW_LPF_DISABLE = 0, 576 ILPS28QSW_LPF_ODR_DIV_4 = 1, 577 ILPS28QSW_LPF_ODR_DIV_9 = 3, 578 } lpf; 579 uint8_t interleaved_mode; 580 } ilps28qsw_md_t; 581 int32_t ilps28qsw_mode_set(stmdev_ctx_t *ctx, ilps28qsw_md_t *val); 582 int32_t ilps28qsw_mode_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *val); 583 584 int32_t ilps28qsw_trigger_sw(stmdev_ctx_t *ctx, ilps28qsw_md_t *md); 585 586 typedef struct 587 { 588 struct 589 { 590 float_t hpa; 591 int32_t raw; /* 32 bit signed-left algned format left */ 592 } pressure; 593 struct 594 { 595 float_t deg_c; 596 int16_t raw; 597 } heat; 598 struct 599 { 600 int32_t lsb; /* 24 bit properly right aligned */ 601 } ah_qvar; 602 } ilps28qsw_data_t; 603 int32_t ilps28qsw_data_get(stmdev_ctx_t *ctx, ilps28qsw_md_t *md, 604 ilps28qsw_data_t *data); 605 typedef struct 606 { 607 float_t mv; /* value converted in mV */ 608 int32_t lsb; /* 24 bit properly right aligned */ 609 int32_t raw; /* 32 bit signed-left algned format left */ 610 } ilps28qsw_ah_qvar_data_t; 611 int32_t ilps28qsw_ah_qvar_data_get(stmdev_ctx_t *ctx, 612 ilps28qsw_ah_qvar_data_t *data); 613 614 typedef struct 615 { 616 enum 617 { 618 ILPS28QSW_BYPASS = 0, 619 ILPS28QSW_FIFO = 1, 620 ILPS28QSW_STREAM = 2, 621 ILPS28QSW_STREAM_TO_FIFO = 7, /* Dynamic-Stream, FIFO on Trigger */ 622 ILPS28QSW_BYPASS_TO_STREAM = 6, /* Bypass, Dynamic-Stream on Trigger */ 623 ILPS28QSW_BYPASS_TO_FIFO = 5, /* Bypass, FIFO on Trigger */ 624 } operation; 625 uint8_t watermark : 7; /* (0 disable) max 128.*/ 626 } ilps28qsw_fifo_md_t; 627 int32_t ilps28qsw_fifo_mode_set(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); 628 int32_t ilps28qsw_fifo_mode_get(stmdev_ctx_t *ctx, ilps28qsw_fifo_md_t *val); 629 630 int32_t ilps28qsw_fifo_level_get(stmdev_ctx_t *ctx, uint8_t *val); 631 632 typedef struct 633 { 634 float_t hpa; 635 int32_t lsb; /* 24 bit properly right aligned */ 636 int32_t raw; 637 } ilps28qsw_fifo_data_t; 638 int32_t ilps28qsw_fifo_data_get(stmdev_ctx_t *ctx, uint8_t samp, 639 ilps28qsw_md_t *md, ilps28qsw_fifo_data_t *data); 640 641 typedef struct 642 { 643 uint8_t int_latched : 1; /* int events are: int on threshold, FIFO */ 644 } ilps28qsw_int_mode_t; 645 int32_t ilps28qsw_interrupt_mode_set(stmdev_ctx_t *ctx, 646 ilps28qsw_int_mode_t *val); 647 int32_t ilps28qsw_interrupt_mode_get(stmdev_ctx_t *ctx, 648 ilps28qsw_int_mode_t *val); 649 650 int32_t ilps28qsw_ah_qvar_disable(stmdev_ctx_t *ctx); 651 int32_t ilps28qsw_ah_qvar_en_set(stmdev_ctx_t *ctx, uint8_t val); 652 int32_t ilps28qsw_ah_qvar_en_get(stmdev_ctx_t *ctx, uint8_t *val); 653 654 typedef struct 655 { 656 uint16_t threshold; /* Threshold in hPa * 16 (@1260hPa) 657 * Threshold in hPa * 8 (@4060hPa) 658 */ 659 uint8_t over_th : 1; /* Pressure data over threshold event */ 660 uint8_t under_th : 1; /* Pressure data under threshold event */ 661 } ilps28qsw_int_th_md_t; 662 int32_t ilps28qsw_int_on_threshold_mode_set(stmdev_ctx_t *ctx, 663 ilps28qsw_int_th_md_t *val); 664 int32_t ilps28qsw_int_on_threshold_mode_get(stmdev_ctx_t *ctx, 665 ilps28qsw_int_th_md_t *val); 666 667 typedef struct 668 { 669 enum 670 { 671 ILPS28QSW_OUT_AND_INTERRUPT = 0, 672 ILPS28QSW_ONLY_INTERRUPT = 1, 673 ILPS28QSW_RST_REFS = 2, 674 } apply_ref; 675 uint8_t get_ref : 1; /* Use current pressure value as reference */ 676 } ilps28qsw_ref_md_t; 677 int32_t ilps28qsw_reference_mode_set(stmdev_ctx_t *ctx, 678 ilps28qsw_ref_md_t *val); 679 int32_t ilps28qsw_reference_mode_get(stmdev_ctx_t *ctx, 680 ilps28qsw_ref_md_t *val); 681 682 int32_t ilps28qsw_opc_set(stmdev_ctx_t *ctx, int16_t val); 683 int32_t ilps28qsw_opc_get(stmdev_ctx_t *ctx, int16_t *val); 684 685 /** 686 *@} 687 * 688 */ 689 690 #ifdef __cplusplus 691 } 692 #endif 693 694 #endif /* ILPS28QSW_REGS_H */ 695 696 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 697
