1 /**
2 ******************************************************************************
3 * @file ilps22qs_reg.c
4 * @author Sensors Software Solution Team
5 * @brief ILPS22QS driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2020 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "ilps22qs_reg.h"
21
22 /**
23 * @defgroup ILPS22QS
24 * @brief This file provides a set of functions needed to drive the
25 * ilps22qs nano pressure sensor.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
ilps22qs_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak ilps22qs_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 if (ctx == NULL)
55 {
56 return -1;
57 }
58
59 ret = ctx->read_reg(ctx->handle, reg, data, len);
60
61 return ret;
62 }
63
64 /**
65 * @brief Write generic device register
66 *
67 * @param ctx read / write interface definitions(ptr)
68 * @param reg register to write
69 * @param data pointer to data to write in register reg(ptr)
70 * @param len number of consecutive register to write
71 * @retval interface status (MANDATORY: return 0 -> no Error)
72 *
73 */
ilps22qs_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)74 int32_t __weak ilps22qs_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL)
80 {
81 return -1;
82 }
83
84 ret = ctx->write_reg(ctx->handle, reg, data, len);
85
86 return ret;
87 }
88
89 /**
90 * @}
91 *
92 */
93
94 /**
95 * @defgroup Private_functions
96 * @brief Section collect all the utility functions needed by APIs.
97 * @{
98 *
99 */
100
bytecpy(uint8_t * target,uint8_t * source)101 static void bytecpy(uint8_t *target, uint8_t *source)
102 {
103 if ((target != NULL) && (source != NULL))
104 {
105 *target = *source;
106 }
107 }
108
109 /**
110 * @}
111 *
112 */
113
114 /**
115 * @defgroup Sensitivity
116 * @brief These functions convert raw-data into engineering units.
117 * @{
118 *
119 */
120
ilps22qs_from_fs1260_to_hPa(int32_t lsb)121 float_t ilps22qs_from_fs1260_to_hPa(int32_t lsb)
122 {
123 return ((float_t)lsb / 1048576.0f); /* 4096.0f * 256 */
124 }
125
ilps22qs_from_fs4000_to_hPa(int32_t lsb)126 float_t ilps22qs_from_fs4000_to_hPa(int32_t lsb)
127 {
128 return ((float_t)lsb / 524288.0f); /* 2048.0f * 256 */
129 }
130
ilps22qs_from_lsb_to_celsius(int16_t lsb)131 float_t ilps22qs_from_lsb_to_celsius(int16_t lsb)
132 {
133 return ((float_t)lsb / 100.0f);
134 }
135
ilps22qs_from_lsb_to_mv(int32_t lsb)136 float_t ilps22qs_from_lsb_to_mv(int32_t lsb)
137 {
138 return ((float_t)lsb) / 438000.0f;
139 }
140
141 /**
142 * @}
143 *
144 */
145
146 /**
147 * @defgroup Basic functions
148 * @brief This section groups all the functions concerning device basic
149 * configuration.
150 * @{
151 *
152 */
153
154 /**
155 * @brief Device "Who am I".[get]
156 *
157 * @param ctx communication interface handler.(ptr)
158 * @param val ID values.(ptr)
159 * @retval interface status (MANDATORY: return 0 -> no Error)
160 *
161 */
ilps22qs_id_get(const stmdev_ctx_t * ctx,ilps22qs_id_t * val)162 int32_t ilps22qs_id_get(const stmdev_ctx_t *ctx, ilps22qs_id_t *val)
163 {
164 uint8_t reg;
165 int32_t ret;
166
167 ret = ilps22qs_read_reg(ctx, ILPS22QS_WHO_AM_I, ®, 1);
168 val->whoami = reg;
169
170 return ret;
171 }
172
173 /**
174 * @brief Configures the bus operating mode.[set]
175 *
176 * @param ctx communication interface handler.(ptr)
177 * @param val configures the bus operating mode.(ptr)
178 * @retval interface status (MANDATORY: return 0 -> no Error)
179 *
180 */
ilps22qs_bus_mode_set(const stmdev_ctx_t * ctx,ilps22qs_bus_mode_t * val)181 int32_t ilps22qs_bus_mode_set(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val)
182 {
183 ilps22qs_i3c_if_ctrl_t i3c_if_ctrl;
184 ilps22qs_if_ctrl_t if_ctrl;
185 int32_t ret;
186
187 ret = ilps22qs_read_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1);
188 if (ret == 0)
189 {
190 if_ctrl.i2c_i3c_dis = ((uint8_t)val->interface & 0x02U) >> 1;
191 if_ctrl.en_spi_read = ((uint8_t)val->interface & 0x01U);
192 ret = ilps22qs_write_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1);
193 }
194 if (ret == 0)
195 {
196 ret = ilps22qs_read_reg(ctx, ILPS22QS_I3C_IF_CTRL,
197 (uint8_t *)&i3c_if_ctrl, 1);
198 }
199 if (ret == 0)
200 {
201 i3c_if_ctrl.asf_on = (uint8_t)val->filter & 0x01U;
202 ret = ilps22qs_write_reg(ctx, ILPS22QS_I3C_IF_CTRL,
203 (uint8_t *)&i3c_if_ctrl, 1);
204 }
205 return ret;
206 }
207
208 /**
209 * @brief Configures the bus operating mode.[set]
210 *
211 * @param ctx communication interface handler.(ptr)
212 * @param val configures the bus operating mode.(ptr)
213 * @retval interface status (MANDATORY: return 0 -> no Error)
214 *
215 */
ilps22qs_bus_mode_get(const stmdev_ctx_t * ctx,ilps22qs_bus_mode_t * val)216 int32_t ilps22qs_bus_mode_get(const stmdev_ctx_t *ctx, ilps22qs_bus_mode_t *val)
217 {
218 ilps22qs_i3c_if_ctrl_t i3c_if_ctrl;
219 ilps22qs_if_ctrl_t if_ctrl;
220 int32_t ret;
221
222 ret = ilps22qs_read_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1);
223 if (ret == 0)
224 {
225 ret = ilps22qs_read_reg(ctx, ILPS22QS_I3C_IF_CTRL,
226 (uint8_t *)&i3c_if_ctrl, 1);
227
228 switch (if_ctrl.i2c_i3c_dis << 1)
229 {
230 case ILPS22QS_SEL_BY_HW:
231 val->interface = ILPS22QS_SEL_BY_HW;
232 break;
233 case ILPS22QS_SPI_3W:
234 val->interface = ILPS22QS_SPI_3W;
235 break;
236 default:
237 val->interface = ILPS22QS_SEL_BY_HW;
238 break;
239 }
240
241 switch (i3c_if_ctrl.asf_on)
242 {
243 case ILPS22QS_FILTER_AUTO:
244 val->filter = ILPS22QS_FILTER_AUTO;
245 break;
246 case ILPS22QS_FILTER_ALWAYS_ON:
247 val->filter = ILPS22QS_FILTER_ALWAYS_ON;
248 break;
249 default:
250 val->filter = ILPS22QS_FILTER_AUTO;
251 break;
252 }
253
254 }
255 return ret;
256 }
257
258 /**
259 * @brief Configures the bus operating mode.[get]
260 *
261 * @param ctx communication interface handler.(ptr)
262 * @param val configures the bus operating mode.(ptr)
263 * @retval interface status (MANDATORY: return 0 -> no Error)
264 *
265 */
ilps22qs_init_set(const stmdev_ctx_t * ctx,ilps22qs_init_t val)266 int32_t ilps22qs_init_set(const stmdev_ctx_t *ctx, ilps22qs_init_t val)
267 {
268 ilps22qs_ctrl_reg2_t ctrl_reg2;
269 ilps22qs_ctrl_reg3_t ctrl_reg3;
270 ilps22qs_int_source_t int_src;
271 ilps22qs_stat_t status;
272 uint8_t reg[2], cnt = 0;
273 int32_t ret;
274
275 ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG2, reg, 2);
276 if (ret == 0)
277 {
278 bytecpy((uint8_t *)&ctrl_reg2, ®[0]);
279 bytecpy((uint8_t *)&ctrl_reg3, ®[1]);
280
281 switch (val)
282 {
283 case ILPS22QS_BOOT:
284 ctrl_reg2.boot = PROPERTY_ENABLE;
285 ret = ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG2,
286 (uint8_t *)&ctrl_reg2, 1);
287 if (ret != 0)
288 {
289 break;
290 }
291
292 do
293 {
294 ret = ilps22qs_read_reg(ctx, ILPS22QS_INT_SOURCE, (uint8_t *)&int_src, 1);
295 if (ret != 0)
296 {
297 break;
298 }
299
300 /* boot procedure ended correctly */
301 if (int_src.boot_on == 0U)
302 {
303 break;
304 }
305
306 if (ctx->mdelay != NULL)
307 {
308 ctx->mdelay(10); /* 10ms of boot time */
309 }
310 } while (cnt++ < 5U);
311
312 if (cnt >= 5U)
313 {
314 ret = -1; /* boot procedure failed */
315 }
316
317 break;
318 case ILPS22QS_RESET:
319 ctrl_reg2.swreset = PROPERTY_ENABLE;
320 ret = ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG2,
321 (uint8_t *)&ctrl_reg2, 1);
322 if (ret != 0)
323 {
324 break;
325 }
326
327 do
328 {
329 ret = ilps22qs_status_get(ctx, &status);
330 if (ret != 0)
331 {
332 break;
333 }
334
335 /* sw-reset procedure ended correctly */
336 if (status.sw_reset == 0U)
337 {
338 break;
339 }
340
341 if (ctx->mdelay != NULL)
342 {
343 ctx->mdelay(1); /* should be 50 us */
344 }
345 } while (cnt++ < 5U);
346
347 if (cnt >= 5U)
348 {
349 ret = -1; /* sw-reset procedure failed */
350 }
351
352 break;
353 case ILPS22QS_DRV_RDY:
354 ctrl_reg2.bdu = PROPERTY_ENABLE;
355 ctrl_reg3.if_add_inc = PROPERTY_ENABLE;
356 bytecpy(®[0], (uint8_t *)&ctrl_reg2);
357 bytecpy(®[1], (uint8_t *)&ctrl_reg3);
358 ret = ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG2, reg, 2);
359 break;
360 default:
361 ctrl_reg2.swreset = PROPERTY_ENABLE;
362 ret = ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG2,
363 (uint8_t *)&ctrl_reg2, 1);
364 break;
365 }
366 }
367
368 return ret;
369 }
370
371 /**
372 * @brief Get the status of the device.[get]
373 *
374 * @param ctx communication interface handler.(ptr)
375 * @param val the status of the device.(ptr)
376 * @retval interface status (MANDATORY: return 0 -> no Error)
377 *
378 */
ilps22qs_status_get(const stmdev_ctx_t * ctx,ilps22qs_stat_t * val)379 int32_t ilps22qs_status_get(const stmdev_ctx_t *ctx, ilps22qs_stat_t *val)
380 {
381 ilps22qs_interrupt_cfg_t interrupt_cfg;
382 ilps22qs_int_source_t int_source;
383 ilps22qs_ctrl_reg2_t ctrl_reg2;
384 ilps22qs_status_t status;
385 int32_t ret;
386
387 ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG2,
388 (uint8_t *)&ctrl_reg2, 1);
389 if (ret == 0)
390 {
391 ret = ilps22qs_read_reg(ctx, ILPS22QS_INT_SOURCE, (uint8_t *)&int_source, 1);
392 }
393 if (ret == 0)
394 {
395 ret = ilps22qs_read_reg(ctx, ILPS22QS_STATUS, (uint8_t *)&status, 1);
396 }
397 if (ret == 0)
398 {
399 ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG,
400 (uint8_t *)&interrupt_cfg, 1);
401 }
402 val->sw_reset = ctrl_reg2.swreset;
403 val->boot = int_source.boot_on;
404 val->drdy_pres = status.p_da;
405 val->drdy_temp = status.t_da;
406 val->ovr_pres = status.p_or;
407 val->ovr_temp = status.t_or;
408 val->end_meas = ~ctrl_reg2.oneshot;
409 val->ref_done = ~interrupt_cfg.autozero;
410
411 return ret;
412 }
413
414 /**
415 * @brief Electrical pin configuration.[set]
416 *
417 * @param ctx communication interface handler.(ptr)
418 * @param val the electrical settings for the configurable pins.(ptr)
419 * @retval interface status (MANDATORY: return 0 -> no Error)
420 *
421 */
ilps22qs_pin_conf_set(const stmdev_ctx_t * ctx,ilps22qs_pin_conf_t * val)422 int32_t ilps22qs_pin_conf_set(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val)
423 {
424 ilps22qs_if_ctrl_t if_ctrl;
425 int32_t ret;
426
427 ret = ilps22qs_read_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1);
428
429 if (ret == 0)
430 {
431 if_ctrl.sda_pu_en = val->sda_pull_up;
432 if_ctrl.cs_pu_dis = ~val->cs_pull_up;
433 ret = ilps22qs_write_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1);
434 }
435
436 return ret;
437 }
438
439 /**
440 * @brief Electrical pin configuration.[get]
441 *
442 * @param ctx communication interface handler.(ptr)
443 * @param val the electrical settings for the configurable pins.(ptr)
444 * @retval interface status (MANDATORY: return 0 -> no Error)
445 *
446 */
ilps22qs_pin_conf_get(const stmdev_ctx_t * ctx,ilps22qs_pin_conf_t * val)447 int32_t ilps22qs_pin_conf_get(const stmdev_ctx_t *ctx, ilps22qs_pin_conf_t *val)
448 {
449 ilps22qs_if_ctrl_t if_ctrl;
450 int32_t ret;
451
452 ret = ilps22qs_read_reg(ctx, ILPS22QS_IF_CTRL, (uint8_t *)&if_ctrl, 1);
453
454 val->sda_pull_up = if_ctrl.sda_pu_en;
455 val->cs_pull_up = ~if_ctrl.cs_pu_dis;
456
457 return ret;
458 }
459
460 /**
461 * @brief Get the status of all the interrupt sources.[get]
462 *
463 * @param ctx communication interface handler.(ptr)
464 * @param val the status of all the interrupt sources.(ptr)
465 * @retval interface status (MANDATORY: return 0 -> no Error)
466 *
467 */
ilps22qs_all_sources_get(const stmdev_ctx_t * ctx,ilps22qs_all_sources_t * val)468 int32_t ilps22qs_all_sources_get(const stmdev_ctx_t *ctx,
469 ilps22qs_all_sources_t *val)
470 {
471 ilps22qs_fifo_status2_t fifo_status2;
472 ilps22qs_int_source_t int_source;
473 ilps22qs_status_t status;
474 int32_t ret;
475
476 ret = ilps22qs_read_reg(ctx, ILPS22QS_STATUS, (uint8_t *)&status, 1);
477 if (ret == 0)
478 {
479 ret = ilps22qs_read_reg(ctx, ILPS22QS_INT_SOURCE,
480 (uint8_t *)&int_source, 1);
481 }
482 if (ret == 0)
483 {
484 ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_STATUS2,
485 (uint8_t *)&fifo_status2, 1);
486 }
487
488 val->drdy_pres = status.p_da;
489 val->drdy_temp = status.t_da;
490 val->over_pres = int_source.ph;
491 val->under_pres = int_source.pl;
492 val->thrsld_pres = int_source.ia;
493 val->fifo_full = fifo_status2.fifo_full_ia;
494 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
495 val->fifo_th = fifo_status2.fifo_wtm_ia;
496
497 return ret;
498 }
499
500
501 /**
502 * @brief Sensor conversion parameters selection.[set]
503 *
504 * @param ctx communication interface handler.(ptr)
505 * @param val set the sensor conversion parameters.(ptr)
506 * @retval interface status (MANDATORY: return 0 -> no Error)
507 *
508 */
ilps22qs_mode_set(const stmdev_ctx_t * ctx,ilps22qs_md_t * val)509 int32_t ilps22qs_mode_set(const stmdev_ctx_t *ctx, ilps22qs_md_t *val)
510 {
511 ilps22qs_ctrl_reg1_t ctrl_reg1;
512 ilps22qs_ctrl_reg2_t ctrl_reg2;
513 ilps22qs_ctrl_reg3_t ctrl_reg3;
514 ilps22qs_fifo_ctrl_t fifo_ctrl;
515 uint8_t odr_save = 0, ah_qvar_en_save = 0;
516 uint8_t reg[3];
517 int32_t ret;
518
519 ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG1, reg, 3);
520
521 if (ret == 0)
522 {
523 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
524 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
525 bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
526
527 /* handle interleaved mode setting */
528 if (ctrl_reg1.odr != 0x0U)
529 {
530 /* power-down */
531 odr_save = ctrl_reg1.odr;
532 ctrl_reg1.odr = 0x0U;
533 ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
534 }
535
536 if (ctrl_reg3.ah_qvar_en != 0U)
537 {
538 /* disable QVAR */
539 ah_qvar_en_save = ctrl_reg3.ah_qvar_en;
540 ctrl_reg3.ah_qvar_en = 0;
541 ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
542 }
543
544 /* set interleaved mode (0 or 1) */
545 ctrl_reg3.ah_qvar_p_auto_en = val->interleaved_mode;
546 ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
547
548 /* set FIFO interleaved mode (0 or 1) */
549 ret += ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
550 fifo_ctrl.ah_qvar_p_fifo_en = val->interleaved_mode;
551 ret += ilps22qs_write_reg(ctx, ILPS22QS_FIFO_CTRL, (uint8_t *)&fifo_ctrl, 1);
552
553 if (ah_qvar_en_save != 0U)
554 {
555 /* restore ah_qvar_en back to previous setting */
556 ctrl_reg3.ah_qvar_en = ah_qvar_en_save;
557 }
558
559 if (odr_save != 0U)
560 {
561 /* restore odr back to previous setting */
562 ctrl_reg1.odr = odr_save;
563 }
564
565 ctrl_reg1.odr = (uint8_t)val->odr;
566 ctrl_reg1.avg = (uint8_t)val->avg;
567 ctrl_reg2.en_lpfp = (uint8_t)val->lpf & 0x01U;
568 ctrl_reg2.lfpf_cfg = ((uint8_t)val->lpf & 0x02U) >> 2;
569 ctrl_reg2.fs_mode = (uint8_t)val->fs;
570
571 bytecpy(®[0], (uint8_t *)&ctrl_reg1);
572 bytecpy(®[1], (uint8_t *)&ctrl_reg2);
573 bytecpy(®[2], (uint8_t *)&ctrl_reg3);
574 ret += ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG1, reg, 3);
575 }
576
577 return ret;
578 }
579
580 /**
581 * @brief Sensor conversion parameters selection.[get]
582 *
583 * @param ctx communication interface handler.(ptr)
584 * @param val get the sensor conversion parameters.(ptr)
585 * @retval interface status (MANDATORY: return 0 -> no Error)
586 *
587 */
ilps22qs_mode_get(const stmdev_ctx_t * ctx,ilps22qs_md_t * val)588 int32_t ilps22qs_mode_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *val)
589 {
590 ilps22qs_ctrl_reg1_t ctrl_reg1;
591 ilps22qs_ctrl_reg2_t ctrl_reg2;
592 ilps22qs_ctrl_reg3_t ctrl_reg3;
593 uint8_t reg[3];
594 int32_t ret;
595
596 ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG1, reg, 3);
597
598 if (ret == 0)
599 {
600 bytecpy((uint8_t *)&ctrl_reg1, ®[0]);
601 bytecpy((uint8_t *)&ctrl_reg2, ®[1]);
602 bytecpy((uint8_t *)&ctrl_reg3, ®[2]);
603
604 switch (ctrl_reg2.fs_mode)
605 {
606 case ILPS22QS_1260hPa:
607 val->fs = ILPS22QS_1260hPa;
608 break;
609 case ILPS22QS_4060hPa:
610 val->fs = ILPS22QS_4060hPa;
611 break;
612 default:
613 val->fs = ILPS22QS_1260hPa;
614 break;
615 }
616
617 switch (ctrl_reg1.odr)
618 {
619 case ILPS22QS_ONE_SHOT:
620 val->odr = ILPS22QS_ONE_SHOT;
621 break;
622 case ILPS22QS_1Hz:
623 val->odr = ILPS22QS_1Hz;
624 break;
625 case ILPS22QS_4Hz:
626 val->odr = ILPS22QS_4Hz;
627 break;
628 case ILPS22QS_10Hz:
629 val->odr = ILPS22QS_10Hz;
630 break;
631 case ILPS22QS_25Hz:
632 val->odr = ILPS22QS_25Hz;
633 break;
634 case ILPS22QS_50Hz:
635 val->odr = ILPS22QS_50Hz;
636 break;
637 case ILPS22QS_75Hz:
638 val->odr = ILPS22QS_75Hz;
639 break;
640 case ILPS22QS_100Hz:
641 val->odr = ILPS22QS_100Hz;
642 break;
643 case ILPS22QS_200Hz:
644 val->odr = ILPS22QS_200Hz;
645 break;
646 default:
647 val->odr = ILPS22QS_ONE_SHOT;
648 break;
649 }
650
651 switch (ctrl_reg1.avg)
652 {
653 case ILPS22QS_4_AVG:
654 val->avg = ILPS22QS_4_AVG;
655 break;
656 case ILPS22QS_8_AVG:
657 val->avg = ILPS22QS_8_AVG;
658 break;
659 case ILPS22QS_16_AVG:
660 val->avg = ILPS22QS_16_AVG;
661 break;
662 case ILPS22QS_32_AVG:
663 val->avg = ILPS22QS_32_AVG;
664 break;
665 case ILPS22QS_64_AVG:
666 val->avg = ILPS22QS_64_AVG;
667 break;
668 case ILPS22QS_128_AVG:
669 val->avg = ILPS22QS_128_AVG;
670 break;
671 case ILPS22QS_256_AVG:
672 val->avg = ILPS22QS_256_AVG;
673 break;
674 case ILPS22QS_512_AVG:
675 val->avg = ILPS22QS_512_AVG;
676 break;
677 default:
678 val->avg = ILPS22QS_4_AVG;
679 break;
680 }
681
682 switch ((ctrl_reg2.lfpf_cfg << 2) | ctrl_reg2.en_lpfp)
683 {
684 case ILPS22QS_LPF_DISABLE:
685 val->lpf = ILPS22QS_LPF_DISABLE;
686 break;
687 case ILPS22QS_LPF_ODR_DIV_4:
688 val->lpf = ILPS22QS_LPF_ODR_DIV_4;
689 break;
690 case ILPS22QS_LPF_ODR_DIV_9:
691 val->lpf = ILPS22QS_LPF_ODR_DIV_9;
692 break;
693 default:
694 val->lpf = ILPS22QS_LPF_DISABLE;
695 break;
696 }
697 val->interleaved_mode = ctrl_reg3.ah_qvar_p_auto_en;
698 }
699 return ret;
700 }
701
702 /**
703 * @brief Software trigger for One-Shot.[get]
704 *
705 * @param ctx communication interface handler.(ptr)
706 * @param md the sensor conversion parameters.(ptr)
707 * @retval interface status (MANDATORY: return 0 -> no Error)
708 *
709 */
ilps22qs_trigger_sw(const stmdev_ctx_t * ctx,ilps22qs_md_t * md)710 int32_t ilps22qs_trigger_sw(const stmdev_ctx_t *ctx, ilps22qs_md_t *md)
711 {
712 ilps22qs_ctrl_reg2_t ctrl_reg2;
713 int32_t ret = 0;
714
715 if (md->odr == ILPS22QS_ONE_SHOT)
716 {
717 ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
718 ctrl_reg2.oneshot = PROPERTY_ENABLE;
719 if (ret == 0)
720 {
721 ret = ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
722 }
723 }
724 return ret;
725 }
726
727 /**
728 * @brief AH/QVAR function enable.[set]
729 *
730 * @param ctx Read / write interface definitions
731 * @param val Change the value of ah_qvar_en in reg CTRL_REG3
732 * @retval Interface status (MANDATORY: return 0 -> no Error).
733 *
734 */
ilps22qs_ah_qvar_en_set(const stmdev_ctx_t * ctx,uint8_t val)735 int32_t ilps22qs_ah_qvar_en_set(const stmdev_ctx_t *ctx, uint8_t val)
736 {
737 ilps22qs_ctrl_reg3_t ctrl_reg3;
738 int32_t ret;
739
740 ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
741
742 if (ret == 0)
743 {
744 ctrl_reg3.ah_qvar_en = val;
745 ret = ilps22qs_write_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
746 }
747
748 return ret;
749 }
750
751 /**
752 * @brief AH/QVAR function enable.[get]
753 *
754 * @param ctx Read / write interface definitions
755 * @param val Return the value of ah_qvar_en in reg CTRL_REG3
756 * @retval Interface status (MANDATORY: return 0 -> no Error).
757 *
758 */
ilps22qs_ah_qvar_en_get(const stmdev_ctx_t * ctx,uint8_t * val)759 int32_t ilps22qs_ah_qvar_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
760 {
761 ilps22qs_ctrl_reg3_t ctrl_reg3;
762 int32_t ret;
763
764 ret = ilps22qs_read_reg(ctx, ILPS22QS_CTRL_REG3, (uint8_t *)&ctrl_reg3, 1);
765 *val = ctrl_reg3.ah_qvar_en;
766
767 return ret;
768 }
769
770 /**
771 * @brief Sensor data.[get]
772 *
773 * @param ctx communication interface handler.(ptr)
774 * @param md the sensor conversion parameters.(ptr)
775 * @param data data retrieved from the sensor.(ptr)
776 * @retval interface status (MANDATORY: return 0 -> no Error)
777 *
778 */
ilps22qs_data_get(const stmdev_ctx_t * ctx,ilps22qs_md_t * md,ilps22qs_data_t * data)779 int32_t ilps22qs_data_get(const stmdev_ctx_t *ctx, ilps22qs_md_t *md,
780 ilps22qs_data_t *data)
781 {
782 uint8_t buff[5];
783 int32_t ret;
784
785 ret = ilps22qs_read_reg(ctx, ILPS22QS_PRESS_OUT_XL, buff, 5);
786
787 /* pressure conversion */
788 data->pressure.raw = (int32_t)buff[2];
789 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[1];
790 data->pressure.raw = (data->pressure.raw * 256) + (int32_t) buff[0];
791 data->pressure.raw = data->pressure.raw * 256;
792
793 if (md->interleaved_mode == 1U)
794 {
795 if ((buff[0] & 0x1U) == 0U)
796 {
797 /* data is a pressure sample */
798 switch (md->fs)
799 {
800 case ILPS22QS_1260hPa:
801 data->pressure.hpa = ilps22qs_from_fs1260_to_hPa(data->pressure.raw);
802 break;
803 case ILPS22QS_4060hPa:
804 data->pressure.hpa = ilps22qs_from_fs4000_to_hPa(data->pressure.raw);
805 break;
806 default:
807 data->pressure.hpa = 0.0f;
808 break;
809 }
810 data->ah_qvar.lsb = 0;
811 }
812 else
813 {
814 /* data is a AH_QVAR sample */
815 data->ah_qvar.lsb = (data->pressure.raw / 256); /* shift 8bit left */
816 data->pressure.hpa = 0.0f;
817 }
818 }
819 else
820 {
821 switch (md->fs)
822 {
823 case ILPS22QS_1260hPa:
824 data->pressure.hpa = ilps22qs_from_fs1260_to_hPa(data->pressure.raw);
825 break;
826 case ILPS22QS_4060hPa:
827 data->pressure.hpa = ilps22qs_from_fs4000_to_hPa(data->pressure.raw);
828 break;
829 default:
830 data->pressure.hpa = 0.0f;
831 break;
832 }
833 data->ah_qvar.lsb = 0;
834 }
835
836
837 /* temperature conversion */
838 data->heat.raw = (int16_t)buff[4];
839 data->heat.raw = (data->heat.raw * 256) + (int16_t) buff[3];
840 data->heat.deg_c = ilps22qs_from_lsb_to_celsius(data->heat.raw);
841
842 return ret;
843 }
844
845 /**
846 * @brief Pressure output value.[get]
847 *
848 * @param ctx read / write interface definitions
849 * @param buff buffer that stores data read
850 * @retval interface status (MANDATORY: return 0 -> no Error)
851 *
852 */
ilps22qs_pressure_raw_get(const stmdev_ctx_t * ctx,uint32_t * buff)853 int32_t ilps22qs_pressure_raw_get(const stmdev_ctx_t *ctx, uint32_t *buff)
854 {
855 int32_t ret;
856 uint8_t reg[3];
857
858 ret = ilps22qs_read_reg(ctx, ILPS22QS_PRESS_OUT_XL, reg, 3);
859 *buff = reg[2];
860 *buff = (*buff * 256U) + reg[1];
861 *buff = (*buff * 256U) + reg[0];
862 *buff *= 256U;
863
864 return ret;
865 }
866
867 /**
868 * @brief Temperature output value.[get]
869 *
870 * @param ctx read / write interface definitions
871 * @param buff buffer that stores data read
872 * @retval interface status (MANDATORY: return 0 -> no Error)
873 *
874 */
ilps22qs_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * buff)875 int32_t ilps22qs_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *buff)
876 {
877 int32_t ret;
878 uint8_t reg[2];
879
880 ret = ilps22qs_read_reg(ctx, ILPS22QS_TEMP_OUT_L, reg, 2);
881 *buff = (int16_t)reg[1];
882 *buff = (*buff * 256) + (int16_t)reg[0];
883
884 return ret;
885 }
886
887 /**
888 * @brief AH/QVAR data read.[get]
889 *
890 * @param ctx communication interface handler.(ptr)
891 * @param md the sensor conversion parameters.(ptr)
892 * @param data data retrieved from the sensor.(ptr)
893 * @retval interface status (MANDATORY: return 0 -> no Error)
894 *
895 */
ilps22qs_ah_qvar_data_get(const stmdev_ctx_t * ctx,ilps22qs_ah_qvar_data_t * data)896 int32_t ilps22qs_ah_qvar_data_get(const stmdev_ctx_t *ctx,
897 ilps22qs_ah_qvar_data_t *data)
898 {
899 uint8_t buff[5];
900 int32_t ret;
901
902 ret = ilps22qs_read_reg(ctx, ILPS22QS_PRESS_OUT_XL, buff, 3);
903
904 /* QVAR conversion */
905 data->raw = (int32_t)buff[2];
906 data->raw = (data->raw * 256) + (int32_t) buff[1];
907 data->raw = (data->raw * 256) + (int32_t) buff[0];
908 data->raw = (data->raw * 256);
909 data->lsb = (data->raw / 256); /* shift 8bit left */
910
911 data->mv = ilps22qs_from_lsb_to_mv(data->lsb);
912
913 return ret;
914 }
915
916 /**
917 * @}
918 *
919 */
920
921 /**
922 * @defgroup FIFO functions
923 * @brief This section groups all the functions concerning the
924 * management of FIFO.
925 * @{
926 *
927 */
928
929 /**
930 * @brief FIFO operation mode selection.[set]
931 *
932 * @param ctx communication interface handler.(ptr)
933 * @param val set the FIFO operation mode.(ptr)
934 * @retval interface status (MANDATORY: return 0 -> no Error)
935 *
936 */
ilps22qs_fifo_mode_set(const stmdev_ctx_t * ctx,ilps22qs_fifo_md_t * val)937 int32_t ilps22qs_fifo_mode_set(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val)
938 {
939 ilps22qs_fifo_ctrl_t fifo_ctrl;
940 ilps22qs_fifo_wtm_t fifo_wtm;
941 uint8_t reg[2];
942 int32_t ret;
943
944 ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, reg, 2);
945 if (ret == 0)
946 {
947 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
948 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
949
950 fifo_ctrl.f_mode = (uint8_t)val->operation & 0x03U;
951 fifo_ctrl.trig_modes = ((uint8_t)val->operation & 0x04U) >> 2;
952
953 if (val->watermark != 0x00U)
954 {
955 fifo_ctrl.stop_on_wtm = PROPERTY_ENABLE;
956 }
957 else
958 {
959 fifo_ctrl.stop_on_wtm = PROPERTY_DISABLE;
960 }
961
962 fifo_wtm.wtm = val->watermark;
963
964 bytecpy(®[0], (uint8_t *)&fifo_ctrl);
965 bytecpy(®[1], (uint8_t *)&fifo_wtm);
966
967 ret = ilps22qs_write_reg(ctx, ILPS22QS_FIFO_CTRL, reg, 2);
968 }
969 return ret;
970 }
971
972 /**
973 * @brief FIFO operation mode selection.[get]
974 *
975 * @param ctx communication interface handler.(ptr)
976 * @param val get the FIFO operation mode.(ptr)
977 * @retval interface status (MANDATORY: return 0 -> no Error)
978 *
979 */
ilps22qs_fifo_mode_get(const stmdev_ctx_t * ctx,ilps22qs_fifo_md_t * val)980 int32_t ilps22qs_fifo_mode_get(const stmdev_ctx_t *ctx, ilps22qs_fifo_md_t *val)
981 {
982 ilps22qs_fifo_ctrl_t fifo_ctrl;
983 ilps22qs_fifo_wtm_t fifo_wtm;
984 uint8_t reg[2];
985 int32_t ret;
986
987 ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_CTRL, reg, 2);
988
989 bytecpy((uint8_t *)&fifo_ctrl, ®[0]);
990 bytecpy((uint8_t *)&fifo_wtm, ®[1]);
991
992 switch ((fifo_ctrl.trig_modes << 2) | fifo_ctrl.f_mode)
993 {
994 case ILPS22QS_BYPASS:
995 val->operation = ILPS22QS_BYPASS;
996 break;
997 case ILPS22QS_FIFO:
998 val->operation = ILPS22QS_FIFO;
999 break;
1000 case ILPS22QS_STREAM:
1001 val->operation = ILPS22QS_STREAM;
1002 break;
1003 case ILPS22QS_STREAM_TO_FIFO:
1004 val->operation = ILPS22QS_STREAM_TO_FIFO;
1005 break;
1006 case ILPS22QS_BYPASS_TO_STREAM:
1007 val->operation = ILPS22QS_BYPASS_TO_STREAM;
1008 break;
1009 case ILPS22QS_BYPASS_TO_FIFO:
1010 val->operation = ILPS22QS_BYPASS_TO_FIFO;
1011 break;
1012 default:
1013 val->operation = ILPS22QS_BYPASS;
1014 break;
1015 }
1016
1017 val->watermark = fifo_wtm.wtm;
1018
1019 return ret;
1020 }
1021
1022 /**
1023 * @brief Get the number of samples stored in FIFO.[get]
1024 *
1025 * @param ctx communication interface handler.(ptr)
1026 * @param val number of samples stored in FIFO.(ptr)
1027 * @retval interface status (MANDATORY: return 0 -> no Error)
1028 *
1029 */
ilps22qs_fifo_level_get(const stmdev_ctx_t * ctx,uint8_t * val)1030 int32_t ilps22qs_fifo_level_get(const stmdev_ctx_t *ctx, uint8_t *val)
1031 {
1032 ilps22qs_fifo_status1_t fifo_status1;
1033 int32_t ret;
1034
1035 ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_STATUS1,
1036 (uint8_t *)&fifo_status1, 1);
1037
1038 *val = fifo_status1.fss;
1039
1040 return ret;
1041 }
1042
1043 /**
1044 * @brief Software trigger for One-Shot.[get]
1045 *
1046 * @param ctx communication interface handler.(ptr)
1047 * @param samp number of samples stored in FIFO.(ptr)
1048 * @param md the sensor conversion parameters.(ptr)
1049 * @param data data retrieved from FIFO.(ptr)
1050 * @retval interface status (MANDATORY: return 0 -> no Error)
1051 *
1052 */
ilps22qs_fifo_data_get(const stmdev_ctx_t * ctx,uint8_t samp,ilps22qs_md_t * md,ilps22qs_fifo_data_t * data)1053 int32_t ilps22qs_fifo_data_get(const stmdev_ctx_t *ctx, uint8_t samp,
1054 ilps22qs_md_t *md, ilps22qs_fifo_data_t *data)
1055 {
1056 uint8_t fifo_data[3];
1057 uint8_t i;
1058 int32_t ret = 0;
1059
1060 for (i = 0U; i < samp; i++)
1061 {
1062 ret = ilps22qs_read_reg(ctx, ILPS22QS_FIFO_DATA_OUT_PRESS_XL, fifo_data, 3);
1063 data[i].raw = (int32_t)fifo_data[2];
1064 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[1];
1065 data[i].raw = (data[i].raw * 256) + (int32_t)fifo_data[0];
1066 data[i].raw = (data[i].raw * 256);
1067 if (md->interleaved_mode == 1U)
1068 {
1069 if ((fifo_data[0] & 0x1U) == 0U)
1070 {
1071 /* data is a pressure sample */
1072 switch (md->fs)
1073 {
1074 case ILPS22QS_1260hPa:
1075 data[i].hpa = ilps22qs_from_fs1260_to_hPa(data[i].raw);
1076 break;
1077 case ILPS22QS_4060hPa:
1078 data[i].hpa = ilps22qs_from_fs4000_to_hPa(data[i].raw);
1079 break;
1080 default:
1081 data[i].hpa = 0.0f;
1082 break;
1083 }
1084 data[i].lsb = 0;
1085 }
1086 else
1087 {
1088 /* data is a AH_QVAR sample */
1089 data[i].lsb = (data[i].raw / 256); /* shift 8bit left */
1090 data[i].hpa = 0.0f;
1091 }
1092 }
1093 else
1094 {
1095 switch (md->fs)
1096 {
1097 case ILPS22QS_1260hPa:
1098 data[i].hpa = ilps22qs_from_fs1260_to_hPa(data[i].raw);
1099 break;
1100 case ILPS22QS_4060hPa:
1101 data[i].hpa = ilps22qs_from_fs4000_to_hPa(data[i].raw);
1102 break;
1103 default:
1104 data[i].hpa = 0.0f;
1105 break;
1106 }
1107 data[i].lsb = 0;
1108 }
1109 }
1110
1111 return ret;
1112 }
1113
1114 /**
1115 * @}
1116 *
1117 */
1118
1119 /**
1120 * @defgroup Interrupt signals
1121 * @brief This section groups all the functions concerning
1122 * the management of interrupt signals.
1123 * @{
1124 *
1125 */
1126
1127 /**
1128 * @brief Interrupt pins hardware signal configuration.[set]
1129 *
1130 * @param ctx communication interface handler.(ptr)
1131 * @param val the pins hardware signal settings.(ptr)
1132 * @retval interface status (MANDATORY: return 0 -> no Error)
1133 *
1134 */
ilps22qs_interrupt_mode_set(const stmdev_ctx_t * ctx,ilps22qs_int_mode_t * val)1135 int32_t ilps22qs_interrupt_mode_set(const stmdev_ctx_t *ctx,
1136 ilps22qs_int_mode_t *val)
1137 {
1138 ilps22qs_interrupt_cfg_t interrupt_cfg;
1139 int32_t ret = 0;
1140
1141 ret += ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG,
1142 (uint8_t *)&interrupt_cfg, 1);
1143 if (ret == 0)
1144 {
1145 interrupt_cfg.lir = val->int_latched ;
1146 ret = ilps22qs_write_reg(ctx, ILPS22QS_INTERRUPT_CFG,
1147 (uint8_t *)&interrupt_cfg, 1);
1148 }
1149 return ret;
1150 }
1151
1152 /**
1153 * @brief Interrupt pins hardware signal configuration.[get]
1154 *
1155 * @param ctx communication interface handler.(ptr)
1156 * @param val the pins hardware signal settings.(ptr)
1157 * @retval interface status (MANDATORY: return 0 -> no Error)
1158 *
1159 */
ilps22qs_interrupt_mode_get(const stmdev_ctx_t * ctx,ilps22qs_int_mode_t * val)1160 int32_t ilps22qs_interrupt_mode_get(const stmdev_ctx_t *ctx,
1161 ilps22qs_int_mode_t *val)
1162 {
1163 ilps22qs_interrupt_cfg_t interrupt_cfg;
1164 int32_t ret = 0;
1165
1166 ret += ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG,
1167 (uint8_t *)&interrupt_cfg, 1);
1168
1169 val->int_latched = interrupt_cfg.lir;
1170
1171 return ret;
1172 }
1173
1174 /**
1175 * @brief AH function disable
1176 *
1177 * @param ctx communication interface handler.(ptr)
1178 * @retval interface status (MANDATORY: return 0 -> no Error)
1179 *
1180 */
ilps22qs_ah_qvar_disable(const stmdev_ctx_t * ctx)1181 int32_t ilps22qs_ah_qvar_disable(const stmdev_ctx_t *ctx)
1182 {
1183 uint32_t val = 0;
1184 int32_t ret;
1185
1186 ret = ilps22qs_write_reg(ctx, ILPS22QS_ANALOGIC_HUB_DISABLE, (uint8_t *)&val, 1);
1187
1188 return ret;
1189 }
1190
1191 /**
1192 * @}
1193 *
1194 */
1195
1196 /**
1197 * @defgroup Interrupt on threshold functions
1198 * @brief This section groups all the functions concerning
1199 * the wake up functionality.
1200 * @{
1201 *
1202 */
1203
1204 /**
1205 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1206 *
1207 * @param ctx communication interface handler.(ptr)
1208 * @param val parameters of configuration.(ptr)
1209 * @retval interface status (MANDATORY: return 0 -> no Error)
1210 *
1211 */
ilps22qs_int_on_threshold_mode_set(const stmdev_ctx_t * ctx,ilps22qs_int_th_md_t * val)1212 int32_t ilps22qs_int_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1213 ilps22qs_int_th_md_t *val)
1214 {
1215 ilps22qs_interrupt_cfg_t interrupt_cfg;
1216 ilps22qs_ths_p_l_t ths_p_l;
1217 ilps22qs_ths_p_h_t ths_p_h;
1218 uint8_t reg[3];
1219 int32_t ret;
1220
1221 ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG, reg, 3);
1222 if (ret == 0)
1223 {
1224 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1225 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1226 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1227
1228 interrupt_cfg.phe = val->over_th;
1229 interrupt_cfg.ple = val->under_th;
1230 ths_p_h.ths = (uint8_t)(val->threshold / 256U);
1231 ths_p_l.ths = (uint8_t)(val->threshold - (ths_p_h.ths * 256U));
1232
1233 bytecpy(®[0], (uint8_t *)&interrupt_cfg);
1234 bytecpy(®[1], (uint8_t *)&ths_p_l);
1235 bytecpy(®[2], (uint8_t *)&ths_p_h);
1236
1237 ret = ilps22qs_write_reg(ctx, ILPS22QS_INTERRUPT_CFG, reg, 3);
1238 }
1239
1240 return ret;
1241 }
1242
1243 /**
1244 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1245 *
1246 * @param ctx communication interface handler.(ptr)
1247 * @param val parameters of configuration.(ptr)
1248 * @retval interface status (MANDATORY: return 0 -> no Error)
1249 *
1250 */
ilps22qs_int_on_threshold_mode_get(const stmdev_ctx_t * ctx,ilps22qs_int_th_md_t * val)1251 int32_t ilps22qs_int_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1252 ilps22qs_int_th_md_t *val)
1253 {
1254 ilps22qs_interrupt_cfg_t interrupt_cfg;
1255 ilps22qs_ths_p_l_t ths_p_l;
1256 ilps22qs_ths_p_h_t ths_p_h;
1257 uint8_t reg[3];
1258 int32_t ret;
1259
1260 ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG, reg, 3);
1261
1262 bytecpy((uint8_t *)&interrupt_cfg, ®[0]);
1263 bytecpy((uint8_t *)&ths_p_l, ®[1]);
1264 bytecpy((uint8_t *)&ths_p_h, ®[2]);
1265
1266 val->over_th = interrupt_cfg.phe;
1267 val->under_th = interrupt_cfg.ple;
1268 val->threshold = ths_p_h.ths;
1269 val->threshold = (val->threshold * 256U) + ths_p_l.ths;
1270
1271 return ret;
1272 }
1273
1274 /**
1275 * @}
1276 *
1277 */
1278
1279 /**
1280 * @defgroup Reference value of pressure
1281 * @brief This section groups all the functions concerning
1282 * the wake up functionality.
1283 * @{
1284 *
1285 */
1286
1287 /**
1288 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1289 *
1290 * @param ctx communication interface handler.(ptr)
1291 * @param val parameters of configuration.(ptr)
1292 * @retval interface status (MANDATORY: return 0 -> no Error)
1293 *
1294 */
ilps22qs_reference_mode_set(const stmdev_ctx_t * ctx,ilps22qs_ref_md_t * val)1295 int32_t ilps22qs_reference_mode_set(const stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val)
1296 {
1297 ilps22qs_interrupt_cfg_t interrupt_cfg;
1298 int32_t ret;
1299
1300 ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG,
1301 (uint8_t *)&interrupt_cfg, 1);
1302 if (ret == 0)
1303 {
1304
1305 interrupt_cfg.autozero = val->get_ref;
1306 interrupt_cfg.autorefp = (uint8_t)val->apply_ref & 0x01U;
1307
1308 interrupt_cfg.reset_az = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1309 interrupt_cfg.reset_arp = ((uint8_t)val->apply_ref & 0x02U) >> 1;
1310
1311 ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG,
1312 (uint8_t *)&interrupt_cfg, 1);
1313 }
1314 return ret;
1315 }
1316
1317 /**
1318 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1319 *
1320 * @param ctx communication interface handler.(ptr)
1321 * @param val parameters of configuration.(ptr)
1322 * @retval interface status (MANDATORY: return 0 -> no Error)
1323 *
1324 */
ilps22qs_reference_mode_get(const stmdev_ctx_t * ctx,ilps22qs_ref_md_t * val)1325 int32_t ilps22qs_reference_mode_get(const stmdev_ctx_t *ctx, ilps22qs_ref_md_t *val)
1326 {
1327 ilps22qs_interrupt_cfg_t interrupt_cfg;
1328 int32_t ret;
1329
1330 ret = ilps22qs_read_reg(ctx, ILPS22QS_INTERRUPT_CFG,
1331 (uint8_t *)&interrupt_cfg, 1);
1332
1333 switch ((interrupt_cfg.reset_az << 1) |
1334 interrupt_cfg.autorefp)
1335 {
1336 case ILPS22QS_OUT_AND_INTERRUPT:
1337 val->apply_ref = ILPS22QS_OUT_AND_INTERRUPT;
1338 break;
1339 case ILPS22QS_ONLY_INTERRUPT:
1340 val->apply_ref = ILPS22QS_ONLY_INTERRUPT;
1341 break;
1342 default:
1343 val->apply_ref = ILPS22QS_RST_REFS;
1344 break;
1345 }
1346 val->get_ref = interrupt_cfg.autozero;
1347
1348 return ret;
1349 }
1350
1351
1352 /**
1353 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1354 *
1355 * @param ctx communication interface handler.(ptr)
1356 * @param val parameters of configuration.(ptr)
1357 * @retval interface status (MANDATORY: return 0 -> no Error)
1358 *
1359 */
ilps22qs_opc_set(const stmdev_ctx_t * ctx,int16_t val)1360 int32_t ilps22qs_opc_set(const stmdev_ctx_t *ctx, int16_t val)
1361 {
1362 uint8_t reg[2];
1363 int32_t ret;
1364
1365 reg[1] = (uint8_t)(((uint16_t)val & 0xFF00U) / 256U);
1366 reg[0] = (uint8_t)((uint16_t)val & 0x00FFU);
1367
1368 ret = ilps22qs_write_reg(ctx, ILPS22QS_RPDS_L, reg, 2);
1369
1370 return ret;
1371 }
1372
1373 /**
1374 * @brief Configuration of Wake-up and Wake-up to Sleep .[set]
1375 *
1376 * @param ctx communication interface handler.(ptr)
1377 * @param val parameters of configuration.(ptr)
1378 * @retval interface status (MANDATORY: return 0 -> no Error)
1379 *
1380 */
ilps22qs_opc_get(const stmdev_ctx_t * ctx,int16_t * val)1381 int32_t ilps22qs_opc_get(const stmdev_ctx_t *ctx, int16_t *val)
1382 {
1383 uint8_t reg[2];
1384 int32_t ret;
1385
1386 ret = ilps22qs_read_reg(ctx, ILPS22QS_RPDS_L, reg, 2);
1387
1388 *val = (int16_t)reg[1];
1389 *val = *val * 256 + (int16_t)reg[0];
1390
1391 return ret;
1392 }
1393
1394 /**
1395 * @}
1396 *
1397 */
1398
1399 /**
1400 * @}
1401 *
1402 */
1403
1404 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1405
