1 /**
2 ******************************************************************************
3 * @file iis328dq_reg.c
4 * @author Sensors Software Solution Team
5 * @brief IIS328DQ driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "iis328dq_reg.h"
21
22 /**
23 * @defgroup IIS328DQ
24 * @brief This file provides a set of functions needed to drive the
25 * iis328dq enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup IIS328DQ_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval Interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
iis328dq_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak iis328dq_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval Interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
iis328dq_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak iis328dq_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup IIS328DQ_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
iis328dq_from_fs2_to_mg(int16_t lsb)93 float_t iis328dq_from_fs2_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.98f / 16.0f);
96 }
97
iis328dq_from_fs4_to_mg(int16_t lsb)98 float_t iis328dq_from_fs4_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 1.95f / 16.0f);
101 }
102
iis328dq_from_fs8_to_mg(int16_t lsb)103 float_t iis328dq_from_fs8_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 3.91f / 16.0f);
106 }
107
108 /**
109 * @}
110 *
111 */
112
113 /**
114 * @defgroup IIS328DQ_Data_Generation
115 * @brief This section group all the functions concerning
116 * data generation
117 * @{
118 *
119 */
120
121 /**
122 * @brief X axis enable/disable.[set]
123 *
124 * @param ctx read / write interface definitions(ptr)
125 * @param val change the values of xen in reg CTRL_REG1
126 * @retval Interface status (MANDATORY: return 0 -> no Error)
127 *
128 */
iis328dq_axis_x_data_set(stmdev_ctx_t * ctx,uint8_t val)129 int32_t iis328dq_axis_x_data_set(stmdev_ctx_t *ctx, uint8_t val)
130 {
131 iis328dq_ctrl_reg1_t ctrl_reg1;
132 int32_t ret;
133
134 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
135 (uint8_t *)&ctrl_reg1, 1);
136
137 if (ret == 0)
138 {
139 ctrl_reg1.xen = val;
140 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
141 (uint8_t *)&ctrl_reg1, 1);
142 }
143
144 return ret;
145 }
146
147 /**
148 * @brief X axis enable/disable.[get]
149 *
150 * @param ctx read / write interface definitions(ptr)
151 * @param val change the values of xen in reg CTRL_REG1
152 * @retval Interface status (MANDATORY: return 0 -> no Error)
153 *
154 */
iis328dq_axis_x_data_get(stmdev_ctx_t * ctx,uint8_t * val)155 int32_t iis328dq_axis_x_data_get(stmdev_ctx_t *ctx, uint8_t *val)
156 {
157 iis328dq_ctrl_reg1_t ctrl_reg1;
158 int32_t ret;
159
160 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
161 (uint8_t *)&ctrl_reg1, 1);
162 *val = ctrl_reg1.xen;
163
164 return ret;
165 }
166
167 /**
168 * @brief Y axis enable/disable.[set]
169 *
170 * @param ctx read / write interface definitions(ptr)
171 * @param val change the values of yen in reg CTRL_REG1
172 * @retval Interface status (MANDATORY: return 0 -> no Error)
173 *
174 */
iis328dq_axis_y_data_set(stmdev_ctx_t * ctx,uint8_t val)175 int32_t iis328dq_axis_y_data_set(stmdev_ctx_t *ctx, uint8_t val)
176 {
177 iis328dq_ctrl_reg1_t ctrl_reg1;
178 int32_t ret;
179
180 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
181 (uint8_t *)&ctrl_reg1, 1);
182
183 if (ret == 0)
184 {
185 ctrl_reg1.yen = val;
186 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
187 (uint8_t *)&ctrl_reg1, 1);
188 }
189
190 return ret;
191 }
192
193 /**
194 * @brief Y axis enable/disable.[get]
195 *
196 * @param ctx read / write interface definitions(ptr)
197 * @param val change the values of yen in reg CTRL_REG1
198 * @retval Interface status (MANDATORY: return 0 -> no Error)
199 *
200 */
iis328dq_axis_y_data_get(stmdev_ctx_t * ctx,uint8_t * val)201 int32_t iis328dq_axis_y_data_get(stmdev_ctx_t *ctx, uint8_t *val)
202 {
203 iis328dq_ctrl_reg1_t ctrl_reg1;
204 int32_t ret;
205
206 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
207 (uint8_t *)&ctrl_reg1, 1);
208 *val = ctrl_reg1.yen;
209
210 return ret;
211 }
212
213 /**
214 * @brief Z axis enable/disable.[set]
215 *
216 * @param ctx read / write interface definitions(ptr)
217 * @param val change the values of zen in reg CTRL_REG1
218 * @retval Interface status (MANDATORY: return 0 -> no Error)
219 *
220 */
iis328dq_axis_z_data_set(stmdev_ctx_t * ctx,uint8_t val)221 int32_t iis328dq_axis_z_data_set(stmdev_ctx_t *ctx, uint8_t val)
222 {
223 iis328dq_ctrl_reg1_t ctrl_reg1;
224 int32_t ret;
225
226 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
227 (uint8_t *)&ctrl_reg1, 1);
228
229 if (ret == 0)
230 {
231 ctrl_reg1.zen = val;
232 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
233 (uint8_t *)&ctrl_reg1, 1);
234 }
235
236 return ret;
237 }
238
239 /**
240 * @brief Z axis enable/disable.[get]
241 *
242 * @param ctx read / write interface definitions(ptr)
243 * @param val change the values of zen in reg CTRL_REG1
244 * @retval Interface status (MANDATORY: return 0 -> no Error)
245 *
246 */
iis328dq_axis_z_data_get(stmdev_ctx_t * ctx,uint8_t * val)247 int32_t iis328dq_axis_z_data_get(stmdev_ctx_t *ctx, uint8_t *val)
248 {
249 iis328dq_ctrl_reg1_t ctrl_reg1;
250 int32_t ret;
251
252 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
253 (uint8_t *)&ctrl_reg1, 1);
254 *val = ctrl_reg1.zen;
255
256 return ret;
257 }
258
259 /**
260 * @brief Accelerometer data rate selection.[set]
261 *
262 * @param ctx read / write interface definitions(ptr)
263 * @param val change the values of dr in reg CTRL_REG1
264 * @retval Interface status (MANDATORY: return 0 -> no Error)
265 *
266 */
iis328dq_data_rate_set(stmdev_ctx_t * ctx,iis328dq_dr_t val)267 int32_t iis328dq_data_rate_set(stmdev_ctx_t *ctx, iis328dq_dr_t val)
268 {
269 iis328dq_ctrl_reg1_t ctrl_reg1;
270 int32_t ret;
271
272 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
273 (uint8_t *)&ctrl_reg1, 1);
274
275 if (ret == 0)
276 {
277 ctrl_reg1.pm = (uint8_t)val & 0x07U;
278 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
279 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG1,
280 (uint8_t *)&ctrl_reg1, 1);
281 }
282
283 return ret;
284 }
285
286 /**
287 * @brief Accelerometer data rate selection.[get]
288 *
289 * @param ctx read / write interface definitions(ptr)
290 * @param val Get the values of dr in reg CTRL_REG1
291 * @retval Interface status (MANDATORY: return 0 -> no Error)
292 *
293 */
iis328dq_data_rate_get(stmdev_ctx_t * ctx,iis328dq_dr_t * val)294 int32_t iis328dq_data_rate_get(stmdev_ctx_t *ctx, iis328dq_dr_t *val)
295 {
296 iis328dq_ctrl_reg1_t ctrl_reg1;
297 int32_t ret;
298
299 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG1,
300 (uint8_t *)&ctrl_reg1, 1);
301
302 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
303 {
304 case IIS328DQ_ODR_OFF:
305 *val = IIS328DQ_ODR_OFF;
306 break;
307
308 case IIS328DQ_ODR_Hz5:
309 *val = IIS328DQ_ODR_Hz5;
310 break;
311
312 case IIS328DQ_ODR_1Hz:
313 *val = IIS328DQ_ODR_1Hz;
314 break;
315
316 case IIS328DQ_ODR_5Hz2:
317 *val = IIS328DQ_ODR_5Hz2;
318 break;
319
320 case IIS328DQ_ODR_5Hz:
321 *val = IIS328DQ_ODR_5Hz;
322 break;
323
324 case IIS328DQ_ODR_10Hz:
325 *val = IIS328DQ_ODR_10Hz;
326 break;
327
328 case IIS328DQ_ODR_50Hz:
329 *val = IIS328DQ_ODR_50Hz;
330 break;
331
332 case IIS328DQ_ODR_100Hz:
333 *val = IIS328DQ_ODR_100Hz;
334 break;
335
336 case IIS328DQ_ODR_400Hz:
337 *val = IIS328DQ_ODR_400Hz;
338 break;
339
340 case IIS328DQ_ODR_1kHz:
341 *val = IIS328DQ_ODR_1kHz;
342 break;
343
344 default:
345 *val = IIS328DQ_ODR_OFF;
346 break;
347 }
348
349 return ret;
350 }
351
352 /**
353 * @brief High pass filter mode selection.[set]
354 *
355 * @param ctx read / write interface definitions(ptr)
356 * @param val change the values of hpm in reg CTRL_REG2
357 * @retval Interface status (MANDATORY: return 0 -> no Error)
358 *
359 */
iis328dq_reference_mode_set(stmdev_ctx_t * ctx,iis328dq_hpm_t val)360 int32_t iis328dq_reference_mode_set(stmdev_ctx_t *ctx,
361 iis328dq_hpm_t val)
362 {
363 iis328dq_ctrl_reg2_t ctrl_reg2;
364 int32_t ret;
365
366 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
367 (uint8_t *)&ctrl_reg2, 1);
368
369 if (ret == 0)
370 {
371 ctrl_reg2.hpm = (uint8_t)val;
372 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
373 (uint8_t *)&ctrl_reg2, 1);
374 }
375
376 return ret;
377 }
378
379 /**
380 * @brief High pass filter mode selection.[get]
381 *
382 * @param ctx read / write interface definitions(ptr)
383 * @param val Get the values of hpm in reg CTRL_REG2
384 * @retval Interface status (MANDATORY: return 0 -> no Error)
385 *
386 */
iis328dq_reference_mode_get(stmdev_ctx_t * ctx,iis328dq_hpm_t * val)387 int32_t iis328dq_reference_mode_get(stmdev_ctx_t *ctx,
388 iis328dq_hpm_t *val)
389 {
390 iis328dq_ctrl_reg2_t ctrl_reg2;
391 int32_t ret;
392
393 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
394 (uint8_t *)&ctrl_reg2, 1);
395
396 switch (ctrl_reg2.hpm)
397 {
398 case IIS328DQ_NORMAL_MODE:
399 *val = IIS328DQ_NORMAL_MODE;
400 break;
401
402 case IIS328DQ_REF_MODE_ENABLE:
403 *val = IIS328DQ_REF_MODE_ENABLE;
404 break;
405
406 default:
407 *val = IIS328DQ_NORMAL_MODE;
408 break;
409 }
410
411 return ret;
412 }
413
414 /**
415 * @brief Accelerometer full-scale selection.[set]
416 *
417 * @param ctx read / write interface definitions(ptr)
418 * @param val change the values of fs in reg CTRL_REG4
419 * @retval Interface status (MANDATORY: return 0 -> no Error)
420 *
421 */
iis328dq_full_scale_set(stmdev_ctx_t * ctx,iis328dq_fs_t val)422 int32_t iis328dq_full_scale_set(stmdev_ctx_t *ctx, iis328dq_fs_t val)
423 {
424 iis328dq_ctrl_reg4_t ctrl_reg4;
425 int32_t ret;
426
427 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
428 (uint8_t *)&ctrl_reg4, 1);
429
430 if (ret == 0)
431 {
432 ctrl_reg4.fs = (uint8_t)val;
433 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
434 (uint8_t *)&ctrl_reg4, 1);
435 }
436
437 return ret;
438 }
439
440 /**
441 * @brief Accelerometer full-scale selection.[get]
442 *
443 * @param ctx read / write interface definitions(ptr)
444 * @param val Get the values of fs in reg CTRL_REG4
445 * @retval Interface status (MANDATORY: return 0 -> no Error)
446 *
447 */
iis328dq_full_scale_get(stmdev_ctx_t * ctx,iis328dq_fs_t * val)448 int32_t iis328dq_full_scale_get(stmdev_ctx_t *ctx, iis328dq_fs_t *val)
449 {
450 iis328dq_ctrl_reg4_t ctrl_reg4;
451 int32_t ret;
452
453 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
454 (uint8_t *)&ctrl_reg4, 1);
455
456 switch (ctrl_reg4.fs)
457 {
458 case IIS328DQ_2g:
459 *val = IIS328DQ_2g;
460 break;
461
462 case IIS328DQ_4g:
463 *val = IIS328DQ_4g;
464 break;
465
466 case IIS328DQ_8g:
467 *val = IIS328DQ_8g;
468 break;
469
470 default:
471 *val = IIS328DQ_2g;
472 break;
473 }
474
475 return ret;
476 }
477
478 /**
479 * @brief Block data update.[set]
480 *
481 * @param ctx read / write interface definitions(ptr)
482 * @param val change the values of bdu in reg CTRL_REG4
483 * @retval Interface status (MANDATORY: return 0 -> no Error)
484 *
485 */
iis328dq_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)486 int32_t iis328dq_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
487 {
488 iis328dq_ctrl_reg4_t ctrl_reg4;
489 int32_t ret;
490
491 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
492 (uint8_t *)&ctrl_reg4, 1);
493
494 if (ret == 0)
495 {
496 ctrl_reg4.bdu = val;
497 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
498 (uint8_t *)&ctrl_reg4, 1);
499 }
500
501 return ret;
502 }
503
504 /**
505 * @brief Block data update.[get]
506 *
507 * @param ctx read / write interface definitions(ptr)
508 * @param val change the values of bdu in reg CTRL_REG4
509 * @retval Interface status (MANDATORY: return 0 -> no Error)
510 *
511 */
iis328dq_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)512 int32_t iis328dq_block_data_update_get(stmdev_ctx_t *ctx,
513 uint8_t *val)
514 {
515 iis328dq_ctrl_reg4_t ctrl_reg4;
516 int32_t ret;
517
518 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
519 (uint8_t *)&ctrl_reg4, 1);
520 *val = ctrl_reg4.bdu;
521
522 return ret;
523 }
524
525 /**
526 * @brief The STATUS_REG register is read by the interface.[get]
527 *
528 * @param ctx read / write interface definitions(ptr)
529 * @param val registers STATUS_REG
530 * @retval Interface status (MANDATORY: return 0 -> no Error)
531 *
532 */
iis328dq_status_reg_get(stmdev_ctx_t * ctx,iis328dq_status_reg_t * val)533 int32_t iis328dq_status_reg_get(stmdev_ctx_t *ctx,
534 iis328dq_status_reg_t *val)
535 {
536 int32_t ret;
537
538 ret = iis328dq_read_reg(ctx, IIS328DQ_STATUS_REG, (uint8_t *) val, 1);
539
540 return ret;
541 }
542
543 /**
544 * @brief Accelerometer new data available.[get]
545 *
546 * @param ctx read / write interface definitions(ptr)
547 * @param val change the values of zyxda in reg STATUS_REG
548 * @retval Interface status (MANDATORY: return 0 -> no Error)
549 *
550 */
iis328dq_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)551 int32_t iis328dq_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
552 {
553 iis328dq_status_reg_t status_reg;
554 int32_t ret;
555
556 ret = iis328dq_read_reg(ctx, IIS328DQ_STATUS_REG,
557 (uint8_t *)&status_reg, 1);
558 *val = status_reg.zyxda;
559
560 return ret;
561 }
562
563 /**
564 * @}
565 *
566 */
567
568 /**
569 * @defgroup IIS328DQ_Data_Output
570 * @brief This section groups all the data output functions.
571 * @{
572 *
573 */
574
575 /**
576 * @brief Linear acceleration output register. The value is expressed
577 * as a 16-bit word in two’s complement.[get]
578 *
579 * @param ctx read / write interface definitions(ptr)
580 * @param buff buffer that stores data read
581 * @retval Interface status (MANDATORY: return 0 -> no Error)
582 *
583 */
iis328dq_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)584 int32_t iis328dq_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
585 {
586 uint8_t buff[6];
587 int32_t ret;
588
589 ret = iis328dq_read_reg(ctx, IIS328DQ_OUT_X_L, buff, 6);
590 val[0] = (int16_t)buff[1];
591 val[0] = (val[0] * 256) + (int16_t)buff[0];
592 val[1] = (int16_t)buff[3];
593 val[1] = (val[1] * 256) + (int16_t)buff[2];
594 val[2] = (int16_t)buff[5];
595 val[2] = (val[2] * 256) + (int16_t)buff[4];
596
597 return ret;
598 }
599
600 /**
601 * @}
602 *
603 */
604
605 /**
606 * @defgroup IIS328DQ_Common
607 * @brief This section groups common useful functions.
608 * @{
609 *
610 */
611
612 /**
613 * @brief Device Who am I.[get]
614 *
615 * @param ctx read / write interface definitions(ptr)
616 * @param buff buffer that stores data read
617 * @retval Interface status (MANDATORY: return 0 -> no Error)
618 *
619 */
iis328dq_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)620 int32_t iis328dq_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
621 {
622 int32_t ret;
623
624 ret = iis328dq_read_reg(ctx, IIS328DQ_WHO_AM_I, buff, 1);
625
626 return ret;
627 }
628
629 /**
630 * @brief Reboot memory content. Reload the calibration parameters.[set]
631 *
632 * @param ctx read / write interface definitions(ptr)
633 * @param val change the values of boot in reg CTRL_REG2
634 * @retval Interface status (MANDATORY: return 0 -> no Error)
635 *
636 */
iis328dq_boot_set(stmdev_ctx_t * ctx,uint8_t val)637 int32_t iis328dq_boot_set(stmdev_ctx_t *ctx, uint8_t val)
638 {
639 iis328dq_ctrl_reg2_t ctrl_reg2;
640 int32_t ret;
641
642 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
643 (uint8_t *)&ctrl_reg2, 1);
644
645 if (ret == 0)
646 {
647 ctrl_reg2.boot = val;
648 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
649 (uint8_t *)&ctrl_reg2, 1);
650 }
651
652 return ret;
653 }
654
655 /**
656 * @brief Reboot memory content. Reload the calibration parameters.[get]
657 *
658 * @param ctx read / write interface definitions(ptr)
659 * @param val change the values of boot in reg CTRL_REG2
660 * @retval Interface status (MANDATORY: return 0 -> no Error)
661 *
662 */
iis328dq_boot_get(stmdev_ctx_t * ctx,uint8_t * val)663 int32_t iis328dq_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
664 {
665 iis328dq_ctrl_reg2_t ctrl_reg2;
666 int32_t ret;
667
668 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
669 (uint8_t *)&ctrl_reg2, 1);
670 *val = ctrl_reg2.boot;
671
672 return ret;
673 }
674
675 /**
676 * @brief Linear acceleration sensor self-test enable.[set]
677 *
678 * @param ctx read / write interface definitions(ptr)
679 * @param val change the values of st in reg CTRL_REG4
680 * @retval Interface status (MANDATORY: return 0 -> no Error)
681 *
682 */
iis328dq_self_test_set(stmdev_ctx_t * ctx,iis328dq_st_t val)683 int32_t iis328dq_self_test_set(stmdev_ctx_t *ctx, iis328dq_st_t val)
684 {
685 iis328dq_ctrl_reg4_t ctrl_reg4;
686 int32_t ret;
687
688 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
689 (uint8_t *)&ctrl_reg4, 1);
690
691 if (ret == 0)
692 {
693 ctrl_reg4.st = (uint8_t)val;
694 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
695 (uint8_t *)&ctrl_reg4, 1);
696 }
697
698 return ret;
699 }
700
701 /**
702 * @brief Linear acceleration sensor self-test enable.[get]
703 *
704 * @param ctx read / write interface definitions(ptr)
705 * @param val Get the values of st in reg CTRL_REG4
706 * @retval Interface status (MANDATORY: return 0 -> no Error)
707 *
708 */
iis328dq_self_test_get(stmdev_ctx_t * ctx,iis328dq_st_t * val)709 int32_t iis328dq_self_test_get(stmdev_ctx_t *ctx, iis328dq_st_t *val)
710 {
711 iis328dq_ctrl_reg4_t ctrl_reg4;
712 int32_t ret;
713
714 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
715 (uint8_t *)&ctrl_reg4, 1);
716
717 switch (ctrl_reg4.st)
718 {
719 case IIS328DQ_ST_DISABLE:
720 *val = IIS328DQ_ST_DISABLE;
721 break;
722
723 case IIS328DQ_ST_POSITIVE:
724 *val = IIS328DQ_ST_POSITIVE;
725 break;
726
727 case IIS328DQ_ST_NEGATIVE:
728 *val = IIS328DQ_ST_NEGATIVE;
729 break;
730
731 default:
732 *val = IIS328DQ_ST_DISABLE;
733 break;
734 }
735
736 return ret;
737 }
738
739 /**
740 * @brief Big/Little Endian Data selection.[set]
741 *
742 * @param ctx read / write interface definitions(ptr)
743 * @param val change the values of ble in reg CTRL_REG4
744 * @retval Interface status (MANDATORY: return 0 -> no Error)
745 *
746 */
iis328dq_data_format_set(stmdev_ctx_t * ctx,iis328dq_ble_t val)747 int32_t iis328dq_data_format_set(stmdev_ctx_t *ctx,
748 iis328dq_ble_t val)
749 {
750 iis328dq_ctrl_reg4_t ctrl_reg4;
751 int32_t ret;
752
753 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
754 (uint8_t *)&ctrl_reg4, 1);
755
756 if (ret == 0)
757 {
758 ctrl_reg4.ble = (uint8_t)val;
759 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
760 (uint8_t *)&ctrl_reg4, 1);
761 }
762
763 return ret;
764 }
765
766 /**
767 * @brief Big/Little Endian Data selection.[get]
768 *
769 * @param ctx read / write interface definitions(ptr)
770 * @param val Get the values of ble in reg CTRL_REG4
771 * @retval Interface status (MANDATORY: return 0 -> no Error)
772 *
773 */
iis328dq_data_format_get(stmdev_ctx_t * ctx,iis328dq_ble_t * val)774 int32_t iis328dq_data_format_get(stmdev_ctx_t *ctx,
775 iis328dq_ble_t *val)
776 {
777 iis328dq_ctrl_reg4_t ctrl_reg4;
778 int32_t ret;
779
780 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
781 (uint8_t *)&ctrl_reg4, 1);
782
783 switch (ctrl_reg4.ble)
784 {
785 case IIS328DQ_LSB_AT_LOW_ADD:
786 *val = IIS328DQ_LSB_AT_LOW_ADD;
787 break;
788
789 case IIS328DQ_MSB_AT_LOW_ADD:
790 *val = IIS328DQ_MSB_AT_LOW_ADD;
791 break;
792
793 default:
794 *val = IIS328DQ_LSB_AT_LOW_ADD;
795 break;
796 }
797
798 return ret;
799 }
800
801 /**
802 * @}
803 *
804 */
805
806 /**
807 * @defgroup IIS328DQ_Filters
808 * @brief This section group all the functions concerning the
809 * filters configuration.
810 * @{
811 *
812 */
813
814 /**
815 * @brief High pass filter cut-off frequency configuration.[set]
816 *
817 * @param ctx read / write interface definitions(ptr)
818 * @param val change the values of hpcf in reg CTRL_REG2
819 * @retval Interface status (MANDATORY: return 0 -> no Error)
820 *
821 */
iis328dq_hp_bandwidth_set(stmdev_ctx_t * ctx,iis328dq_hpcf_t val)822 int32_t iis328dq_hp_bandwidth_set(stmdev_ctx_t *ctx,
823 iis328dq_hpcf_t val)
824 {
825 iis328dq_ctrl_reg2_t ctrl_reg2;
826 int32_t ret;
827
828 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
829 (uint8_t *)&ctrl_reg2, 1);
830
831 if (ret == 0)
832 {
833 ctrl_reg2.hpcf = (uint8_t)val;
834 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
835 (uint8_t *)&ctrl_reg2, 1);
836 }
837
838 return ret;
839 }
840
841 /**
842 * @brief High pass filter cut-off frequency configuration.[get]
843 *
844 * @param ctx read / write interface definitions(ptr)
845 * @param val Get the values of hpcf in reg CTRL_REG2
846 * @retval Interface status (MANDATORY: return 0 -> no Error)
847 *
848 */
iis328dq_hp_bandwidth_get(stmdev_ctx_t * ctx,iis328dq_hpcf_t * val)849 int32_t iis328dq_hp_bandwidth_get(stmdev_ctx_t *ctx,
850 iis328dq_hpcf_t *val)
851 {
852 iis328dq_ctrl_reg2_t ctrl_reg2;
853 int32_t ret;
854
855 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
856 (uint8_t *)&ctrl_reg2, 1);
857
858 switch (ctrl_reg2.hpcf)
859 {
860 case IIS328DQ_CUT_OFF_8Hz:
861 *val = IIS328DQ_CUT_OFF_8Hz;
862 break;
863
864 case IIS328DQ_CUT_OFF_16Hz:
865 *val = IIS328DQ_CUT_OFF_16Hz;
866 break;
867
868 case IIS328DQ_CUT_OFF_32Hz:
869 *val = IIS328DQ_CUT_OFF_32Hz;
870 break;
871
872 case IIS328DQ_CUT_OFF_64Hz:
873 *val = IIS328DQ_CUT_OFF_64Hz;
874 break;
875
876 default:
877 *val = IIS328DQ_CUT_OFF_8Hz;
878 break;
879 }
880
881 return ret;
882 }
883
884 /**
885 * @brief Select High Pass filter path.[set]
886 *
887 * @param ctx read / write interface definitions(ptr)
888 * @param val change the values of hpen in reg CTRL_REG2
889 * @retval Interface status (MANDATORY: return 0 -> no Error)
890 *
891 */
iis328dq_hp_path_set(stmdev_ctx_t * ctx,iis328dq_hpen_t val)892 int32_t iis328dq_hp_path_set(stmdev_ctx_t *ctx, iis328dq_hpen_t val)
893 {
894 iis328dq_ctrl_reg2_t ctrl_reg2;
895 int32_t ret;
896
897 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
898 (uint8_t *)&ctrl_reg2, 1);
899
900 if (ret == 0)
901 {
902 ctrl_reg2.hpen = (uint8_t)val & 0x03U;
903 ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
904 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG2,
905 (uint8_t *)&ctrl_reg2, 1);
906 }
907
908 return ret;
909 }
910
911 /**
912 * @brief Select High Pass filter path.[get]
913 *
914 * @param ctx read / write interface definitions(ptr)
915 * @param val Get the values of hpen in reg CTRL_REG2
916 * @retval Interface status (MANDATORY: return 0 -> no Error)
917 *
918 */
iis328dq_hp_path_get(stmdev_ctx_t * ctx,iis328dq_hpen_t * val)919 int32_t iis328dq_hp_path_get(stmdev_ctx_t *ctx, iis328dq_hpen_t *val)
920 {
921 iis328dq_ctrl_reg2_t ctrl_reg2;
922 int32_t ret;
923
924 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG2,
925 (uint8_t *)&ctrl_reg2, 1);
926
927 switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
928 {
929 case IIS328DQ_HP_DISABLE:
930 *val = IIS328DQ_HP_DISABLE;
931 break;
932
933 case IIS328DQ_HP_ON_OUT:
934 *val = IIS328DQ_HP_ON_OUT;
935 break;
936
937 case IIS328DQ_HP_ON_INT1:
938 *val = IIS328DQ_HP_ON_INT1;
939 break;
940
941 case IIS328DQ_HP_ON_INT2:
942 *val = IIS328DQ_HP_ON_INT2;
943 break;
944
945 case IIS328DQ_HP_ON_INT1_INT2:
946 *val = IIS328DQ_HP_ON_INT1_INT2;
947 break;
948
949 case IIS328DQ_HP_ON_INT1_INT2_OUT:
950 *val = IIS328DQ_HP_ON_INT1_INT2_OUT;
951 break;
952
953 case IIS328DQ_HP_ON_INT2_OUT:
954 *val = IIS328DQ_HP_ON_INT2_OUT;
955 break;
956
957 case IIS328DQ_HP_ON_INT1_OUT:
958 *val = IIS328DQ_HP_ON_INT1_OUT;
959 break;
960
961 default:
962 *val = IIS328DQ_HP_DISABLE;
963 break;
964 }
965
966 return ret;
967 }
968
969 /**
970 * @brief Reading at this address zeroes instantaneously
971 * the content of the internal high pass-filter.
972 * If the high pass filter is enabled all three axes
973 * are instantaneously set to 0g. This allows to
974 * overcome the settling time of the high pass
975 * filter.[get]
976 *
977 * @param ctx read / write interface definitions(ptr)
978 * @retval Interface status (MANDATORY: return 0 -> no Error)
979 *
980 */
iis328dq_hp_reset_get(stmdev_ctx_t * ctx)981 int32_t iis328dq_hp_reset_get(stmdev_ctx_t *ctx)
982 {
983 uint8_t dummy;
984 int32_t ret;
985
986 ret = iis328dq_read_reg(ctx, IIS328DQ_HP_FILTER_RESET,
987 (uint8_t *)&dummy, 1);
988
989 return ret;
990 }
991
992 /**
993 * @brief Reference value for high-pass filter.[set]
994 *
995 * @param ctx read / write interface definitions(ptr)
996 * @param val change the values of ref in reg REFERENCE
997 * @retval Interface status (MANDATORY: return 0 -> no Error)
998 *
999 */
iis328dq_hp_reference_value_set(stmdev_ctx_t * ctx,uint8_t val)1000 int32_t iis328dq_hp_reference_value_set(stmdev_ctx_t *ctx,
1001 uint8_t val)
1002 {
1003 int32_t ret;
1004
1005 ret = iis328dq_write_reg(ctx, IIS328DQ_REFERENCE, (uint8_t *)&val, 1);
1006
1007 return ret;
1008 }
1009
1010 /**
1011 * @brief Reference value for high-pass filter.[get]
1012 *
1013 * @param ctx read / write interface definitions(ptr)
1014 * @param val change the values of ref in reg REFERENCE
1015 * @retval Interface status (MANDATORY: return 0 -> no Error)
1016 *
1017 */
iis328dq_hp_reference_value_get(stmdev_ctx_t * ctx,uint8_t * val)1018 int32_t iis328dq_hp_reference_value_get(stmdev_ctx_t *ctx,
1019 uint8_t *val)
1020 {
1021 int32_t ret;
1022
1023 ret = iis328dq_read_reg(ctx, IIS328DQ_REFERENCE, val, 1);
1024
1025 return ret;
1026 }
1027
1028 /**
1029 * @}
1030 *
1031 */
1032
1033 /**
1034 * @defgroup IIS328DQ_Serial_Interface
1035 * @brief This section groups all the functions concerning serial
1036 * interface management.
1037 * @{
1038 *
1039 */
1040
1041 /**
1042 * @brief SPI 3- or 4-wire interface.[set]
1043 *
1044 * @param ctx read / write interface definitions(ptr)
1045 * @param val change the values of sim in reg CTRL_REG4
1046 * @retval Interface status (MANDATORY: return 0 -> no Error)
1047 *
1048 */
iis328dq_spi_mode_set(stmdev_ctx_t * ctx,iis328dq_sim_t val)1049 int32_t iis328dq_spi_mode_set(stmdev_ctx_t *ctx, iis328dq_sim_t val)
1050 {
1051 iis328dq_ctrl_reg4_t ctrl_reg4;
1052 int32_t ret;
1053
1054 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
1055 (uint8_t *)&ctrl_reg4, 1);
1056
1057 if (ret == 0)
1058 {
1059 ctrl_reg4.sim = (uint8_t)val;
1060 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG4,
1061 (uint8_t *)&ctrl_reg4, 1);
1062 }
1063
1064 return ret;
1065 }
1066
1067 /**
1068 * @brief SPI 3- or 4-wire interface.[get]
1069 *
1070 * @param ctx read / write interface definitions(ptr)
1071 * @param val Get the values of sim in reg CTRL_REG4
1072 * @retval Interface status (MANDATORY: return 0 -> no Error)
1073 *
1074 */
iis328dq_spi_mode_get(stmdev_ctx_t * ctx,iis328dq_sim_t * val)1075 int32_t iis328dq_spi_mode_get(stmdev_ctx_t *ctx, iis328dq_sim_t *val)
1076 {
1077 iis328dq_ctrl_reg4_t ctrl_reg4;
1078 int32_t ret;
1079
1080 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG4,
1081 (uint8_t *)&ctrl_reg4, 1);
1082
1083 switch (ctrl_reg4.sim)
1084 {
1085 case IIS328DQ_SPI_4_WIRE:
1086 *val = IIS328DQ_SPI_4_WIRE;
1087 break;
1088
1089 case IIS328DQ_SPI_3_WIRE:
1090 *val = IIS328DQ_SPI_3_WIRE;
1091 break;
1092
1093 default:
1094 *val = IIS328DQ_SPI_4_WIRE;
1095 break;
1096 }
1097
1098 return ret;
1099 }
1100
1101 /**
1102 * @}
1103 *
1104 */
1105
1106 /**
1107 * @defgroup IIS328DQ_Interrupt_Pins
1108 * @brief This section groups all the functions that manage
1109 * interrupt pins.
1110 * @{
1111 *
1112 */
1113
1114 /**
1115 * @brief Data signal on INT 1 pad control bits.[set]
1116 *
1117 * @param ctx read / write interface definitions(ptr)
1118 * @param val change the values of i1_cfg in reg CTRL_REG3
1119 * @retval Interface status (MANDATORY: return 0 -> no Error)
1120 *
1121 */
iis328dq_pin_int1_route_set(stmdev_ctx_t * ctx,iis328dq_i1_cfg_t val)1122 int32_t iis328dq_pin_int1_route_set(stmdev_ctx_t *ctx,
1123 iis328dq_i1_cfg_t val)
1124 {
1125 iis328dq_ctrl_reg3_t ctrl_reg3;
1126 int32_t ret;
1127
1128 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1129 (uint8_t *)&ctrl_reg3, 1);
1130
1131 if (ret == 0)
1132 {
1133 ctrl_reg3.i1_cfg = (uint8_t)val;
1134 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
1135 (uint8_t *)&ctrl_reg3, 1);
1136 }
1137
1138 return ret;
1139 }
1140
1141 /**
1142 * @brief Data signal on INT 1 pad control bits.[get]
1143 *
1144 * @param ctx read / write interface definitions(ptr)
1145 * @param val Get the values of i1_cfg in reg CTRL_REG3
1146 * @retval Interface status (MANDATORY: return 0 -> no Error)
1147 *
1148 */
iis328dq_pin_int1_route_get(stmdev_ctx_t * ctx,iis328dq_i1_cfg_t * val)1149 int32_t iis328dq_pin_int1_route_get(stmdev_ctx_t *ctx,
1150 iis328dq_i1_cfg_t *val)
1151 {
1152 iis328dq_ctrl_reg3_t ctrl_reg3;
1153 int32_t ret;
1154
1155 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1156 (uint8_t *)&ctrl_reg3, 1);
1157
1158 switch (ctrl_reg3.i1_cfg)
1159 {
1160 case IIS328DQ_PAD1_INT1_SRC:
1161 *val = IIS328DQ_PAD1_INT1_SRC;
1162 break;
1163
1164 case IIS328DQ_PAD1_INT1_OR_INT2_SRC:
1165 *val = IIS328DQ_PAD1_INT1_OR_INT2_SRC;
1166 break;
1167
1168 case IIS328DQ_PAD1_DRDY:
1169 *val = IIS328DQ_PAD1_DRDY;
1170 break;
1171
1172 case IIS328DQ_PAD1_BOOT:
1173 *val = IIS328DQ_PAD1_BOOT;
1174 break;
1175
1176 default:
1177 *val = IIS328DQ_PAD1_INT1_SRC;
1178 break;
1179 }
1180
1181 return ret;
1182 }
1183
1184 /**
1185 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1186 * register cleared by reading INT1_SRC register.[set]
1187 *
1188 * @param ctx read / write interface definitions(ptr)
1189 * @param val change the values of lir1 in reg CTRL_REG3
1190 * @retval Interface status (MANDATORY: return 0 -> no Error)
1191 *
1192 */
iis328dq_int1_notification_set(stmdev_ctx_t * ctx,iis328dq_lir1_t val)1193 int32_t iis328dq_int1_notification_set(stmdev_ctx_t *ctx,
1194 iis328dq_lir1_t val)
1195 {
1196 iis328dq_ctrl_reg3_t ctrl_reg3;
1197 int32_t ret;
1198
1199 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1200 (uint8_t *)&ctrl_reg3, 1);
1201
1202 if (ret == 0)
1203 {
1204 ctrl_reg3.lir1 = (uint8_t)val;
1205 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
1206 (uint8_t *)&ctrl_reg3, 1);
1207 }
1208
1209 return ret;
1210 }
1211
1212 /**
1213 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1214 * register cleared by reading INT1_SRC register.[get]
1215 *
1216 * @param ctx read / write interface definitions(ptr)
1217 * @param val Get the values of lir1 in reg CTRL_REG3
1218 * @retval Interface status (MANDATORY: return 0 -> no Error)
1219 *
1220 */
iis328dq_int1_notification_get(stmdev_ctx_t * ctx,iis328dq_lir1_t * val)1221 int32_t iis328dq_int1_notification_get(stmdev_ctx_t *ctx,
1222 iis328dq_lir1_t *val)
1223 {
1224 iis328dq_ctrl_reg3_t ctrl_reg3;
1225 int32_t ret;
1226
1227 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1228 (uint8_t *)&ctrl_reg3, 1);
1229
1230 switch (ctrl_reg3.lir1)
1231 {
1232 case IIS328DQ_INT1_PULSED:
1233 *val = IIS328DQ_INT1_PULSED;
1234 break;
1235
1236 case IIS328DQ_INT1_LATCHED:
1237 *val = IIS328DQ_INT1_LATCHED;
1238 break;
1239
1240 default:
1241 *val = IIS328DQ_INT1_PULSED;
1242 break;
1243 }
1244
1245 return ret;
1246 }
1247
1248 /**
1249 * @brief Data signal on INT 2 pad control bits.[set]
1250 *
1251 * @param ctx read / write interface definitions(ptr)
1252 * @param val change the values of i2_cfg in reg CTRL_REG3
1253 * @retval Interface status (MANDATORY: return 0 -> no Error)
1254 *
1255 */
iis328dq_pin_int2_route_set(stmdev_ctx_t * ctx,iis328dq_i2_cfg_t val)1256 int32_t iis328dq_pin_int2_route_set(stmdev_ctx_t *ctx,
1257 iis328dq_i2_cfg_t val)
1258 {
1259 iis328dq_ctrl_reg3_t ctrl_reg3;
1260 int32_t ret;
1261
1262 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1263 (uint8_t *)&ctrl_reg3, 1);
1264
1265 if (ret == 0)
1266 {
1267 ctrl_reg3.i2_cfg = (uint8_t)val;
1268 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
1269 (uint8_t *)&ctrl_reg3, 1);
1270 }
1271
1272 return ret;
1273 }
1274
1275 /**
1276 * @brief Data signal on INT 2 pad control bits.[get]
1277 *
1278 * @param ctx read / write interface definitions(ptr)
1279 * @param val Get the values of i2_cfg in reg CTRL_REG3
1280 * @retval Interface status (MANDATORY: return 0 -> no Error)
1281 *
1282 */
iis328dq_pin_int2_route_get(stmdev_ctx_t * ctx,iis328dq_i2_cfg_t * val)1283 int32_t iis328dq_pin_int2_route_get(stmdev_ctx_t *ctx,
1284 iis328dq_i2_cfg_t *val)
1285 {
1286 iis328dq_ctrl_reg3_t ctrl_reg3;
1287 int32_t ret;
1288
1289 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1290 (uint8_t *)&ctrl_reg3, 1);
1291
1292 switch (ctrl_reg3.i2_cfg)
1293 {
1294 case IIS328DQ_PAD2_INT2_SRC:
1295 *val = IIS328DQ_PAD2_INT2_SRC;
1296 break;
1297
1298 case IIS328DQ_PAD2_INT1_OR_INT2_SRC:
1299 *val = IIS328DQ_PAD2_INT1_OR_INT2_SRC;
1300 break;
1301
1302 case IIS328DQ_PAD2_DRDY:
1303 *val = IIS328DQ_PAD2_DRDY;
1304 break;
1305
1306 case IIS328DQ_PAD2_BOOT:
1307 *val = IIS328DQ_PAD2_BOOT;
1308 break;
1309
1310 default:
1311 *val = IIS328DQ_PAD2_INT2_SRC;
1312 break;
1313 }
1314
1315 return ret;
1316 }
1317
1318 /**
1319 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1320 * register cleared by reading INT2_SRC itself.[set]
1321 *
1322 * @param ctx read / write interface definitions(ptr)
1323 * @param val change the values of lir2 in reg CTRL_REG3
1324 * @retval Interface status (MANDATORY: return 0 -> no Error)
1325 *
1326 */
iis328dq_int2_notification_set(stmdev_ctx_t * ctx,iis328dq_lir2_t val)1327 int32_t iis328dq_int2_notification_set(stmdev_ctx_t *ctx,
1328 iis328dq_lir2_t val)
1329 {
1330 iis328dq_ctrl_reg3_t ctrl_reg3;
1331 int32_t ret;
1332
1333 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1334 (uint8_t *)&ctrl_reg3, 1);
1335
1336 if (ret == 0)
1337 {
1338 ctrl_reg3.lir2 = (uint8_t)val;
1339 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
1340 (uint8_t *)&ctrl_reg3, 1);
1341 }
1342
1343 return ret;
1344 }
1345
1346 /**
1347 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1348 * register cleared by reading INT2_SRC itself.[get]
1349 *
1350 * @param ctx read / write interface definitions(ptr)
1351 * @param val Get the values of lir2 in reg CTRL_REG3
1352 * @retval Interface status (MANDATORY: return 0 -> no Error)
1353 *
1354 */
iis328dq_int2_notification_get(stmdev_ctx_t * ctx,iis328dq_lir2_t * val)1355 int32_t iis328dq_int2_notification_get(stmdev_ctx_t *ctx,
1356 iis328dq_lir2_t *val)
1357 {
1358 iis328dq_ctrl_reg3_t ctrl_reg3;
1359 int32_t ret;
1360
1361 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1362 (uint8_t *)&ctrl_reg3, 1);
1363
1364 switch (ctrl_reg3.lir2)
1365 {
1366 case IIS328DQ_INT2_PULSED:
1367 *val = IIS328DQ_INT2_PULSED;
1368 break;
1369
1370 case IIS328DQ_INT2_LATCHED:
1371 *val = IIS328DQ_INT2_LATCHED;
1372 break;
1373
1374 default:
1375 *val = IIS328DQ_INT2_PULSED;
1376 break;
1377 }
1378
1379 return ret;
1380 }
1381
1382 /**
1383 * @brief Push-pull/open drain selection on interrupt pads.[set]
1384 *
1385 * @param ctx read / write interface definitions(ptr)
1386 * @param val change the values of pp_od in reg CTRL_REG3
1387 * @retval Interface status (MANDATORY: return 0 -> no Error)
1388 *
1389 */
iis328dq_pin_mode_set(stmdev_ctx_t * ctx,iis328dq_pp_od_t val)1390 int32_t iis328dq_pin_mode_set(stmdev_ctx_t *ctx, iis328dq_pp_od_t val)
1391 {
1392 iis328dq_ctrl_reg3_t ctrl_reg3;
1393 int32_t ret;
1394
1395 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1396 (uint8_t *)&ctrl_reg3, 1);
1397
1398 if (ret == 0)
1399 {
1400 ctrl_reg3.pp_od = (uint8_t)val;
1401 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
1402 (uint8_t *)&ctrl_reg3, 1);
1403 }
1404
1405 return ret;
1406 }
1407
1408 /**
1409 * @brief Push-pull/open drain selection on interrupt pads.[get]
1410 *
1411 * @param ctx read / write interface definitions(ptr)
1412 * @param val Get the values of pp_od in reg CTRL_REG3
1413 * @retval Interface status (MANDATORY: return 0 -> no Error)
1414 *
1415 */
iis328dq_pin_mode_get(stmdev_ctx_t * ctx,iis328dq_pp_od_t * val)1416 int32_t iis328dq_pin_mode_get(stmdev_ctx_t *ctx,
1417 iis328dq_pp_od_t *val)
1418 {
1419 iis328dq_ctrl_reg3_t ctrl_reg3;
1420 int32_t ret;
1421
1422 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1423 (uint8_t *)&ctrl_reg3, 1);
1424
1425 switch (ctrl_reg3.pp_od)
1426 {
1427 case IIS328DQ_PUSH_PULL:
1428 *val = IIS328DQ_PUSH_PULL;
1429 break;
1430
1431 case IIS328DQ_OPEN_DRAIN:
1432 *val = IIS328DQ_OPEN_DRAIN;
1433 break;
1434
1435 default:
1436 *val = IIS328DQ_PUSH_PULL;
1437 break;
1438 }
1439
1440 return ret;
1441 }
1442
1443 /**
1444 * @brief Interrupt active-high/low.[set]
1445 *
1446 * @param ctx read / write interface definitions(ptr)
1447 * @param val change the values of ihl in reg CTRL_REG3
1448 * @retval Interface status (MANDATORY: return 0 -> no Error)
1449 *
1450 */
iis328dq_pin_polarity_set(stmdev_ctx_t * ctx,iis328dq_ihl_t val)1451 int32_t iis328dq_pin_polarity_set(stmdev_ctx_t *ctx,
1452 iis328dq_ihl_t val)
1453 {
1454 iis328dq_ctrl_reg3_t ctrl_reg3;
1455 int32_t ret;
1456
1457 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1458 (uint8_t *)&ctrl_reg3, 1);
1459
1460 if (ret == 0)
1461 {
1462 ctrl_reg3.ihl = (uint8_t)val;
1463 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG3,
1464 (uint8_t *)&ctrl_reg3, 1);
1465 }
1466
1467 return ret;
1468 }
1469
1470 /**
1471 * @brief Interrupt active-high/low.[get]
1472 *
1473 * @param ctx read / write interface definitions(ptr)
1474 * @param val Get the values of ihl in reg CTRL_REG3
1475 * @retval Interface status (MANDATORY: return 0 -> no Error)
1476 *
1477 */
iis328dq_pin_polarity_get(stmdev_ctx_t * ctx,iis328dq_ihl_t * val)1478 int32_t iis328dq_pin_polarity_get(stmdev_ctx_t *ctx,
1479 iis328dq_ihl_t *val)
1480 {
1481 iis328dq_ctrl_reg3_t ctrl_reg3;
1482 int32_t ret;
1483
1484 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG3,
1485 (uint8_t *)&ctrl_reg3, 1);
1486
1487 switch (ctrl_reg3.ihl)
1488 {
1489 case IIS328DQ_ACTIVE_HIGH:
1490 *val = IIS328DQ_ACTIVE_HIGH;
1491 break;
1492
1493 case IIS328DQ_ACTIVE_LOW:
1494 *val = IIS328DQ_ACTIVE_LOW;
1495 break;
1496
1497 default:
1498 *val = IIS328DQ_ACTIVE_HIGH;
1499 break;
1500 }
1501
1502 return ret;
1503 }
1504
1505 /**
1506 * @}
1507 *
1508 */
1509
1510 /**
1511 * @defgroup IIS328DQ_interrupt_on_threshold
1512 * @brief This section groups all the functions that manage
1513 * the interrupt on threshold event generation.
1514 * @{
1515 *
1516 */
1517
1518 /**
1519 * @brief Configure the interrupt 1 threshold sign.[set]
1520 *
1521 * @param ctx read / write interface definitions(ptr)
1522 * @param val enable sign and axis for interrupt on threshold
1523 * @retval Interface status (MANDATORY: return 0 -> no Error)
1524 *
1525 */
iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t * ctx,int1_on_th_conf_t val)1526 int32_t iis328dq_int1_on_threshold_conf_set(stmdev_ctx_t *ctx,
1527 int1_on_th_conf_t val)
1528 {
1529 iis328dq_int1_cfg_t int1_cfg;
1530 int32_t ret;
1531
1532 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1533
1534 if (ret == 0)
1535 {
1536 int1_cfg.xlie = val.int1_xlie;
1537 int1_cfg.xhie = val.int1_xhie;
1538 int1_cfg.ylie = val.int1_ylie;
1539 int1_cfg.yhie = val.int1_yhie;
1540 int1_cfg.zlie = val.int1_zlie;
1541 int1_cfg.zhie = val.int1_zhie;
1542 ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_CFG,
1543 (uint8_t *)&int1_cfg, 1);
1544 }
1545
1546 return ret;
1547 }
1548
1549 /**
1550 * @brief Configure the interrupt 1 threshold sign.[get]
1551 *
1552 * @param ctx read / write interface definitions(ptr)
1553 * @param val enable sign and axis for interrupt on threshold
1554 * @retval Interface status (MANDATORY: return 0 -> no Error)
1555 *
1556 */
iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t * ctx,int1_on_th_conf_t * val)1557 int32_t iis328dq_int1_on_threshold_conf_get(stmdev_ctx_t *ctx,
1558 int1_on_th_conf_t *val)
1559 {
1560 iis328dq_int1_cfg_t int1_cfg;
1561 int32_t ret;
1562
1563 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1564 val->int1_xlie = int1_cfg.xlie;
1565 val->int1_xhie = int1_cfg.xhie;
1566 val->int1_ylie = int1_cfg.ylie;
1567 val->int1_yhie = int1_cfg.yhie;
1568 val->int1_zlie = int1_cfg.zlie;
1569 val->int1_zhie = int1_cfg.zhie;
1570
1571 return ret;
1572 }
1573
1574 /**
1575 * @brief AND/OR combination of Interrupt 1 events.[set]
1576 *
1577 * @param ctx read / write interface definitions(ptr)
1578 * @param val change the values of aoi in reg INT1_CFG
1579 * @retval Interface status (MANDATORY: return 0 -> no Error)
1580 *
1581 */
iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t * ctx,iis328dq_int1_aoi_t val)1582 int32_t iis328dq_int1_on_threshold_mode_set(stmdev_ctx_t *ctx,
1583 iis328dq_int1_aoi_t val)
1584 {
1585 iis328dq_int1_cfg_t int1_cfg;
1586 int32_t ret;
1587
1588 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1589
1590 if (ret == 0)
1591 {
1592 int1_cfg.aoi = (uint8_t) val;
1593 ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_CFG,
1594 (uint8_t *)&int1_cfg, 1);
1595 }
1596
1597 return ret;
1598 }
1599
1600 /**
1601 * @brief AND/OR combination of Interrupt 1 events.[get]
1602 *
1603 * @param ctx read / write interface definitions(ptr)
1604 * @param val Get the values of aoi in reg INT1_CFG
1605 * @retval Interface status (MANDATORY: return 0 -> no Error)
1606 *
1607 */
iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t * ctx,iis328dq_int1_aoi_t * val)1608 int32_t iis328dq_int1_on_threshold_mode_get(stmdev_ctx_t *ctx,
1609 iis328dq_int1_aoi_t *val)
1610 {
1611 iis328dq_int1_cfg_t int1_cfg;
1612 int32_t ret;
1613
1614 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
1615
1616 switch (int1_cfg.aoi)
1617 {
1618 case IIS328DQ_INT1_ON_THRESHOLD_OR:
1619 *val = IIS328DQ_INT1_ON_THRESHOLD_OR;
1620 break;
1621
1622 case IIS328DQ_INT1_ON_THRESHOLD_AND:
1623 *val = IIS328DQ_INT1_ON_THRESHOLD_AND;
1624 break;
1625
1626 default:
1627 *val = IIS328DQ_INT1_ON_THRESHOLD_OR;
1628 break;
1629 }
1630
1631 return ret;
1632 }
1633
1634 /**
1635 * @brief Interrupt generator 1 on threshold source register.[get]
1636 *
1637 * @param ctx read / write interface definitions(ptr)
1638 * @param val registers INT1_SRC
1639 * @retval Interface status (MANDATORY: return 0 -> no Error)
1640 *
1641 */
iis328dq_int1_src_get(stmdev_ctx_t * ctx,iis328dq_int1_src_t * val)1642 int32_t iis328dq_int1_src_get(stmdev_ctx_t *ctx,
1643 iis328dq_int1_src_t *val)
1644 {
1645 int32_t ret;
1646
1647 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_SRC, (uint8_t *) val, 1);
1648
1649 return ret;
1650 }
1651
1652 /**
1653 * @brief Interrupt 1 threshold.[set]
1654 *
1655 * @param ctx read / write interface definitions(ptr)
1656 * @param val change the values of ths in reg INT1_THS
1657 * @retval Interface status (MANDATORY: return 0 -> no Error)
1658 *
1659 */
iis328dq_int1_treshold_set(stmdev_ctx_t * ctx,uint8_t val)1660 int32_t iis328dq_int1_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
1661 {
1662 iis328dq_int1_ths_t int1_ths;
1663 int32_t ret;
1664
1665 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
1666
1667 if (ret == 0)
1668 {
1669 int1_ths.ths = val;
1670 ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_THS,
1671 (uint8_t *)&int1_ths, 1);
1672 }
1673
1674 return ret;
1675 }
1676
1677 /**
1678 * @brief Interrupt 1 threshold.[get]
1679 *
1680 * @param ctx read / write interface definitions(ptr)
1681 * @param val change the values of ths in reg INT1_THS
1682 * @retval Interface status (MANDATORY: return 0 -> no Error)
1683 *
1684 */
iis328dq_int1_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)1685 int32_t iis328dq_int1_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1686 {
1687 iis328dq_int1_ths_t int1_ths;
1688 int32_t ret;
1689
1690 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
1691 *val = int1_ths.ths;
1692
1693 return ret;
1694 }
1695
1696 /**
1697 * @brief Duration value for interrupt 1 generator.[set]
1698 *
1699 * @param ctx read / write interface definitions(ptr)
1700 * @param val change the values of d in reg INT1_DURATION
1701 * @retval Interface status (MANDATORY: return 0 -> no Error)
1702 *
1703 */
iis328dq_int1_dur_set(stmdev_ctx_t * ctx,uint8_t val)1704 int32_t iis328dq_int1_dur_set(stmdev_ctx_t *ctx, uint8_t val)
1705 {
1706 iis328dq_int1_duration_t int1_duration;
1707 int32_t ret;
1708
1709 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_DURATION,
1710 (uint8_t *)&int1_duration, 1);
1711
1712 if (ret == 0)
1713 {
1714 int1_duration.d = val;
1715 ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_DURATION,
1716 (uint8_t *)&int1_duration, 1);
1717 }
1718
1719 return ret;
1720 }
1721
1722 /**
1723 * @brief Duration value for interrupt 1 generator.[get]
1724 *
1725 * @param ctx read / write interface definitions(ptr)
1726 * @param val change the values of d in reg INT1_DURATION
1727 * @retval Interface status (MANDATORY: return 0 -> no Error)
1728 *
1729 */
iis328dq_int1_dur_get(stmdev_ctx_t * ctx,uint8_t * val)1730 int32_t iis328dq_int1_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
1731 {
1732 iis328dq_int1_duration_t int1_duration;
1733 int32_t ret;
1734
1735 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_DURATION,
1736 (uint8_t *)&int1_duration, 1);
1737 *val = int1_duration.d;
1738
1739 return ret;
1740 }
1741
1742 /**
1743 * @brief Configure the interrupt 2 threshold sign.[set]
1744 *
1745 * @param ctx read / write interface definitions(ptr)
1746 * @param val enable sign and axis for interrupt on threshold
1747 * @retval Interface status (MANDATORY: return 0 -> no Error)
1748 *
1749 */
iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t * ctx,int2_on_th_conf_t val)1750 int32_t iis328dq_int2_on_threshold_conf_set(stmdev_ctx_t *ctx,
1751 int2_on_th_conf_t val)
1752 {
1753 iis328dq_int2_cfg_t int2_cfg;
1754 int32_t ret;
1755
1756 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG,
1757 (uint8_t *)&int2_cfg, 1);
1758
1759 if (ret == 0)
1760 {
1761 int2_cfg.xlie = val.int2_xlie;
1762 int2_cfg.xhie = val.int2_xhie;
1763 int2_cfg.ylie = val.int2_ylie;
1764 int2_cfg.yhie = val.int2_yhie;
1765 int2_cfg.zlie = val.int2_zlie;
1766 int2_cfg.zhie = val.int2_zhie;
1767 ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_CFG,
1768 (uint8_t *)&int2_cfg, 1);
1769 }
1770
1771 return ret;
1772 }
1773
1774 /**
1775 * @brief Configure the interrupt 2 threshold sign.[get]
1776 *
1777 * @param ctx read / write interface definitions(ptr)
1778 * @param val enable sign and axis for interrupt on threshold
1779 * @retval Interface status (MANDATORY: return 0 -> no Error)
1780 *
1781 */
iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t * ctx,int2_on_th_conf_t * val)1782 int32_t iis328dq_int2_on_threshold_conf_get(stmdev_ctx_t *ctx,
1783 int2_on_th_conf_t *val)
1784 {
1785 iis328dq_int2_cfg_t int2_cfg;
1786 int32_t ret;
1787
1788 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
1789 val->int2_xlie = int2_cfg.xlie;
1790 val->int2_xhie = int2_cfg.xhie;
1791 val->int2_ylie = int2_cfg.ylie;
1792 val->int2_yhie = int2_cfg.yhie;
1793 val->int2_zlie = int2_cfg.zlie;
1794 val->int2_zhie = int2_cfg.zhie;
1795
1796 return ret;
1797 }
1798
1799 /**
1800 * @brief AND/OR combination of Interrupt 2 events.[set]
1801 *
1802 * @param ctx read / write interface definitions(ptr)
1803 * @param val change the values of aoi in reg INT2_CFG
1804 * @retval Interface status (MANDATORY: return 0 -> no Error)
1805 *
1806 */
iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t * ctx,iis328dq_int2_aoi_t val)1807 int32_t iis328dq_int2_on_threshold_mode_set(stmdev_ctx_t *ctx,
1808 iis328dq_int2_aoi_t val)
1809 {
1810 iis328dq_int2_cfg_t int2_cfg;
1811 int32_t ret;
1812
1813 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
1814
1815 if (ret == 0)
1816 {
1817 int2_cfg.aoi = (uint8_t) val;
1818 ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_CFG,
1819 (uint8_t *)&int2_cfg, 1);
1820 }
1821
1822 return ret;
1823 }
1824
1825 /**
1826 * @brief AND/OR combination of Interrupt 2 events.[get]
1827 *
1828 * @param ctx read / write interface definitions(ptr)
1829 * @param val Get the values of aoi in reg INT2_CFG
1830 * @retval Interface status (MANDATORY: return 0 -> no Error)
1831 *
1832 */
iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t * ctx,iis328dq_int2_aoi_t * val)1833 int32_t iis328dq_int2_on_threshold_mode_get(stmdev_ctx_t *ctx,
1834 iis328dq_int2_aoi_t *val)
1835 {
1836 iis328dq_int2_cfg_t int2_cfg;
1837 int32_t ret;
1838
1839 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
1840
1841 switch (int2_cfg.aoi)
1842 {
1843 case IIS328DQ_INT2_ON_THRESHOLD_OR:
1844 *val = IIS328DQ_INT2_ON_THRESHOLD_OR;
1845 break;
1846
1847 case IIS328DQ_INT2_ON_THRESHOLD_AND:
1848 *val = IIS328DQ_INT2_ON_THRESHOLD_AND;
1849 break;
1850
1851 default:
1852 *val = IIS328DQ_INT2_ON_THRESHOLD_OR;
1853 break;
1854 }
1855
1856 return ret;
1857 }
1858
1859 /**
1860 * @brief Interrupt generator 1 on threshold source register.[get]
1861 *
1862 * @param ctx read / write interface definitions(ptr)
1863 * @param val registers INT2_SRC
1864 * @retval Interface status (MANDATORY: return 0 -> no Error)
1865 *
1866 */
iis328dq_int2_src_get(stmdev_ctx_t * ctx,iis328dq_int2_src_t * val)1867 int32_t iis328dq_int2_src_get(stmdev_ctx_t *ctx,
1868 iis328dq_int2_src_t *val)
1869 {
1870 int32_t ret;
1871
1872 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_SRC, (uint8_t *) val, 1);
1873
1874 return ret;
1875 }
1876
1877 /**
1878 * @brief Interrupt 2 threshold.[set]
1879 *
1880 * @param ctx read / write interface definitions(ptr)
1881 * @param val change the values of ths in reg INT2_THS
1882 * @retval Interface status (MANDATORY: return 0 -> no Error)
1883 *
1884 */
iis328dq_int2_treshold_set(stmdev_ctx_t * ctx,uint8_t val)1885 int32_t iis328dq_int2_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
1886 {
1887 iis328dq_int2_ths_t int2_ths;
1888 int32_t ret;
1889
1890 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
1891
1892 if (ret == 0)
1893 {
1894 int2_ths.ths = val;
1895 ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_THS,
1896 (uint8_t *)&int2_ths, 1);
1897 }
1898
1899 return ret;
1900 }
1901
1902 /**
1903 * @brief Interrupt 2 threshold.[get]
1904 *
1905 * @param ctx read / write interface definitions(ptr)
1906 * @param val change the values of ths in reg INT2_THS
1907 * @retval Interface status (MANDATORY: return 0 -> no Error)
1908 *
1909 */
iis328dq_int2_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)1910 int32_t iis328dq_int2_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1911 {
1912 iis328dq_int2_ths_t int2_ths;
1913 int32_t ret;
1914
1915 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
1916 *val = int2_ths.ths;
1917
1918 return ret;
1919 }
1920
1921 /**
1922 * @brief Duration value for interrupt 2 generator.[set]
1923 *
1924 * @param ctx read / write interface definitions(ptr)
1925 * @param val change the values of d in reg INT2_DURATION
1926 * @retval Interface status (MANDATORY: return 0 -> no Error)
1927 *
1928 */
iis328dq_int2_dur_set(stmdev_ctx_t * ctx,uint8_t val)1929 int32_t iis328dq_int2_dur_set(stmdev_ctx_t *ctx, uint8_t val)
1930 {
1931 iis328dq_int2_duration_t int2_duration;
1932 int32_t ret;
1933
1934 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_DURATION,
1935 (uint8_t *)&int2_duration, 1);
1936
1937 if (ret == 0)
1938 {
1939 int2_duration.d = val;
1940 ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_DURATION,
1941 (uint8_t *)&int2_duration, 1);
1942 }
1943
1944 return ret;
1945 }
1946
1947 /**
1948 * @brief Duration value for interrupt 2 generator.[get]
1949 *
1950 * @param ctx read / write interface definitions(ptr)
1951 * @param val change the values of d in reg INT2_DURATION
1952 * @retval Interface status (MANDATORY: return 0 -> no Error)
1953 *
1954 */
iis328dq_int2_dur_get(stmdev_ctx_t * ctx,uint8_t * val)1955 int32_t iis328dq_int2_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
1956 {
1957 iis328dq_int2_duration_t int2_duration;
1958 int32_t ret;
1959
1960 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_DURATION,
1961 (uint8_t *)&int2_duration, 1);
1962 *val = int2_duration.d;
1963
1964 return ret;
1965 }
1966
1967 /**
1968 * @}
1969 *
1970 */
1971
1972 /**
1973 * @defgroup IIS328DQ_Wake_Up_Event
1974 * @brief This section groups all the functions that manage the
1975 * Wake Up event generation.
1976 * @{
1977 *
1978 */
1979
1980 /**
1981 * @brief Turn-on mode selection for sleep to wake function.[set]
1982 *
1983 * @param ctx read / write interface definitions(ptr)
1984 * @param val change the values of turnon in reg CTRL_REG5
1985 * @retval Interface status (MANDATORY: return 0 -> no Error)
1986 *
1987 */
iis328dq_wkup_to_sleep_set(stmdev_ctx_t * ctx,uint8_t val)1988 int32_t iis328dq_wkup_to_sleep_set(stmdev_ctx_t *ctx, uint8_t val)
1989 {
1990 iis328dq_ctrl_reg5_t ctrl_reg5;
1991 int32_t ret;
1992
1993 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG5,
1994 (uint8_t *)&ctrl_reg5, 1);
1995
1996 if (ret == 0)
1997 {
1998 ctrl_reg5.turnon = val;
1999 ret = iis328dq_write_reg(ctx, IIS328DQ_CTRL_REG5,
2000 (uint8_t *)&ctrl_reg5, 1);
2001 }
2002
2003 return ret;
2004 }
2005
2006 /**
2007 * @brief Turn-on mode selection for sleep to wake function.[get]
2008 *
2009 * @param ctx read / write interface definitions(ptr)
2010 * @param val change the values of turnon in reg CTRL_REG5
2011 * @retval Interface status (MANDATORY: return 0 -> no Error)
2012 *
2013 */
iis328dq_wkup_to_sleep_get(stmdev_ctx_t * ctx,uint8_t * val)2014 int32_t iis328dq_wkup_to_sleep_get(stmdev_ctx_t *ctx, uint8_t *val)
2015 {
2016 iis328dq_ctrl_reg5_t ctrl_reg5;
2017 int32_t ret;
2018
2019 ret = iis328dq_read_reg(ctx, IIS328DQ_CTRL_REG5,
2020 (uint8_t *)&ctrl_reg5, 1);
2021 *val = ctrl_reg5.turnon;
2022
2023 return ret;
2024 }
2025
2026 /**
2027 * @}
2028 *
2029 */
2030
2031 /**
2032 * @defgroup IIS328DQ_Six_Position_Detection
2033 * @brief This section groups all the functions concerning six
2034 * position detection (6D).
2035 * @{
2036 *
2037 */
2038
2039 /**
2040 * @brief Configure the 6d on interrupt 1 generator.[set]
2041 *
2042 * @param ctx read / write interface definitions(ptr)
2043 * @param val change the values of 6d in reg INT1_CFG
2044 * @retval Interface status (MANDATORY: return 0 -> no Error)
2045 *
2046 */
iis328dq_int1_6d_mode_set(stmdev_ctx_t * ctx,iis328dq_int1_6d_t val)2047 int32_t iis328dq_int1_6d_mode_set(stmdev_ctx_t *ctx,
2048 iis328dq_int1_6d_t val)
2049 {
2050 iis328dq_int1_cfg_t int1_cfg;
2051 int32_t ret;
2052
2053 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
2054
2055 if (ret == 0)
2056 {
2057 int1_cfg._6d = (uint8_t)val & 0x01U;
2058 int1_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2059 ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
2060 }
2061
2062 return ret;
2063 }
2064
2065 /**
2066 * @brief Configure the 6d on interrupt 1 generator.[get]
2067 *
2068 * @param ctx read / write interface definitions(ptr)
2069 * @param val Get the values of 6d in reg INT1_CFG
2070 * @retval Interface status (MANDATORY: return 0 -> no Error)
2071 *
2072 */
iis328dq_int1_6d_mode_get(stmdev_ctx_t * ctx,iis328dq_int1_6d_t * val)2073 int32_t iis328dq_int1_6d_mode_get(stmdev_ctx_t *ctx,
2074 iis328dq_int1_6d_t *val)
2075 {
2076 iis328dq_int1_cfg_t int1_cfg;
2077 int32_t ret;
2078
2079 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_CFG, (uint8_t *)&int1_cfg, 1);
2080
2081 switch ((int1_cfg.aoi << 1) + int1_cfg._6d)
2082 {
2083 case IIS328DQ_6D_INT1_DISABLE:
2084 *val = IIS328DQ_6D_INT1_DISABLE;
2085 break;
2086
2087 case IIS328DQ_6D_INT1_MOVEMENT:
2088 *val = IIS328DQ_6D_INT1_MOVEMENT;
2089 break;
2090
2091 case IIS328DQ_6D_INT1_POSITION:
2092 *val = IIS328DQ_6D_INT1_POSITION;
2093 break;
2094
2095 default:
2096 *val = IIS328DQ_6D_INT1_DISABLE;
2097 break;
2098 }
2099
2100 return ret;
2101 }
2102
2103 /**
2104 * @brief 6D on interrupt generator 1 source register.[get]
2105 *
2106 * @param ctx read / write interface definitions(ptr)
2107 * @param val registers INT1_SRC
2108 * @retval Interface status (MANDATORY: return 0 -> no Error)
2109 *
2110 */
iis328dq_int1_6d_src_get(stmdev_ctx_t * ctx,iis328dq_int1_src_t * val)2111 int32_t iis328dq_int1_6d_src_get(stmdev_ctx_t *ctx,
2112 iis328dq_int1_src_t *val)
2113 {
2114 int32_t ret;
2115
2116 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_SRC, (uint8_t *) val, 1);
2117
2118 return ret;
2119 }
2120
2121 /**
2122 * @brief Interrupt 1 threshold.[set]
2123 *
2124 * @param ctx read / write interface definitions(ptr)
2125 * @param val change the values of ths in reg INT1_THS
2126 * @retval Interface status (MANDATORY: return 0 -> no Error)
2127 *
2128 */
iis328dq_int1_6d_treshold_set(stmdev_ctx_t * ctx,uint8_t val)2129 int32_t iis328dq_int1_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
2130 {
2131 iis328dq_int1_ths_t int1_ths;
2132 int32_t ret;
2133
2134 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
2135
2136 if (ret == 0)
2137 {
2138 int1_ths.ths = val;
2139 ret = iis328dq_write_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
2140 }
2141
2142 return ret;
2143 }
2144
2145 /**
2146 * @brief Interrupt 1 threshold.[get]
2147 *
2148 * @param ctx read / write interface definitions(ptr)
2149 * @param val change the values of ths in reg INT1_THS
2150 * @retval Interface status (MANDATORY: return 0 -> no Error)
2151 *
2152 */
iis328dq_int1_6d_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)2153 int32_t iis328dq_int1_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2154 {
2155 iis328dq_int1_ths_t int1_ths;
2156 int32_t ret;
2157
2158 ret = iis328dq_read_reg(ctx, IIS328DQ_INT1_THS, (uint8_t *)&int1_ths, 1);
2159 *val = int1_ths.ths;
2160
2161 return ret;
2162 }
2163
2164 /**
2165 * @brief Configure the 6d on interrupt 2 generator.[set]
2166 *
2167 * @param ctx read / write interface definitions(ptr)
2168 * @param val change the values of 6d in reg INT2_CFG
2169 * @retval Interface status (MANDATORY: return 0 -> no Error)
2170 *
2171 */
iis328dq_int2_6d_mode_set(stmdev_ctx_t * ctx,iis328dq_int2_6d_t val)2172 int32_t iis328dq_int2_6d_mode_set(stmdev_ctx_t *ctx,
2173 iis328dq_int2_6d_t val)
2174 {
2175 iis328dq_int2_cfg_t int2_cfg;
2176 int32_t ret;
2177
2178 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
2179
2180 if (ret == 0)
2181 {
2182 int2_cfg._6d = (uint8_t)val & 0x01U;
2183 int2_cfg.aoi = ((uint8_t)val & 0x02U) >> 1;
2184 ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_CFG,
2185 (uint8_t *)&int2_cfg, 1);
2186 }
2187
2188 return ret;
2189 }
2190
2191 /**
2192 * @brief Configure the 6d on interrupt 2 generator.[get]
2193 *
2194 * @param ctx read / write interface definitions(ptr)
2195 * @param val Get the values of 6d in reg INT2_CFG
2196 * @retval Interface status (MANDATORY: return 0 -> no Error)
2197 *
2198 */
iis328dq_int2_6d_mode_get(stmdev_ctx_t * ctx,iis328dq_int2_6d_t * val)2199 int32_t iis328dq_int2_6d_mode_get(stmdev_ctx_t *ctx,
2200 iis328dq_int2_6d_t *val)
2201 {
2202 iis328dq_int2_cfg_t int2_cfg;
2203 int32_t ret;
2204
2205 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_CFG, (uint8_t *)&int2_cfg, 1);
2206
2207 switch ((int2_cfg.aoi << 1) + int2_cfg._6d)
2208 {
2209 case IIS328DQ_6D_INT2_DISABLE:
2210 *val = IIS328DQ_6D_INT2_DISABLE;
2211 break;
2212
2213 case IIS328DQ_6D_INT2_MOVEMENT:
2214 *val = IIS328DQ_6D_INT2_MOVEMENT;
2215 break;
2216
2217 case IIS328DQ_6D_INT2_POSITION:
2218 *val = IIS328DQ_6D_INT2_POSITION;
2219 break;
2220
2221 default:
2222 *val = IIS328DQ_6D_INT2_DISABLE;
2223 break;
2224 }
2225
2226 return ret;
2227 }
2228
2229 /**
2230 * @brief 6D on interrupt generator 2 source register.[get]
2231 *
2232 * @param ctx read / write interface definitions(ptr)
2233 * @param val registers INT2_SRC
2234 * @retval Interface status (MANDATORY: return 0 -> no Error)
2235 *
2236 */
iis328dq_int2_6d_src_get(stmdev_ctx_t * ctx,iis328dq_int2_src_t * val)2237 int32_t iis328dq_int2_6d_src_get(stmdev_ctx_t *ctx,
2238 iis328dq_int2_src_t *val)
2239 {
2240 int32_t ret;
2241
2242 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_SRC, (uint8_t *) val, 1);
2243
2244 return ret;
2245 }
2246
2247 /**
2248 * @brief Interrupt 2 threshold.[set]
2249 *
2250 * @param ctx read / write interface definitions(ptr)
2251 * @param val change the values of ths in reg INT2_THS
2252 * @retval Interface status (MANDATORY: return 0 -> no Error)
2253 *
2254 */
iis328dq_int2_6d_treshold_set(stmdev_ctx_t * ctx,uint8_t val)2255 int32_t iis328dq_int2_6d_treshold_set(stmdev_ctx_t *ctx, uint8_t val)
2256 {
2257 iis328dq_int2_ths_t int2_ths;
2258 int32_t ret;
2259
2260 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
2261
2262 if (ret == 0)
2263 {
2264 int2_ths.ths = val;
2265 ret = iis328dq_write_reg(ctx, IIS328DQ_INT2_THS,
2266 (uint8_t *)&int2_ths, 1);
2267 }
2268
2269 return ret;
2270 }
2271
2272 /**
2273 * @brief Interrupt 2 threshold.[get]
2274 *
2275 * @param ctx read / write interface definitions(ptr)
2276 * @param val change the values of ths in reg INT2_THS
2277 * @retval Interface status (MANDATORY: return 0 -> no Error)
2278 *
2279 */
iis328dq_int2_6d_treshold_get(stmdev_ctx_t * ctx,uint8_t * val)2280 int32_t iis328dq_int2_6d_treshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2281 {
2282 iis328dq_int2_ths_t int2_ths;
2283 int32_t ret;
2284
2285 ret = iis328dq_read_reg(ctx, IIS328DQ_INT2_THS, (uint8_t *)&int2_ths, 1);
2286 *val = int2_ths.ths;
2287
2288 return ret;
2289 }
2290
2291 /**
2292 * @}
2293 *
2294 */
2295
2296 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2297
