1 /**
2 ******************************************************************************
3 * @file iis2iclx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief IIS2ICLX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "iis2iclx_reg.h"
21
22 /**
23 * @defgroup IIS2ICLX
24 * @brief This file provides a set of functions needed to drive the
25 * iis2iclx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup IIS2ICLX_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
iis2iclx_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak iis2iclx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
iis2iclx_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak iis2iclx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup IIS2ICLX_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
iis2iclx_from_fs500mg_to_mg(int16_t lsb)93 float_t iis2iclx_from_fs500mg_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.015f);
96 }
97
iis2iclx_from_fs1g_to_mg(int16_t lsb)98 float_t iis2iclx_from_fs1g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.031f);
101 }
102
iis2iclx_from_fs2g_to_mg(int16_t lsb)103 float_t iis2iclx_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
iis2iclx_from_fs3g_to_mg(int16_t lsb)108 float_t iis2iclx_from_fs3g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
iis2iclx_from_lsb_to_celsius(int16_t lsb)113 float_t iis2iclx_from_lsb_to_celsius(int16_t lsb)
114 {
115 return (((float_t)lsb / 256.0f) + 25.0f);
116 }
117
iis2iclx_from_lsb_to_nsec(int32_t lsb)118 float_t iis2iclx_from_lsb_to_nsec(int32_t lsb)
119 {
120 return ((float_t)lsb * 25000.0f);
121 }
122
123 /**
124 * @}
125 *
126 */
127
128 /**
129 * @defgroup LSM9DS1_Data_generation
130 * @brief This section groups all the functions concerning data
131 * generation
132 * @{
133 *
134 */
135
136 /**
137 * @brief Accelerometer full-scale selection[set]
138 *
139 * @param ctx Read / write interface definitions.(ptr)
140 * @param val Change the values of fs_xl in reg CTRL1_XL
141 * @retval Interface status (MANDATORY: return 0 -> no Error).
142 *
143 */
iis2iclx_xl_full_scale_set(stmdev_ctx_t * ctx,iis2iclx_fs_xl_t val)144 int32_t iis2iclx_xl_full_scale_set(stmdev_ctx_t *ctx,
145 iis2iclx_fs_xl_t val)
146 {
147 iis2iclx_ctrl1_xl_t ctrl1_xl;
148 int32_t ret;
149
150 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
151
152 if (ret == 0)
153 {
154 ctrl1_xl.fs_xl = (uint8_t)val;
155 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL1_XL,
156 (uint8_t *)&ctrl1_xl, 1);
157 }
158
159 return ret;
160 }
161
162 /**
163 * @brief Accelerometer full-scale selection.[get]
164 *
165 * @param ctx Read / write interface definitions.(ptr)
166 * @param val Get the values of fs_xl in reg CTRL1_XL
167 * @retval Interface status (MANDATORY: return 0 -> no Error).
168 *
169 */
iis2iclx_xl_full_scale_get(stmdev_ctx_t * ctx,iis2iclx_fs_xl_t * val)170 int32_t iis2iclx_xl_full_scale_get(stmdev_ctx_t *ctx,
171 iis2iclx_fs_xl_t *val)
172 {
173 iis2iclx_ctrl1_xl_t ctrl1_xl;
174 int32_t ret;
175
176 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
177
178 switch (ctrl1_xl.fs_xl)
179 {
180 case IIS2ICLX_500mg:
181 *val = IIS2ICLX_500mg;
182 break;
183
184 case IIS2ICLX_3g:
185 *val = IIS2ICLX_3g;
186 break;
187
188 case IIS2ICLX_1g:
189 *val = IIS2ICLX_1g;
190 break;
191
192 case IIS2ICLX_2g:
193 *val = IIS2ICLX_2g;
194 break;
195
196 default:
197 *val = IIS2ICLX_500mg;
198 break;
199 }
200
201 return ret;
202 }
203
204 /**
205 * @brief Accelerometer UI data rate selection.[set]
206 *
207 * @param ctx Read / write interface definitions.(ptr)
208 * @param val Change the values of odr_xl in reg CTRL1_XL
209 * @retval Interface status (MANDATORY: return 0 -> no Error).
210 *
211 */
iis2iclx_xl_data_rate_set(stmdev_ctx_t * ctx,iis2iclx_odr_xl_t val)212 int32_t iis2iclx_xl_data_rate_set(stmdev_ctx_t *ctx,
213 iis2iclx_odr_xl_t val)
214 {
215 iis2iclx_odr_xl_t odr_xl = val;
216 iis2iclx_emb_fsm_enable_t fsm_enable;
217 iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
218 iis2iclx_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
219 iis2iclx_page_sel_t page_sel;
220 iis2iclx_fsm_odr_t fsm_odr;
221 uint8_t mlc_enable;
222 iis2iclx_mlc_odr_t mlc_odr;
223 iis2iclx_ctrl1_xl_t ctrl1_xl;
224 int32_t ret;
225
226 /* Check the Finite State Machine data rate constraints */
227 ret = iis2iclx_fsm_enable_get(ctx, &fsm_enable);
228
229 if (ret == 0)
230 {
231 if ((fsm_enable.fsm_enable_a.fsm1_en |
232 fsm_enable.fsm_enable_a.fsm2_en |
233 fsm_enable.fsm_enable_a.fsm3_en |
234 fsm_enable.fsm_enable_a.fsm4_en |
235 fsm_enable.fsm_enable_a.fsm5_en |
236 fsm_enable.fsm_enable_a.fsm6_en |
237 fsm_enable.fsm_enable_a.fsm7_en |
238 fsm_enable.fsm_enable_a.fsm8_en |
239 fsm_enable.fsm_enable_b.fsm9_en |
240 fsm_enable.fsm_enable_b.fsm10_en |
241 fsm_enable.fsm_enable_b.fsm11_en |
242 fsm_enable.fsm_enable_b.fsm12_en |
243 fsm_enable.fsm_enable_b.fsm13_en |
244 fsm_enable.fsm_enable_b.fsm14_en |
245 fsm_enable.fsm_enable_b.fsm15_en |
246 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
247 {
248 ret = iis2iclx_fsm_data_rate_get(ctx, &fsm_odr);
249
250 if (ret == 0)
251 {
252 switch (fsm_odr)
253 {
254 case IIS2ICLX_ODR_FSM_12Hz5:
255 if (val == IIS2ICLX_XL_ODR_OFF)
256 {
257 odr_xl = IIS2ICLX_XL_ODR_12Hz5;
258 }
259
260 else
261 {
262 odr_xl = val;
263 }
264
265 break;
266
267 case IIS2ICLX_ODR_FSM_26Hz:
268 if (val == IIS2ICLX_XL_ODR_OFF)
269 {
270 odr_xl = IIS2ICLX_XL_ODR_26Hz;
271 }
272
273 else if (val == IIS2ICLX_XL_ODR_12Hz5)
274 {
275 odr_xl = IIS2ICLX_XL_ODR_26Hz;
276 }
277
278 else
279 {
280 odr_xl = val;
281 }
282
283 break;
284
285 case IIS2ICLX_ODR_FSM_52Hz:
286 if (val == IIS2ICLX_XL_ODR_OFF)
287 {
288 odr_xl = IIS2ICLX_XL_ODR_52Hz;
289 }
290
291 else if (val == IIS2ICLX_XL_ODR_12Hz5)
292 {
293 odr_xl = IIS2ICLX_XL_ODR_52Hz;
294 }
295
296 else if (val == IIS2ICLX_XL_ODR_26Hz)
297 {
298 odr_xl = IIS2ICLX_XL_ODR_52Hz;
299 }
300
301 else
302 {
303 odr_xl = val;
304 }
305
306 break;
307
308 case IIS2ICLX_ODR_FSM_104Hz:
309 if (val == IIS2ICLX_XL_ODR_OFF)
310 {
311 odr_xl = IIS2ICLX_XL_ODR_104Hz;
312 }
313
314 else if (val == IIS2ICLX_XL_ODR_12Hz5)
315 {
316 odr_xl = IIS2ICLX_XL_ODR_104Hz;
317 }
318
319 else if (val == IIS2ICLX_XL_ODR_26Hz)
320 {
321 odr_xl = IIS2ICLX_XL_ODR_104Hz;
322 }
323
324 else if (val == IIS2ICLX_XL_ODR_52Hz)
325 {
326 odr_xl = IIS2ICLX_XL_ODR_104Hz;
327 }
328
329 else
330 {
331 odr_xl = val;
332 }
333
334 break;
335
336 default:
337 odr_xl = val;
338 break;
339 }
340 }
341 }
342 }
343
344 /* Check the Machine Learning Core data rate constraints */
345 mlc_enable = PROPERTY_DISABLE;
346
347 if (ret == 0)
348 {
349 ret = iis2iclx_mlc_get(ctx, &mlc_enable);
350
351 if (mlc_enable == PROPERTY_ENABLE)
352 {
353 ret = iis2iclx_mlc_data_rate_get(ctx, &mlc_odr);
354
355 if (ret == 0)
356 {
357 switch (mlc_odr)
358 {
359 case IIS2ICLX_ODR_PRGS_12Hz5:
360 if (val == IIS2ICLX_XL_ODR_OFF)
361 {
362 odr_xl = IIS2ICLX_XL_ODR_12Hz5;
363 }
364
365 else
366 {
367 odr_xl = val;
368 }
369
370 break;
371
372 case IIS2ICLX_ODR_PRGS_26Hz:
373 if (val == IIS2ICLX_XL_ODR_OFF)
374 {
375 odr_xl = IIS2ICLX_XL_ODR_26Hz;
376 }
377
378 else if (val == IIS2ICLX_XL_ODR_12Hz5)
379 {
380 odr_xl = IIS2ICLX_XL_ODR_26Hz;
381 }
382
383 else
384 {
385 odr_xl = val;
386 }
387
388 break;
389
390 case IIS2ICLX_ODR_PRGS_52Hz:
391 if (val == IIS2ICLX_XL_ODR_OFF)
392 {
393 odr_xl = IIS2ICLX_XL_ODR_52Hz;
394 }
395
396 else if (val == IIS2ICLX_XL_ODR_12Hz5)
397 {
398 odr_xl = IIS2ICLX_XL_ODR_52Hz;
399 }
400
401 else if (val == IIS2ICLX_XL_ODR_26Hz)
402 {
403 odr_xl = IIS2ICLX_XL_ODR_52Hz;
404 }
405
406 else
407 {
408 odr_xl = val;
409 }
410
411 break;
412
413 case IIS2ICLX_ODR_PRGS_104Hz:
414 if (val == IIS2ICLX_XL_ODR_OFF)
415 {
416 odr_xl = IIS2ICLX_XL_ODR_104Hz;
417 }
418
419 else if (val == IIS2ICLX_XL_ODR_12Hz5)
420 {
421 odr_xl = IIS2ICLX_XL_ODR_104Hz;
422 }
423
424 else if (val == IIS2ICLX_XL_ODR_26Hz)
425 {
426 odr_xl = IIS2ICLX_XL_ODR_104Hz;
427 }
428
429 else if (val == IIS2ICLX_XL_ODR_52Hz)
430 {
431 odr_xl = IIS2ICLX_XL_ODR_104Hz;
432 }
433
434 else
435 {
436 odr_xl = val;
437 }
438
439 break;
440
441 default:
442 odr_xl = val;
443 break;
444 }
445 }
446 }
447 }
448
449 if (ret == 0)
450 {
451 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
452
453 if (ret == 0)
454 {
455 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
456 }
457
458 if (ret == 0)
459 {
460 page_sel.not_used_01 = 0x01U;
461 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
462 (uint8_t *)&page_sel, 1);
463 }
464
465 if (ret == 0)
466 {
467 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
468 (uint8_t *)&emb_func_odr_cfg_b, 1);
469 }
470
471 if (ret == 0)
472 {
473 emb_func_odr_cfg_b.not_used_01 = 0x03U;
474 emb_func_odr_cfg_b.not_used_02 = 0x02U;
475 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
476 (uint8_t *)&emb_func_odr_cfg_b, 1);
477 }
478
479 if (ret == 0)
480 {
481 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
482 (uint8_t *)&emb_func_odr_cfg_c, 1);
483 }
484
485 if (ret == 0)
486 {
487 emb_func_odr_cfg_c.not_used_01 = 0x05U;
488 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
489 (uint8_t *)&emb_func_odr_cfg_c, 1);
490 }
491
492 if (ret == 0)
493 {
494 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
495 }
496 }
497
498 if (ret == 0)
499 {
500 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
501 }
502
503 if (ret == 0)
504 {
505 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
506 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL1_XL,
507 (uint8_t *)&ctrl1_xl, 1);
508 }
509
510 return ret;
511 }
512
513 /**
514 * @brief Accelerometer UI data rate selection.[get]
515 *
516 * @param ctx Read / write interface definitions.(ptr)
517 * @param val Get the values of odr_xl in reg CTRL1_XL
518 * @retval Interface status (MANDATORY: return 0 -> no Error).
519 *
520 */
iis2iclx_xl_data_rate_get(stmdev_ctx_t * ctx,iis2iclx_odr_xl_t * val)521 int32_t iis2iclx_xl_data_rate_get(stmdev_ctx_t *ctx,
522 iis2iclx_odr_xl_t *val)
523 {
524 iis2iclx_ctrl1_xl_t ctrl1_xl;
525 int32_t ret;
526
527 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
528
529 switch (ctrl1_xl.odr_xl)
530 {
531 case IIS2ICLX_XL_ODR_OFF:
532 *val = IIS2ICLX_XL_ODR_OFF;
533 break;
534
535 case IIS2ICLX_XL_ODR_12Hz5:
536 *val = IIS2ICLX_XL_ODR_12Hz5;
537 break;
538
539 case IIS2ICLX_XL_ODR_26Hz:
540 *val = IIS2ICLX_XL_ODR_26Hz;
541 break;
542
543 case IIS2ICLX_XL_ODR_52Hz:
544 *val = IIS2ICLX_XL_ODR_52Hz;
545 break;
546
547 case IIS2ICLX_XL_ODR_104Hz:
548 *val = IIS2ICLX_XL_ODR_104Hz;
549 break;
550
551 case IIS2ICLX_XL_ODR_208Hz:
552 *val = IIS2ICLX_XL_ODR_208Hz;
553 break;
554
555 case IIS2ICLX_XL_ODR_416Hz:
556 *val = IIS2ICLX_XL_ODR_416Hz;
557 break;
558
559 case IIS2ICLX_XL_ODR_833Hz:
560 *val = IIS2ICLX_XL_ODR_833Hz;
561 break;
562
563 default:
564 *val = IIS2ICLX_XL_ODR_OFF;
565 break;
566 }
567
568 return ret;
569 }
570
571 /**
572 * @brief Block data update.[set]
573 *
574 * @param ctx Read / write interface definitions.(ptr)
575 * @param val Change the values of bdu in reg CTRL3_C
576 * @retval Interface status (MANDATORY: return 0 -> no Error).
577 *
578 */
iis2iclx_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)579 int32_t iis2iclx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
580 {
581 iis2iclx_ctrl3_c_t ctrl3_c;
582 int32_t ret;
583
584 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
585
586 if (ret == 0)
587 {
588 ctrl3_c.bdu = (uint8_t)val;
589 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
590 }
591
592 return ret;
593 }
594
595 /**
596 * @brief Block data update.[get]
597 *
598 * @param ctx Read / write interface definitions.(ptr)
599 * @param val Change the values of bdu in reg CTRL3_C
600 * @retval Interface status (MANDATORY: return 0 -> no Error).
601 *
602 */
iis2iclx_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)603 int32_t iis2iclx_block_data_update_get(stmdev_ctx_t *ctx,
604 uint8_t *val)
605 {
606 iis2iclx_ctrl3_c_t ctrl3_c;
607 int32_t ret;
608
609 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
610 *val = ctrl3_c.bdu;
611
612 return ret;
613 }
614
615 /**
616 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
617 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
618 *
619 * @param ctx Read / write interface definitions.(ptr)
620 * @param val Change the values of usr_off_w in reg CTRL6_C
621 * @retval Interface status (MANDATORY: return 0 -> no Error).
622 *
623 */
iis2iclx_xl_offset_weight_set(stmdev_ctx_t * ctx,iis2iclx_usr_off_w_t val)624 int32_t iis2iclx_xl_offset_weight_set(stmdev_ctx_t *ctx,
625 iis2iclx_usr_off_w_t val)
626 {
627 iis2iclx_ctrl6_c_t ctrl6_c;
628 int32_t ret;
629
630 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
631
632 if (ret == 0)
633 {
634 ctrl6_c.usr_off_w = (uint8_t)val;
635 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
636 }
637
638 return ret;
639 }
640
641 /**
642 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
643 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
644 *
645 * @param ctx Read / write interface definitions.(ptr)
646 * @param val Get the values of usr_off_w in reg CTRL6_C
647 * @retval Interface status (MANDATORY: return 0 -> no Error).
648 *
649 */
iis2iclx_xl_offset_weight_get(stmdev_ctx_t * ctx,iis2iclx_usr_off_w_t * val)650 int32_t iis2iclx_xl_offset_weight_get(stmdev_ctx_t *ctx,
651 iis2iclx_usr_off_w_t *val)
652 {
653 iis2iclx_ctrl6_c_t ctrl6_c;
654 int32_t ret;
655
656 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
657
658 switch (ctrl6_c.usr_off_w)
659 {
660 case IIS2ICLX_LSb_1mg:
661 *val = IIS2ICLX_LSb_1mg;
662 break;
663
664 case IIS2ICLX_LSb_16mg:
665 *val = IIS2ICLX_LSb_16mg;
666 break;
667
668 default:
669 *val = IIS2ICLX_LSb_1mg;
670 break;
671 }
672
673 return ret;
674 }
675
676 /**
677 * @brief Read all the interrupt flag of the device.
678 *[get]
679 * @param ctx Read / write interface definitions.(ptr)
680 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
681 * TAP_SRC; D6D_SRC; STATUS_REG;
682 * EMB_FUNC_STATUS; FSM_STATUS_A/B
683 * @retval Interface status (MANDATORY: return 0 -> no Error).
684 *
685 */
iis2iclx_all_sources_get(stmdev_ctx_t * ctx,iis2iclx_all_sources_t * val)686 int32_t iis2iclx_all_sources_get(stmdev_ctx_t *ctx,
687 iis2iclx_all_sources_t *val)
688 {
689 int32_t ret;
690
691 ret = iis2iclx_read_reg(ctx, IIS2ICLX_ALL_INT_SRC,
692 (uint8_t *)&val->all_int_src, 1);
693
694 if (ret == 0)
695 {
696 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_SRC,
697 (uint8_t *)&val->wake_up_src, 1);
698 }
699
700 if (ret == 0)
701 {
702 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_SRC,
703 (uint8_t *)&val->tap_src, 1);
704 }
705
706 if (ret == 0)
707 {
708 ret = iis2iclx_read_reg(ctx, IIS2ICLX_DEN_SRC,
709 (uint8_t *)&val->den_src, 1);
710 }
711
712 if (ret == 0)
713 {
714 ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG,
715 (uint8_t *)&val->status_reg, 1);
716 }
717
718 if (ret == 0)
719 {
720 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
721 }
722
723 if (ret == 0)
724 {
725 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_STATUS,
726 (uint8_t *)&val->emb_func_status, 1);
727 }
728
729 if (ret == 0)
730 {
731 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_A,
732 (uint8_t *)&val->fsm_status_a, 1);
733 }
734
735 if (ret == 0)
736 {
737 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_STATUS_B,
738 (uint8_t *)&val->fsm_status_b, 1);
739 }
740
741 if (ret == 0)
742 {
743 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
744 }
745
746 return ret;
747 }
748
749 /**
750 * @brief The STATUS_REG register is read by the primary interface.[get]
751 *
752 * @param ctx Read / write interface definitions.(ptr)
753 * @param val Get register STATUS_REG
754 * @retval Interface status (MANDATORY: return 0 -> no Error).
755 *
756 */
iis2iclx_status_reg_get(stmdev_ctx_t * ctx,iis2iclx_status_reg_t * val)757 int32_t iis2iclx_status_reg_get(stmdev_ctx_t *ctx,
758 iis2iclx_status_reg_t *val)
759 {
760 int32_t ret;
761
762 ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG, (uint8_t *) val, 1);
763
764 return ret;
765 }
766
767 /**
768 * @brief Accelerometer new data available.[get]
769 *
770 * @param ctx Read / write interface definitions.(ptr)
771 * @param val Change the values of xlda in reg STATUS_REG
772 * @retval Interface status (MANDATORY: return 0 -> no Error).
773 *
774 */
iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)775 int32_t iis2iclx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
776 uint8_t *val)
777 {
778 iis2iclx_status_reg_t status_reg;
779 int32_t ret;
780
781 ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG,
782 (uint8_t *)&status_reg, 1);
783 *val = status_reg.xlda;
784
785 return ret;
786 }
787
788 /**
789 * @brief Temperature new data available.[get]
790 *
791 * @param ctx Read / write interface definitions.(ptr)
792 * @param val Change the values of tda in reg STATUS_REG
793 * @retval Interface status (MANDATORY: return 0 -> no Error).
794 *
795 */
iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)796 int32_t iis2iclx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
797 uint8_t *val)
798 {
799 iis2iclx_status_reg_t status_reg;
800 int32_t ret;
801
802 ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_REG,
803 (uint8_t *)&status_reg, 1);
804 *val = status_reg.tda;
805
806 return ret;
807 }
808
809 /**
810 * @brief Accelerometer X-axis user offset correction expressed in two’s
811 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
812 * The value must be in the range [-127 127].[set]
813 *
814 * @param ctx Read / write interface definitions.(ptr)
815 * @param buff Buffer that contains data to write
816 * @retval Interface status (MANDATORY: return 0 -> no Error).
817 *
818 */
iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t * ctx,uint8_t * buff)819 int32_t iis2iclx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
820 {
821 int32_t ret;
822
823 ret = iis2iclx_write_reg(ctx, IIS2ICLX_X_OFS_USR, buff, 1);
824
825 return ret;
826 }
827
828 /**
829 * @brief Accelerometer X-axis user offset correction expressed in two’s
830 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
831 * The value must be in the range [-127 127].[get]
832 *
833 * @param ctx Read / write interface definitions.(ptr)
834 * @param buff Buffer that stores data read
835 * @retval Interface status (MANDATORY: return 0 -> no Error).
836 *
837 */
iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t * ctx,uint8_t * buff)838 int32_t iis2iclx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
839 {
840 int32_t ret;
841
842 ret = iis2iclx_read_reg(ctx, IIS2ICLX_X_OFS_USR, buff, 1);
843
844 return ret;
845 }
846
847 /**
848 * @brief Accelerometer Y-axis user offset correction expressed in two’s
849 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
850 * The value must be in the range [-127 127].[set]
851 *
852 * @param ctx Read / write interface definitions.(ptr)
853 * @param buff Buffer that contains data to write
854 * @retval Interface status (MANDATORY: return 0 -> no Error).
855 *
856 */
iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t * ctx,uint8_t * buff)857 int32_t iis2iclx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
858 {
859 int32_t ret;
860
861 ret = iis2iclx_write_reg(ctx, IIS2ICLX_Y_OFS_USR, buff, 1);
862
863 return ret;
864 }
865
866 /**
867 * @brief Accelerometer Y-axis user offset correction expressed in two’s
868 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
869 * The value must be in the range [-127 127].[get]
870 *
871 * @param ctx Read / write interface definitions.(ptr)
872 * @param buff Buffer that stores data read
873 * @retval Interface status (MANDATORY: return 0 -> no Error).
874 *
875 */
iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t * ctx,uint8_t * buff)876 int32_t iis2iclx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
877 {
878 int32_t ret;
879
880 ret = iis2iclx_read_reg(ctx, IIS2ICLX_Y_OFS_USR, buff, 1);
881
882 return ret;
883 }
884
885 /**
886 * @brief Enables user offset on out.[set]
887 *
888 * @param ctx Read / write interface definitions.(ptr)
889 * @param val Change the values of usr_off_on_out in reg CTRL7_G
890 * @retval Interface status (MANDATORY: return 0 -> no Error).
891 *
892 */
iis2iclx_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t val)893 int32_t iis2iclx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
894 {
895 iis2iclx_ctrl7_xl_t ctrl7_xl;
896 int32_t ret;
897
898 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t *)&ctrl7_xl, 1);
899
900 if (ret == 0)
901 {
902 ctrl7_xl.usr_off_on_out = (uint8_t)val;
903 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t *)&ctrl7_xl, 1);
904 }
905
906 return ret;
907 }
908
909 /**
910 * @brief Get user offset on out flag.[get]
911 *
912 * @param ctx Read / write interface definitions.(ptr)
913 * @param val Get values of usr_off_on_out in reg CTRL7_G
914 * @retval Interface status (MANDATORY: return 0 -> no Error).
915 *
916 */
iis2iclx_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * val)917 int32_t iis2iclx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
918 {
919 iis2iclx_ctrl7_xl_t ctrl7_xl;
920 int32_t ret;
921
922 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL7_XL, (uint8_t *)&ctrl7_xl, 1);
923 *val = ctrl7_xl.usr_off_on_out;
924
925 return ret;
926 }
927
928 /**
929 * @}
930 *
931 */
932
933 /**
934 * @defgroup IIS2ICLX_Timestamp
935 * @brief This section groups all the functions that manage the
936 * timestamp generation.
937 * @{
938 *
939 */
940
941 /**
942 * @brief Enables timestamp counter.[set]
943 *
944 * @param ctx Read / write interface definitions.(ptr)
945 * @param val Change the values of timestamp_en in reg CTRL10_C
946 * @retval Interface status (MANDATORY: return 0 -> no Error).
947 *
948 */
iis2iclx_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)949 int32_t iis2iclx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
950 {
951 iis2iclx_ctrl10_c_t ctrl10_c;
952 int32_t ret;
953
954 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
955
956 if (ret == 0)
957 {
958 ctrl10_c.timestamp_en = (uint8_t)val;
959 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL10_C,
960 (uint8_t *)&ctrl10_c, 1);
961 }
962
963 return ret;
964 }
965
966 /**
967 * @brief Enables timestamp counter.[get]
968 *
969 * @param ctx Read / write interface definitions.(ptr)
970 * @param val Change the values of timestamp_en in reg CTRL10_C
971 * @retval Interface status (MANDATORY: return 0 -> no Error).
972 *
973 */
iis2iclx_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)974 int32_t iis2iclx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
975 {
976 iis2iclx_ctrl10_c_t ctrl10_c;
977 int32_t ret;
978
979 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
980 *val = ctrl10_c.timestamp_en;
981
982 return ret;
983 }
984
985 /**
986 * @brief Timestamp first data output register (r).
987 * The value is expressed as a 32-bit word and the bit resolution
988 * is 25 μs.[get]
989 *
990 * @param ctx Read / write interface definitions.(ptr)
991 * @param buff Buffer that stores data read
992 * @retval Interface status (MANDATORY: return 0 -> no Error).
993 *
994 */
iis2iclx_timestamp_raw_get(stmdev_ctx_t * ctx,int32_t * val)995 int32_t iis2iclx_timestamp_raw_get(stmdev_ctx_t *ctx, int32_t *val)
996 {
997 uint8_t buff[4];
998 int32_t ret;
999
1000 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TIMESTAMP0, buff, 4);
1001 val[0] = (int16_t)buff[1];
1002 val[0] = (val[0] * 256) + (int16_t)buff[0];
1003 val[1] = (int16_t)buff[3];
1004 val[1] = (val[1] * 256) + (int16_t)buff[2];
1005
1006 return ret;
1007 }
1008
1009 /**
1010 * @}
1011 *
1012 */
1013
1014 /**
1015 * @defgroup IIS2ICLX_Data output
1016 * @brief This section groups all the data output functions.
1017 * @{
1018 *
1019 */
1020
1021 /**
1022 * @brief Temperature data output register (r).
1023 * L and H registers together express a 16-bit word in two’s
1024 * complement.[get]
1025 *
1026 * @param ctx Read / write interface definitions.(ptr)
1027 * @param buff Buffer that stores data read
1028 * @retval Interface status (MANDATORY: return 0 -> no Error).
1029 *
1030 */
iis2iclx_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1031 int32_t iis2iclx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1032 {
1033 uint8_t buff[2];
1034 int32_t ret;
1035
1036 ret = iis2iclx_read_reg(ctx, IIS2ICLX_OUT_TEMP_L, buff, 2);
1037 *val = (int16_t)buff[1];
1038 *val = (*val * 256) + (int16_t)buff[0];
1039
1040 return ret;
1041 }
1042
1043 /**
1044 * @brief Linear acceleration output register. The value is expressed as a
1045 * 16-bit word in two’s complement.[get]
1046 *
1047 * @param ctx Read / write interface definitions.(ptr)
1048 * @param buff Buffer that stores data read
1049 * @retval Interface status (MANDATORY: return 0 -> no Error).
1050 *
1051 */
iis2iclx_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1052 int32_t iis2iclx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1053 {
1054 uint8_t buff[4];
1055 int32_t ret;
1056
1057 ret = iis2iclx_read_reg(ctx, IIS2ICLX_OUTX_L_A, buff, 4);
1058 val[0] = (int16_t)buff[1];
1059 val[0] = (val[0] * 256) + (int16_t)buff[0];
1060 val[1] = (int16_t)buff[3];
1061 val[1] = (val[1] * 256) + (int16_t)buff[2];
1062
1063 return ret;
1064 }
1065
1066 /**
1067 * @brief FIFO data output.[get]
1068 *
1069 * @param ctx Read / write interface definitions.(ptr)
1070 * @param buff Buffer that stores data read
1071 * @retval Interface status (MANDATORY: return 0 -> no Error).
1072 *
1073 */
iis2iclx_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)1074 int32_t iis2iclx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
1075 {
1076 int32_t ret;
1077
1078 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_DATA_OUT_X_L, buff, 6);
1079
1080 return ret;
1081 }
1082
1083 /**
1084 * @}
1085 *
1086 */
1087
1088 /**
1089 * @defgroup IIS2ICLX_common
1090 * @brief This section groups common useful functions.
1091 * @{
1092 *
1093 */
1094
1095 /**
1096 * @brief DEVICE_CONF bit configuration[set]
1097 *
1098 * @param ctx Read / write interface definitions.(ptr)
1099 * @param val Change the values of device_conf in reg CTRL9_XL
1100 * @retval Interface status (MANDATORY: return 0 -> no Error).
1101 *
1102 */
iis2iclx_device_conf_set(stmdev_ctx_t * ctx,uint8_t val)1103 int32_t iis2iclx_device_conf_set(stmdev_ctx_t *ctx, uint8_t val)
1104 {
1105 iis2iclx_ctrl9_xl_t ctrl9_xl;
1106 int32_t ret;
1107
1108 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
1109
1110 if (ret == 0)
1111 {
1112 ctrl9_xl.device_conf = (uint8_t)val;
1113 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
1114 }
1115
1116 return ret;
1117 }
1118
1119 /**
1120 * @brief DEVICE_CONF bit configuration[get]
1121 *
1122 * @param ctx Read / write interface definitions.(ptr)
1123 * @param val Get the values of device_conf in reg CTRL9_XL
1124 * @retval Interface status (MANDATORY: return 0 -> no Error).
1125 *
1126 */
iis2iclx_device_conf_get(stmdev_ctx_t * ctx,uint8_t * val)1127 int32_t iis2iclx_device_conf_get(stmdev_ctx_t *ctx, uint8_t *val)
1128 {
1129 iis2iclx_ctrl9_xl_t ctrl9_xl;
1130 int32_t ret;
1131
1132 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
1133 *val = ctrl9_xl.device_conf;
1134
1135 return ret;
1136 }
1137
1138 /**
1139 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1140 * with respect to the typical.[set]
1141 * Step: 0.15%. 8-bit format, 2's complement.
1142 *
1143 * @param ctx Read / write interface definitions.(ptr)
1144 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1145 * @retval Interface status (MANDATORY: return 0 -> no Error).
1146 *
1147 */
iis2iclx_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)1148 int32_t iis2iclx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
1149 {
1150 iis2iclx_internal_freq_fine_t internal_freq_fine;
1151 int32_t ret;
1152
1153 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INTERNAL_FREQ_FINE,
1154 (uint8_t *)&internal_freq_fine, 1);
1155
1156 if (ret == 0)
1157 {
1158 internal_freq_fine.freq_fine = (uint8_t)val;
1159 ret = iis2iclx_write_reg(ctx, IIS2ICLX_INTERNAL_FREQ_FINE,
1160 (uint8_t *)&internal_freq_fine, 1);
1161 }
1162
1163 return ret;
1164 }
1165
1166 /**
1167 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1168 * with respect to the typical.[get]
1169 * Step: 0.15%. 8-bit format, 2's complement.
1170 *
1171 * @param ctx Read / write interface definitions.(ptr)
1172 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1173 * @retval Interface status (MANDATORY: return 0 -> no Error).
1174 *
1175 */
iis2iclx_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)1176 int32_t iis2iclx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
1177 {
1178 iis2iclx_internal_freq_fine_t internal_freq_fine;
1179 int32_t ret;
1180
1181 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INTERNAL_FREQ_FINE,
1182 (uint8_t *)&internal_freq_fine, 1);
1183 *val = internal_freq_fine.freq_fine;
1184
1185 return ret;
1186 }
1187
1188 /**
1189 * @brief Enable access to the embedded functions/sensor hub configuration
1190 * registers.[set]
1191 *
1192 * @param ctx Read / write interface definitions.(ptr)
1193 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1194 * @retval Interface status (MANDATORY: return 0 -> no Error).
1195 *
1196 */
iis2iclx_mem_bank_set(stmdev_ctx_t * ctx,iis2iclx_reg_access_t val)1197 int32_t iis2iclx_mem_bank_set(stmdev_ctx_t *ctx,
1198 iis2iclx_reg_access_t val)
1199 {
1200 iis2iclx_func_cfg_access_t func_cfg_access;
1201 int32_t ret;
1202
1203 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FUNC_CFG_ACCESS,
1204 (uint8_t *)&func_cfg_access, 1);
1205
1206 if (ret == 0)
1207 {
1208 func_cfg_access.reg_access = (uint8_t)val;
1209 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FUNC_CFG_ACCESS,
1210 (uint8_t *)&func_cfg_access, 1);
1211 }
1212
1213 return ret;
1214 }
1215
1216 /**
1217 * @brief Enable access to the embedded functions/sensor hub configuration
1218 * registers.[get]
1219 *
1220 * @param ctx Read / write interface definitions.(ptr)
1221 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1222 * @retval Interface status (MANDATORY: return 0 -> no Error).
1223 *
1224 */
iis2iclx_mem_bank_get(stmdev_ctx_t * ctx,iis2iclx_reg_access_t * val)1225 int32_t iis2iclx_mem_bank_get(stmdev_ctx_t *ctx,
1226 iis2iclx_reg_access_t *val)
1227 {
1228 iis2iclx_func_cfg_access_t func_cfg_access;
1229 int32_t ret;
1230
1231 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FUNC_CFG_ACCESS,
1232 (uint8_t *)&func_cfg_access, 1);
1233
1234 switch (func_cfg_access.reg_access)
1235 {
1236 case IIS2ICLX_USER_BANK:
1237 *val = IIS2ICLX_USER_BANK;
1238 break;
1239
1240 case IIS2ICLX_SENSOR_HUB_BANK:
1241 *val = IIS2ICLX_SENSOR_HUB_BANK;
1242 break;
1243
1244 case IIS2ICLX_EMBEDDED_FUNC_BANK:
1245 *val = IIS2ICLX_EMBEDDED_FUNC_BANK;
1246 break;
1247
1248 default:
1249 *val = IIS2ICLX_USER_BANK;
1250 break;
1251 }
1252
1253 return ret;
1254 }
1255
1256 /**
1257 * @brief Write a line(byte) in a page.[set]
1258 *
1259 * @param ctx Read / write interface definitions.(ptr)
1260 * @param add Page line address
1261 * @param val Value to write
1262 * @retval Interface status (MANDATORY: return 0 -> no Error).
1263 *
1264 */
iis2iclx_ln_pg_write_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1265 int32_t iis2iclx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
1266 uint8_t *val)
1267 {
1268 iis2iclx_page_rw_t page_rw;
1269 iis2iclx_page_sel_t page_sel;
1270 iis2iclx_page_address_t page_address;
1271 int32_t ret;
1272
1273 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
1274
1275 if (ret == 0)
1276 {
1277 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1278 }
1279
1280 if (ret == 0)
1281 {
1282 page_rw.page_rw = 0x02U; /* page_write enable */
1283 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1284 }
1285
1286 if (ret == 0)
1287 {
1288 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1289 }
1290
1291 if (ret == 0)
1292 {
1293 page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
1294 page_sel.not_used_01 = 1;
1295 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
1296 (uint8_t *)&page_sel, 1);
1297 }
1298
1299 if (ret == 0)
1300 {
1301 page_address.page_addr = (uint8_t)(add & 0xFFU);
1302 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS,
1303 (uint8_t *)&page_address, 1);
1304 }
1305
1306 if (ret == 0)
1307 {
1308 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_VALUE, val, 1);
1309 }
1310
1311 if (ret == 0)
1312 {
1313 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1314 }
1315
1316 if (ret == 0)
1317 {
1318 page_rw.page_rw = 0x00; /* page_write disable */
1319 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1320 }
1321
1322 if (ret == 0)
1323 {
1324 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
1325 }
1326
1327 return ret;
1328 }
1329
1330 /**
1331 * @brief Write buffer in a page.[set]
1332 *
1333 * @param ctx Read / write interface definitions.(ptr)
1334 * @param buf Page line address.(ptr)
1335 * @param val Value to write.
1336 * @param len buffer length.
1337 * @retval Interface status (MANDATORY: return 0 -> no Error).
1338 *
1339 */
iis2iclx_ln_pg_write(stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)1340 int32_t iis2iclx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
1341 uint8_t *buf, uint8_t len)
1342 {
1343 iis2iclx_page_rw_t page_rw;
1344 iis2iclx_page_sel_t page_sel;
1345 iis2iclx_page_address_t page_address;
1346 int32_t ret;
1347
1348 uint8_t msb, lsb;
1349 uint8_t i ;
1350 msb = (uint8_t)((add >> 8) & 0x0FU);
1351 lsb = (uint8_t)(add & 0xFFU);
1352 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
1353
1354 if (ret == 0)
1355 {
1356 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1357 }
1358
1359 if (ret == 0)
1360 {
1361 page_rw.page_rw = 0x02U; /* page_write enable*/
1362 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1363 }
1364
1365 if (ret == 0)
1366 {
1367 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1368 }
1369
1370 if (ret == 0)
1371 {
1372 page_sel.page_sel = msb;
1373 page_sel.not_used_01 = 1;
1374 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
1375 (uint8_t *)&page_sel, 1);
1376 }
1377
1378 if (ret == 0)
1379 {
1380 page_address.page_addr = lsb;
1381 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS,
1382 (uint8_t *)&page_address, 1);
1383 }
1384
1385 for (i = 0; i < len; i++)
1386 {
1387 if (ret == 0)
1388 {
1389 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_VALUE, &buf[i], 1);
1390
1391 if (ret == 0)
1392 {
1393 /* Check if page wrap */
1394 if (lsb == 0x00U)
1395 {
1396 msb++;
1397 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL,
1398 (uint8_t *)&page_sel, 1);
1399 }
1400
1401 lsb++;
1402 }
1403
1404 if (ret == 0)
1405 {
1406 page_sel.page_sel = msb;
1407 page_sel.not_used_01 = 1;
1408 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
1409 (uint8_t *)&page_sel, 1);
1410 }
1411 }
1412 }
1413
1414 if (ret == 0)
1415 {
1416 page_sel.page_sel = 0;
1417 page_sel.not_used_01 = 1;
1418 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
1419 (uint8_t *)&page_sel, 1);
1420 }
1421
1422 if (ret == 0)
1423 {
1424 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1425 }
1426
1427 if (ret == 0)
1428 {
1429 page_rw.page_rw = 0x00U; /* page_write disable */
1430 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1431 }
1432
1433 if (ret == 0)
1434 {
1435 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
1436 }
1437
1438 return ret;
1439 }
1440
1441 /**
1442 * @brief Read a line(byte) in a page.[get]
1443 *
1444 * @param ctx Read / write interface definitions.(ptr)
1445 * @param add Page line address.
1446 * @param val Read value.(ptr)
1447 * @retval Interface status (MANDATORY: return 0 -> no Error).
1448 *
1449 */
iis2iclx_ln_pg_read_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1450 int32_t iis2iclx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
1451 uint8_t *val)
1452 {
1453 iis2iclx_page_rw_t page_rw;
1454 iis2iclx_page_sel_t page_sel;
1455 iis2iclx_page_address_t page_address;
1456 int32_t ret;
1457
1458 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
1459
1460 if (ret == 0)
1461 {
1462 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1463 }
1464
1465 if (ret == 0)
1466 {
1467 page_rw.page_rw = 0x01U; /* page_read enable*/
1468 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1469 }
1470
1471 if (ret == 0)
1472 {
1473 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1474 }
1475
1476 if (ret == 0)
1477 {
1478 page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
1479 page_sel.not_used_01 = 1;
1480 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_SEL,
1481 (uint8_t *)&page_sel, 1);
1482 }
1483
1484 if (ret == 0)
1485 {
1486 page_address.page_addr = (uint8_t)(add & 0x00FFU);
1487 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_ADDRESS,
1488 (uint8_t *)&page_address, 1);
1489 }
1490
1491 if (ret == 0)
1492 {
1493 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_VALUE, val, 2);
1494 }
1495
1496 if (ret == 0)
1497 {
1498 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1499 }
1500
1501 if (ret == 0)
1502 {
1503 page_rw.page_rw = 0x00U; /* page_read disable */
1504 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
1505 }
1506
1507 if (ret == 0)
1508 {
1509 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
1510 }
1511
1512 return ret;
1513 }
1514
1515 /**
1516 * @brief Data-ready pulsed / letched mode.[set]
1517 *
1518 * @param ctx Read / write interface definitions.(ptr)
1519 * @param val Change the values of dataready_pulsed in
1520 * reg COUNTER_BDR_REG1
1521 * @retval Interface status (MANDATORY: return 0 -> no Error).
1522 *
1523 */
iis2iclx_data_ready_mode_set(stmdev_ctx_t * ctx,iis2iclx_dataready_pulsed_t val)1524 int32_t iis2iclx_data_ready_mode_set(stmdev_ctx_t *ctx,
1525 iis2iclx_dataready_pulsed_t val)
1526 {
1527 iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
1528 int32_t ret;
1529
1530 ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
1531 (uint8_t *)&counter_bdr_reg1, 1);
1532
1533 if (ret == 0)
1534 {
1535 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
1536 ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
1537 (uint8_t *)&counter_bdr_reg1, 1);
1538 }
1539
1540 return ret;
1541 }
1542
1543 /**
1544 * @brief Data-ready pulsed / letched mode.[get]
1545 *
1546 * @param ctx Read / write interface definitions.(ptr)
1547 * @param val Get the values of dataready_pulsed in
1548 * reg COUNTER_BDR_REG1
1549 * @retval Interface status (MANDATORY: return 0 -> no Error).
1550 *
1551 */
iis2iclx_data_ready_mode_get(stmdev_ctx_t * ctx,iis2iclx_dataready_pulsed_t * val)1552 int32_t iis2iclx_data_ready_mode_get(stmdev_ctx_t *ctx,
1553 iis2iclx_dataready_pulsed_t *val)
1554 {
1555 iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
1556 int32_t ret;
1557
1558 ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
1559 (uint8_t *)&counter_bdr_reg1, 1);
1560
1561 switch (counter_bdr_reg1.dataready_pulsed)
1562 {
1563 case IIS2ICLX_DRDY_LATCHED:
1564 *val = IIS2ICLX_DRDY_LATCHED;
1565 break;
1566
1567 case IIS2ICLX_DRDY_PULSED:
1568 *val = IIS2ICLX_DRDY_PULSED;
1569 break;
1570
1571 default:
1572 *val = IIS2ICLX_DRDY_LATCHED;
1573 break;
1574 }
1575
1576 return ret;
1577 }
1578
1579 /**
1580 * @brief Device Who am I.[get]
1581 *
1582 * @param ctx Read / write interface definitions.(ptr)
1583 * @param buff Buffer that stores data read
1584 * @retval Interface status (MANDATORY: return 0 -> no Error).
1585 *
1586 */
iis2iclx_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)1587 int32_t iis2iclx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
1588 {
1589 int32_t ret;
1590
1591 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WHO_AM_I, buff, 1);
1592
1593 return ret;
1594 }
1595
1596 /**
1597 * @brief Software reset. Restore the default values in user registers.[set]
1598 *
1599 * @param ctx Read / write interface definitions.(ptr)
1600 * @param val Change the values of sw_reset in reg CTRL3_C
1601 * @retval Interface status (MANDATORY: return 0 -> no Error).
1602 *
1603 */
iis2iclx_reset_set(stmdev_ctx_t * ctx,uint8_t val)1604 int32_t iis2iclx_reset_set(stmdev_ctx_t *ctx, uint8_t val)
1605 {
1606 iis2iclx_ctrl3_c_t ctrl3_c;
1607 int32_t ret;
1608
1609 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1610
1611 if (ret == 0)
1612 {
1613 ctrl3_c.sw_reset = (uint8_t)val;
1614 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1615 }
1616
1617 return ret;
1618 }
1619
1620 /**
1621 * @brief Software reset. Restore the default values in user registers.[get]
1622 *
1623 * @param ctx Read / write interface definitions.(ptr)
1624 * @param val Change the values of sw_reset in reg CTRL3_C
1625 * @retval Interface status (MANDATORY: return 0 -> no Error).
1626 *
1627 */
iis2iclx_reset_get(stmdev_ctx_t * ctx,uint8_t * val)1628 int32_t iis2iclx_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
1629 {
1630 iis2iclx_ctrl3_c_t ctrl3_c;
1631 int32_t ret;
1632
1633 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1634 *val = ctrl3_c.sw_reset;
1635
1636 return ret;
1637 }
1638
1639 /**
1640 * @brief Register address automatically incremented during a multiple byte
1641 * access with a serial interface.[set]
1642 *
1643 * @param ctx Read / write interface definitions.(ptr)
1644 * @param val Change the values of if_inc in reg CTRL3_C
1645 * @retval Interface status (MANDATORY: return 0 -> no Error).
1646 *
1647 */
iis2iclx_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)1648 int32_t iis2iclx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
1649 {
1650 iis2iclx_ctrl3_c_t ctrl3_c;
1651 int32_t ret;
1652
1653 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1654
1655 if (ret == 0)
1656 {
1657 ctrl3_c.if_inc = (uint8_t)val;
1658 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1659 }
1660
1661 return ret;
1662 }
1663
1664 /**
1665 * @brief Register address automatically incremented during a multiple byte
1666 * access with a serial interface.[get]
1667 *
1668 * @param ctx Read / write interface definitions.(ptr)
1669 * @param val Change the values of if_inc in reg CTRL3_C
1670 * @retval Interface status (MANDATORY: return 0 -> no Error).
1671 *
1672 */
iis2iclx_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)1673 int32_t iis2iclx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
1674 {
1675 iis2iclx_ctrl3_c_t ctrl3_c;
1676 int32_t ret;
1677
1678 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1679 *val = ctrl3_c.if_inc;
1680
1681 return ret;
1682 }
1683
1684 /**
1685 * @brief Reboot memory content. Reload the calibration parameters.[set]
1686 *
1687 * @param ctx Read / write interface definitions.(ptr)
1688 * @param val Change the values of boot in reg CTRL3_C
1689 * @retval Interface status (MANDATORY: return 0 -> no Error).
1690 *
1691 */
iis2iclx_boot_set(stmdev_ctx_t * ctx,uint8_t val)1692 int32_t iis2iclx_boot_set(stmdev_ctx_t *ctx, uint8_t val)
1693 {
1694 iis2iclx_ctrl3_c_t ctrl3_c;
1695 int32_t ret;
1696
1697 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1698
1699 if (ret == 0)
1700 {
1701 ctrl3_c.boot = (uint8_t)val;
1702 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1703 }
1704
1705 return ret;
1706 }
1707
1708 /**
1709 * @brief Reboot memory content. Reload the calibration parameters.[get]
1710 *
1711 * @param ctx Read / write interface definitions.(ptr)
1712 * @param val Change the values of boot in reg CTRL3_C
1713 * @retval Interface status (MANDATORY: return 0 -> no Error).
1714 *
1715 */
iis2iclx_boot_get(stmdev_ctx_t * ctx,uint8_t * val)1716 int32_t iis2iclx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
1717 {
1718 iis2iclx_ctrl3_c_t ctrl3_c;
1719 int32_t ret;
1720
1721 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1722 *val = ctrl3_c.boot;
1723
1724 return ret;
1725 }
1726
1727
1728
1729 /**
1730 * @brief Linear acceleration sensor self-test enable.[set]
1731 *
1732 * @param ctx Read / write interface definitions.(ptr)
1733 * @param val Change the values of st_xl in reg CTRL5_C
1734 * @retval Interface status (MANDATORY: return 0 -> no Error).
1735 *
1736 */
iis2iclx_xl_self_test_set(stmdev_ctx_t * ctx,iis2iclx_st_xl_t val)1737 int32_t iis2iclx_xl_self_test_set(stmdev_ctx_t *ctx,
1738 iis2iclx_st_xl_t val)
1739 {
1740 iis2iclx_ctrl5_c_t ctrl5_c;
1741 int32_t ret;
1742
1743 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1744
1745 if (ret == 0)
1746 {
1747 ctrl5_c.st_xl = (uint8_t)val;
1748 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1749 }
1750
1751 return ret;
1752 }
1753
1754 /**
1755 * @brief Linear acceleration sensor self-test enable.[get]
1756 *
1757 * @param ctx Read / write interface definitions.(ptr)
1758 * @param val Get the values of st_xl in reg CTRL5_C
1759 * @retval Interface status (MANDATORY: return 0 -> no Error).
1760 *
1761 */
iis2iclx_xl_self_test_get(stmdev_ctx_t * ctx,iis2iclx_st_xl_t * val)1762 int32_t iis2iclx_xl_self_test_get(stmdev_ctx_t *ctx,
1763 iis2iclx_st_xl_t *val)
1764 {
1765 iis2iclx_ctrl5_c_t ctrl5_c;
1766 int32_t ret;
1767
1768 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1769
1770 switch (ctrl5_c.st_xl)
1771 {
1772 case IIS2ICLX_XL_ST_DISABLE:
1773 *val = IIS2ICLX_XL_ST_DISABLE;
1774 break;
1775
1776 case IIS2ICLX_XL_ST_POSITIVE:
1777 *val = IIS2ICLX_XL_ST_POSITIVE;
1778 break;
1779
1780 case IIS2ICLX_XL_ST_NEGATIVE:
1781 *val = IIS2ICLX_XL_ST_NEGATIVE;
1782 break;
1783
1784 default:
1785 *val = IIS2ICLX_XL_ST_DISABLE;
1786 break;
1787 }
1788
1789 return ret;
1790 }
1791
1792 /**
1793 * @}
1794 *
1795 */
1796
1797 /**
1798 * @defgroup IIS2ICLX_filters
1799 * @brief This section group all the functions concerning the
1800 * filters configuration
1801 * @{
1802 *
1803 */
1804
1805 /**
1806 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
1807 *
1808 * @param ctx Read / write interface definitions.(ptr)
1809 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
1810 * @retval Interface status (MANDATORY: return 0 -> no Error).
1811 *
1812 */
iis2iclx_xl_filter_lp2_set(stmdev_ctx_t * ctx,uint8_t val)1813 int32_t iis2iclx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
1814 {
1815 iis2iclx_ctrl1_xl_t ctrl1_xl;
1816 int32_t ret;
1817
1818 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1819
1820 if (ret == 0)
1821 {
1822 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
1823 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL1_XL,
1824 (uint8_t *)&ctrl1_xl, 1);
1825 }
1826
1827 return ret;
1828 }
1829
1830 /**
1831 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
1832 *
1833 * @param ctx Read / write interface definitions.(ptr)
1834 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
1835 * @retval Interface status (MANDATORY: return 0 -> no Error).
1836 *
1837 */
iis2iclx_xl_filter_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)1838 int32_t iis2iclx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
1839 {
1840 iis2iclx_ctrl1_xl_t ctrl1_xl;
1841 int32_t ret;
1842
1843 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1844 *val = ctrl1_xl.lpf2_xl_en;
1845
1846 return ret;
1847 }
1848
1849 /**
1850 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1851 * (XL and Gyro independently masked).[set]
1852 *
1853 * @param ctx Read / write interface definitions.(ptr)
1854 * @param val Change the values of drdy_mask in reg CTRL4_C
1855 * @retval Interface status (MANDATORY: return 0 -> no Error).
1856 *
1857 */
iis2iclx_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)1858 int32_t iis2iclx_filter_settling_mask_set(stmdev_ctx_t *ctx,
1859 uint8_t val)
1860 {
1861 iis2iclx_ctrl4_c_t ctrl4_c;
1862 int32_t ret;
1863
1864 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1865
1866 if (ret == 0)
1867 {
1868 ctrl4_c.drdy_mask = (uint8_t)val;
1869 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1870 }
1871
1872 return ret;
1873 }
1874
1875 /**
1876 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1877 * (XL and Gyro independently masked).[get]
1878 *
1879 * @param ctx Read / write interface definitions.(ptr)
1880 * @param val Change the values of drdy_mask in reg CTRL4_C
1881 * @retval Interface status (MANDATORY: return 0 -> no Error).
1882 *
1883 */
iis2iclx_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)1884 int32_t iis2iclx_filter_settling_mask_get(stmdev_ctx_t *ctx,
1885 uint8_t *val)
1886 {
1887 iis2iclx_ctrl4_c_t ctrl4_c;
1888 int32_t ret;
1889
1890 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1891 *val = ctrl4_c.drdy_mask;
1892
1893 return ret;
1894 }
1895
1896 /**
1897 * @brief Accelerometer slope filter / high-pass filter selection
1898 * on output.[set]
1899 *
1900 * @param ctx Read / write interface definitions.(ptr)
1901 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
1902 * @retval Interface status (MANDATORY: return 0 -> no Error).
1903 *
1904 */
iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t * ctx,iis2iclx_hp_slope_xl_en_t val)1905 int32_t iis2iclx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
1906 iis2iclx_hp_slope_xl_en_t val)
1907 {
1908 iis2iclx_ctrl8_xl_t ctrl8_xl;
1909 int32_t ret;
1910
1911 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
1912
1913 if (ret == 0)
1914 {
1915 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
1916 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
1917 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
1918 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL8_XL,
1919 (uint8_t *)&ctrl8_xl, 1);
1920 }
1921
1922 return ret;
1923 }
1924
1925 /**
1926 * @brief Accelerometer slope filter / high-pass filter selection on
1927 * output.[get]
1928 *
1929 * @param ctx Read / write interface definitions.(ptr)
1930 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
1931 * @retval Interface status (MANDATORY: return 0 -> no Error).
1932 *
1933 */
iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t * ctx,iis2iclx_hp_slope_xl_en_t * val)1934 int32_t iis2iclx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
1935 iis2iclx_hp_slope_xl_en_t *val)
1936 {
1937 iis2iclx_ctrl8_xl_t ctrl8_xl;
1938 int32_t ret;
1939
1940 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
1941
1942 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
1943 4) +
1944 ctrl8_xl.hpcf_xl))
1945 {
1946 case IIS2ICLX_HP_PATH_DISABLE_ON_OUT:
1947 *val = IIS2ICLX_HP_PATH_DISABLE_ON_OUT;
1948 break;
1949
1950 case IIS2ICLX_SLOPE_ODR_DIV_4:
1951 *val = IIS2ICLX_SLOPE_ODR_DIV_4;
1952 break;
1953
1954 case IIS2ICLX_HP_ODR_DIV_10:
1955 *val = IIS2ICLX_HP_ODR_DIV_10;
1956 break;
1957
1958 case IIS2ICLX_HP_ODR_DIV_20:
1959 *val = IIS2ICLX_HP_ODR_DIV_20;
1960 break;
1961
1962 case IIS2ICLX_HP_ODR_DIV_45:
1963 *val = IIS2ICLX_HP_ODR_DIV_45;
1964 break;
1965
1966 case IIS2ICLX_HP_ODR_DIV_100:
1967 *val = IIS2ICLX_HP_ODR_DIV_100;
1968 break;
1969
1970 case IIS2ICLX_HP_ODR_DIV_200:
1971 *val = IIS2ICLX_HP_ODR_DIV_200;
1972 break;
1973
1974 case IIS2ICLX_HP_ODR_DIV_400:
1975 *val = IIS2ICLX_HP_ODR_DIV_400;
1976 break;
1977
1978 case IIS2ICLX_HP_ODR_DIV_800:
1979 *val = IIS2ICLX_HP_ODR_DIV_800;
1980 break;
1981
1982 case IIS2ICLX_HP_REF_MD_ODR_DIV_10:
1983 *val = IIS2ICLX_HP_REF_MD_ODR_DIV_10;
1984 break;
1985
1986 case IIS2ICLX_HP_REF_MD_ODR_DIV_20:
1987 *val = IIS2ICLX_HP_REF_MD_ODR_DIV_20;
1988 break;
1989
1990 case IIS2ICLX_HP_REF_MD_ODR_DIV_45:
1991 *val = IIS2ICLX_HP_REF_MD_ODR_DIV_45;
1992 break;
1993
1994 case IIS2ICLX_HP_REF_MD_ODR_DIV_100:
1995 *val = IIS2ICLX_HP_REF_MD_ODR_DIV_100;
1996 break;
1997
1998 case IIS2ICLX_HP_REF_MD_ODR_DIV_200:
1999 *val = IIS2ICLX_HP_REF_MD_ODR_DIV_200;
2000 break;
2001
2002 case IIS2ICLX_HP_REF_MD_ODR_DIV_400:
2003 *val = IIS2ICLX_HP_REF_MD_ODR_DIV_400;
2004 break;
2005
2006 case IIS2ICLX_HP_REF_MD_ODR_DIV_800:
2007 *val = IIS2ICLX_HP_REF_MD_ODR_DIV_800;
2008 break;
2009
2010 case IIS2ICLX_LP_ODR_DIV_10:
2011 *val = IIS2ICLX_LP_ODR_DIV_10;
2012 break;
2013
2014 case IIS2ICLX_LP_ODR_DIV_20:
2015 *val = IIS2ICLX_LP_ODR_DIV_20;
2016 break;
2017
2018 case IIS2ICLX_LP_ODR_DIV_45:
2019 *val = IIS2ICLX_LP_ODR_DIV_45;
2020 break;
2021
2022 case IIS2ICLX_LP_ODR_DIV_100:
2023 *val = IIS2ICLX_LP_ODR_DIV_100;
2024 break;
2025
2026 case IIS2ICLX_LP_ODR_DIV_200:
2027 *val = IIS2ICLX_LP_ODR_DIV_200;
2028 break;
2029
2030 case IIS2ICLX_LP_ODR_DIV_400:
2031 *val = IIS2ICLX_LP_ODR_DIV_400;
2032 break;
2033
2034 case IIS2ICLX_LP_ODR_DIV_800:
2035 *val = IIS2ICLX_LP_ODR_DIV_800;
2036 break;
2037
2038 default:
2039 *val = IIS2ICLX_HP_PATH_DISABLE_ON_OUT;
2040 break;
2041 }
2042
2043 return ret;
2044 }
2045
2046 /**
2047 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2048 * The filter sets the second samples after writing this bit.
2049 * Active only during device exit from powerdown mode.[set]
2050 *
2051 * @param ctx Read / write interface definitions.(ptr)
2052 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2053 * @retval Interface status (MANDATORY: return 0 -> no Error).
2054 *
2055 */
iis2iclx_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2056 int32_t iis2iclx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
2057 {
2058 iis2iclx_ctrl8_xl_t ctrl8_xl;
2059 int32_t ret;
2060
2061 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2062
2063 if (ret == 0)
2064 {
2065 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
2066 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL8_XL,
2067 (uint8_t *)&ctrl8_xl, 1);
2068 }
2069
2070 return ret;
2071 }
2072
2073 /**
2074 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2075 * The filter sets the second samples after writing
2076 * this bit. Active only during device exit from powerdown mode.[get]
2077 *
2078 * @param ctx Read / write interface definitions.(ptr)
2079 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2080 * @retval Interface status (MANDATORY: return 0 -> no Error).
2081 *
2082 */
iis2iclx_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)2083 int32_t iis2iclx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
2084 {
2085 iis2iclx_ctrl8_xl_t ctrl8_xl;
2086 int32_t ret;
2087
2088 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2089 *val = ctrl8_xl.fastsettl_mode_xl;
2090
2091 return ret;
2092 }
2093
2094 /**
2095 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2096 * functions.[set]
2097 *
2098 * @param ctx Read / write interface definitions.(ptr)
2099 * @param val Change the values of slope_fds in reg TAP_CFG0
2100 * @retval Interface status (MANDATORY: return 0 -> no Error).
2101 *
2102 */
iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t * ctx,iis2iclx_slope_fds_t val)2103 int32_t iis2iclx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
2104 iis2iclx_slope_fds_t val)
2105 {
2106 iis2iclx_tap_cfg0_t tap_cfg0;
2107 int32_t ret;
2108
2109 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2110
2111 if (ret == 0)
2112 {
2113 tap_cfg0.slope_fds = (uint8_t)val;
2114 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
2115 (uint8_t *)&tap_cfg0, 1);
2116 }
2117
2118 return ret;
2119 }
2120
2121 /**
2122 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2123 * functions.[get]
2124 *
2125 * @param ctx Read / write interface definitions.(ptr)
2126 * @param val Get the values of slope_fds in reg TAP_CFG0
2127 * @retval Interface status (MANDATORY: return 0 -> no Error).
2128 *
2129 */
iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t * ctx,iis2iclx_slope_fds_t * val)2130 int32_t iis2iclx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
2131 iis2iclx_slope_fds_t *val)
2132 {
2133 iis2iclx_tap_cfg0_t tap_cfg0;
2134 int32_t ret;
2135
2136 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2137
2138 switch (tap_cfg0.slope_fds)
2139 {
2140 case IIS2ICLX_USE_SLOPE:
2141 *val = IIS2ICLX_USE_SLOPE;
2142 break;
2143
2144 case IIS2ICLX_USE_HPF:
2145 *val = IIS2ICLX_USE_HPF;
2146 break;
2147
2148 default:
2149 *val = IIS2ICLX_USE_SLOPE;
2150 break;
2151 }
2152
2153 return ret;
2154 }
2155
2156 /**
2157 * @}
2158 *
2159 */
2160
2161 /**
2162 * @defgroup IIS2ICLX_ main_serial_interface
2163 * @brief This section groups all the functions concerning main
2164 * serial interface management (not auxiliary)
2165 * @{
2166 *
2167 */
2168
2169 /**
2170 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2171 *
2172 * @param ctx Read / write interface definitions.(ptr)
2173 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
2174 * @retval Interface status (MANDATORY: return 0 -> no Error).
2175 *
2176 */
iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t * ctx,iis2iclx_sdo_pu_en_t val)2177 int32_t iis2iclx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
2178 iis2iclx_sdo_pu_en_t val)
2179 {
2180 iis2iclx_pin_ctrl_t pin_ctrl;
2181 int32_t ret;
2182
2183 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2184
2185 if (ret == 0)
2186 {
2187 pin_ctrl.sdo_pu_en = (uint8_t)val;
2188 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2189 }
2190
2191 return ret;
2192 }
2193
2194 /**
2195 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2196 *
2197 * @param ctx Read / write interface definitions.(ptr)
2198 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
2199 * @retval Interface status (MANDATORY: return 0 -> no Error).
2200 *
2201 */
iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t * ctx,iis2iclx_sdo_pu_en_t * val)2202 int32_t iis2iclx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
2203 iis2iclx_sdo_pu_en_t *val)
2204 {
2205 iis2iclx_pin_ctrl_t pin_ctrl;
2206 int32_t ret;
2207
2208 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2209
2210 switch (pin_ctrl.sdo_pu_en)
2211 {
2212 case IIS2ICLX_PULL_UP_DISC:
2213 *val = IIS2ICLX_PULL_UP_DISC;
2214 break;
2215
2216 case IIS2ICLX_PULL_UP_CONNECT:
2217 *val = IIS2ICLX_PULL_UP_CONNECT;
2218 break;
2219
2220 default:
2221 *val = IIS2ICLX_PULL_UP_DISC;
2222 break;
2223 }
2224
2225 return ret;
2226 }
2227
2228 /**
2229 * @brief SPI Serial Interface Mode selection.[set]
2230 *
2231 * @param ctx Read / write interface definitions.(ptr)
2232 * @param val Change the values of sim in reg CTRL3_C
2233 * @retval Interface status (MANDATORY: return 0 -> no Error).
2234 *
2235 */
iis2iclx_spi_mode_set(stmdev_ctx_t * ctx,iis2iclx_sim_t val)2236 int32_t iis2iclx_spi_mode_set(stmdev_ctx_t *ctx, iis2iclx_sim_t val)
2237 {
2238 iis2iclx_ctrl3_c_t ctrl3_c;
2239 int32_t ret;
2240
2241 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2242
2243 if (ret == 0)
2244 {
2245 ctrl3_c.sim = (uint8_t)val;
2246 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2247 }
2248
2249 return ret;
2250 }
2251
2252 /**
2253 * @brief SPI Serial Interface Mode selection.[get]
2254 *
2255 * @param ctx Read / write interface definitions.(ptr)
2256 * @param val Get the values of sim in reg CTRL3_C
2257 * @retval Interface status (MANDATORY: return 0 -> no Error).
2258 *
2259 */
iis2iclx_spi_mode_get(stmdev_ctx_t * ctx,iis2iclx_sim_t * val)2260 int32_t iis2iclx_spi_mode_get(stmdev_ctx_t *ctx, iis2iclx_sim_t *val)
2261 {
2262 iis2iclx_ctrl3_c_t ctrl3_c;
2263 int32_t ret;
2264
2265 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2266
2267 switch (ctrl3_c.sim)
2268 {
2269 case IIS2ICLX_SPI_4_WIRE:
2270 *val = IIS2ICLX_SPI_4_WIRE;
2271 break;
2272
2273 case IIS2ICLX_SPI_3_WIRE:
2274 *val = IIS2ICLX_SPI_3_WIRE;
2275 break;
2276
2277 default:
2278 *val = IIS2ICLX_SPI_4_WIRE;
2279 break;
2280 }
2281
2282 return ret;
2283 }
2284
2285 /**
2286 * @brief Disable / Enable I2C interface.[set]
2287 *
2288 * @param ctx Read / write interface definitions.(ptr)
2289 * @param val Change the values of i2c_disable in reg CTRL4_C
2290 * @retval Interface status (MANDATORY: return 0 -> no Error).
2291 *
2292 */
iis2iclx_i2c_interface_set(stmdev_ctx_t * ctx,iis2iclx_i2c_disable_t val)2293 int32_t iis2iclx_i2c_interface_set(stmdev_ctx_t *ctx,
2294 iis2iclx_i2c_disable_t val)
2295 {
2296 iis2iclx_ctrl4_c_t ctrl4_c;
2297 int32_t ret;
2298
2299 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2300
2301 if (ret == 0)
2302 {
2303 ctrl4_c.i2c_disable = (uint8_t)val;
2304 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2305 }
2306
2307 return ret;
2308 }
2309
2310 /**
2311 * @brief Disable / Enable I2C interface.[get]
2312 *
2313 * @param ctx Read / write interface definitions.(ptr)
2314 * @param val Get the values of i2c reg CTRL4_C
2315 * @retval Interface status (MANDATORY: return 0 -> no Error).
2316 *
2317 */
iis2iclx_i2c_interface_get(stmdev_ctx_t * ctx,iis2iclx_i2c_disable_t * val)2318 int32_t iis2iclx_i2c_interface_get(stmdev_ctx_t *ctx,
2319 iis2iclx_i2c_disable_t *val)
2320 {
2321 iis2iclx_ctrl4_c_t ctrl4_c;
2322 int32_t ret;
2323
2324 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2325
2326 switch (ctrl4_c.i2c_disable)
2327 {
2328 case IIS2ICLX_I2C_ENABLE:
2329 *val = IIS2ICLX_I2C_ENABLE;
2330 break;
2331
2332 case IIS2ICLX_I2C_DISABLE:
2333 *val = IIS2ICLX_I2C_DISABLE;
2334 break;
2335
2336 default:
2337 *val = IIS2ICLX_I2C_ENABLE;
2338 break;
2339 }
2340
2341 return ret;
2342 }
2343
2344 /**
2345 * @}
2346 *
2347 */
2348
2349 /**
2350 * @defgroup IIS2ICLX_interrupt_pins
2351 * @brief This section groups all the functions that manage
2352 * interrupt pins
2353 * @{
2354 *
2355 */
2356
2357 /**
2358 * @brief Select the signal that need to route on int1 pad[set]
2359 *
2360 * @param ctx Read / write interface definitions.(ptr)
2361 * @param val Structure of registers: INT1_CTRL,MD1_CFG,
2362 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
2363 * @retval Interface status (MANDATORY: return 0 -> no Error).
2364 *
2365 */
iis2iclx_pin_int1_route_set(stmdev_ctx_t * ctx,iis2iclx_pin_int1_route_t * val)2366 int32_t iis2iclx_pin_int1_route_set(stmdev_ctx_t *ctx,
2367 iis2iclx_pin_int1_route_t *val)
2368 {
2369 iis2iclx_pin_int2_route_t pin_int2_route;
2370 iis2iclx_tap_cfg2_t tap_cfg2;
2371 int32_t ret;
2372
2373 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
2374
2375 if (ret == 0)
2376 {
2377 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MLC_INT1,
2378 (uint8_t *)&val->mlc_int1, 1);
2379 }
2380
2381 if (ret == 0)
2382 {
2383 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INT1,
2384 (uint8_t *)&val->emb_func_int1, 1);
2385 }
2386
2387 if (ret == 0)
2388 {
2389 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT1_A,
2390 (uint8_t *)&val->fsm_int1_a, 1);
2391 }
2392
2393 if (ret == 0)
2394 {
2395 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT1_B,
2396 (uint8_t *)&val->fsm_int1_b, 1);
2397 }
2398
2399 if (ret == 0)
2400 {
2401 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
2402 }
2403
2404 if (ret == 0)
2405 {
2406 if ((val->emb_func_int1.int1_fsm_lc
2407 | val->fsm_int1_a.int1_fsm1
2408 | val->fsm_int1_a.int1_fsm2
2409 | val->fsm_int1_a.int1_fsm3
2410 | val->fsm_int1_a.int1_fsm4
2411 | val->fsm_int1_a.int1_fsm5
2412 | val->fsm_int1_a.int1_fsm6
2413 | val->fsm_int1_a.int1_fsm7
2414 | val->fsm_int1_a.int1_fsm8
2415 | val->fsm_int1_b.int1_fsm9
2416 | val->fsm_int1_b.int1_fsm10
2417 | val->fsm_int1_b.int1_fsm11
2418 | val->fsm_int1_b.int1_fsm12
2419 | val->fsm_int1_b.int1_fsm13
2420 | val->fsm_int1_b.int1_fsm14
2421 | val->fsm_int1_b.int1_fsm15
2422 | val->fsm_int1_b.int1_fsm16
2423 | val->mlc_int1.int1_mlc1
2424 | val->mlc_int1.int1_mlc2
2425 | val->mlc_int1.int1_mlc3
2426 | val->mlc_int1.int1_mlc4
2427 | val->mlc_int1.int1_mlc5
2428 | val->mlc_int1.int1_mlc6
2429 | val->mlc_int1.int1_mlc7
2430 | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
2431 {
2432 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
2433 }
2434
2435 else
2436 {
2437 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
2438 }
2439
2440 ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT1_CTRL,
2441 (uint8_t *)&val->int1_ctrl, 1);
2442 }
2443
2444 if (ret == 0)
2445 {
2446 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MD1_CFG,
2447 (uint8_t *)&val->md1_cfg, 1);
2448 }
2449
2450 if (ret == 0)
2451 {
2452 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
2453 }
2454
2455 if (ret == 0)
2456 {
2457 ret = iis2iclx_pin_int2_route_get(ctx, &pin_int2_route);
2458 }
2459
2460 if (ret == 0)
2461 {
2462 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
2463 | pin_int2_route.int2_ctrl.int2_drdy_temp
2464 | pin_int2_route.int2_ctrl.int2_drdy_xl
2465 | pin_int2_route.int2_ctrl.int2_fifo_full
2466 | pin_int2_route.int2_ctrl.int2_fifo_ovr
2467 | pin_int2_route.int2_ctrl.int2_fifo_th
2468 | pin_int2_route.md2_cfg.int2_double_tap
2469 | pin_int2_route.md2_cfg.int2_wu
2470 | pin_int2_route.md2_cfg.int2_single_tap
2471 | pin_int2_route.md2_cfg.int2_sleep_change
2472 | val->int1_ctrl.den_drdy_flag
2473 | val->int1_ctrl.int1_boot
2474 | val->int1_ctrl.int1_cnt_bdr
2475 | val->int1_ctrl.int1_drdy_xl
2476 | val->int1_ctrl.int1_fifo_full
2477 | val->int1_ctrl.int1_fifo_ovr
2478 | val->int1_ctrl.int1_fifo_th
2479 | val->md1_cfg.int1_shub
2480 | val->md1_cfg.int1_double_tap
2481 | val->md1_cfg.int1_wu
2482 | val->md1_cfg.int1_single_tap
2483 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
2484 {
2485 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
2486 }
2487
2488 else
2489 {
2490 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
2491 }
2492
2493 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2,
2494 (uint8_t *) &tap_cfg2, 1);
2495 }
2496
2497 return ret;
2498 }
2499
2500 /**
2501 * @brief Select the signal that need to route on int1 pad.[get]
2502 *
2503 * @param ctx Read / write interface definitions.(ptr)
2504 * @param val Structure of registers: INT1_CTRL, MD1_CFG,
2505 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B.(ptr)
2506 * @retval Interface status (MANDATORY: return 0 -> no Error).
2507 *
2508 */
iis2iclx_pin_int1_route_get(stmdev_ctx_t * ctx,iis2iclx_pin_int1_route_t * val)2509 int32_t iis2iclx_pin_int1_route_get(stmdev_ctx_t *ctx,
2510 iis2iclx_pin_int1_route_t *val)
2511 {
2512 int32_t ret;
2513
2514 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
2515
2516 if (ret == 0)
2517 {
2518 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC_INT1,
2519 (uint8_t *)&val->mlc_int1, 1);
2520 }
2521
2522 if (ret == 0)
2523 {
2524 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INT1,
2525 (uint8_t *)&val->emb_func_int1, 1);
2526 }
2527
2528 if (ret == 0)
2529 {
2530 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT1_A,
2531 (uint8_t *)&val->fsm_int1_a, 1);
2532 }
2533
2534 if (ret == 0)
2535 {
2536 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT1_B,
2537 (uint8_t *)&val->fsm_int1_b, 1);
2538 }
2539
2540 if (ret == 0)
2541 {
2542 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
2543 }
2544
2545 if (ret == 0)
2546 {
2547 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT1_CTRL,
2548 (uint8_t *)&val->int1_ctrl, 1);
2549 }
2550
2551 if (ret == 0)
2552 {
2553 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MD1_CFG,
2554 (uint8_t *)&val->md1_cfg, 1);
2555 }
2556
2557 return ret;
2558 }
2559
2560 /**
2561 * @brief Select the signal that need to route on int2 pad[set]
2562 *
2563 * @param ctx Read / write interface definitions.(ptr)
2564 * @param val Structure of registers INT2_CTRL, MD2_CFG,
2565 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
2566 * @retval Interface status (MANDATORY: return 0 -> no Error).
2567 *
2568 */
iis2iclx_pin_int2_route_set(stmdev_ctx_t * ctx,iis2iclx_pin_int2_route_t * val)2569 int32_t iis2iclx_pin_int2_route_set(stmdev_ctx_t *ctx,
2570 iis2iclx_pin_int2_route_t *val)
2571 {
2572 iis2iclx_pin_int1_route_t pin_int1_route;
2573 iis2iclx_tap_cfg2_t tap_cfg2;
2574 int32_t ret;
2575
2576 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
2577
2578 if (ret == 0)
2579 {
2580 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MLC_INT2,
2581 (uint8_t *)&val->mlc_int2, 1);
2582 }
2583
2584 if (ret == 0)
2585 {
2586 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INT2,
2587 (uint8_t *)&val->emb_func_int2, 1);
2588 }
2589
2590 if (ret == 0)
2591 {
2592 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT2_A,
2593 (uint8_t *)&val->fsm_int2_a, 1);
2594 }
2595
2596 if (ret == 0)
2597 {
2598 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_INT2_B,
2599 (uint8_t *)&val->fsm_int2_b, 1);
2600 }
2601
2602 if (ret == 0)
2603 {
2604 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
2605 }
2606
2607 if (ret == 0)
2608 {
2609 if ((val->emb_func_int2.int2_fsm_lc
2610 | val->fsm_int2_a.int2_fsm1
2611 | val->fsm_int2_a.int2_fsm2
2612 | val->fsm_int2_a.int2_fsm3
2613 | val->fsm_int2_a.int2_fsm4
2614 | val->fsm_int2_a.int2_fsm5
2615 | val->fsm_int2_a.int2_fsm6
2616 | val->fsm_int2_a.int2_fsm7
2617 | val->fsm_int2_a.int2_fsm8
2618 | val->fsm_int2_b.int2_fsm9
2619 | val->fsm_int2_b.int2_fsm10
2620 | val->fsm_int2_b.int2_fsm11
2621 | val->fsm_int2_b.int2_fsm12
2622 | val->fsm_int2_b.int2_fsm13
2623 | val->fsm_int2_b.int2_fsm14
2624 | val->fsm_int2_b.int2_fsm15
2625 | val->fsm_int2_b.int2_fsm16
2626 | val->mlc_int2.int2_mlc1
2627 | val->mlc_int2.int2_mlc2
2628 | val->mlc_int2.int2_mlc3
2629 | val->mlc_int2.int2_mlc4
2630 | val->mlc_int2.int2_mlc5
2631 | val->mlc_int2.int2_mlc6
2632 | val->mlc_int2.int2_mlc7
2633 | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
2634 {
2635 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
2636 }
2637
2638 else
2639 {
2640 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
2641 }
2642
2643 ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT2_CTRL,
2644 (uint8_t *)&val->int2_ctrl, 1);
2645 }
2646
2647 if (ret == 0)
2648 {
2649 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MD2_CFG,
2650 (uint8_t *)&val->md2_cfg, 1);
2651 }
2652
2653 if (ret == 0)
2654 {
2655 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
2656 }
2657
2658 if (ret == 0)
2659 {
2660 ret = iis2iclx_pin_int1_route_get(ctx, &pin_int1_route);
2661 }
2662
2663 if (ret == 0)
2664 {
2665 if ((val->int2_ctrl.int2_cnt_bdr
2666 | val->int2_ctrl.int2_drdy_temp
2667 | val->int2_ctrl.int2_drdy_xl
2668 | val->int2_ctrl.int2_fifo_full
2669 | val->int2_ctrl.int2_fifo_ovr
2670 | val->int2_ctrl.int2_fifo_th
2671 | val->md2_cfg.int2_double_tap
2672 | val->md2_cfg.int2_wu
2673 | val->md2_cfg.int2_single_tap
2674 | val->md2_cfg.int2_sleep_change
2675 | pin_int1_route.int1_ctrl.den_drdy_flag
2676 | pin_int1_route.int1_ctrl.int1_boot
2677 | pin_int1_route.int1_ctrl.int1_cnt_bdr
2678 | pin_int1_route.int1_ctrl.int1_drdy_xl
2679 | pin_int1_route.int1_ctrl.int1_fifo_full
2680 | pin_int1_route.int1_ctrl.int1_fifo_ovr
2681 | pin_int1_route.int1_ctrl.int1_fifo_th
2682 | pin_int1_route.md1_cfg.int1_double_tap
2683 | pin_int1_route.md1_cfg.int1_wu
2684 | pin_int1_route.md1_cfg.int1_single_tap
2685 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
2686 {
2687 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
2688 }
2689
2690 else
2691 {
2692 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
2693 }
2694
2695 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2,
2696 (uint8_t *) &tap_cfg2, 1);
2697 }
2698
2699 return ret;
2700 }
2701
2702 /**
2703 * @brief Select the signal that need to route on int2 pad.[get]
2704 *
2705 * @param ctx Read / write interface definitions.(ptr)
2706 * @param val Structure of registers INT2_CTRL, MD2_CFG,
2707 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B.[get]
2708 * @retval Interface status (MANDATORY: return 0 -> no Error).
2709 *
2710 */
iis2iclx_pin_int2_route_get(stmdev_ctx_t * ctx,iis2iclx_pin_int2_route_t * val)2711 int32_t iis2iclx_pin_int2_route_get(stmdev_ctx_t *ctx,
2712 iis2iclx_pin_int2_route_t *val)
2713 {
2714 int32_t ret;
2715
2716 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
2717
2718 if (ret == 0)
2719 {
2720 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC_INT2,
2721 (uint8_t *)&val->mlc_int2, 1);
2722 }
2723
2724 if (ret == 0)
2725 {
2726 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INT2,
2727 (uint8_t *)&val->emb_func_int2, 1);
2728 }
2729
2730 if (ret == 0)
2731 {
2732 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT2_A,
2733 (uint8_t *)&val->fsm_int2_a, 1);
2734 }
2735
2736 if (ret == 0)
2737 {
2738 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_INT2_B,
2739 (uint8_t *)&val->fsm_int2_b, 1);
2740 }
2741
2742 if (ret == 0)
2743 {
2744 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
2745 }
2746
2747 if (ret == 0)
2748 {
2749 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT2_CTRL,
2750 (uint8_t *)&val->int2_ctrl, 1);
2751 }
2752
2753 if (ret == 0)
2754 {
2755 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MD2_CFG,
2756 (uint8_t *)&val->md2_cfg, 1);
2757 }
2758
2759 return ret;
2760 }
2761
2762 /**
2763 * @brief Push-pull/open drain selection on interrupt pads.[set]
2764 *
2765 * @param ctx Read / write interface definitions.(ptr)
2766 * @param val Change the values of pp_od in reg CTRL3_C
2767 * @retval Interface status (MANDATORY: return 0 -> no Error).
2768 *
2769 */
iis2iclx_pin_mode_set(stmdev_ctx_t * ctx,iis2iclx_pp_od_t val)2770 int32_t iis2iclx_pin_mode_set(stmdev_ctx_t *ctx, iis2iclx_pp_od_t val)
2771 {
2772 iis2iclx_ctrl3_c_t ctrl3_c;
2773 int32_t ret;
2774
2775 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2776
2777 if (ret == 0)
2778 {
2779 ctrl3_c.pp_od = (uint8_t)val;
2780 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2781 }
2782
2783 return ret;
2784 }
2785
2786 /**
2787 * @brief Push-pull/open drain selection on interrupt pads.[get]
2788 *
2789 * @param ctx Read / write interface definitions.(ptr)
2790 * @param val Get the values of pp_od in reg CTRL3_C
2791 * @retval Interface status (MANDATORY: return 0 -> no Error).
2792 *
2793 */
iis2iclx_pin_mode_get(stmdev_ctx_t * ctx,iis2iclx_pp_od_t * val)2794 int32_t iis2iclx_pin_mode_get(stmdev_ctx_t *ctx,
2795 iis2iclx_pp_od_t *val)
2796 {
2797 iis2iclx_ctrl3_c_t ctrl3_c;
2798 int32_t ret;
2799
2800 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2801
2802 switch (ctrl3_c.pp_od)
2803 {
2804 case IIS2ICLX_PUSH_PULL:
2805 *val = IIS2ICLX_PUSH_PULL;
2806 break;
2807
2808 case IIS2ICLX_OPEN_DRAIN:
2809 *val = IIS2ICLX_OPEN_DRAIN;
2810 break;
2811
2812 default:
2813 *val = IIS2ICLX_PUSH_PULL;
2814 break;
2815 }
2816
2817 return ret;
2818 }
2819
2820 /**
2821 * @brief Interrupt active-high/low.[set]
2822 *
2823 * @param ctx Read / write interface definitions.(ptr)
2824 * @param val Change the values of h_lactive in reg CTRL3_C
2825 * @retval Interface status (MANDATORY: return 0 -> no Error).
2826 *
2827 */
iis2iclx_pin_polarity_set(stmdev_ctx_t * ctx,iis2iclx_h_lactive_t val)2828 int32_t iis2iclx_pin_polarity_set(stmdev_ctx_t *ctx,
2829 iis2iclx_h_lactive_t val)
2830 {
2831 iis2iclx_ctrl3_c_t ctrl3_c;
2832 int32_t ret;
2833
2834 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2835
2836 if (ret == 0)
2837 {
2838 ctrl3_c.h_lactive = (uint8_t)val;
2839 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2840 }
2841
2842 return ret;
2843 }
2844
2845 /**
2846 * @brief Interrupt active-high/low.[get]
2847 *
2848 * @param ctx Read / write interface definitions.(ptr)
2849 * @param val Get the values of h_lactive in reg CTRL3_C
2850 * @retval Interface status (MANDATORY: return 0 -> no Error).
2851 *
2852 */
iis2iclx_pin_polarity_get(stmdev_ctx_t * ctx,iis2iclx_h_lactive_t * val)2853 int32_t iis2iclx_pin_polarity_get(stmdev_ctx_t *ctx,
2854 iis2iclx_h_lactive_t *val)
2855 {
2856 iis2iclx_ctrl3_c_t ctrl3_c;
2857 int32_t ret;
2858
2859 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2860
2861 switch (ctrl3_c.h_lactive)
2862 {
2863 case IIS2ICLX_ACTIVE_HIGH:
2864 *val = IIS2ICLX_ACTIVE_HIGH;
2865 break;
2866
2867 case IIS2ICLX_ACTIVE_LOW:
2868 *val = IIS2ICLX_ACTIVE_LOW;
2869 break;
2870
2871 default:
2872 *val = IIS2ICLX_ACTIVE_HIGH;
2873 break;
2874 }
2875
2876 return ret;
2877 }
2878
2879 /**
2880 * @brief All interrupt signals become available on INT1 pin.[set]
2881 *
2882 * @param ctx Read / write interface definitions.(ptr)
2883 * @param val Change the values of int2_on_int1 in reg CTRL4_C
2884 * @retval Interface status (MANDATORY: return 0 -> no Error).
2885 *
2886 */
iis2iclx_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)2887 int32_t iis2iclx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
2888 {
2889 iis2iclx_ctrl4_c_t ctrl4_c;
2890 int32_t ret;
2891
2892 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2893
2894 if (ret == 0)
2895 {
2896 ctrl4_c.int2_on_int1 = (uint8_t)val;
2897 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2898 }
2899
2900 return ret;
2901 }
2902
2903 /**
2904 * @brief All interrupt signals become available on INT1 pin.[get]
2905 *
2906 * @param ctx Read / write interface definitions.(ptr)
2907 * @param val Change the values of int2_on_int1 in reg CTRL4_C
2908 * @retval Interface status (MANDATORY: return 0 -> no Error).
2909 *
2910 */
iis2iclx_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)2911 int32_t iis2iclx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
2912 {
2913 iis2iclx_ctrl4_c_t ctrl4_c;
2914 int32_t ret;
2915
2916 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2917 *val = ctrl4_c.int2_on_int1;
2918
2919 return ret;
2920 }
2921
2922 /**
2923 * @brief All interrupt signals notification mode.[set]
2924 *
2925 * @param ctx Read / write interface definitions.(ptr)
2926 * @param val Change the values of lir in reg TAP_CFG0
2927 * @retval Interface status (MANDATORY: return 0 -> no Error).
2928 *
2929 */
iis2iclx_int_notification_set(stmdev_ctx_t * ctx,iis2iclx_lir_t val)2930 int32_t iis2iclx_int_notification_set(stmdev_ctx_t *ctx,
2931 iis2iclx_lir_t val)
2932 {
2933 iis2iclx_tap_cfg0_t tap_cfg0;
2934 iis2iclx_page_rw_t page_rw;
2935 int32_t ret;
2936
2937 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2938
2939 if (ret == 0)
2940 {
2941 tap_cfg0.lir = (uint8_t)val & 0x01U;
2942 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
2943 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
2944 (uint8_t *)&tap_cfg0, 1);
2945 }
2946
2947 if (ret == 0)
2948 {
2949 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
2950 }
2951
2952 if (ret == 0)
2953 {
2954 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
2955 }
2956
2957 if (ret == 0)
2958 {
2959 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
2960 ret = iis2iclx_write_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
2961 }
2962
2963 if (ret == 0)
2964 {
2965 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
2966 }
2967
2968 return ret;
2969 }
2970
2971 /**
2972 * @brief All interrupt signals notification mode.[get]
2973 *
2974 * @param ctx Read / write interface definitions.(ptr)
2975 * @param val Get the values of lir in reg TAP_CFG0
2976 * @retval Interface status (MANDATORY: return 0 -> no Error).
2977 *
2978 */
iis2iclx_int_notification_get(stmdev_ctx_t * ctx,iis2iclx_lir_t * val)2979 int32_t iis2iclx_int_notification_get(stmdev_ctx_t *ctx,
2980 iis2iclx_lir_t *val)
2981 {
2982 iis2iclx_tap_cfg0_t tap_cfg0;
2983 iis2iclx_page_rw_t page_rw;
2984 int32_t ret;
2985
2986 *val = IIS2ICLX_ALL_INT_PULSED;
2987 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2988
2989 if (ret == 0)
2990 {
2991 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
2992 }
2993
2994 if (ret == 0)
2995 {
2996 ret = iis2iclx_read_reg(ctx, IIS2ICLX_PAGE_RW, (uint8_t *)&page_rw, 1);
2997 }
2998
2999 if (ret == 0)
3000 {
3001 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
3002 }
3003
3004 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
3005 {
3006 case IIS2ICLX_ALL_INT_PULSED:
3007 *val = IIS2ICLX_ALL_INT_PULSED;
3008 break;
3009
3010 case IIS2ICLX_BASE_LATCHED_EMB_PULSED:
3011 *val = IIS2ICLX_BASE_LATCHED_EMB_PULSED;
3012 break;
3013
3014 case IIS2ICLX_BASE_PULSED_EMB_LATCHED:
3015 *val = IIS2ICLX_BASE_PULSED_EMB_LATCHED;
3016 break;
3017
3018 case IIS2ICLX_ALL_INT_LATCHED:
3019 *val = IIS2ICLX_ALL_INT_LATCHED;
3020 break;
3021
3022 default:
3023 *val = IIS2ICLX_ALL_INT_PULSED;
3024 break;
3025 }
3026
3027 return ret;
3028 }
3029
3030 /**
3031 * @}
3032 *
3033 */
3034
3035 /**
3036 * @defgroup IIS2ICLX_Wake_Up_event
3037 * @brief This section groups all the functions that manage the
3038 * Wake Up event generation.
3039 * @{
3040 *
3041 */
3042
3043 /**
3044 * @brief Weight of 1 LSB of wakeup threshold.[set]
3045 * 0: 1 LSB =FS_XL / 64
3046 * 1: 1 LSB = FS_XL / 256
3047 *
3048 * @param ctx Read / write interface definitions.(ptr)
3049 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
3050 * @retval Interface status (MANDATORY: return 0 -> no Error).
3051 *
3052 */
iis2iclx_wkup_ths_weight_set(stmdev_ctx_t * ctx,iis2iclx_wake_ths_w_t val)3053 int32_t iis2iclx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
3054 iis2iclx_wake_ths_w_t val)
3055 {
3056 iis2iclx_wake_up_dur_t wake_up_dur;
3057 int32_t ret;
3058
3059 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3060 (uint8_t *)&wake_up_dur, 1);
3061
3062 if (ret == 0)
3063 {
3064 wake_up_dur.wake_ths_w = (uint8_t)val;
3065 ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3066 (uint8_t *)&wake_up_dur, 1);
3067 }
3068
3069 return ret;
3070 }
3071
3072 /**
3073 * @brief Weight of 1 LSB of wakeup threshold.[get]
3074 * 0: 1 LSB =FS_XL / 64
3075 * 1: 1 LSB = FS_XL / 256
3076 *
3077 * @param ctx Read / write interface definitions.(ptr)
3078 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
3079 * @retval Interface status (MANDATORY: return 0 -> no Error).
3080 *
3081 */
iis2iclx_wkup_ths_weight_get(stmdev_ctx_t * ctx,iis2iclx_wake_ths_w_t * val)3082 int32_t iis2iclx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
3083 iis2iclx_wake_ths_w_t *val)
3084 {
3085 iis2iclx_wake_up_dur_t wake_up_dur;
3086 int32_t ret;
3087
3088 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3089 (uint8_t *)&wake_up_dur, 1);
3090
3091 switch (wake_up_dur.wake_ths_w)
3092 {
3093 case IIS2ICLX_LSb_FS_DIV_64:
3094 *val = IIS2ICLX_LSb_FS_DIV_64;
3095 break;
3096
3097 case IIS2ICLX_LSb_FS_DIV_256:
3098 *val = IIS2ICLX_LSb_FS_DIV_256;
3099 break;
3100
3101 default:
3102 *val = IIS2ICLX_LSb_FS_DIV_64;
3103 break;
3104 }
3105
3106 return ret;
3107 }
3108
3109 /**
3110 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3111 * WAKE_UP_DUR.[set]
3112 *
3113 * @param ctx Read / write interface definitions.(ptr)
3114 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3115 * @retval Interface status (MANDATORY: return 0 -> no Error).
3116 *
3117 */
iis2iclx_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)3118 int32_t iis2iclx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
3119 {
3120 iis2iclx_wake_up_ths_t wake_up_ths;
3121 int32_t ret;
3122
3123 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3124 (uint8_t *)&wake_up_ths, 1);
3125
3126 if (ret == 0)
3127 {
3128 wake_up_ths.wk_ths = (uint8_t)val;
3129 ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3130 (uint8_t *)&wake_up_ths, 1);
3131 }
3132
3133 return ret;
3134 }
3135
3136 /**
3137 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3138 * WAKE_UP_DUR.[get]
3139 *
3140 * @param ctx Read / write interface definitions.(ptr)
3141 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3142 * @retval Interface status (MANDATORY: return 0 -> no Error).
3143 *
3144 */
iis2iclx_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)3145 int32_t iis2iclx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
3146 {
3147 iis2iclx_wake_up_ths_t wake_up_ths;
3148 int32_t ret;
3149
3150 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3151 (uint8_t *)&wake_up_ths, 1);
3152 *val = wake_up_ths.wk_ths;
3153
3154 return ret;
3155 }
3156
3157 /**
3158 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
3159 *
3160 * @param ctx Read / write interface definitions.(ptr)
3161 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3162 * @retval Interface status (MANDATORY: return 0 -> no Error).
3163 *
3164 */
iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t * ctx,uint8_t val)3165 int32_t iis2iclx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
3166 uint8_t val)
3167 {
3168 iis2iclx_wake_up_ths_t wake_up_ths;
3169 int32_t ret;
3170
3171 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3172 (uint8_t *)&wake_up_ths, 1);
3173
3174 if (ret == 0)
3175 {
3176 wake_up_ths.usr_off_on_wu = (uint8_t)val;
3177 ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3178 (uint8_t *)&wake_up_ths, 1);
3179 }
3180
3181 return ret;
3182 }
3183
3184 /**
3185 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
3186 *
3187 * @param ctx Read / write interface definitions.(ptr)
3188 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
3189 * @retval Interface status (MANDATORY: return 0 -> no Error).
3190 *
3191 */
iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t * ctx,uint8_t * val)3192 int32_t iis2iclx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
3193 uint8_t *val)
3194 {
3195 iis2iclx_wake_up_ths_t wake_up_ths;
3196 int32_t ret;
3197
3198 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3199 (uint8_t *)&wake_up_ths, 1);
3200 *val = wake_up_ths.usr_off_on_wu;
3201
3202 return ret;
3203 }
3204
3205 /**
3206 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
3207 *
3208 * @param ctx Read / write interface definitions.(ptr)
3209 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3210 * @retval Interface status (MANDATORY: return 0 -> no Error).
3211 *
3212 */
iis2iclx_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)3213 int32_t iis2iclx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3214 {
3215 iis2iclx_wake_up_dur_t wake_up_dur;
3216 int32_t ret;
3217
3218 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3219 (uint8_t *)&wake_up_dur, 1);
3220
3221 if (ret == 0)
3222 {
3223 wake_up_dur.wake_dur = (uint8_t)val;
3224 ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3225 (uint8_t *)&wake_up_dur, 1);
3226 }
3227
3228 return ret;
3229 }
3230
3231 /**
3232 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
3233 *
3234 * @param ctx Read / write interface definitions.(ptr)
3235 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3236 * @retval Interface status (MANDATORY: return 0 -> no Error).
3237 *
3238 */
iis2iclx_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3239 int32_t iis2iclx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3240 {
3241 iis2iclx_wake_up_dur_t wake_up_dur;
3242 int32_t ret;
3243
3244 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3245 (uint8_t *)&wake_up_dur, 1);
3246 *val = wake_up_dur.wake_dur;
3247
3248 return ret;
3249 }
3250
3251 /**
3252 * @}
3253 *
3254 */
3255
3256 /**
3257 * @defgroup IIS2ICLX_ Activity/Inactivity_detection
3258 * @brief This section groups all the functions concerning
3259 * activity/inactivity detection.
3260 * @{
3261 *
3262 */
3263
3264 /**
3265 * @brief Drives the sleep status instead of sleep change on INT pins
3266 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
3267 * are enabled).[set]
3268 *
3269 * @param ctx Read / write interface definitions.(ptr)
3270 * @param val Change the values of sleep_status_on_int in reg TAP_CFG0
3271 * @retval Interface status (MANDATORY: return 0 -> no Error).
3272 *
3273 */
iis2iclx_act_pin_notification_set(stmdev_ctx_t * ctx,iis2iclx_sleep_status_on_int_t val)3274 int32_t iis2iclx_act_pin_notification_set(stmdev_ctx_t *ctx,
3275 iis2iclx_sleep_status_on_int_t val)
3276 {
3277 iis2iclx_tap_cfg0_t tap_cfg0;
3278 int32_t ret;
3279
3280 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3281
3282 if (ret == 0)
3283 {
3284 tap_cfg0. sleep_status_on_int = (uint8_t)val;
3285 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
3286 (uint8_t *)&tap_cfg0, 1);
3287 }
3288
3289 return ret;
3290 }
3291
3292 /**
3293 * @brief Drives the sleep status instead of sleep change on INT pins
3294 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
3295 * are enabled).[get]
3296 *
3297 * @param ctx Read / write interface definitions.(ptr)
3298 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
3299 * @retval Interface status (MANDATORY: return 0 -> no Error).
3300 *
3301 */
iis2iclx_act_pin_notification_get(stmdev_ctx_t * ctx,iis2iclx_sleep_status_on_int_t * val)3302 int32_t iis2iclx_act_pin_notification_get(stmdev_ctx_t *ctx,
3303 iis2iclx_sleep_status_on_int_t *val)
3304 {
3305 iis2iclx_tap_cfg0_t tap_cfg0;
3306 int32_t ret;
3307
3308 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3309
3310 switch (tap_cfg0. sleep_status_on_int)
3311 {
3312 case IIS2ICLX_DRIVE_SLEEP_CHG_EVENT:
3313 *val = IIS2ICLX_DRIVE_SLEEP_CHG_EVENT;
3314 break;
3315
3316 case IIS2ICLX_DRIVE_SLEEP_STATUS:
3317 *val = IIS2ICLX_DRIVE_SLEEP_STATUS;
3318 break;
3319
3320 default:
3321 *val = IIS2ICLX_DRIVE_SLEEP_CHG_EVENT;
3322 break;
3323 }
3324
3325 return ret;
3326 }
3327
3328 /**
3329 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
3330 *
3331 * @param ctx Read / write interface definitions.(ptr)
3332 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
3333 * @retval Interface status (MANDATORY: return 0 -> no Error).
3334 *
3335 */
iis2iclx_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)3336 int32_t iis2iclx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3337 {
3338 iis2iclx_wake_up_dur_t wake_up_dur;
3339 int32_t ret;
3340
3341 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3342 (uint8_t *)&wake_up_dur, 1);
3343
3344 if (ret == 0)
3345 {
3346 wake_up_dur.sleep_dur = (uint8_t)val;
3347 ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3348 (uint8_t *)&wake_up_dur, 1);
3349 }
3350
3351 return ret;
3352 }
3353
3354 /**
3355 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
3356 *
3357 * @param ctx Read / write interface definitions.(ptr)
3358 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
3359 * @retval Interface status (MANDATORY: return 0 -> no Error).
3360 *
3361 */
iis2iclx_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3362 int32_t iis2iclx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3363 {
3364 iis2iclx_wake_up_dur_t wake_up_dur;
3365 int32_t ret;
3366
3367 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_DUR,
3368 (uint8_t *)&wake_up_dur, 1);
3369 *val = wake_up_dur.sleep_dur;
3370
3371 return ret;
3372 }
3373
3374 /**
3375 * @}
3376 *
3377 */
3378
3379 /**
3380 * @defgroup IIS2ICLX_tap_generator
3381 * @brief This section groups all the functions that manage the
3382 * tap and double tap event generation.
3383 * @{
3384 *
3385 */
3386
3387 /**
3388 * @brief Enable Y direction in tap recognition.[set]
3389 *
3390 * @param ctx Read / write interface definitions.(ptr)
3391 * @param val Change the values of tap_y_en in reg TAP_CFG0
3392 * @retval Interface status (MANDATORY: return 0 -> no Error).
3393 *
3394 */
iis2iclx_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)3395 int32_t iis2iclx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
3396 uint8_t val)
3397 {
3398 iis2iclx_tap_cfg0_t tap_cfg0;
3399 int32_t ret;
3400
3401 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3402
3403 if (ret == 0)
3404 {
3405 tap_cfg0.tap_y_en = (uint8_t)val;
3406 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
3407 (uint8_t *)&tap_cfg0, 1);
3408 }
3409
3410 return ret;
3411 }
3412
3413 /**
3414 * @brief Enable Y direction in tap recognition.[get]
3415 *
3416 * @param ctx Read / write interface definitions.(ptr)
3417 * @param val Change the values of tap_y_en in reg TAP_CFG0
3418 * @retval Interface status (MANDATORY: return 0 -> no Error).
3419 *
3420 */
iis2iclx_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)3421 int32_t iis2iclx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
3422 uint8_t *val)
3423 {
3424 iis2iclx_tap_cfg0_t tap_cfg0;
3425 int32_t ret;
3426
3427 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3428 *val = tap_cfg0.tap_y_en;
3429
3430 return ret;
3431 }
3432
3433 /**
3434 * @brief Enable X direction in tap recognition.[set]
3435 *
3436 * @param ctx Read / write interface definitions.(ptr)
3437 * @param val Change the values of tap_x_en in reg TAP_CFG0
3438 * @retval Interface status (MANDATORY: return 0 -> no Error).
3439 *
3440 */
iis2iclx_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)3441 int32_t iis2iclx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
3442 uint8_t val)
3443 {
3444 iis2iclx_tap_cfg0_t tap_cfg0;
3445 int32_t ret;
3446
3447 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3448
3449 if (ret == 0)
3450 {
3451 tap_cfg0.tap_x_en = (uint8_t)val;
3452 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG0,
3453 (uint8_t *)&tap_cfg0, 1);
3454 }
3455
3456 return ret;
3457 }
3458
3459 /**
3460 * @brief Enable X direction in tap recognition.[get]
3461 *
3462 * @param ctx Read / write interface definitions.(ptr)
3463 * @param val Change the values of tap_x_en in reg TAP_CFG0
3464 * @retval Interface status (MANDATORY: return 0 -> no Error).
3465 *
3466 */
iis2iclx_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)3467 int32_t iis2iclx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
3468 uint8_t *val)
3469 {
3470 iis2iclx_tap_cfg0_t tap_cfg0;
3471 int32_t ret;
3472
3473 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3474 *val = tap_cfg0.tap_x_en;
3475
3476 return ret;
3477 }
3478
3479 /**
3480 * @brief X-axis tap recognition threshold.[set]
3481 *
3482 * @param ctx Read / write interface definitions.(ptr)
3483 * @param val Change the values of tap_ths_x in reg TAP_CFG1
3484 * @retval Interface status (MANDATORY: return 0 -> no Error).
3485 *
3486 */
iis2iclx_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)3487 int32_t iis2iclx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
3488 {
3489 iis2iclx_tap_cfg1_t tap_cfg1;
3490 int32_t ret;
3491
3492 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3493
3494 if (ret == 0)
3495 {
3496 tap_cfg1.tap_ths_x = (uint8_t)val;
3497 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG1,
3498 (uint8_t *)&tap_cfg1, 1);
3499 }
3500
3501 return ret;
3502 }
3503
3504 /**
3505 * @brief X-axis tap recognition threshold.[get]
3506 *
3507 * @param ctx Read / write interface definitions.(ptr)
3508 * @param val Change the values of tap_ths_x in reg TAP_CFG1
3509 * @retval Interface status (MANDATORY: return 0 -> no Error).
3510 *
3511 */
iis2iclx_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)3512 int32_t iis2iclx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
3513 {
3514 iis2iclx_tap_cfg1_t tap_cfg1;
3515 int32_t ret;
3516
3517 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3518 *val = tap_cfg1.tap_ths_x;
3519
3520 return ret;
3521 }
3522
3523 /**
3524 * @brief Selection of axis priority for TAP detection.[set]
3525 *
3526 * @param ctx Read / write interface definitions.(ptr)
3527 * @param val Change the values of tap_priority in reg TAP_CFG1
3528 * @retval Interface status (MANDATORY: return 0 -> no Error).
3529 *
3530 */
iis2iclx_tap_axis_priority_set(stmdev_ctx_t * ctx,iis2iclx_tap_priority_t val)3531 int32_t iis2iclx_tap_axis_priority_set(stmdev_ctx_t *ctx,
3532 iis2iclx_tap_priority_t val)
3533 {
3534 iis2iclx_tap_cfg1_t tap_cfg1;
3535 int32_t ret;
3536
3537 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3538
3539 if (ret == 0)
3540 {
3541 tap_cfg1.tap_priority = (uint8_t)val;
3542 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3543 }
3544
3545 return ret;
3546 }
3547
3548 /**
3549 * @brief Selection of axis priority for TAP detection[get]
3550 *
3551 * @param ctx Read / write interface definitions.(ptr)
3552 * @param val Get the values of tap_priority in reg TAP_CFG1
3553 * @retval Interface status (MANDATORY: return 0 -> no Error).
3554 *
3555 */
iis2iclx_tap_axis_priority_get(stmdev_ctx_t * ctx,iis2iclx_tap_priority_t * val)3556 int32_t iis2iclx_tap_axis_priority_get(stmdev_ctx_t *ctx,
3557 iis2iclx_tap_priority_t *val)
3558 {
3559 iis2iclx_tap_cfg1_t tap_cfg1;
3560 int32_t ret;
3561
3562 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
3563
3564 switch (tap_cfg1.tap_priority)
3565 {
3566 case IIS2ICLX_XY:
3567 *val = IIS2ICLX_XY;
3568 break;
3569
3570 case IIS2ICLX_YX:
3571 *val = IIS2ICLX_YX;
3572 break;
3573
3574 default:
3575 *val = IIS2ICLX_XY;
3576 break;
3577 }
3578
3579 return ret;
3580 }
3581
3582 /**
3583 * @brief Y-axis tap recognition threshold.[set]
3584 *
3585 * @param ctx Read / write interface definitions.(ptr)
3586 * @param val Change the values of tap_ths_y in reg TAP_CFG2
3587 * @retval Interface status (MANDATORY: return 0 -> no Error).
3588 *
3589 */
iis2iclx_tap_threshold_y_set(stmdev_ctx_t * ctx,uint8_t val)3590 int32_t iis2iclx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
3591 {
3592 iis2iclx_tap_cfg2_t tap_cfg2;
3593 int32_t ret;
3594
3595 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3596
3597 if (ret == 0)
3598 {
3599 tap_cfg2.tap_ths_y = (uint8_t)val;
3600 ret = iis2iclx_write_reg(ctx, IIS2ICLX_TAP_CFG2,
3601 (uint8_t *)&tap_cfg2, 1);
3602 }
3603
3604 return ret;
3605 }
3606
3607 /**
3608 * @brief Y-axis tap recognition threshold.[get]
3609 *
3610 * @param ctx Read / write interface definitions.(ptr)
3611 * @param val Change the values of tap_ths_y in reg TAP_CFG2
3612 * @retval Interface status (MANDATORY: return 0 -> no Error).
3613 *
3614 */
iis2iclx_tap_threshold_y_get(stmdev_ctx_t * ctx,uint8_t * val)3615 int32_t iis2iclx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
3616 {
3617 iis2iclx_tap_cfg2_t tap_cfg2;
3618 int32_t ret;
3619
3620 ret = iis2iclx_read_reg(ctx, IIS2ICLX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
3621 *val = tap_cfg2.tap_ths_y;
3622
3623 return ret;
3624 }
3625
3626 /**
3627 * @brief Maximum duration is the maximum time of an overthreshold signal
3628 * detection to be recognized as a tap event. The default value of
3629 * these bits is 00b which corresponds to 4*ODR_XL time.
3630 * If the SHOCK[1:0] bits are set to a different value, 1LSB
3631 * corresponds to 8*ODR_XL time.[set]
3632 *
3633 * @param ctx Read / write interface definitions.(ptr)
3634 * @param val Change the values of shock in reg INT_DUR2
3635 * @retval Interface status (MANDATORY: return 0 -> no Error).
3636 *
3637 */
iis2iclx_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)3638 int32_t iis2iclx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
3639 {
3640 iis2iclx_int_dur2_t int_dur2;
3641 int32_t ret;
3642
3643 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
3644
3645 if (ret == 0)
3646 {
3647 int_dur2.shock = (uint8_t)val;
3648 ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT_DUR2,
3649 (uint8_t *)&int_dur2, 1);
3650 }
3651
3652 return ret;
3653 }
3654
3655 /**
3656 * @brief Maximum duration is the maximum time of an overthreshold signal
3657 * detection to be recognized as a tap event. The default value of
3658 * these bits is 00b which corresponds to 4*ODR_XL time.
3659 * If the SHOCK[1:0] bits are set to a different value, 1LSB
3660 * corresponds to 8*ODR_XL time.[get]
3661 *
3662 * @param ctx Read / write interface definitions.(ptr)
3663 * @param val Change the values of shock in reg INT_DUR2
3664 * @retval Interface status (MANDATORY: return 0 -> no Error).
3665 *
3666 */
iis2iclx_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)3667 int32_t iis2iclx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
3668 {
3669 iis2iclx_int_dur2_t int_dur2;
3670 int32_t ret;
3671
3672 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
3673 *val = int_dur2.shock;
3674
3675 return ret;
3676 }
3677
3678 /**
3679 * @brief Quiet time is the time after the first detected tap in which
3680 * there must not be any overthreshold event.
3681 * The default value of these bits is 00b which corresponds to
3682 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
3683 * value, 1LSB corresponds to 4*ODR_XL time.[set]
3684 *
3685 * @param ctx Read / write interface definitions.(ptr)
3686 * @param val Change the values of quiet in reg INT_DUR2
3687 * @retval Interface status (MANDATORY: return 0 -> no Error).
3688 *
3689 */
iis2iclx_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)3690 int32_t iis2iclx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
3691 {
3692 iis2iclx_int_dur2_t int_dur2;
3693 int32_t ret;
3694
3695 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
3696
3697 if (ret == 0)
3698 {
3699 int_dur2.quiet = (uint8_t)val;
3700 ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT_DUR2,
3701 (uint8_t *)&int_dur2, 1);
3702 }
3703
3704 return ret;
3705 }
3706
3707 /**
3708 * @brief Quiet time is the time after the first detected tap in which
3709 * there must not be any overthreshold event.
3710 * The default value of these bits is 00b which corresponds to
3711 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
3712 * value, 1LSB corresponds to 4*ODR_XL time.[get]
3713 *
3714 * @param ctx Read / write interface definitions.(ptr)
3715 * @param val Change the values of quiet in reg INT_DUR2
3716 * @retval Interface status (MANDATORY: return 0 -> no Error).
3717 *
3718 */
iis2iclx_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)3719 int32_t iis2iclx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
3720 {
3721 iis2iclx_int_dur2_t int_dur2;
3722 int32_t ret;
3723
3724 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
3725 *val = int_dur2.quiet;
3726
3727 return ret;
3728 }
3729
3730 /**
3731 * @brief When double tap recognition is enabled, this register expresses
3732 * the maximum time between two consecutive detected taps to
3733 * determine a double tap event.
3734 * The default value of these bits is 0000b which corresponds to
3735 * 16*ODR_XL time.
3736 * If the DUR[3:0] bits are set to a different value, 1LSB
3737 * corresponds to 32*ODR_XL time.[set]
3738 *
3739 * @param ctx Read / write interface definitions.(ptr)
3740 * @param val Change the values of dur in reg INT_DUR2
3741 * @retval Interface status (MANDATORY: return 0 -> no Error).
3742 *
3743 */
iis2iclx_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)3744 int32_t iis2iclx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3745 {
3746 iis2iclx_int_dur2_t int_dur2;
3747 int32_t ret;
3748
3749 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
3750
3751 if (ret == 0)
3752 {
3753 int_dur2.dur = (uint8_t)val;
3754 ret = iis2iclx_write_reg(ctx, IIS2ICLX_INT_DUR2,
3755 (uint8_t *)&int_dur2, 1);
3756 }
3757
3758 return ret;
3759 }
3760
3761 /**
3762 * @brief When double tap recognition is enabled, this register expresses the
3763 * maximum time between two consecutive detected taps to determine
3764 * a double tap event. The default value of these bits is 0000b which
3765 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to
3766 * a different value, 1LSB corresponds to 32*ODR_XL time.[get]
3767 *
3768 * @param ctx Read / write interface definitions.(ptr)
3769 * @param val Change the values of dur in reg INT_DUR2
3770 * @retval Interface status (MANDATORY: return 0 -> no Error).
3771 *
3772 */
iis2iclx_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3773 int32_t iis2iclx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3774 {
3775 iis2iclx_int_dur2_t int_dur2;
3776 int32_t ret;
3777
3778 ret = iis2iclx_read_reg(ctx, IIS2ICLX_INT_DUR2, (uint8_t *)&int_dur2, 1);
3779 *val = int_dur2.dur;
3780
3781 return ret;
3782 }
3783
3784 /**
3785 * @brief Single/double-tap event enable.[set]
3786 *
3787 * @param ctx Read / write interface definitions.(ptr)
3788 * @param val Change the values of single_double_tap in reg WAKE_UP_THS
3789 * @retval Interface status (MANDATORY: return 0 -> no Error).
3790 *
3791 */
iis2iclx_tap_mode_set(stmdev_ctx_t * ctx,iis2iclx_single_double_tap_t val)3792 int32_t iis2iclx_tap_mode_set(stmdev_ctx_t *ctx,
3793 iis2iclx_single_double_tap_t val)
3794 {
3795 iis2iclx_wake_up_ths_t wake_up_ths;
3796 int32_t ret;
3797
3798 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3799 (uint8_t *)&wake_up_ths, 1);
3800
3801 if (ret == 0)
3802 {
3803 wake_up_ths.single_double_tap = (uint8_t)val;
3804 ret = iis2iclx_write_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3805 (uint8_t *)&wake_up_ths, 1);
3806 }
3807
3808 return ret;
3809 }
3810
3811 /**
3812 * @brief Single/double-tap event enable.[get]
3813 *
3814 * @param ctx Read / write interface definitions.(ptr)
3815 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
3816 * @retval Interface status (MANDATORY: return 0 -> no Error).
3817 *
3818 */
iis2iclx_tap_mode_get(stmdev_ctx_t * ctx,iis2iclx_single_double_tap_t * val)3819 int32_t iis2iclx_tap_mode_get(stmdev_ctx_t *ctx,
3820 iis2iclx_single_double_tap_t *val)
3821 {
3822 iis2iclx_wake_up_ths_t wake_up_ths;
3823 int32_t ret;
3824
3825 ret = iis2iclx_read_reg(ctx, IIS2ICLX_WAKE_UP_THS,
3826 (uint8_t *)&wake_up_ths, 1);
3827
3828 switch (wake_up_ths.single_double_tap)
3829 {
3830 case IIS2ICLX_ONLY_SINGLE:
3831 *val = IIS2ICLX_ONLY_SINGLE;
3832 break;
3833
3834 case IIS2ICLX_BOTH_SINGLE_DOUBLE:
3835 *val = IIS2ICLX_BOTH_SINGLE_DOUBLE;
3836 break;
3837
3838 default:
3839 *val = IIS2ICLX_ONLY_SINGLE;
3840 break;
3841 }
3842
3843 return ret;
3844 }
3845
3846 /**
3847 * @}
3848 *
3849 */
3850
3851 /**
3852 * @defgroup IIS2ICLX_fifo
3853 * @brief This section group all the functions concerning
3854 * the fifo usage
3855 * @{
3856 *
3857 */
3858
3859 /**
3860 * @brief FIFO watermark level selection.[set]
3861 *
3862 * @param ctx Read / write interface definitions.(ptr)
3863 * @param val Change the values of wtm in reg FIFO_CTRL1
3864 * @retval Interface status (MANDATORY: return 0 -> no Error).
3865 *
3866 */
iis2iclx_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)3867 int32_t iis2iclx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
3868 {
3869 iis2iclx_fifo_ctrl1_t fifo_ctrl1;
3870 iis2iclx_fifo_ctrl2_t fifo_ctrl2;
3871 int32_t ret;
3872
3873 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3874 (uint8_t *)&fifo_ctrl2, 1);
3875
3876 if (ret == 0)
3877 {
3878 fifo_ctrl1.wtm = (uint8_t)(0x00FFU & val);
3879 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL1,
3880 (uint8_t *)&fifo_ctrl1, 1);
3881 }
3882
3883 if (ret == 0)
3884 {
3885 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
3886 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3887 (uint8_t *)&fifo_ctrl2, 1);
3888 }
3889
3890 return ret;
3891 }
3892
3893 /**
3894 * @brief FIFO watermark level selection.[get]
3895 *
3896 * @param ctx Read / write interface definitions.(ptr)
3897 * @param val Change the values of wtm in reg FIFO_CTRL1
3898 * @retval Interface status (MANDATORY: return 0 -> no Error).
3899 *
3900 */
iis2iclx_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)3901 int32_t iis2iclx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
3902 {
3903 iis2iclx_fifo_ctrl1_t fifo_ctrl1;
3904 iis2iclx_fifo_ctrl2_t fifo_ctrl2;
3905 int32_t ret;
3906
3907 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3908 (uint8_t *)&fifo_ctrl2, 1);
3909
3910 if (ret == 0)
3911 {
3912 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL1,
3913 (uint8_t *)&fifo_ctrl1, 1);
3914 }
3915
3916 *val = fifo_ctrl2.wtm;
3917 *val = *val << 8;
3918 *val += fifo_ctrl1.wtm;
3919
3920 return ret;
3921 }
3922
3923 /**
3924 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
3925 *
3926 * @param ctx Read / write interface definitions.(ptr)
3927 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
3928 * @retval Interface status (MANDATORY: return 0 -> no Error).
3929 *
3930 */
iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)3931 int32_t iis2iclx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
3932 uint8_t val)
3933 {
3934 iis2iclx_fifo_ctrl2_t fifo_ctrl2;
3935 int32_t ret;
3936
3937 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3938 (uint8_t *)&fifo_ctrl2, 1);
3939
3940 if (ret == 0)
3941 {
3942 fifo_ctrl2.odrchg_en = (uint8_t)val;
3943 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3944 (uint8_t *)&fifo_ctrl2, 1);
3945 }
3946
3947 return ret;
3948 }
3949
3950 /**
3951 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
3952 *
3953 * @param ctx Read / write interface definitions.(ptr)
3954 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
3955 * @retval Interface status (MANDATORY: return 0 -> no Error).
3956 *
3957 */
iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)3958 int32_t iis2iclx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
3959 uint8_t *val)
3960 {
3961 iis2iclx_fifo_ctrl2_t fifo_ctrl2;
3962 int32_t ret;
3963
3964 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3965 (uint8_t *)&fifo_ctrl2, 1);
3966 *val = fifo_ctrl2.odrchg_en;
3967
3968 return ret;
3969 }
3970
3971 /**
3972 * @brief Sensing chain FIFO stop values memorization at threshold
3973 * level.[set]
3974 *
3975 * @param ctx Read / write interface definitions.(ptr)
3976 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
3977 * @retval Interface status (MANDATORY: return 0 -> no Error).
3978 *
3979 */
iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)3980 int32_t iis2iclx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
3981 {
3982 iis2iclx_fifo_ctrl2_t fifo_ctrl2;
3983 int32_t ret;
3984
3985 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3986 (uint8_t *)&fifo_ctrl2, 1);
3987
3988 if (ret == 0)
3989 {
3990 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
3991 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL2,
3992 (uint8_t *)&fifo_ctrl2, 1);
3993 }
3994
3995 return ret;
3996 }
3997
3998 /**
3999 * @brief Sensing chain FIFO stop values memorization at threshold
4000 * level.[get]
4001 *
4002 * @param ctx Read / write interface definitions.(ptr)
4003 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
4004 * @retval Interface status (MANDATORY: return 0 -> no Error).
4005 *
4006 */
iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)4007 int32_t iis2iclx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
4008 {
4009 iis2iclx_fifo_ctrl2_t fifo_ctrl2;
4010 int32_t ret;
4011
4012 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL2,
4013 (uint8_t *)&fifo_ctrl2, 1);
4014 *val = fifo_ctrl2.stop_on_wtm;
4015
4016 return ret;
4017 }
4018
4019 /**
4020 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4021 * for accelerometer data.[set]
4022 *
4023 * @param ctx Read / write interface definitions.(ptr)
4024 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
4025 * @retval Interface status (MANDATORY: return 0 -> no Error).
4026 *
4027 */
iis2iclx_fifo_xl_batch_set(stmdev_ctx_t * ctx,iis2iclx_bdr_xl_t val)4028 int32_t iis2iclx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
4029 iis2iclx_bdr_xl_t val)
4030 {
4031 iis2iclx_fifo_ctrl3_t fifo_ctrl3;
4032 int32_t ret;
4033
4034 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL3,
4035 (uint8_t *)&fifo_ctrl3, 1);
4036
4037 if (ret == 0)
4038 {
4039 fifo_ctrl3.bdr_xl = (uint8_t)val;
4040 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL3,
4041 (uint8_t *)&fifo_ctrl3, 1);
4042 }
4043
4044 return ret;
4045 }
4046
4047 /**
4048 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4049 * for accelerometer data.[get]
4050 *
4051 * @param ctx Read / write interface definitions.(ptr)
4052 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
4053 * @retval Interface status (MANDATORY: return 0 -> no Error).
4054 *
4055 */
iis2iclx_fifo_xl_batch_get(stmdev_ctx_t * ctx,iis2iclx_bdr_xl_t * val)4056 int32_t iis2iclx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
4057 iis2iclx_bdr_xl_t *val)
4058 {
4059 iis2iclx_fifo_ctrl3_t fifo_ctrl3;
4060 int32_t ret;
4061
4062 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL3,
4063 (uint8_t *)&fifo_ctrl3, 1);
4064
4065 switch (fifo_ctrl3.bdr_xl)
4066 {
4067 case IIS2ICLX_XL_NOT_BATCHED:
4068 *val = IIS2ICLX_XL_NOT_BATCHED;
4069 break;
4070
4071 case IIS2ICLX_XL_BATCHED_AT_1Hz6:
4072 *val = IIS2ICLX_XL_BATCHED_AT_1Hz6;
4073 break;
4074
4075 case IIS2ICLX_XL_BATCHED_AT_12Hz5:
4076 *val = IIS2ICLX_XL_BATCHED_AT_12Hz5;
4077 break;
4078
4079 case IIS2ICLX_XL_BATCHED_AT_26Hz:
4080 *val = IIS2ICLX_XL_BATCHED_AT_26Hz;
4081 break;
4082
4083 case IIS2ICLX_XL_BATCHED_AT_52Hz:
4084 *val = IIS2ICLX_XL_BATCHED_AT_52Hz;
4085 break;
4086
4087 case IIS2ICLX_XL_BATCHED_AT_104Hz:
4088 *val = IIS2ICLX_XL_BATCHED_AT_104Hz;
4089 break;
4090
4091 case IIS2ICLX_XL_BATCHED_AT_208Hz:
4092 *val = IIS2ICLX_XL_BATCHED_AT_208Hz;
4093 break;
4094
4095 case IIS2ICLX_XL_BATCHED_AT_417Hz:
4096 *val = IIS2ICLX_XL_BATCHED_AT_417Hz;
4097 break;
4098
4099 case IIS2ICLX_XL_BATCHED_AT_833Hz:
4100 *val = IIS2ICLX_XL_BATCHED_AT_833Hz;
4101 break;
4102
4103 default:
4104 *val = IIS2ICLX_XL_NOT_BATCHED;
4105 break;
4106 }
4107
4108 return ret;
4109 }
4110
4111 /**
4112 * @brief FIFO mode selection.[set]
4113 *
4114 * @param ctx Read / write interface definitions.(ptr)
4115 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
4116 * @retval Interface status (MANDATORY: return 0 -> no Error).
4117 *
4118 */
iis2iclx_fifo_mode_set(stmdev_ctx_t * ctx,iis2iclx_fifo_mode_t val)4119 int32_t iis2iclx_fifo_mode_set(stmdev_ctx_t *ctx,
4120 iis2iclx_fifo_mode_t val)
4121 {
4122 iis2iclx_fifo_ctrl4_t fifo_ctrl4;
4123 int32_t ret;
4124
4125 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4126 (uint8_t *)&fifo_ctrl4, 1);
4127
4128 if (ret == 0)
4129 {
4130 fifo_ctrl4.fifo_mode = (uint8_t)val;
4131 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4132 (uint8_t *)&fifo_ctrl4, 1);
4133 }
4134
4135 return ret;
4136 }
4137
4138 /**
4139 * @brief FIFO mode selection.[get]
4140 *
4141 * @param ctx Read / write interface definitions.(ptr)
4142 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
4143 * @retval Interface status (MANDATORY: return 0 -> no Error).
4144 *
4145 */
iis2iclx_fifo_mode_get(stmdev_ctx_t * ctx,iis2iclx_fifo_mode_t * val)4146 int32_t iis2iclx_fifo_mode_get(stmdev_ctx_t *ctx,
4147 iis2iclx_fifo_mode_t *val)
4148 {
4149 iis2iclx_fifo_ctrl4_t fifo_ctrl4;
4150 int32_t ret;
4151
4152 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4153 (uint8_t *)&fifo_ctrl4, 1);
4154
4155 switch (fifo_ctrl4.fifo_mode)
4156 {
4157 case IIS2ICLX_BYPASS_MODE:
4158 *val = IIS2ICLX_BYPASS_MODE;
4159 break;
4160
4161 case IIS2ICLX_FIFO_MODE:
4162 *val = IIS2ICLX_FIFO_MODE;
4163 break;
4164
4165 case IIS2ICLX_STREAM_TO_FIFO_MODE:
4166 *val = IIS2ICLX_STREAM_TO_FIFO_MODE;
4167 break;
4168
4169 case IIS2ICLX_BYPASS_TO_STREAM_MODE:
4170 *val = IIS2ICLX_BYPASS_TO_STREAM_MODE;
4171 break;
4172
4173 case IIS2ICLX_STREAM_MODE:
4174 *val = IIS2ICLX_STREAM_MODE;
4175 break;
4176
4177 case IIS2ICLX_BYPASS_TO_FIFO_MODE:
4178 *val = IIS2ICLX_BYPASS_TO_FIFO_MODE;
4179 break;
4180
4181 default:
4182 *val = IIS2ICLX_BYPASS_MODE;
4183 break;
4184 }
4185
4186 return ret;
4187 }
4188
4189 /**
4190 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4191 * for temperature data.[set]
4192 *
4193 * @param ctx Read / write interface definitions.(ptr)
4194 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
4195 * @retval Interface status (MANDATORY: return 0 -> no Error).
4196 *
4197 */
iis2iclx_fifo_temp_batch_set(stmdev_ctx_t * ctx,iis2iclx_odr_t_batch_t val)4198 int32_t iis2iclx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
4199 iis2iclx_odr_t_batch_t val)
4200 {
4201 iis2iclx_fifo_ctrl4_t fifo_ctrl4;
4202 int32_t ret;
4203
4204 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4205 (uint8_t *)&fifo_ctrl4, 1);
4206
4207 if (ret == 0)
4208 {
4209 fifo_ctrl4.odr_t_batch = (uint8_t)val;
4210 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4211 (uint8_t *)&fifo_ctrl4, 1);
4212 }
4213
4214 return ret;
4215 }
4216
4217 /**
4218 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4219 * for temperature data.[get]
4220 *
4221 * @param ctx Read / write interface definitions.(ptr)
4222 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
4223 * @retval Interface status (MANDATORY: return 0 -> no Error).
4224 *
4225 */
iis2iclx_fifo_temp_batch_get(stmdev_ctx_t * ctx,iis2iclx_odr_t_batch_t * val)4226 int32_t iis2iclx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
4227 iis2iclx_odr_t_batch_t *val)
4228 {
4229 iis2iclx_fifo_ctrl4_t fifo_ctrl4;
4230 int32_t ret;
4231
4232 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4233 (uint8_t *)&fifo_ctrl4, 1);
4234
4235 switch (fifo_ctrl4.odr_t_batch)
4236 {
4237 case IIS2ICLX_TEMP_NOT_BATCHED:
4238 *val = IIS2ICLX_TEMP_NOT_BATCHED;
4239 break;
4240
4241 case IIS2ICLX_TEMP_BATCHED_AT_1Hz6:
4242 *val = IIS2ICLX_TEMP_BATCHED_AT_1Hz6;
4243 break;
4244
4245 case IIS2ICLX_TEMP_BATCHED_AT_52Hz:
4246 *val = IIS2ICLX_TEMP_BATCHED_AT_52Hz;
4247 break;
4248
4249 case IIS2ICLX_TEMP_BATCHED_AT_12Hz5:
4250 *val = IIS2ICLX_TEMP_BATCHED_AT_12Hz5;
4251 break;
4252
4253 default:
4254 *val = IIS2ICLX_TEMP_NOT_BATCHED;
4255 break;
4256 }
4257
4258 return ret;
4259 }
4260
4261 /**
4262 * @brief Selects decimation for timestamp batching in FIFO.
4263 * Writing rate will be the maximum rate between XL and
4264 * GYRO BDR divided by decimation decoder.[set]
4265 *
4266 * @param ctx Read / write interface definitions.(ptr)
4267 * @param val Change the values of odr_ts_batch in reg FIFO_CTRL4
4268 * @retval Interface status (MANDATORY: return 0 -> no Error).
4269 *
4270 */
iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t * ctx,iis2iclx_odr_ts_batch_t val)4271 int32_t iis2iclx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
4272 iis2iclx_odr_ts_batch_t val)
4273 {
4274 iis2iclx_fifo_ctrl4_t fifo_ctrl4;
4275 int32_t ret;
4276
4277 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4278 (uint8_t *)&fifo_ctrl4, 1);
4279
4280 if (ret == 0)
4281 {
4282 fifo_ctrl4.odr_ts_batch = (uint8_t)val;
4283 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4284 (uint8_t *)&fifo_ctrl4, 1);
4285 }
4286
4287 return ret;
4288 }
4289
4290 /**
4291 * @brief Selects decimation for timestamp batching in FIFO.
4292 * Writing rate will be the maximum rate between XL and
4293 * GYRO BDR divided by decimation decoder.[get]
4294 *
4295 * @param ctx Read / write interface definitions.(ptr)
4296 * @param val Get the values of odr_ts_batch in reg
4297 * FIFO_CTRL4
4298 * @retval Interface status (MANDATORY: return 0 -> no Error).
4299 *
4300 */
iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t * ctx,iis2iclx_odr_ts_batch_t * val)4301 int32_t iis2iclx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
4302 iis2iclx_odr_ts_batch_t *val)
4303 {
4304 iis2iclx_fifo_ctrl4_t fifo_ctrl4;
4305 int32_t ret;
4306
4307 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_CTRL4,
4308 (uint8_t *)&fifo_ctrl4, 1);
4309
4310 switch (fifo_ctrl4.odr_ts_batch)
4311 {
4312 case IIS2ICLX_NO_DECIMATION:
4313 *val = IIS2ICLX_NO_DECIMATION;
4314 break;
4315
4316 case IIS2ICLX_DEC_1:
4317 *val = IIS2ICLX_DEC_1;
4318 break;
4319
4320 case IIS2ICLX_DEC_8:
4321 *val = IIS2ICLX_DEC_8;
4322 break;
4323
4324 case IIS2ICLX_DEC_32:
4325 *val = IIS2ICLX_DEC_32;
4326 break;
4327
4328 default:
4329 *val = IIS2ICLX_NO_DECIMATION;
4330 break;
4331 }
4332
4333 return ret;
4334 }
4335
4336 /**
4337 * @brief Resets the internal counter of batching events for a single sensor.
4338 * This bit is automatically reset to zero if it was set to ‘1’.[set]
4339 *
4340 * @param ctx Read / write interface definitions.(ptr)
4341 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
4342 * @retval Interface status (MANDATORY: return 0 -> no Error).
4343 *
4344 */
iis2iclx_rst_batch_counter_set(stmdev_ctx_t * ctx,uint8_t val)4345 int32_t iis2iclx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
4346 {
4347 iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
4348 int32_t ret;
4349
4350 ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
4351 (uint8_t *)&counter_bdr_reg1, 1);
4352
4353 if (ret == 0)
4354 {
4355 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
4356 ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
4357 (uint8_t *)&counter_bdr_reg1, 1);
4358 }
4359
4360 return ret;
4361 }
4362
4363 /**
4364 * @brief Resets the internal counter of batching events for a single sensor.
4365 * This bit is automatically reset to zero if it was set to ‘1’.[get]
4366 *
4367 * @param ctx Read / write interface definitions.(ptr)
4368 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
4369 * @retval Interface status (MANDATORY: return 0 -> no Error).
4370 *
4371 */
iis2iclx_rst_batch_counter_get(stmdev_ctx_t * ctx,uint8_t * val)4372 int32_t iis2iclx_rst_batch_counter_get(stmdev_ctx_t *ctx,
4373 uint8_t *val)
4374 {
4375 iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
4376 int32_t ret;
4377
4378 ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
4379 (uint8_t *)&counter_bdr_reg1, 1);
4380 *val = counter_bdr_reg1.rst_counter_bdr;
4381
4382 return ret;
4383 }
4384
4385 /**
4386 * @brief Batch data rate counter.[set]
4387 *
4388 * @param ctx Read / write interface definitions.(ptr)
4389 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
4390 * and COUNTER_BDR_REG1.
4391 * @retval Interface status (MANDATORY: return 0 -> no Error).
4392 *
4393 */
iis2iclx_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)4394 int32_t iis2iclx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
4395 uint16_t val)
4396 {
4397 iis2iclx_counter_bdr_reg2_t counter_bdr_reg1;
4398 iis2iclx_counter_bdr_reg2_t counter_bdr_reg2;
4399 int32_t ret;
4400
4401 ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
4402 (uint8_t *)&counter_bdr_reg1, 1);
4403
4404 if (ret == 0)
4405 {
4406 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((0x0700U & val) >> 8);
4407 ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
4408 (uint8_t *)&counter_bdr_reg1, 1);
4409 }
4410
4411 if (ret == 0)
4412 {
4413 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(0x00FFU & val);
4414 ret = iis2iclx_write_reg(ctx, IIS2ICLX_COUNTER_BDR_REG2,
4415 (uint8_t *)&counter_bdr_reg2, 1);
4416 }
4417
4418 return ret;
4419 }
4420
4421 /**
4422 * @brief Batch data rate counter.[get]
4423 *
4424 * @param ctx Read / write interface definitions.(ptr)
4425 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
4426 * and COUNTER_BDR_REG1.
4427 * @retval Interface status (MANDATORY: return 0 -> no Error).
4428 *
4429 */
iis2iclx_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)4430 int32_t iis2iclx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
4431 uint16_t *val)
4432 {
4433 iis2iclx_counter_bdr_reg1_t counter_bdr_reg1;
4434 iis2iclx_counter_bdr_reg2_t counter_bdr_reg2;
4435 int32_t ret;
4436
4437 ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG1,
4438 (uint8_t *)&counter_bdr_reg1, 1);
4439
4440 if (ret == 0)
4441 {
4442 ret = iis2iclx_read_reg(ctx, IIS2ICLX_COUNTER_BDR_REG2,
4443 (uint8_t *)&counter_bdr_reg2, 1);
4444 }
4445
4446 *val = counter_bdr_reg1.cnt_bdr_th;
4447 *val = *val << 8;
4448 *val += counter_bdr_reg2.cnt_bdr_th;
4449
4450 return ret;
4451 }
4452
4453 /**
4454 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
4455 *
4456 * @param ctx Read / write interface definitions.(ptr)
4457 * @param val Change the values of diff_fifo in reg FIFO_STATUS1
4458 * @retval Interface status (MANDATORY: return 0 -> no Error).
4459 *
4460 */
iis2iclx_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)4461 int32_t iis2iclx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
4462 {
4463 iis2iclx_fifo_status1_t fifo_status1;
4464 iis2iclx_fifo_status2_t fifo_status2;
4465 int32_t ret;
4466
4467 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS1,
4468 (uint8_t *)&fifo_status1, 1);
4469
4470 if (ret == 0)
4471 {
4472 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
4473 (uint8_t *)&fifo_status2, 1);
4474 *val = fifo_status2.diff_fifo;
4475 *val = *val << 8;
4476 *val += fifo_status1.diff_fifo;
4477 }
4478
4479 return ret;
4480 }
4481
4482 /**
4483 * @brief Smart FIFO status.[get]
4484 *
4485 * @param ctx Read / write interface definitions.(ptr)
4486 * @param val Registers FIFO_STATUS2
4487 * @retval Interface status (MANDATORY: return 0 -> no Error).
4488 *
4489 */
iis2iclx_fifo_status_get(stmdev_ctx_t * ctx,iis2iclx_fifo_status2_t * val)4490 int32_t iis2iclx_fifo_status_get(stmdev_ctx_t *ctx,
4491 iis2iclx_fifo_status2_t *val)
4492 {
4493 int32_t ret;
4494
4495 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2, (uint8_t *)val, 1);
4496
4497 return ret;
4498 }
4499
4500 /**
4501 * @brief Smart FIFO full status.[get]
4502 *
4503 * @param ctx Read / write interface definitions.(ptr)
4504 * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2
4505 * @retval Interface status (MANDATORY: return 0 -> no Error).
4506 *
4507 */
iis2iclx_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)4508 int32_t iis2iclx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
4509 {
4510 iis2iclx_fifo_status2_t fifo_status2;
4511 int32_t ret;
4512
4513 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
4514 (uint8_t *)&fifo_status2, 1);
4515 *val = fifo_status2.fifo_full_ia;
4516
4517 return ret;
4518 }
4519
4520 /**
4521 * @brief FIFO overrun status.[get]
4522 *
4523 * @param ctx Read / write interface definitions.(ptr)
4524 * @param val Change the values of fifo_over_run_latched in
4525 * reg FIFO_STATUS2
4526 * @retval Interface status (MANDATORY: return 0 -> no Error).
4527 *
4528 */
iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)4529 int32_t iis2iclx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
4530 {
4531 iis2iclx_fifo_status2_t fifo_status2;
4532 int32_t ret;
4533
4534 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
4535 (uint8_t *)&fifo_status2, 1);
4536 *val = fifo_status2. fifo_ovr_ia;
4537
4538 return ret;
4539 }
4540
4541 /**
4542 * @brief FIFO watermark status.[get]
4543 *
4544 * @param ctx Read / write interface definitions.(ptr)
4545 * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2
4546 * @retval Interface status (MANDATORY: return 0 -> no Error).
4547 *
4548 */
iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)4549 int32_t iis2iclx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
4550 {
4551 iis2iclx_fifo_status2_t fifo_status2;
4552 int32_t ret;
4553
4554 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_STATUS2,
4555 (uint8_t *)&fifo_status2, 1);
4556 *val = fifo_status2.fifo_wtm_ia;
4557
4558 return ret;
4559 }
4560
4561 /**
4562 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
4563 *
4564 * @param ctx Read / write interface definitions.(ptr)
4565 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
4566 * @retval Interface status (MANDATORY: return 0 -> no Error).
4567 *
4568 */
iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t * ctx,iis2iclx_fifo_tag_t * val)4569 int32_t iis2iclx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
4570 iis2iclx_fifo_tag_t *val)
4571 {
4572 iis2iclx_fifo_data_out_tag_t fifo_data_out_tag;
4573 int32_t ret;
4574
4575 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FIFO_DATA_OUT_TAG,
4576 (uint8_t *)&fifo_data_out_tag, 1);
4577
4578 switch (fifo_data_out_tag.tag_sensor)
4579 {
4580 case IIS2ICLX_XL_NC_TAG:
4581 *val = IIS2ICLX_XL_NC_TAG;
4582 break;
4583
4584 case IIS2ICLX_TEMPERATURE_TAG:
4585 *val = IIS2ICLX_TEMPERATURE_TAG;
4586 break;
4587
4588 case IIS2ICLX_TIMESTAMP_TAG:
4589 *val = IIS2ICLX_TIMESTAMP_TAG;
4590 break;
4591
4592 case IIS2ICLX_CFG_CHANGE_TAG:
4593 *val = IIS2ICLX_CFG_CHANGE_TAG;
4594 break;
4595
4596 case IIS2ICLX_SENSORHUB_SLAVE0_TAG:
4597 *val = IIS2ICLX_SENSORHUB_SLAVE0_TAG;
4598 break;
4599
4600 case IIS2ICLX_SENSORHUB_SLAVE1_TAG:
4601 *val = IIS2ICLX_SENSORHUB_SLAVE1_TAG;
4602 break;
4603
4604 case IIS2ICLX_SENSORHUB_SLAVE2_TAG:
4605 *val = IIS2ICLX_SENSORHUB_SLAVE2_TAG;
4606 break;
4607
4608 case IIS2ICLX_SENSORHUB_SLAVE3_TAG:
4609 *val = IIS2ICLX_SENSORHUB_SLAVE3_TAG;
4610 break;
4611
4612 case IIS2ICLX_SENSORHUB_NACK_TAG:
4613 *val = IIS2ICLX_SENSORHUB_NACK_TAG;
4614 break;
4615
4616 default:
4617 *val = IIS2ICLX_SENSORHUB_NACK_TAG;
4618 break;
4619 }
4620
4621 return ret;
4622 }
4623
4624 /**
4625 * @brief Enable FIFO batching data of first slave.[set]
4626 *
4627 * @param ctx Read / write interface definitions.(ptr)
4628 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
4629 * @retval Interface status (MANDATORY: return 0 -> no Error).
4630 *
4631 */
iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t * ctx,uint8_t val)4632 int32_t iis2iclx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
4633 {
4634 iis2iclx_slv0_config_t slv0_config;
4635 int32_t ret;
4636
4637 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4638
4639 if (ret == 0)
4640 {
4641 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
4642 (uint8_t *)&slv0_config, 1);
4643 }
4644
4645 if (ret == 0)
4646 {
4647 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
4648 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_CONFIG,
4649 (uint8_t *)&slv0_config, 1);
4650 }
4651
4652 if (ret == 0)
4653 {
4654 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4655 }
4656
4657 return ret;
4658 }
4659
4660 /**
4661 * @brief Enable FIFO batching data of first slave.[get]
4662 *
4663 * @param ctx Read / write interface definitions.(ptr)
4664 * @param val Change the values of batch_ext_sens_0_en in
4665 * reg SLV0_CONFIG
4666 * @retval Interface status (MANDATORY: return 0 -> no Error).
4667 *
4668 */
iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t * ctx,uint8_t * val)4669 int32_t iis2iclx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
4670 {
4671 iis2iclx_slv0_config_t slv0_config;
4672 int32_t ret;
4673
4674 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4675
4676 if (ret == 0)
4677 {
4678 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
4679 (uint8_t *)&slv0_config, 1);
4680 }
4681
4682 if (ret == 0)
4683 {
4684 *val = slv0_config. batch_ext_sens_0_en;
4685 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4686 }
4687
4688 return ret;
4689 }
4690
4691 /**
4692 * @brief Enable FIFO batching data of second slave.[set]
4693 *
4694 * @param ctx Read / write interface definitions.(ptr)
4695 * @param val Change the values of batch_ext_sens_1_en in
4696 * reg SLV1_CONFIG
4697 * @retval Interface status (MANDATORY: return 0 -> no Error).
4698 *
4699 */
iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t * ctx,uint8_t val)4700 int32_t iis2iclx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
4701 {
4702 iis2iclx_slv1_config_t slv1_config;
4703 int32_t ret;
4704
4705 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4706
4707 if (ret == 0)
4708 {
4709 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV1_CONFIG,
4710 (uint8_t *)&slv1_config, 1);
4711 }
4712
4713 if (ret == 0)
4714 {
4715 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
4716 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_CONFIG,
4717 (uint8_t *)&slv1_config, 1);
4718 }
4719
4720 if (ret == 0)
4721 {
4722 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4723 }
4724
4725 return ret;
4726 }
4727
4728 /**
4729 * @brief Enable FIFO batching data of second slave.[get]
4730 *
4731 * @param ctx Read / write interface definitions.(ptr)
4732 * @param val Change the values of batch_ext_sens_1_en in
4733 * reg SLV1_CONFIG
4734 * @retval Interface status (MANDATORY: return 0 -> no Error).
4735 *
4736 */
iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t * ctx,uint8_t * val)4737 int32_t iis2iclx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
4738 {
4739 iis2iclx_slv1_config_t slv1_config;
4740 int32_t ret;
4741
4742 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4743
4744 if (ret == 0)
4745 {
4746 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV1_CONFIG,
4747 (uint8_t *)&slv1_config, 1);
4748 *val = slv1_config. batch_ext_sens_1_en;
4749 }
4750
4751 if (ret == 0)
4752 {
4753 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4754 }
4755
4756 return ret;
4757 }
4758
4759 /**
4760 * @brief Enable FIFO batching data of third slave.[set]
4761 *
4762 * @param ctx Read / write interface definitions.(ptr)
4763 * @param val Change the values of batch_ext_sens_2_en in
4764 * reg SLV2_CONFIG
4765 * @retval Interface status (MANDATORY: return 0 -> no Error).
4766 *
4767 */
iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t * ctx,uint8_t val)4768 int32_t iis2iclx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
4769 {
4770 iis2iclx_slv2_config_t slv2_config;
4771 int32_t ret;
4772
4773 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4774
4775 if (ret == 0)
4776 {
4777 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV2_CONFIG,
4778 (uint8_t *)&slv2_config, 1);
4779 }
4780
4781 if (ret == 0)
4782 {
4783 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
4784 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_CONFIG,
4785 (uint8_t *)&slv2_config, 1);
4786 }
4787
4788 if (ret == 0)
4789 {
4790 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4791 }
4792
4793 return ret;
4794 }
4795
4796 /**
4797 * @brief Enable FIFO batching data of third slave.[get]
4798 *
4799 * @param ctx Read / write interface definitions.(ptr)
4800 * @param val Change the values of batch_ext_sens_2_en in
4801 * reg SLV2_CONFIG
4802 * @retval Interface status (MANDATORY: return 0 -> no Error).
4803 *
4804 */
iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t * ctx,uint8_t * val)4805 int32_t iis2iclx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
4806 {
4807 iis2iclx_slv2_config_t slv2_config;
4808 int32_t ret;
4809
4810 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4811
4812 if (ret == 0)
4813 {
4814 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV2_CONFIG,
4815 (uint8_t *)&slv2_config, 1);
4816 }
4817
4818 if (ret == 0)
4819 {
4820 *val = slv2_config. batch_ext_sens_2_en;
4821 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4822 }
4823
4824 return ret;
4825 }
4826
4827 /**
4828 * @brief Enable FIFO batching data of fourth slave.[set]
4829 *
4830 * @param ctx Read / write interface definitions.(ptr)
4831 * @param val Change the values of batch_ext_sens_3_en in
4832 * reg SLV3_CONFIG
4833 * @retval Interface status (MANDATORY: return 0 -> no Error).
4834 *
4835 */
iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t * ctx,uint8_t val)4836 int32_t iis2iclx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
4837 {
4838 iis2iclx_slv3_config_t slv3_config;
4839 int32_t ret;
4840
4841 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4842
4843 if (ret == 0)
4844 {
4845 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV3_CONFIG,
4846 (uint8_t *)&slv3_config, 1);
4847 }
4848
4849 if (ret == 0)
4850 {
4851 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
4852 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_CONFIG,
4853 (uint8_t *)&slv3_config, 1);
4854 }
4855
4856 if (ret == 0)
4857 {
4858 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4859 }
4860
4861 return ret;
4862 }
4863
4864 /**
4865 * @brief Enable FIFO batching data of fourth slave.[get]
4866 *
4867 * @param ctx Read / write interface definitions.(ptr)
4868 * @param val Change the values of batch_ext_sens_3_en in
4869 * reg SLV3_CONFIG
4870 * @retval Interface status (MANDATORY: return 0 -> no Error).
4871 *
4872 */
iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t * ctx,uint8_t * val)4873 int32_t iis2iclx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
4874 {
4875 iis2iclx_slv3_config_t slv3_config;
4876 int32_t ret;
4877
4878 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
4879
4880 if (ret == 0)
4881 {
4882 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV3_CONFIG,
4883 (uint8_t *)&slv3_config, 1);
4884 *val = slv3_config. batch_ext_sens_3_en;
4885 }
4886
4887 if (ret == 0)
4888 {
4889 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
4890 }
4891
4892 return ret;
4893 }
4894
4895 /**
4896 * @}
4897 *
4898 */
4899
4900 /**
4901 * @defgroup IIS2ICLX_DEN_functionality
4902 * @brief This section groups all the functions concerning
4903 * DEN functionality.
4904 * @{
4905 *
4906 */
4907
4908 /**
4909 * @brief DEN functionality marking mode.[set]
4910 *
4911 * @param ctx Read / write interface definitions.(ptr)
4912 * @param val Change the values of den_mode in reg CTRL6_C
4913 * @retval Interface status (MANDATORY: return 0 -> no Error).
4914 *
4915 */
iis2iclx_den_mode_set(stmdev_ctx_t * ctx,iis2iclx_den_mode_t val)4916 int32_t iis2iclx_den_mode_set(stmdev_ctx_t *ctx,
4917 iis2iclx_den_mode_t val)
4918 {
4919 iis2iclx_ctrl6_c_t ctrl6_c;
4920 iis2iclx_ctrl9_xl_t ctrl9_xl;
4921 int32_t ret;
4922
4923 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4924
4925 if (ret == 0)
4926 {
4927 ctrl9_xl.den_en = ((uint8_t)val & 0x70U) >> 4;
4928 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL,
4929 (uint8_t *)&ctrl9_xl, 1);
4930 }
4931
4932 if (ret == 0)
4933 {
4934 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
4935 }
4936
4937 if (ret == 0)
4938 {
4939 ctrl6_c.den_mode = (uint8_t)val & 0x07U;
4940 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
4941 }
4942
4943 return ret;
4944 }
4945
4946 /**
4947 * @brief DEN functionality marking mode.[get]
4948 *
4949 * @param ctx Read / write interface definitions.(ptr)
4950 * @param val Get the values of den_mode in reg CTRL6_C
4951 * @retval Interface status (MANDATORY: return 0 -> no Error).
4952 *
4953 */
iis2iclx_den_mode_get(stmdev_ctx_t * ctx,iis2iclx_den_mode_t * val)4954 int32_t iis2iclx_den_mode_get(stmdev_ctx_t *ctx,
4955 iis2iclx_den_mode_t *val)
4956 {
4957 iis2iclx_ctrl6_c_t ctrl6_c;
4958 iis2iclx_ctrl9_xl_t ctrl9_xl;
4959 int32_t ret;
4960
4961 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
4962
4963 if (ret == 0)
4964 {
4965 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4966 }
4967
4968 switch ((ctrl9_xl.den_en << 4) + ctrl6_c.den_mode)
4969 {
4970 case IIS2ICLX_DEN_DISABLE:
4971 *val = IIS2ICLX_DEN_DISABLE;
4972 break;
4973
4974 case IIS2ICLX_LEVEL_FIFO:
4975 *val = IIS2ICLX_LEVEL_FIFO;
4976 break;
4977
4978 case IIS2ICLX_LEVEL_LETCHED:
4979 *val = IIS2ICLX_LEVEL_LETCHED;
4980 break;
4981
4982 case IIS2ICLX_LEVEL_TRIGGER:
4983 *val = IIS2ICLX_LEVEL_TRIGGER;
4984 break;
4985
4986 case IIS2ICLX_EDGE_TRIGGER:
4987 *val = IIS2ICLX_EDGE_TRIGGER;
4988 break;
4989
4990 default:
4991 *val = IIS2ICLX_DEN_DISABLE;
4992 break;
4993 }
4994
4995 return ret;
4996 }
4997
4998 /**
4999 * @brief DEN active level configuration.[set]
5000 *
5001 * @param ctx Read / write interface definitions.(ptr)
5002 * @param val Change the values of den_lh in reg CTRL9_XL
5003 * @retval Interface status (MANDATORY: return 0 -> no Error).
5004 *
5005 */
iis2iclx_den_polarity_set(stmdev_ctx_t * ctx,iis2iclx_den_lh_t val)5006 int32_t iis2iclx_den_polarity_set(stmdev_ctx_t *ctx,
5007 iis2iclx_den_lh_t val)
5008 {
5009 iis2iclx_ctrl9_xl_t ctrl9_xl;
5010 int32_t ret;
5011
5012 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5013
5014 if (ret == 0)
5015 {
5016 ctrl9_xl.den_lh = (uint8_t)val;
5017 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL,
5018 (uint8_t *)&ctrl9_xl, 1);
5019 }
5020
5021 return ret;
5022 }
5023
5024 /**
5025 * @brief DEN active level configuration.[get]
5026 *
5027 * @param ctx Read / write interface definitions.(ptr)
5028 * @param val Get the values of den_lh in reg CTRL9_XL
5029 * @retval Interface status (MANDATORY: return 0 -> no Error).
5030 *
5031 */
iis2iclx_den_polarity_get(stmdev_ctx_t * ctx,iis2iclx_den_lh_t * val)5032 int32_t iis2iclx_den_polarity_get(stmdev_ctx_t *ctx,
5033 iis2iclx_den_lh_t *val)
5034 {
5035 iis2iclx_ctrl9_xl_t ctrl9_xl;
5036 int32_t ret;
5037
5038 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5039
5040 switch (ctrl9_xl.den_lh)
5041 {
5042 case IIS2ICLX_DEN_ACT_LOW:
5043 *val = IIS2ICLX_DEN_ACT_LOW;
5044 break;
5045
5046 case IIS2ICLX_DEN_ACT_HIGH:
5047 *val = IIS2ICLX_DEN_ACT_HIGH;
5048 break;
5049
5050 default:
5051 *val = IIS2ICLX_DEN_ACT_LOW;
5052 break;
5053 }
5054
5055 return ret;
5056 }
5057
5058 /**
5059 * @brief DEN value stored in LSB of Y-axis.[set]
5060 *
5061 * @param ctx Read / write interface definitions.(ptr)
5062 * @param val Change the values of den_y in reg CTRL9_XL
5063 * @retval Interface status (MANDATORY: return 0 -> no Error).
5064 *
5065 */
iis2iclx_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)5066 int32_t iis2iclx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
5067 {
5068 iis2iclx_ctrl9_xl_t ctrl9_xl;
5069 int32_t ret;
5070
5071 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5072
5073 if (ret == 0)
5074 {
5075 ctrl9_xl.den_y = (uint8_t)val;
5076 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL,
5077 (uint8_t *)&ctrl9_xl, 1);
5078 }
5079
5080 return ret;
5081 }
5082
5083 /**
5084 * @brief DEN value stored in LSB of Y-axis.[get]
5085 *
5086 * @param ctx Read / write interface definitions.(ptr)
5087 * @param val Change the values of den_y in reg CTRL9_XL
5088 * @retval Interface status (MANDATORY: return 0 -> no Error).
5089 *
5090 */
iis2iclx_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)5091 int32_t iis2iclx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
5092 {
5093 iis2iclx_ctrl9_xl_t ctrl9_xl;
5094 int32_t ret;
5095
5096 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5097 *val = ctrl9_xl.den_y;
5098
5099 return ret;
5100 }
5101
5102 /**
5103 * @brief DEN value stored in LSB of Z-axis.[set]
5104 *
5105 * @param ctx Read / write interface definitions.(ptr)
5106 * @param val Change the values of den_x in reg CTRL9_XL
5107 * @retval Interface status (MANDATORY: return 0 -> no Error).
5108 *
5109 */
iis2iclx_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)5110 int32_t iis2iclx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
5111 {
5112 iis2iclx_ctrl9_xl_t ctrl9_xl;
5113 int32_t ret;
5114
5115 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5116
5117 if (ret == 0)
5118 {
5119 ctrl9_xl.den_x = (uint8_t)val;
5120 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5121 }
5122
5123 return ret;
5124 }
5125
5126 /**
5127 * @brief DEN value stored in LSB of Z-axis.[get]
5128 *
5129 * @param ctx Read / write interface definitions.(ptr)
5130 * @param val Change the values of den_x in reg CTRL9_XL
5131 * @retval Interface status (MANDATORY: return 0 -> no Error).
5132 *
5133 */
iis2iclx_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)5134 int32_t iis2iclx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
5135 {
5136 iis2iclx_ctrl9_xl_t ctrl9_xl;
5137 int32_t ret;
5138
5139 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5140 *val = ctrl9_xl.den_x;
5141
5142 return ret;
5143 }
5144
5145 /**
5146 * @}
5147 *
5148 */
5149
5150 /**
5151 * @defgroup IIS2ICLX_finite_state_machine
5152 * @brief This section groups all the functions that manage the
5153 * state_machine.
5154 * @{
5155 *
5156 */
5157
5158 /**
5159 * @brief Interrupt status bit for FSM long counter timeout interrupt
5160 * event.[get]
5161 *
5162 * @param ctx Read / write interface definitions.(ptr)
5163 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
5164 * @retval Interface status (MANDATORY: return 0 -> no Error).
5165 *
5166 */
iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)5167 int32_t iis2iclx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
5168 uint8_t *val)
5169 {
5170 iis2iclx_emb_func_status_t emb_func_status;
5171 int32_t ret;
5172
5173 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5174
5175 if (ret == 0)
5176 {
5177 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_STATUS,
5178 (uint8_t *)&emb_func_status, 1);
5179 }
5180
5181 if (ret == 0)
5182 {
5183 *val = emb_func_status.is_fsm_lc;
5184 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5185 }
5186
5187 return ret;
5188 }
5189
5190 /**
5191 * @brief Embedded final state machine functions mode.[set]
5192 *
5193 * @param ctx Read / write interface definitions.(ptr)
5194 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
5195 * @retval Interface status (MANDATORY: return 0 -> no Error).
5196 *
5197 */
iis2iclx_emb_fsm_en_set(stmdev_ctx_t * ctx,uint8_t val)5198 int32_t iis2iclx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
5199 {
5200 int32_t ret;
5201
5202 iis2iclx_emb_func_en_b_t emb_func_en_b;
5203 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5204
5205 if (ret == 0)
5206 {
5207 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
5208 (uint8_t *)&emb_func_en_b, 1);
5209 }
5210
5211 if (ret == 0)
5212 {
5213 emb_func_en_b.fsm_en = (uint8_t)val;
5214 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
5215 (uint8_t *)&emb_func_en_b, 1);
5216 }
5217
5218 if (ret == 0)
5219 {
5220 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5221 }
5222
5223 return ret;
5224 }
5225
5226 /**
5227 * @brief Embedded final state machine functions mode.[get]
5228 *
5229 * @param ctx Read / write interface definitions.(ptr)
5230 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
5231 * @retval Interface status (MANDATORY: return 0 -> no Error).
5232 *
5233 */
iis2iclx_emb_fsm_en_get(stmdev_ctx_t * ctx,uint8_t * val)5234 int32_t iis2iclx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
5235 {
5236 int32_t ret;
5237
5238 iis2iclx_emb_func_en_b_t emb_func_en_b;
5239 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5240
5241 if (ret == 0)
5242 {
5243 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
5244 (uint8_t *)&emb_func_en_b, 1);
5245 }
5246
5247 if (ret == 0)
5248 {
5249 *val = emb_func_en_b.fsm_en;
5250 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
5251 (uint8_t *)&emb_func_en_b, 1);
5252 }
5253
5254 if (ret == 0)
5255 {
5256 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5257 }
5258
5259 return ret;
5260 }
5261
5262 /**
5263 * @brief Embedded final state machine functions mode.[set]
5264 *
5265 * @param ctx Read / write interface definitions.(ptr)
5266 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
5267 * @retval Interface status (MANDATORY: return 0 -> no Error).
5268 *
5269 */
iis2iclx_fsm_enable_set(stmdev_ctx_t * ctx,iis2iclx_emb_fsm_enable_t * val)5270 int32_t iis2iclx_fsm_enable_set(stmdev_ctx_t *ctx,
5271 iis2iclx_emb_fsm_enable_t *val)
5272 {
5273 iis2iclx_emb_func_en_b_t emb_func_en_b;
5274 int32_t ret;
5275
5276 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5277
5278 if (ret == 0)
5279 {
5280 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_ENABLE_A,
5281 (uint8_t *)&val->fsm_enable_a, 1);
5282 }
5283
5284 if (ret == 0)
5285 {
5286 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_ENABLE_B,
5287 (uint8_t *)&val->fsm_enable_b, 1);
5288 }
5289
5290 if (ret == 0)
5291 {
5292 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
5293 (uint8_t *)&emb_func_en_b, 1);
5294 }
5295
5296 if (ret == 0)
5297 {
5298 if ((val->fsm_enable_a.fsm1_en |
5299 val->fsm_enable_a.fsm2_en |
5300 val->fsm_enable_a.fsm3_en |
5301 val->fsm_enable_a.fsm4_en |
5302 val->fsm_enable_a.fsm5_en |
5303 val->fsm_enable_a.fsm6_en |
5304 val->fsm_enable_a.fsm7_en |
5305 val->fsm_enable_a.fsm8_en |
5306 val->fsm_enable_b.fsm9_en |
5307 val->fsm_enable_b.fsm10_en |
5308 val->fsm_enable_b.fsm11_en |
5309 val->fsm_enable_b.fsm12_en |
5310 val->fsm_enable_b.fsm13_en |
5311 val->fsm_enable_b.fsm14_en |
5312 val->fsm_enable_b.fsm15_en |
5313 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
5314 {
5315 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
5316 }
5317
5318 else
5319 {
5320 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
5321 }
5322 }
5323
5324 if (ret == 0)
5325 {
5326 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B,
5327 (uint8_t *)&emb_func_en_b, 1);
5328 }
5329
5330 if (ret == 0)
5331 {
5332 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5333 }
5334
5335 return ret;
5336 }
5337
5338 /**
5339 * @brief Embedded final state machine functions mode.[get]
5340 *
5341 * @param ctx Read / write interface definitions.(ptr)
5342 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
5343 * @retval Interface status (MANDATORY: return 0 -> no Error).
5344 *
5345 */
iis2iclx_fsm_enable_get(stmdev_ctx_t * ctx,iis2iclx_emb_fsm_enable_t * val)5346 int32_t iis2iclx_fsm_enable_get(stmdev_ctx_t *ctx,
5347 iis2iclx_emb_fsm_enable_t *val)
5348 {
5349 int32_t ret;
5350
5351 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5352
5353 if (ret == 0)
5354 {
5355 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_ENABLE_A,
5356 (uint8_t *)&val->fsm_enable_a, 1);
5357 }
5358
5359 if (ret == 0)
5360 {
5361 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_ENABLE_B,
5362 (uint8_t *)&val->fsm_enable_b, 1);
5363 }
5364
5365 if (ret == 0)
5366 {
5367 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5368 }
5369
5370 return ret;
5371 }
5372
5373 /**
5374 * @brief FSM long counter status register. Long counter value is an
5375 * unsigned integer value (16-bit format).[set]
5376 *
5377 * @param ctx Read / write interface definitions.(ptr)
5378 * @param buff Buffer that contains data to write
5379 * @retval Interface status (MANDATORY: return 0 -> no Error).
5380 *
5381 */
iis2iclx_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)5382 int32_t iis2iclx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
5383 {
5384 uint8_t buff[2];
5385 int32_t ret;
5386
5387 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5388
5389 if (ret == 0)
5390 {
5391 buff[1] = (uint8_t)(val / 256U);
5392 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5393 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_L, buff, 2);
5394 }
5395
5396 if (ret == 0)
5397 {
5398 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5399 }
5400
5401 return ret;
5402 }
5403
5404 /**
5405 * @brief FSM long counter status register. Long counter value is an
5406 * unsigned integer value (16-bit format).[get]
5407 *
5408 * @param ctx Read / write interface definitions.(ptr)
5409 * @param buff Buffer that stores data read
5410 * @retval Interface status (MANDATORY: return 0 -> no Error).
5411 *
5412 */
iis2iclx_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)5413 int32_t iis2iclx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
5414 {
5415 uint8_t buff[2];
5416 int32_t ret;
5417
5418 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5419
5420 if (ret == 0)
5421 {
5422 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_L, buff, 2);
5423 *val = buff[1];
5424 *val = (*val * 256U) + buff[0];
5425 }
5426
5427 if (ret == 0)
5428 {
5429 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5430 }
5431
5432 return ret;
5433 }
5434
5435 /**
5436 * @brief Clear FSM long counter value.[set]
5437 *
5438 * @param ctx Read / write interface definitions.(ptr)
5439 * @param val Change the values of fsm_lc_clr in reg
5440 * FSM_LONG_COUNTER_CLEAR
5441 * @retval Interface status (MANDATORY: return 0 -> no Error).
5442 *
5443 */
iis2iclx_long_clr_set(stmdev_ctx_t * ctx,iis2iclx_fsm_lc_clr_t val)5444 int32_t iis2iclx_long_clr_set(stmdev_ctx_t *ctx,
5445 iis2iclx_fsm_lc_clr_t val)
5446 {
5447 iis2iclx_fsm_long_counter_clear_t fsm_long_counter_clear;
5448 int32_t ret;
5449
5450 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5451
5452 if (ret == 0)
5453 {
5454 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_CLEAR,
5455 (uint8_t *)&fsm_long_counter_clear, 1);
5456 }
5457
5458 if (ret == 0)
5459 {
5460 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
5461 ret = iis2iclx_write_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_CLEAR,
5462 (uint8_t *)&fsm_long_counter_clear, 1);
5463 }
5464
5465 if (ret == 0)
5466 {
5467 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5468 }
5469
5470 return ret;
5471 }
5472
5473 /**
5474 * @brief Clear FSM long counter value.[get]
5475 *
5476 * @param ctx Read / write interface definitions.(ptr)
5477 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
5478 * @retval Interface status (MANDATORY: return 0 -> no Error).
5479 *
5480 */
iis2iclx_long_clr_get(stmdev_ctx_t * ctx,iis2iclx_fsm_lc_clr_t * val)5481 int32_t iis2iclx_long_clr_get(stmdev_ctx_t *ctx,
5482 iis2iclx_fsm_lc_clr_t *val)
5483 {
5484 iis2iclx_fsm_long_counter_clear_t fsm_long_counter_clear;
5485 int32_t ret;
5486
5487 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5488
5489 if (ret == 0)
5490 {
5491 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_LONG_COUNTER_CLEAR,
5492 (uint8_t *)&fsm_long_counter_clear, 1);
5493 }
5494
5495 if (ret == 0)
5496 {
5497 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5498 }
5499
5500 switch (fsm_long_counter_clear.fsm_lc_clr)
5501 {
5502 case IIS2ICLX_LC_NORMAL:
5503 *val = IIS2ICLX_LC_NORMAL;
5504 break;
5505
5506 case IIS2ICLX_LC_CLEAR:
5507 *val = IIS2ICLX_LC_CLEAR;
5508 break;
5509
5510 case IIS2ICLX_LC_CLEAR_DONE:
5511 *val = IIS2ICLX_LC_CLEAR_DONE;
5512 break;
5513
5514 default:
5515 *val = IIS2ICLX_LC_NORMAL;
5516 break;
5517 }
5518
5519 return ret;
5520 }
5521
5522 /**
5523 * @brief FSM output registers.[get]
5524 *
5525 * @param ctx Read / write interface definitions.(ptr)
5526 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
5527 * @retval Interface status (MANDATORY: return 0 -> no Error).
5528 *
5529 */
iis2iclx_fsm_out_get(stmdev_ctx_t * ctx,iis2iclx_fsm_out_t * val)5530 int32_t iis2iclx_fsm_out_get(stmdev_ctx_t *ctx,
5531 iis2iclx_fsm_out_t *val)
5532 {
5533 int32_t ret;
5534
5535 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5536
5537 if (ret == 0)
5538 {
5539 ret = iis2iclx_read_reg(ctx, IIS2ICLX_FSM_OUTS1,
5540 (uint8_t *)&val->fsm_outs1, 16);
5541 }
5542
5543 if (ret == 0)
5544 {
5545 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5546 }
5547
5548 return ret;
5549 }
5550
5551 /**
5552 * @brief Finite State Machine ODR configuration.[set]
5553 *
5554 * @param ctx Read / write interface definitions.(ptr)
5555 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
5556 * @retval Interface status (MANDATORY: return 0 -> no Error).
5557 *
5558 */
iis2iclx_fsm_data_rate_set(stmdev_ctx_t * ctx,iis2iclx_fsm_odr_t val)5559 int32_t iis2iclx_fsm_data_rate_set(stmdev_ctx_t *ctx,
5560 iis2iclx_fsm_odr_t val)
5561 {
5562 iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
5563 int32_t ret;
5564
5565 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5566
5567 if (ret == 0)
5568 {
5569 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
5570 (uint8_t *)&emb_func_odr_cfg_b, 1);
5571 }
5572
5573 if (ret == 0)
5574 {
5575 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
5576 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
5577 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
5578 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
5579 (uint8_t *)&emb_func_odr_cfg_b, 1);
5580 }
5581
5582 if (ret == 0)
5583 {
5584 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5585 }
5586
5587 return ret;
5588 }
5589
5590 /**
5591 * @brief Finite State Machine ODR configuration.[get]
5592 *
5593 * @param ctx Read / write interface definitions.(ptr)
5594 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
5595 * @retval Interface status (MANDATORY: return 0 -> no Error).
5596 *
5597 */
iis2iclx_fsm_data_rate_get(stmdev_ctx_t * ctx,iis2iclx_fsm_odr_t * val)5598 int32_t iis2iclx_fsm_data_rate_get(stmdev_ctx_t *ctx,
5599 iis2iclx_fsm_odr_t *val)
5600 {
5601 iis2iclx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
5602 int32_t ret;
5603
5604 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5605
5606 if (ret == 0)
5607 {
5608 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_B,
5609 (uint8_t *)&emb_func_odr_cfg_b, 1);
5610 }
5611
5612 if (ret == 0)
5613 {
5614 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5615 }
5616
5617 switch (emb_func_odr_cfg_b.fsm_odr)
5618 {
5619 case IIS2ICLX_ODR_FSM_12Hz5:
5620 *val = IIS2ICLX_ODR_FSM_12Hz5;
5621 break;
5622
5623 case IIS2ICLX_ODR_FSM_26Hz:
5624 *val = IIS2ICLX_ODR_FSM_26Hz;
5625 break;
5626
5627 case IIS2ICLX_ODR_FSM_52Hz:
5628 *val = IIS2ICLX_ODR_FSM_52Hz;
5629 break;
5630
5631 case IIS2ICLX_ODR_FSM_104Hz:
5632 *val = IIS2ICLX_ODR_FSM_104Hz;
5633 break;
5634
5635 default:
5636 *val = IIS2ICLX_ODR_FSM_12Hz5;
5637 break;
5638 }
5639
5640 return ret;
5641 }
5642
5643 /**
5644 * @brief FSM initialization request.[set]
5645 *
5646 * @param ctx Read / write interface definitions.(ptr)
5647 * @param val Change the values of fsm_init in reg FSM_INIT
5648 * @retval Interface status (MANDATORY: return 0 -> no Error).
5649 *
5650 */
iis2iclx_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)5651 int32_t iis2iclx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
5652 {
5653 iis2iclx_emb_func_init_b_t emb_func_init_b;
5654 int32_t ret;
5655
5656 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5657
5658 if (ret == 0)
5659 {
5660 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
5661 (uint8_t *)&emb_func_init_b, 1);
5662 }
5663
5664 if (ret == 0)
5665 {
5666 emb_func_init_b.fsm_init = (uint8_t)val;
5667 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
5668 (uint8_t *)&emb_func_init_b, 1);
5669 }
5670
5671 if (ret == 0)
5672 {
5673 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5674 }
5675
5676 return ret;
5677 }
5678
5679 /**
5680 * @brief FSM initialization request.[get]
5681 *
5682 * @param ctx Read / write interface definitions.(ptr)
5683 * @param val Change the values of fsm_init in reg FSM_INIT
5684 * @retval Interface status (MANDATORY: return 0 -> no Error).
5685 *
5686 */
iis2iclx_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)5687 int32_t iis2iclx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
5688 {
5689 iis2iclx_emb_func_init_b_t emb_func_init_b;
5690 int32_t ret;
5691
5692 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5693
5694 if (ret == 0)
5695 {
5696 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
5697 (uint8_t *)&emb_func_init_b, 1);
5698 }
5699
5700 if (ret == 0)
5701 {
5702 *val = emb_func_init_b.fsm_init;
5703 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5704 }
5705
5706 return ret;
5707 }
5708
5709 /**
5710 * @brief FSM long counter timeout register (r/w). The long counter
5711 * timeout value is an unsigned integer value (16-bit format).
5712 * When the long counter value reached this value, the FSM
5713 * generates an interrupt.[set]
5714 *
5715 * @param ctx Read / write interface definitions.(ptr)
5716 * @param buff Buffer that contains data to write
5717 * @retval Interface status (MANDATORY: return 0 -> no Error).
5718 *
5719 */
iis2iclx_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)5720 int32_t iis2iclx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
5721 uint16_t val)
5722 {
5723 uint8_t buff[2];
5724 int32_t ret;
5725
5726 buff[1] = (uint8_t)(val / 256U);
5727 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5728 ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_L,
5729 &buff[0]);
5730
5731 if (ret == 0)
5732 {
5733 ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_H,
5734 &buff[1]);
5735 }
5736
5737 return ret;
5738 }
5739
5740 /**
5741 * @brief FSM long counter timeout register (r/w). The long counter
5742 * timeout value is an unsigned integer value (16-bit format).
5743 * When the long counter value reached this value, the FSM generates
5744 * an interrupt.[get]
5745 *
5746 * @param ctx Read / write interface definitions.(ptr)
5747 * @param buff Buffer that stores data read
5748 * @retval Interface status (MANDATORY: return 0 -> no Error).
5749 *
5750 */
iis2iclx_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)5751 int32_t iis2iclx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
5752 uint16_t *val)
5753 {
5754 uint8_t buff[2];
5755 int32_t ret;
5756
5757 ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_L,
5758 &buff[0]);
5759
5760 if (ret == 0)
5761 {
5762 ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_LC_TIMEOUT_H,
5763 &buff[1]);
5764 *val = buff[1];
5765 *val = (*val * 256U) + buff[0];
5766 }
5767
5768 return ret;
5769 }
5770
5771 /**
5772 * @brief FSM number of programs register.[set]
5773 *
5774 * @param ctx Read / write interface definitions.(ptr)
5775 * @param buff Buffer that contains data to write
5776 * @retval Interface status (MANDATORY: return 0 -> no Error).
5777 *
5778 */
iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t * buff)5779 int32_t iis2iclx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
5780 uint8_t *buff)
5781 {
5782 int32_t ret;
5783
5784 ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_PROGRAMS, buff);
5785
5786 if (ret == 0)
5787 {
5788 ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_PROGRAMS + 0x01U,
5789 buff);
5790 }
5791
5792 return ret;
5793 }
5794
5795 /**
5796 * @brief FSM number of programs register.[get]
5797 *
5798 * @param ctx Read / write interface definitions.(ptr)
5799 * @param buff Buffer that stores data read
5800 * @retval Interface status (MANDATORY: return 0 -> no Error).
5801 *
5802 */
iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * buff)5803 int32_t iis2iclx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
5804 uint8_t *buff)
5805 {
5806 int32_t ret;
5807
5808 ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_PROGRAMS, buff);
5809
5810 return ret;
5811 }
5812
5813 /**
5814 * @brief FSM start address register (r/w). First available address is
5815 * 0x033C.[set]
5816 *
5817 * @param ctx Read / write interface definitions.(ptr)
5818 * @param buff Buffer that contains data to write
5819 * @retval Interface status (MANDATORY: return 0 -> no Error).
5820 *
5821 */
iis2iclx_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)5822 int32_t iis2iclx_fsm_start_address_set(stmdev_ctx_t *ctx,
5823 uint16_t val)
5824 {
5825 uint8_t buff[2];
5826 int32_t ret;
5827
5828 buff[1] = (uint8_t)(val / 256U);
5829 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5830 ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_START_ADD_L,
5831 &buff[0]);
5832
5833 if (ret == 0)
5834 {
5835 ret = iis2iclx_ln_pg_write_byte(ctx, IIS2ICLX_FSM_START_ADD_H,
5836 &buff[1]);
5837 }
5838
5839 return ret;
5840 }
5841
5842 /**
5843 * @brief FSM start address register (r/w). First available address
5844 * is 0x033C.[get]
5845 *
5846 * @param ctx Read / write interface definitions.(ptr)
5847 * @param buff Buffer that stores data read
5848 * @retval Interface status (MANDATORY: return 0 -> no Error).
5849 *
5850 */
iis2iclx_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)5851 int32_t iis2iclx_fsm_start_address_get(stmdev_ctx_t *ctx,
5852 uint16_t *val)
5853 {
5854 uint8_t buff[2];
5855 int32_t ret;
5856
5857 ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_START_ADD_L,
5858 &buff[0]);
5859
5860 if (ret == 0)
5861 {
5862 ret = iis2iclx_ln_pg_read_byte(ctx, IIS2ICLX_FSM_START_ADD_H,
5863 &buff[1]);
5864 *val = buff[1];
5865 *val = (*val * 256U) + buff[0];
5866 }
5867
5868 return ret;
5869 }
5870
5871 /**
5872 * @}
5873 *
5874 */
5875
5876 /**
5877 * @addtogroup Machine Learning Core
5878 * @brief This section group all the functions concerning the
5879 * usage of Machine Learning Core
5880 * @{
5881 *
5882 */
5883
5884 /**
5885 * @brief Enable Machine Learning Core.[set]
5886 *
5887 * @param ctx read / write interface definitions
5888 * @param val change the values of mlc_en in
5889 * reg EMB_FUNC_EN_B and mlc_init
5890 * in EMB_FUNC_INIT_B
5891 *
5892 */
iis2iclx_mlc_set(stmdev_ctx_t * ctx,uint8_t val)5893 int32_t iis2iclx_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
5894 {
5895 iis2iclx_emb_func_en_b_t reg;
5896 int32_t ret;
5897
5898 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5899
5900 if (ret == 0)
5901 {
5902 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
5903 }
5904
5905 if (ret == 0)
5906 {
5907 reg.mlc_en = val;
5908 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
5909 }
5910
5911 if ((val != PROPERTY_DISABLE) && (ret == 0))
5912 {
5913 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
5914 (uint8_t *)®, 1);
5915
5916 if (ret == 0)
5917 {
5918 reg.mlc_en = val;
5919 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_INIT_B,
5920 (uint8_t *)®, 1);
5921 }
5922 }
5923
5924 if (ret == 0)
5925 {
5926 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5927 }
5928
5929 return ret;
5930 }
5931
5932 /**
5933 * @brief Enable Machine Learning Core.[get]
5934 *
5935 * @param ctx read / write interface definitions
5936 * @param val Get the values of mlc_en in
5937 * reg EMB_FUNC_EN_B
5938 *
5939 */
iis2iclx_mlc_get(stmdev_ctx_t * ctx,uint8_t * val)5940 int32_t iis2iclx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
5941 {
5942 iis2iclx_emb_func_en_b_t reg;
5943 int32_t ret;
5944
5945 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5946
5947 if (ret == 0)
5948 {
5949 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
5950 }
5951
5952 if (ret == 0)
5953 {
5954 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
5955 *val = reg.mlc_en;
5956 }
5957
5958 return ret;
5959 }
5960
5961 /**
5962 * @brief Machine Learning Core status register[get]
5963 *
5964 * @param ctx read / write interface definitions
5965 * @param val register MLC_STATUS_MAINPAGE
5966 *
5967 */
iis2iclx_mlc_status_get(stmdev_ctx_t * ctx,iis2iclx_mlc_status_mainpage_t * val)5968 int32_t iis2iclx_mlc_status_get(stmdev_ctx_t *ctx,
5969 iis2iclx_mlc_status_mainpage_t *val)
5970 {
5971 return iis2iclx_read_reg(ctx, IIS2ICLX_MLC_STATUS_MAINPAGE,
5972 (uint8_t *) val, 1);
5973 }
5974
5975 /**
5976 * @brief Machine Learning Core data rate selection.[set]
5977 *
5978 * @param ctx read / write interface definitions
5979 * @param val get the values of mlc_odr in
5980 * reg EMB_FUNC_ODR_CFG_C
5981 *
5982 */
iis2iclx_mlc_data_rate_set(stmdev_ctx_t * ctx,iis2iclx_mlc_odr_t val)5983 int32_t iis2iclx_mlc_data_rate_set(stmdev_ctx_t *ctx,
5984 iis2iclx_mlc_odr_t val)
5985 {
5986 iis2iclx_emb_func_odr_cfg_c_t reg;
5987 int32_t ret;
5988
5989 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
5990
5991 if (ret == 0)
5992 {
5993 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
5994 (uint8_t *)®, 1);
5995 }
5996
5997 if (ret == 0)
5998 {
5999 reg.mlc_odr = (uint8_t)val;
6000 ret = iis2iclx_write_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
6001 (uint8_t *)®, 1);
6002 }
6003
6004 if (ret == 0)
6005 {
6006 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6007 }
6008
6009 return ret;
6010 }
6011
6012 /**
6013 * @brief Machine Learning Core data rate selection.[get]
6014 *
6015 * @param ctx read / write interface definitions
6016 * @param val change the values of mlc_odr in
6017 * reg EMB_FUNC_ODR_CFG_C
6018 *
6019 */
iis2iclx_mlc_data_rate_get(stmdev_ctx_t * ctx,iis2iclx_mlc_odr_t * val)6020 int32_t iis2iclx_mlc_data_rate_get(stmdev_ctx_t *ctx,
6021 iis2iclx_mlc_odr_t *val)
6022 {
6023 iis2iclx_emb_func_odr_cfg_c_t reg;
6024 int32_t ret;
6025
6026 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
6027
6028 if (ret == 0)
6029 {
6030 ret = iis2iclx_read_reg(ctx, IIS2ICLX_EMB_FUNC_ODR_CFG_C,
6031 (uint8_t *)®, 1);
6032 }
6033
6034 if (ret == 0)
6035 {
6036 switch (reg.mlc_odr)
6037 {
6038 case IIS2ICLX_ODR_PRGS_12Hz5:
6039 *val = IIS2ICLX_ODR_PRGS_12Hz5;
6040 break;
6041
6042 case IIS2ICLX_ODR_PRGS_26Hz:
6043 *val = IIS2ICLX_ODR_PRGS_26Hz;
6044 break;
6045
6046 case IIS2ICLX_ODR_PRGS_52Hz:
6047 *val = IIS2ICLX_ODR_PRGS_52Hz;
6048 break;
6049
6050 case IIS2ICLX_ODR_PRGS_104Hz:
6051 *val = IIS2ICLX_ODR_PRGS_104Hz;
6052 break;
6053
6054 default:
6055 *val = IIS2ICLX_ODR_PRGS_12Hz5;
6056 break;
6057 }
6058
6059 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6060 }
6061
6062 return ret;
6063 }
6064
6065 /**
6066 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
6067 *
6068 * @param ctx_t *ctx: read / write interface definitions
6069 * @param uint8_t * : buffer that stores data read
6070 *
6071 */
iis2iclx_mlc_out_get(stmdev_ctx_t * ctx,uint8_t * buff)6072 int32_t iis2iclx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
6073 {
6074 int32_t ret;
6075
6076 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_EMBEDDED_FUNC_BANK);
6077
6078 if (ret == 0)
6079 {
6080 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MLC0_SRC, buff, 8);
6081 }
6082
6083 if (ret == 0)
6084 {
6085 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6086 }
6087
6088 return ret;
6089 }
6090
6091 /**
6092 * @}
6093 *
6094 */
6095
6096 /**
6097 * @defgroup IIS2ICLX_Sensor_hub
6098 * @brief This section groups all the functions that manage the
6099 * sensor hub.
6100 * @{
6101 *
6102 */
6103
6104 /**
6105 * @brief Sensor hub output registers.[get]
6106 *
6107 * @param ctx Read / write interface definitions.(ptr)
6108 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
6109 * @retval Interface status (MANDATORY: return 0 -> no Error).
6110 *
6111 */
iis2iclx_sh_read_data_raw_get(stmdev_ctx_t * ctx,iis2iclx_emb_sh_read_t * val)6112 int32_t iis2iclx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
6113 iis2iclx_emb_sh_read_t *val)
6114 {
6115 int32_t ret;
6116
6117 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6118
6119 if (ret == 0)
6120 {
6121 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SENSOR_HUB_1, (uint8_t *)val,
6122 18);
6123 }
6124
6125 if (ret == 0)
6126 {
6127 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6128 }
6129
6130 return ret;
6131 }
6132
6133 /**
6134 * @brief Number of external sensors to be read by the sensor hub.[set]
6135 *
6136 * @param ctx Read / write interface definitions.(ptr)
6137 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
6138 * @retval Interface status (MANDATORY: return 0 -> no Error).
6139 *
6140 */
iis2iclx_sh_slave_connected_set(stmdev_ctx_t * ctx,iis2iclx_aux_sens_on_t val)6141 int32_t iis2iclx_sh_slave_connected_set(stmdev_ctx_t *ctx,
6142 iis2iclx_aux_sens_on_t val)
6143 {
6144 iis2iclx_master_config_t master_config;
6145 int32_t ret;
6146
6147 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6148
6149 if (ret == 0)
6150 {
6151 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6152 (uint8_t *)&master_config, 1);
6153 }
6154
6155 if (ret == 0)
6156 {
6157 master_config.aux_sens_on = (uint8_t)val;
6158 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6159 (uint8_t *)&master_config, 1);
6160 }
6161
6162 if (ret == 0)
6163 {
6164 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6165 }
6166
6167 return ret;
6168 }
6169
6170 /**
6171 * @brief Number of external sensors to be read by the sensor hub.[get]
6172 *
6173 * @param ctx Read / write interface definitions.(ptr)
6174 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
6175 * @retval Interface status (MANDATORY: return 0 -> no Error).
6176 *
6177 */
iis2iclx_sh_slave_connected_get(stmdev_ctx_t * ctx,iis2iclx_aux_sens_on_t * val)6178 int32_t iis2iclx_sh_slave_connected_get(stmdev_ctx_t *ctx,
6179 iis2iclx_aux_sens_on_t *val)
6180 {
6181 iis2iclx_master_config_t master_config;
6182 int32_t ret;
6183
6184 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6185
6186 if (ret == 0)
6187 {
6188 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6189 (uint8_t *)&master_config, 1);
6190 }
6191
6192 if (ret == 0)
6193 {
6194 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6195 }
6196
6197 switch (master_config.aux_sens_on)
6198 {
6199 case IIS2ICLX_SLV_0:
6200 *val = IIS2ICLX_SLV_0;
6201 break;
6202
6203 case IIS2ICLX_SLV_0_1:
6204 *val = IIS2ICLX_SLV_0_1;
6205 break;
6206
6207 case IIS2ICLX_SLV_0_1_2:
6208 *val = IIS2ICLX_SLV_0_1_2;
6209 break;
6210
6211 case IIS2ICLX_SLV_0_1_2_3:
6212 *val = IIS2ICLX_SLV_0_1_2_3;
6213 break;
6214
6215 default:
6216 *val = IIS2ICLX_SLV_0;
6217 break;
6218 }
6219
6220 return ret;
6221 }
6222
6223 /**
6224 * @brief Sensor hub I2C master enable.[set]
6225 *
6226 * @param ctx Read / write interface definitions.(ptr)
6227 * @param val Change the values of master_on in reg MASTER_CONFIG
6228 * @retval Interface status (MANDATORY: return 0 -> no Error).
6229 *
6230 */
iis2iclx_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)6231 int32_t iis2iclx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
6232 {
6233 iis2iclx_master_config_t master_config;
6234 int32_t ret;
6235
6236 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6237
6238 if (ret == 0)
6239 {
6240 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6241 (uint8_t *)&master_config, 1);
6242 }
6243
6244 if (ret == 0)
6245 {
6246 master_config.master_on = (uint8_t)val;
6247 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6248 (uint8_t *)&master_config, 1);
6249 }
6250
6251 if (ret == 0)
6252 {
6253 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6254 }
6255
6256 return ret;
6257 }
6258
6259 /**
6260 * @brief Sensor hub I2C master enable.[get]
6261 *
6262 * @param ctx Read / write interface definitions.(ptr)
6263 * @param val Change the values of master_on in reg MASTER_CONFIG
6264 * @retval Interface status (MANDATORY: return 0 -> no Error).
6265 *
6266 */
iis2iclx_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)6267 int32_t iis2iclx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
6268 {
6269 iis2iclx_master_config_t master_config;
6270 int32_t ret;
6271
6272 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6273
6274 if (ret == 0)
6275 {
6276 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6277 (uint8_t *)&master_config, 1);
6278 }
6279
6280 if (ret == 0)
6281 {
6282 *val = master_config.master_on;
6283 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6284 }
6285
6286 return ret;
6287 }
6288
6289 /**
6290 * @brief Master I2C pull-up enable.[set]
6291 *
6292 * @param ctx Read / write interface definitions.(ptr)
6293 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
6294 * @retval Interface status (MANDATORY: return 0 -> no Error).
6295 *
6296 */
iis2iclx_sh_pin_mode_set(stmdev_ctx_t * ctx,iis2iclx_shub_pu_en_t val)6297 int32_t iis2iclx_sh_pin_mode_set(stmdev_ctx_t *ctx,
6298 iis2iclx_shub_pu_en_t val)
6299 {
6300 iis2iclx_master_config_t master_config;
6301 int32_t ret;
6302
6303 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6304
6305 if (ret == 0)
6306 {
6307 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6308 (uint8_t *)&master_config, 1);
6309 }
6310
6311 if (ret == 0)
6312 {
6313 master_config.shub_pu_en = (uint8_t)val;
6314 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6315 (uint8_t *)&master_config, 1);
6316 }
6317
6318 if (ret == 0)
6319 {
6320 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6321 }
6322
6323 return ret;
6324 }
6325
6326 /**
6327 * @brief Master I2C pull-up enable.[get]
6328 *
6329 * @param ctx Read / write interface definitions.(ptr)
6330 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
6331 * @retval Interface status (MANDATORY: return 0 -> no Error).
6332 *
6333 */
iis2iclx_sh_pin_mode_get(stmdev_ctx_t * ctx,iis2iclx_shub_pu_en_t * val)6334 int32_t iis2iclx_sh_pin_mode_get(stmdev_ctx_t *ctx,
6335 iis2iclx_shub_pu_en_t *val)
6336 {
6337 iis2iclx_master_config_t master_config;
6338 int32_t ret;
6339
6340 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6341
6342 if (ret == 0)
6343 {
6344 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6345 (uint8_t *)&master_config, 1);
6346 }
6347
6348 if (ret == 0)
6349 {
6350 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6351 }
6352
6353 switch (master_config.shub_pu_en)
6354 {
6355 case IIS2ICLX_EXT_PULL_UP:
6356 *val = IIS2ICLX_EXT_PULL_UP;
6357 break;
6358
6359 case IIS2ICLX_INTERNAL_PULL_UP:
6360 *val = IIS2ICLX_INTERNAL_PULL_UP;
6361 break;
6362
6363 default:
6364 *val = IIS2ICLX_EXT_PULL_UP;
6365 break;
6366 }
6367
6368 return ret;
6369 }
6370
6371 /**
6372 * @brief I2C interface pass-through.[set]
6373 *
6374 * @param ctx Read / write interface definitions.(ptr)
6375 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
6376 * @retval Interface status (MANDATORY: return 0 -> no Error).
6377 *
6378 */
iis2iclx_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)6379 int32_t iis2iclx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
6380 {
6381 iis2iclx_master_config_t master_config;
6382 int32_t ret;
6383
6384 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6385
6386 if (ret == 0)
6387 {
6388 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6389 (uint8_t *)&master_config, 1);
6390 }
6391
6392 if (ret == 0)
6393 {
6394 master_config.pass_through_mode = (uint8_t)val;
6395 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6396 (uint8_t *)&master_config, 1);
6397 }
6398
6399 if (ret == 0)
6400 {
6401 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6402 }
6403
6404 return ret;
6405 }
6406
6407 /**
6408 * @brief I2C interface pass-through.[get]
6409 *
6410 * @param ctx Read / write interface definitions.(ptr)
6411 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
6412 * @retval Interface status (MANDATORY: return 0 -> no Error).
6413 *
6414 */
iis2iclx_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)6415 int32_t iis2iclx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
6416 {
6417 iis2iclx_master_config_t master_config;
6418 int32_t ret;
6419
6420 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6421
6422 if (ret == 0)
6423 {
6424 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6425 (uint8_t *)&master_config, 1);
6426 }
6427
6428 if (ret == 0)
6429 {
6430 *val = master_config.pass_through_mode;
6431 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6432 }
6433
6434 return ret;
6435 }
6436
6437 /**
6438 * @brief Sensor hub trigger signal selection.[set]
6439 *
6440 * @param ctx Read / write interface definitions.(ptr)
6441 * @param val Change the values of start_config in reg MASTER_CONFIG
6442 * @retval Interface status (MANDATORY: return 0 -> no Error).
6443 *
6444 */
iis2iclx_sh_syncro_mode_set(stmdev_ctx_t * ctx,iis2iclx_start_config_t val)6445 int32_t iis2iclx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
6446 iis2iclx_start_config_t val)
6447 {
6448 iis2iclx_master_config_t master_config;
6449 int32_t ret;
6450
6451 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6452
6453 if (ret == 0)
6454 {
6455 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6456 (uint8_t *)&master_config, 1);
6457 }
6458
6459 if (ret == 0)
6460 {
6461 master_config.start_config = (uint8_t)val;
6462 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6463 (uint8_t *)&master_config, 1);
6464 }
6465
6466 if (ret == 0)
6467 {
6468 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6469 }
6470
6471 return ret;
6472 }
6473
6474 /**
6475 * @brief Sensor hub trigger signal selection.[get]
6476 *
6477 * @param ctx Read / write interface definitions.(ptr)
6478 * @param val Get the values of start_config in reg MASTER_CONFIG
6479 * @retval Interface status (MANDATORY: return 0 -> no Error).
6480 *
6481 */
iis2iclx_sh_syncro_mode_get(stmdev_ctx_t * ctx,iis2iclx_start_config_t * val)6482 int32_t iis2iclx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
6483 iis2iclx_start_config_t *val)
6484 {
6485 iis2iclx_master_config_t master_config;
6486 int32_t ret;
6487
6488 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6489
6490 if (ret == 0)
6491 {
6492 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6493 (uint8_t *)&master_config, 1);
6494 }
6495
6496 if (ret == 0)
6497 {
6498 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6499 }
6500
6501 switch (master_config.start_config)
6502 {
6503 case IIS2ICLX_EXT_ON_INT2_PIN:
6504 *val = IIS2ICLX_EXT_ON_INT2_PIN;
6505 break;
6506
6507 case IIS2ICLX_XL_GY_DRDY:
6508 *val = IIS2ICLX_XL_GY_DRDY;
6509 break;
6510
6511 default:
6512 *val = IIS2ICLX_EXT_ON_INT2_PIN;
6513 break;
6514 }
6515
6516 return ret;
6517 }
6518
6519 /**
6520 * @brief Slave 0 write operation is performed only at the first sensor
6521 * hub cycle.[set]
6522 *
6523 * @param ctx Read / write interface definitions.(ptr)
6524 * @param val Change the values of write_once in reg MASTER_CONFIG
6525 * @retval Interface status (MANDATORY: return 0 -> no Error).
6526 *
6527 */
iis2iclx_sh_write_mode_set(stmdev_ctx_t * ctx,iis2iclx_write_once_t val)6528 int32_t iis2iclx_sh_write_mode_set(stmdev_ctx_t *ctx,
6529 iis2iclx_write_once_t val)
6530 {
6531 iis2iclx_master_config_t master_config;
6532 int32_t ret;
6533
6534 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6535
6536 if (ret == 0)
6537 {
6538 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6539 (uint8_t *)&master_config, 1);
6540 }
6541
6542 if (ret == 0)
6543 {
6544 master_config.write_once = (uint8_t)val;
6545 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6546 (uint8_t *)&master_config, 1);
6547 }
6548
6549 if (ret == 0)
6550 {
6551 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6552 }
6553
6554 return ret;
6555 }
6556
6557 /**
6558 * @brief Slave 0 write operation is performed only at the first sensor
6559 * hub cycle.[get]
6560 *
6561 * @param ctx Read / write interface definitions.(ptr)
6562 * @param val Get the values of write_once in reg MASTER_CONFIG
6563 * @retval Interface status (MANDATORY: return 0 -> no Error).
6564 *
6565 */
iis2iclx_sh_write_mode_get(stmdev_ctx_t * ctx,iis2iclx_write_once_t * val)6566 int32_t iis2iclx_sh_write_mode_get(stmdev_ctx_t *ctx,
6567 iis2iclx_write_once_t *val)
6568 {
6569 iis2iclx_master_config_t master_config;
6570 int32_t ret;
6571
6572 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6573
6574 if (ret == 0)
6575 {
6576 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6577 (uint8_t *)&master_config, 1);
6578 }
6579
6580 if (ret == 0)
6581 {
6582 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6583 }
6584
6585 switch (master_config.write_once)
6586 {
6587 case IIS2ICLX_EACH_SH_CYCLE:
6588 *val = IIS2ICLX_EACH_SH_CYCLE;
6589 break;
6590
6591 case IIS2ICLX_ONLY_FIRST_CYCLE:
6592 *val = IIS2ICLX_ONLY_FIRST_CYCLE;
6593 break;
6594
6595 default:
6596 *val = IIS2ICLX_EACH_SH_CYCLE;
6597 break;
6598 }
6599
6600 return ret;
6601 }
6602
6603 /**
6604 * @brief Reset Master logic and output registers.[set]
6605 *
6606 * @param ctx Read / write interface definitions.(ptr)
6607 * @retval Interface status (MANDATORY: return 0 -> no Error).
6608 *
6609 */
iis2iclx_sh_reset_set(stmdev_ctx_t * ctx)6610 int32_t iis2iclx_sh_reset_set(stmdev_ctx_t *ctx)
6611 {
6612 iis2iclx_master_config_t master_config;
6613 int32_t ret;
6614
6615 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6616
6617 if (ret == 0)
6618 {
6619 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6620 (uint8_t *)&master_config, 1);
6621 }
6622
6623 if (ret == 0)
6624 {
6625 master_config.rst_master_regs = PROPERTY_ENABLE;
6626 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6627 (uint8_t *)&master_config, 1);
6628 }
6629
6630 if (ret == 0)
6631 {
6632 master_config.rst_master_regs = PROPERTY_DISABLE;
6633 ret = iis2iclx_write_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6634 (uint8_t *)&master_config, 1);
6635 }
6636
6637 if (ret == 0)
6638 {
6639 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6640 }
6641
6642 return ret;
6643 }
6644
6645 /**
6646 * @brief Reset Master logic and output registers.[get]
6647 *
6648 * @param ctx Read / write interface definitions.(ptr)
6649 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
6650 * @retval Interface status (MANDATORY: return 0 -> no Error).
6651 *
6652 */
iis2iclx_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)6653 int32_t iis2iclx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
6654 {
6655 iis2iclx_master_config_t master_config;
6656 int32_t ret;
6657
6658 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6659
6660 if (ret == 0)
6661 {
6662 ret = iis2iclx_read_reg(ctx, IIS2ICLX_MASTER_CONFIG,
6663 (uint8_t *)&master_config, 1);
6664 *val = master_config.rst_master_regs;
6665 }
6666
6667 if (ret == 0)
6668 {
6669 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6670 }
6671
6672 return ret;
6673 }
6674
6675 /**
6676 * @brief Rate at which the master communicates.[set]
6677 *
6678 * @param ctx Read / write interface definitions.(ptr)
6679 * @param val Change the values of shub_odr in reg SLV0_CONFIG
6680 * @retval Interface status (MANDATORY: return 0 -> no Error).
6681 *
6682 */
iis2iclx_sh_data_rate_set(stmdev_ctx_t * ctx,iis2iclx_shub_odr_t val)6683 int32_t iis2iclx_sh_data_rate_set(stmdev_ctx_t *ctx,
6684 iis2iclx_shub_odr_t val)
6685 {
6686 iis2iclx_slv0_config_t slv0_config;
6687 int32_t ret;
6688
6689 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6690
6691 if (ret == 0)
6692 {
6693 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
6694 (uint8_t *)&slv0_config, 1);
6695 }
6696
6697 if (ret == 0)
6698 {
6699 slv0_config.shub_odr = (uint8_t)val;
6700 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_CONFIG,
6701 (uint8_t *)&slv0_config, 1);
6702 }
6703
6704 if (ret == 0)
6705 {
6706 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6707 }
6708
6709 return ret;
6710 }
6711
6712 /**
6713 * @brief Rate at which the master communicates.[get]
6714 *
6715 * @param ctx Read / write interface definitions.(ptr)
6716 * @param val Get the values of shub_odr in reg slv1_CONFIG
6717 * @retval Interface status (MANDATORY: return 0 -> no Error).
6718 *
6719 */
iis2iclx_sh_data_rate_get(stmdev_ctx_t * ctx,iis2iclx_shub_odr_t * val)6720 int32_t iis2iclx_sh_data_rate_get(stmdev_ctx_t *ctx,
6721 iis2iclx_shub_odr_t *val)
6722 {
6723 iis2iclx_slv0_config_t slv0_config;
6724 int32_t ret;
6725
6726 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6727
6728 if (ret == 0)
6729 {
6730 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
6731 (uint8_t *)&slv0_config, 1);
6732 }
6733
6734 if (ret == 0)
6735 {
6736 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6737 }
6738
6739 switch (slv0_config.shub_odr)
6740 {
6741 case IIS2ICLX_SH_ODR_104Hz:
6742 *val = IIS2ICLX_SH_ODR_104Hz;
6743 break;
6744
6745 case IIS2ICLX_SH_ODR_52Hz:
6746 *val = IIS2ICLX_SH_ODR_52Hz;
6747 break;
6748
6749 case IIS2ICLX_SH_ODR_26Hz:
6750 *val = IIS2ICLX_SH_ODR_26Hz;
6751 break;
6752
6753 case IIS2ICLX_SH_ODR_13Hz:
6754 *val = IIS2ICLX_SH_ODR_13Hz;
6755 break;
6756
6757 default:
6758 *val = IIS2ICLX_SH_ODR_104Hz;
6759 break;
6760 }
6761
6762 return ret;
6763 }
6764
6765 /**
6766 * @brief Configure slave 0 for perform a write.[set]
6767 *
6768 * @param ctx Read / write interface definitions.(ptr)
6769 * @param val Structure that contain
6770 * - uint8_t slv0_add; 8 bit i2c device address
6771 * - uint8_t slv0_subadd; 8 bit register device address
6772 * - uint8_t slv0_data; 8 bit data to write
6773 * @retval Interface status (MANDATORY: return 0 -> no Error).
6774 *
6775 */
iis2iclx_sh_cfg_write(stmdev_ctx_t * ctx,iis2iclx_sh_cfg_write_t * val)6776 int32_t iis2iclx_sh_cfg_write(stmdev_ctx_t *ctx,
6777 iis2iclx_sh_cfg_write_t *val)
6778 {
6779 iis2iclx_slv0_add_t slv0_add;
6780 int32_t ret;
6781
6782 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6783
6784 if (ret == 0)
6785 {
6786 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
6787 slv0_add.rw_0 = 0;
6788 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_ADD,
6789 (uint8_t *) & (slv0_add), 1);
6790 }
6791
6792 if (ret == 0)
6793 {
6794 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_SUBADD,
6795 (uint8_t *) & (val->slv0_subadd), 1);
6796 }
6797
6798 if (ret == 0)
6799 {
6800 ret = iis2iclx_write_reg(ctx, IIS2ICLX_DATAWRITE_SLV0,
6801 (uint8_t *) & (val->slv0_data), 1);
6802 }
6803
6804 if (ret == 0)
6805 {
6806 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6807 }
6808
6809 return ret;
6810 }
6811
6812 /**
6813 * @brief Configure slave 0 for perform a write/read.[get]
6814 *
6815 * @param ctx Read / write interface definitions.(ptr)
6816 * @param val Structure that contain
6817 * - uint8_t slv_add; 8 bit i2c device address
6818 * - uint8_t slv_subadd; 8 bit register device address
6819 * - uint8_t slv_len; num of bit to read
6820 * @retval Interface status (MANDATORY: return 0 -> no Error).
6821 *
6822 */
iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t * ctx,iis2iclx_sh_cfg_read_t * val)6823 int32_t iis2iclx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
6824 iis2iclx_sh_cfg_read_t *val)
6825 {
6826 iis2iclx_slv0_config_t slv0_config;
6827 iis2iclx_slv0_add_t slv0_add;
6828 int32_t ret;
6829
6830 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6831
6832 if (ret == 0)
6833 {
6834 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
6835 slv0_add.rw_0 = 1;
6836 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_ADD,
6837 (uint8_t *) & (slv0_add), 1);
6838 }
6839
6840 if (ret == 0)
6841 {
6842 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_SUBADD,
6843 &(val->slv_subadd), 1);
6844 }
6845
6846 if (ret == 0)
6847 {
6848 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV0_CONFIG,
6849 (uint8_t *)&slv0_config, 1);
6850 }
6851
6852 if (ret == 0)
6853 {
6854 slv0_config.slave0_numop = val->slv_len;
6855 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV0_CONFIG,
6856 (uint8_t *)&slv0_config, 1);
6857 }
6858
6859 if (ret == 0)
6860 {
6861 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6862 }
6863
6864 return ret;
6865 }
6866
6867 /**
6868 * @brief Configure slave 0 for perform a write/read.[get]
6869 *
6870 * @param ctx Read / write interface definitions.(ptr)
6871 * @param val Structure that contain
6872 * - uint8_t slv_add; 8 bit i2c device address
6873 * - uint8_t slv_subadd; 8 bit register device address
6874 * - uint8_t slv_len; num of bit to read
6875 * @retval Interface status (MANDATORY: return 0 -> no Error).
6876 *
6877 */
iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t * ctx,iis2iclx_sh_cfg_read_t * val)6878 int32_t iis2iclx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
6879 iis2iclx_sh_cfg_read_t *val)
6880 {
6881 iis2iclx_slv1_config_t slv1_config;
6882 iis2iclx_slv1_add_t slv1_add;
6883 int32_t ret;
6884
6885 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6886
6887 if (ret == 0)
6888 {
6889 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
6890 slv1_add.r_1 = 1;
6891 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_ADD, (uint8_t *)&slv1_add, 1);
6892 }
6893
6894 if (ret == 0)
6895 {
6896 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_SUBADD,
6897 &(val->slv_subadd), 1);
6898 }
6899
6900 if (ret == 0)
6901 {
6902 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV1_CONFIG,
6903 (uint8_t *)&slv1_config, 1);
6904 }
6905
6906 if (ret == 0)
6907 {
6908 slv1_config.slave1_numop = val->slv_len;
6909 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV1_CONFIG,
6910 (uint8_t *)&slv1_config, 1);
6911 }
6912
6913 if (ret == 0)
6914 {
6915 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6916 }
6917
6918 return ret;
6919 }
6920
6921 /**
6922 * @brief Configure slave 2 for perform a write/read.[get]
6923 *
6924 * @param ctx Read / write interface definitions.(ptr)
6925 * @param val Structure that contain
6926 * - uint8_t slv_add; 8 bit i2c device address
6927 * - uint8_t slv_subadd; 8 bit register device address
6928 * - uint8_t slv_len; num of bit to read
6929 * @retval Interface status (MANDATORY: return 0 -> no Error).
6930 *
6931 */
iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t * ctx,iis2iclx_sh_cfg_read_t * val)6932 int32_t iis2iclx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
6933 iis2iclx_sh_cfg_read_t *val)
6934 {
6935 iis2iclx_slv2_config_t slv2_config;
6936 iis2iclx_slv2_add_t slv2_add;
6937 int32_t ret;
6938
6939 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6940
6941 if (ret == 0)
6942 {
6943 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
6944 slv2_add.r_2 = 1;
6945 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_ADD,
6946 (uint8_t *)&slv2_add, 1);
6947 }
6948
6949 if (ret == 0)
6950 {
6951 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_SUBADD,
6952 (uint8_t *) & (val->slv_subadd), 1);
6953 }
6954
6955 if (ret == 0)
6956 {
6957 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV2_CONFIG,
6958 (uint8_t *)&slv2_config, 1);
6959 }
6960
6961 if (ret == 0)
6962 {
6963 slv2_config.slave2_numop = val->slv_len;
6964 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV2_CONFIG,
6965 (uint8_t *)&slv2_config, 1);
6966 }
6967
6968 if (ret == 0)
6969 {
6970 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
6971 }
6972
6973 return ret;
6974 }
6975
6976 /**
6977 * @brief Configure slave 3 for perform a write/read.[get]
6978 *
6979 * @param ctx Read / write interface definitions.(ptr)
6980 * @param val Structure that contain
6981 * - uint8_t slv_add; 8 bit i2c device address
6982 * - uint8_t slv_subadd; 8 bit register device address
6983 * - uint8_t slv_len; num of bit to read
6984 * @retval Interface status (MANDATORY: return 0 -> no Error).
6985 *
6986 */
iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t * ctx,iis2iclx_sh_cfg_read_t * val)6987 int32_t iis2iclx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
6988 iis2iclx_sh_cfg_read_t *val)
6989 {
6990 iis2iclx_slv3_config_t slv3_config;
6991 iis2iclx_slv3_add_t slv3_add;
6992 int32_t ret;
6993
6994 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
6995
6996 if (ret == 0)
6997 {
6998 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
6999 slv3_add.r_3 = 1;
7000 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_ADD,
7001 (uint8_t *)&slv3_add, 1);
7002 }
7003
7004 if (ret == 0)
7005 {
7006 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_SUBADD,
7007 &(val->slv_subadd), 1);
7008 }
7009
7010 if (ret == 0)
7011 {
7012 ret = iis2iclx_read_reg(ctx, IIS2ICLX_SLV3_CONFIG,
7013 (uint8_t *)&slv3_config, 1);
7014 }
7015
7016 if (ret == 0)
7017 {
7018 slv3_config.slave3_numop = val->slv_len;
7019 ret = iis2iclx_write_reg(ctx, IIS2ICLX_SLV3_CONFIG,
7020 (uint8_t *)&slv3_config, 1);
7021 }
7022
7023 if (ret == 0)
7024 {
7025 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
7026 }
7027
7028 return ret;
7029 }
7030
7031 /**
7032 * @brief Sensor hub source register.[get]
7033 *
7034 * @param ctx Read / write interface definitions.(ptr)
7035 * @param val Registers from STATUS_MASTER
7036 * @retval Interface status (MANDATORY: return 0 -> no Error).
7037 *
7038 */
iis2iclx_sh_status_get(stmdev_ctx_t * ctx,iis2iclx_status_master_t * val)7039 int32_t iis2iclx_sh_status_get(stmdev_ctx_t *ctx,
7040 iis2iclx_status_master_t *val)
7041 {
7042 int32_t ret;
7043
7044 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_SENSOR_HUB_BANK);
7045
7046 if (ret == 0)
7047 {
7048 ret = iis2iclx_read_reg(ctx, IIS2ICLX_STATUS_MASTER, (uint8_t *)val, 1);
7049 }
7050
7051 if (ret == 0)
7052 {
7053 ret = iis2iclx_mem_bank_set(ctx, IIS2ICLX_USER_BANK);
7054 }
7055
7056 return ret;
7057 }
7058
iis2iclx_bus_mode_set(stmdev_ctx_t * ctx,iis2iclx_bus_mode_t val)7059 int32_t iis2iclx_bus_mode_set(stmdev_ctx_t *ctx,
7060 iis2iclx_bus_mode_t val)
7061 {
7062 iis2iclx_ctrl9_xl_t ctrl9_xl;
7063 iis2iclx_ctrl3_c_t ctrl3_c;
7064 iis2iclx_ctrl4_c_t ctrl4_c;
7065 int32_t ret;
7066
7067 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7068
7069 if (ret == 0)
7070 {
7071 ctrl9_xl.device_conf = PROPERTY_ENABLE;
7072 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7073 }
7074
7075 if (ret == 0)
7076 {
7077 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
7078 }
7079
7080 if (ret == 0)
7081 {
7082 ctrl3_c.sim = ((uint8_t)val & 0x02U) >> 1;
7083 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
7084 }
7085
7086 if (ret == 0)
7087 {
7088 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
7089 }
7090
7091 if (ret == 0)
7092 {
7093 ctrl4_c.i2c_disable = ((uint8_t)val & 0x01U);
7094 ret = iis2iclx_write_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
7095 }
7096
7097 return ret;
7098 }
7099
iis2iclx_bus_mode_get(stmdev_ctx_t * ctx,iis2iclx_bus_mode_t * val)7100 int32_t iis2iclx_bus_mode_get(stmdev_ctx_t *ctx,
7101 iis2iclx_bus_mode_t *val)
7102 {
7103 iis2iclx_ctrl3_c_t ctrl3_c;
7104 iis2iclx_ctrl4_c_t ctrl4_c;
7105 int32_t ret;
7106
7107 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
7108
7109 if (ret == 0)
7110 {
7111 ret = iis2iclx_read_reg(ctx, IIS2ICLX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
7112 }
7113
7114 switch ((ctrl3_c.sim << 1) | ctrl4_c.i2c_disable)
7115 {
7116 case IIS2ICLX_SEL_BY_HW:
7117 *val = IIS2ICLX_SEL_BY_HW;
7118 break;
7119
7120 case IIS2ICLX_SPI_4W:
7121 *val = IIS2ICLX_SPI_4W;
7122 break;
7123
7124 case IIS2ICLX_SPI_3W:
7125 *val = IIS2ICLX_SPI_3W;
7126 break;
7127
7128 default:
7129 *val = IIS2ICLX_SEL_BY_HW;
7130 break;
7131 }
7132
7133 return ret;
7134 }
7135
7136 /**
7137 * @}
7138 *
7139 */
7140
7141 /**
7142 * @}
7143 *
7144 */
7145
7146 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7147
