1 /**
2 ******************************************************************************
3 * @file iis2dh_reg.c
4 * @author Sensors Software Solution Team
5 * @brief IIS2DH driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "iis2dh_reg.h"
21
22 /**
23 * @defgroup IIS2DH
24 * @brief This file provides a set of functions needed to drive the
25 * iis2dh enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup IIS2DH_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
iis2dh_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak iis2dh_read_reg(stmdev_ctx_t *ctx, uint8_t reg, uint8_t *data,
50 uint16_t len)
51 {
52 int32_t ret;
53
54 ret = ctx->read_reg(ctx->handle, reg, data, len);
55
56 return ret;
57 }
58
59 /**
60 * @brief Write generic device register
61 *
62 * @param ctx read / write interface definitions(ptr)
63 * @param reg register to write
64 * @param data pointer to data to write in register reg(ptr)
65 * @param len number of consecutive register to write
66 * @retval interface status (MANDATORY: return 0 -> no Error)
67 *
68 */
iis2dh_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)69 int32_t __weak iis2dh_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
70 uint8_t *data,
71 uint16_t len)
72 {
73 int32_t ret;
74
75 ret = ctx->write_reg(ctx->handle, reg, data, len);
76
77 return ret;
78 }
79
80 /**
81 * @}
82 *
83 */
84
85 /**
86 * @defgroup IIS2DH_Sensitivity
87 * @brief These functions convert raw-data into engineering units.
88 * @{
89 *
90 */
91
iis2dh_from_fs2_hr_to_mg(int16_t lsb)92 float_t iis2dh_from_fs2_hr_to_mg(int16_t lsb)
93 {
94 return ((float_t)lsb / 16.0f) * 0.98f;
95 }
96
iis2dh_from_fs4_hr_to_mg(int16_t lsb)97 float_t iis2dh_from_fs4_hr_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb / 16.0f) * 1.95f;
100 }
101
iis2dh_from_fs8_hr_to_mg(int16_t lsb)102 float_t iis2dh_from_fs8_hr_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb / 16.0f) * 3.91f;
105 }
106
iis2dh_from_fs16_hr_to_mg(int16_t lsb)107 float_t iis2dh_from_fs16_hr_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb / 16.0f) * 11.72f;
110 }
111
iis2dh_from_lsb_hr_to_celsius(int16_t lsb)112 float_t iis2dh_from_lsb_hr_to_celsius(int16_t lsb)
113 {
114 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
115 }
116
iis2dh_from_fs2_nm_to_mg(int16_t lsb)117 float_t iis2dh_from_fs2_nm_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb / 64.0f) * 3.91f;
120 }
121
iis2dh_from_fs4_nm_to_mg(int16_t lsb)122 float_t iis2dh_from_fs4_nm_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb / 64.0f) * 7.81f;
125 }
126
iis2dh_from_fs8_nm_to_mg(int16_t lsb)127 float_t iis2dh_from_fs8_nm_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb / 64.0f) * 15.63f;
130 }
131
iis2dh_from_fs16_nm_to_mg(int16_t lsb)132 float_t iis2dh_from_fs16_nm_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb / 64.0f) * 46.95f;
135 }
136
iis2dh_from_lsb_nm_to_celsius(int16_t lsb)137 float_t iis2dh_from_lsb_nm_to_celsius(int16_t lsb)
138 {
139 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
140 }
141
iis2dh_from_fs2_lp_to_mg(int16_t lsb)142 float_t iis2dh_from_fs2_lp_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb / 256.0f) * 15.63f;
145 }
146
iis2dh_from_fs4_lp_to_mg(int16_t lsb)147 float_t iis2dh_from_fs4_lp_to_mg(int16_t lsb)
148 {
149 return ((float_t)lsb / 256.0f) * 31.25f;
150 }
151
iis2dh_from_fs8_lp_to_mg(int16_t lsb)152 float_t iis2dh_from_fs8_lp_to_mg(int16_t lsb)
153 {
154 return ((float_t)lsb / 256.0f) * 62.5f;
155 }
156
iis2dh_from_fs16_lp_to_mg(int16_t lsb)157 float_t iis2dh_from_fs16_lp_to_mg(int16_t lsb)
158 {
159 return ((float_t)lsb / 256.0f) * 188.68f;
160 }
161
iis2dh_from_lsb_lp_to_celsius(int16_t lsb)162 float_t iis2dh_from_lsb_lp_to_celsius(int16_t lsb)
163 {
164 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
165 }
166
167 /**
168 * @}
169 *
170 */
171
172 /**
173 * @defgroup IIS2DH_Data_generation
174 * @brief This section group all the functions concerning data generation.
175 * @{
176 *
177 */
178
179 /**
180 * @brief Temperature status register.[get]
181 *
182 * @param ctx read / write interface definitions
183 * @param buff buffer that stores data read
184 * @retval interface status (MANDATORY: return 0 -> no Error)
185 *
186 */
iis2dh_temp_status_reg_get(stmdev_ctx_t * ctx,uint8_t * buff)187 int32_t iis2dh_temp_status_reg_get(stmdev_ctx_t *ctx, uint8_t *buff)
188 {
189 int32_t ret;
190
191 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX, buff, 1);
192
193 return ret;
194 }
195 /**
196 * @brief Temperature data available.[get]
197 *
198 * @param ctx read / write interface definitions
199 * @param val change the values of tda in reg STATUS_REG_AUX
200 * @retval interface status (MANDATORY: return 0 -> no Error)
201 *
202 */
iis2dh_temp_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)203 int32_t iis2dh_temp_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
204 {
205 iis2dh_status_reg_aux_t status_reg_aux;
206 int32_t ret;
207
208 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX,
209 (uint8_t *)&status_reg_aux, 1);
210 *val = status_reg_aux.tda;
211
212 return ret;
213 }
214 /**
215 * @brief Temperature data overrun.[get]
216 *
217 * @param ctx read / write interface definitions
218 * @param val change the values of tor in reg STATUS_REG_AUX
219 * @retval interface status (MANDATORY: return 0 -> no Error)
220 *
221 */
iis2dh_temp_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)222 int32_t iis2dh_temp_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
223 {
224 iis2dh_status_reg_aux_t status_reg_aux;
225 int32_t ret;
226
227 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG_AUX,
228 (uint8_t *)&status_reg_aux, 1);
229 *val = status_reg_aux.tor;
230
231 return ret;
232 }
233 /**
234 * @brief Temperature output value.[get]
235 *
236 * @param ctx read / write interface definitions
237 * @param buff buffer that stores data read
238 * @retval interface status (MANDATORY: return 0 -> no Error)
239 *
240 */
iis2dh_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)241 int32_t iis2dh_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
242 {
243 uint8_t buff[2];
244 int32_t ret;
245
246 ret = iis2dh_read_reg(ctx, IIS2DH_OUT_TEMP_L, buff, 2);
247 *val = (int16_t)buff[1];
248 *val = (*val * 256) + (int16_t)buff[0];
249
250 return ret;
251 }
252 /**
253 * @brief Temperature sensor enable.[set]
254 *
255 * @param ctx read / write interface definitions
256 * @param val change the values of temp_en in reg TEMP_CFG_REG
257 * @retval interface status (MANDATORY: return 0 -> no Error)
258 *
259 */
iis2dh_temperature_meas_set(stmdev_ctx_t * ctx,iis2dh_temp_en_t val)260 int32_t iis2dh_temperature_meas_set(stmdev_ctx_t *ctx,
261 iis2dh_temp_en_t val)
262 {
263 iis2dh_temp_cfg_reg_t temp_cfg_reg;
264 int32_t ret;
265
266 ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG,
267 (uint8_t *)&temp_cfg_reg, 1);
268
269 if (ret == 0)
270 {
271 temp_cfg_reg.temp_en = (uint8_t) val;
272 ret = iis2dh_write_reg(ctx, IIS2DH_TEMP_CFG_REG,
273 (uint8_t *)&temp_cfg_reg, 1);
274 }
275
276 return ret;
277 }
278
279 /**
280 * @brief Temperature sensor enable.[get]
281 *
282 * @param ctx read / write interface definitions
283 * @param val get the values of temp_en in reg TEMP_CFG_REG
284 * @retval interface status (MANDATORY: return 0 -> no Error)
285 *
286 */
iis2dh_temperature_meas_get(stmdev_ctx_t * ctx,iis2dh_temp_en_t * val)287 int32_t iis2dh_temperature_meas_get(stmdev_ctx_t *ctx,
288 iis2dh_temp_en_t *val)
289 {
290 iis2dh_temp_cfg_reg_t temp_cfg_reg;
291 int32_t ret;
292
293 ret = iis2dh_read_reg(ctx, IIS2DH_TEMP_CFG_REG,
294 (uint8_t *)&temp_cfg_reg, 1);
295
296 switch (temp_cfg_reg.temp_en)
297 {
298 case IIS2DH_TEMP_DISABLE:
299 *val = IIS2DH_TEMP_DISABLE;
300 break;
301
302 case IIS2DH_TEMP_ENABLE:
303 *val = IIS2DH_TEMP_ENABLE;
304 break;
305
306 default:
307 *val = IIS2DH_TEMP_DISABLE;
308 break;
309 }
310
311 return ret;
312 }
313
314 /**
315 * @brief Operating mode selection.[set]
316 *
317 * @param ctx read / write interface definitions
318 * @param val change the values of lpen in reg CTRL_REG1
319 * and HR in reg CTRL_REG4
320 * @retval interface status (MANDATORY: return 0 -> no Error)
321 *
322 */
iis2dh_operating_mode_set(stmdev_ctx_t * ctx,iis2dh_op_md_t val)323 int32_t iis2dh_operating_mode_set(stmdev_ctx_t *ctx,
324 iis2dh_op_md_t val)
325 {
326 iis2dh_ctrl_reg1_t ctrl_reg1;
327 iis2dh_ctrl_reg4_t ctrl_reg4;
328 int32_t ret;
329
330 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
331
332 if (ret == 0)
333 {
334 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
335 }
336
337 if (ret == 0)
338 {
339 if (val == IIS2DH_HR_12bit)
340 {
341 ctrl_reg1.lpen = 0;
342 ctrl_reg4.hr = 1;
343 }
344
345 if (val == IIS2DH_NM_10bit)
346 {
347 ctrl_reg1.lpen = 0;
348 ctrl_reg4.hr = 0;
349 }
350
351 if (val == IIS2DH_LP_8bit)
352 {
353 ctrl_reg1.lpen = 1;
354 ctrl_reg4.hr = 0;
355 }
356
357 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
358 }
359
360 if (ret == 0)
361 {
362 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
363 }
364
365 return ret;
366 }
367
368 /**
369 * @brief Operating mode selection.[get]
370 *
371 * @param ctx read / write interface definitions
372 * @param val change the values of lpen in reg CTRL_REG1
373 * @retval interface status (MANDATORY: return 0 -> no Error)
374 *
375 */
iis2dh_operating_mode_get(stmdev_ctx_t * ctx,iis2dh_op_md_t * val)376 int32_t iis2dh_operating_mode_get(stmdev_ctx_t *ctx,
377 iis2dh_op_md_t *val)
378 {
379 iis2dh_ctrl_reg1_t ctrl_reg1;
380 iis2dh_ctrl_reg4_t ctrl_reg4;
381 int32_t ret;
382
383 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
384
385 if (ret == 0)
386 {
387 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
388
389 if (ctrl_reg1.lpen == PROPERTY_ENABLE)
390 {
391 *val = IIS2DH_LP_8bit;
392 }
393
394 else if (ctrl_reg4.hr == PROPERTY_ENABLE)
395 {
396 *val = IIS2DH_HR_12bit;
397 }
398
399 else
400 {
401 *val = IIS2DH_NM_10bit;
402 }
403 }
404
405 return ret;
406 }
407
408 /**
409 * @brief Output data rate selection.[set]
410 *
411 * @param ctx read / write interface definitions
412 * @param val change the values of odr in reg CTRL_REG1
413 * @retval interface status (MANDATORY: return 0 -> no Error)
414 *
415 */
iis2dh_data_rate_set(stmdev_ctx_t * ctx,iis2dh_odr_t val)416 int32_t iis2dh_data_rate_set(stmdev_ctx_t *ctx, iis2dh_odr_t val)
417 {
418 iis2dh_ctrl_reg1_t ctrl_reg1;
419 int32_t ret;
420
421 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
422
423 if (ret == 0)
424 {
425 ctrl_reg1.odr = (uint8_t)val;
426 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
427 }
428
429 return ret;
430 }
431
432 /**
433 * @brief Output data rate selection.[get]
434 *
435 * @param ctx read / write interface definitions
436 * @param val get the values of odr in reg CTRL_REG1
437 * @retval interface status (MANDATORY: return 0 -> no Error)
438 *
439 */
iis2dh_data_rate_get(stmdev_ctx_t * ctx,iis2dh_odr_t * val)440 int32_t iis2dh_data_rate_get(stmdev_ctx_t *ctx, iis2dh_odr_t *val)
441 {
442 iis2dh_ctrl_reg1_t ctrl_reg1;
443 int32_t ret;
444
445 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG1, (uint8_t *)&ctrl_reg1, 1);
446
447 switch (ctrl_reg1.odr)
448 {
449 case IIS2DH_POWER_DOWN:
450 *val = IIS2DH_POWER_DOWN;
451 break;
452
453 case IIS2DH_ODR_1Hz:
454 *val = IIS2DH_ODR_1Hz;
455 break;
456
457 case IIS2DH_ODR_10Hz:
458 *val = IIS2DH_ODR_10Hz;
459 break;
460
461 case IIS2DH_ODR_25Hz:
462 *val = IIS2DH_ODR_25Hz;
463 break;
464
465 case IIS2DH_ODR_50Hz:
466 *val = IIS2DH_ODR_50Hz;
467 break;
468
469 case IIS2DH_ODR_100Hz:
470 *val = IIS2DH_ODR_100Hz;
471 break;
472
473 case IIS2DH_ODR_200Hz:
474 *val = IIS2DH_ODR_200Hz;
475 break;
476
477 case IIS2DH_ODR_400Hz:
478 *val = IIS2DH_ODR_400Hz;
479 break;
480
481 case IIS2DH_ODR_1kHz620_LP:
482 *val = IIS2DH_ODR_1kHz620_LP;
483 break;
484
485 case IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP:
486 *val = IIS2DH_ODR_5kHz376_LP_1kHz344_NM_HP;
487 break;
488
489 default:
490 *val = IIS2DH_POWER_DOWN;
491 break;
492 }
493
494 return ret;
495 }
496
497 /**
498 * @brief High pass data from internal filter sent to output register
499 * and FIFO.
500 *
501 * @param ctx read / write interface definitions
502 * @param val change the values of fds in reg CTRL_REG2
503 * @retval interface status (MANDATORY: return 0 -> no Error)
504 *
505 */
iis2dh_high_pass_on_outputs_set(stmdev_ctx_t * ctx,uint8_t val)506 int32_t iis2dh_high_pass_on_outputs_set(stmdev_ctx_t *ctx,
507 uint8_t val)
508 {
509 iis2dh_ctrl_reg2_t ctrl_reg2;
510 int32_t ret;
511
512 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
513
514 if (ret == 0)
515 {
516 ctrl_reg2.fds = val;
517 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
518 }
519
520 return ret;
521 }
522
523 /**
524 * @brief High pass data from internal filter sent to output register
525 * and FIFO.[get]
526 *
527 * @param ctx read / write interface definitions
528 * @param val change the values of fds in reg CTRL_REG2
529 * @retval interface status (MANDATORY: return 0 -> no Error)
530 *
531 */
iis2dh_high_pass_on_outputs_get(stmdev_ctx_t * ctx,uint8_t * val)532 int32_t iis2dh_high_pass_on_outputs_get(stmdev_ctx_t *ctx,
533 uint8_t *val)
534 {
535 iis2dh_ctrl_reg2_t ctrl_reg2;
536 int32_t ret;
537
538 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
539 *val = (uint8_t)ctrl_reg2.fds;
540
541 return ret;
542 }
543
544 /**
545 * @brief High-pass filter cutoff frequency selection.[set]
546 *
547 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
548 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
549 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
550 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
551 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
552 *
553 * @param ctx read / write interface definitions
554 * @param val change the values of hpcf in reg CTRL_REG2
555 * @retval interface status (MANDATORY: return 0 -> no Error)
556 *
557 */
iis2dh_high_pass_bandwidth_set(stmdev_ctx_t * ctx,iis2dh_hpcf_t val)558 int32_t iis2dh_high_pass_bandwidth_set(stmdev_ctx_t *ctx,
559 iis2dh_hpcf_t val)
560 {
561 iis2dh_ctrl_reg2_t ctrl_reg2;
562 int32_t ret;
563
564 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
565
566 if (ret == 0)
567 {
568 ctrl_reg2.hpcf = (uint8_t)val;
569 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
570 }
571
572 return ret;
573 }
574
575 /**
576 * @brief High-pass filter cutoff frequency selection.[get]
577 *
578 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
579 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
580 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
581 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
582 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
583 *
584 * @param ctx read / write interface definitions
585 * @param val get the values of hpcf in reg CTRL_REG2
586 * @retval interface status (MANDATORY: return 0 -> no Error)
587 *
588 */
iis2dh_high_pass_bandwidth_get(stmdev_ctx_t * ctx,iis2dh_hpcf_t * val)589 int32_t iis2dh_high_pass_bandwidth_get(stmdev_ctx_t *ctx,
590 iis2dh_hpcf_t *val)
591 {
592 iis2dh_ctrl_reg2_t ctrl_reg2;
593 int32_t ret;
594
595 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
596
597 switch (ctrl_reg2.hpcf)
598 {
599 case IIS2DH_AGGRESSIVE:
600 *val = IIS2DH_AGGRESSIVE;
601 break;
602
603 case IIS2DH_STRONG:
604 *val = IIS2DH_STRONG;
605 break;
606
607 case IIS2DH_MEDIUM:
608 *val = IIS2DH_MEDIUM;
609 break;
610
611 case IIS2DH_LIGHT:
612 *val = IIS2DH_LIGHT;
613 break;
614
615 default:
616 *val = IIS2DH_LIGHT;
617 break;
618 }
619
620 return ret;
621 }
622
623 /**
624 * @brief High-pass filter mode selection.[set]
625 *
626 * @param ctx read / write interface definitions
627 * @param val change the values of hpm in reg CTRL_REG2
628 * @retval interface status (MANDATORY: return 0 -> no Error)
629 *
630 */
iis2dh_high_pass_mode_set(stmdev_ctx_t * ctx,iis2dh_hpm_t val)631 int32_t iis2dh_high_pass_mode_set(stmdev_ctx_t *ctx, iis2dh_hpm_t val)
632 {
633 iis2dh_ctrl_reg2_t ctrl_reg2;
634 int32_t ret;
635
636 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
637
638 if (ret == 0)
639 {
640 ctrl_reg2.hpm = (uint8_t)val;
641 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
642 }
643
644 return ret;
645 }
646
647 /**
648 * @brief High-pass filter mode selection.[get]
649 *
650 * @param ctx read / write interface definitions
651 * @param val get the values of hpm in reg CTRL_REG2
652 * @retval interface status (MANDATORY: return 0 -> no Error)
653 *
654 */
iis2dh_high_pass_mode_get(stmdev_ctx_t * ctx,iis2dh_hpm_t * val)655 int32_t iis2dh_high_pass_mode_get(stmdev_ctx_t *ctx,
656 iis2dh_hpm_t *val)
657 {
658 iis2dh_ctrl_reg2_t ctrl_reg2;
659 int32_t ret;
660
661 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
662
663 switch (ctrl_reg2.hpm)
664 {
665 case IIS2DH_NORMAL_WITH_RST:
666 *val = IIS2DH_NORMAL_WITH_RST;
667 break;
668
669 case IIS2DH_REFERENCE_MODE:
670 *val = IIS2DH_REFERENCE_MODE;
671 break;
672
673 case IIS2DH_NORMAL:
674 *val = IIS2DH_NORMAL;
675 break;
676
677 case IIS2DH_AUTORST_ON_INT:
678 *val = IIS2DH_AUTORST_ON_INT;
679 break;
680
681 default:
682 *val = IIS2DH_NORMAL_WITH_RST;
683 break;
684 }
685
686 return ret;
687 }
688
689 /**
690 * @brief Full-scale configuration.[set]
691 *
692 * @param ctx read / write interface definitions
693 * @param val change the values of fs in reg CTRL_REG4
694 * @retval interface status (MANDATORY: return 0 -> no Error)
695 *
696 */
iis2dh_full_scale_set(stmdev_ctx_t * ctx,iis2dh_fs_t val)697 int32_t iis2dh_full_scale_set(stmdev_ctx_t *ctx, iis2dh_fs_t val)
698 {
699 iis2dh_ctrl_reg4_t ctrl_reg4;
700 int32_t ret;
701
702 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
703
704 if (ret == 0)
705 {
706 ctrl_reg4.fs = (uint8_t)val;
707 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
708 }
709
710 return ret;
711 }
712
713 /**
714 * @brief Full-scale configuration.[get]
715 *
716 * @param ctx read / write interface definitions
717 * @param val get the values of fs in reg CTRL_REG4
718 * @retval interface status (MANDATORY: return 0 -> no Error)
719 *
720 */
iis2dh_full_scale_get(stmdev_ctx_t * ctx,iis2dh_fs_t * val)721 int32_t iis2dh_full_scale_get(stmdev_ctx_t *ctx, iis2dh_fs_t *val)
722 {
723 iis2dh_ctrl_reg4_t ctrl_reg4;
724 int32_t ret;
725
726 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
727
728 switch (ctrl_reg4.fs)
729 {
730 case IIS2DH_2g:
731 *val = IIS2DH_2g;
732 break;
733
734 case IIS2DH_4g:
735 *val = IIS2DH_4g;
736 break;
737
738 case IIS2DH_8g:
739 *val = IIS2DH_8g;
740 break;
741
742 case IIS2DH_16g:
743 *val = IIS2DH_16g;
744 break;
745
746 default:
747 *val = IIS2DH_2g;
748 break;
749 }
750
751 return ret;
752 }
753
754 /**
755 * @brief Block Data Update.[set]
756 *
757 * @param ctx read / write interface definitions
758 * @param val change the values of bdu in reg CTRL_REG4
759 * @retval interface status (MANDATORY: return 0 -> no Error)
760 *
761 */
iis2dh_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)762 int32_t iis2dh_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
763 {
764 iis2dh_ctrl_reg4_t ctrl_reg4;
765 int32_t ret;
766
767 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
768
769 if (ret == 0)
770 {
771 ctrl_reg4.bdu = val;
772 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
773 }
774
775 return ret;
776 }
777
778 /**
779 * @brief Block Data Update.[get]
780 *
781 * @param ctx read / write interface definitions
782 * @param val change the values of bdu in reg CTRL_REG4
783 * @retval interface status (MANDATORY: return 0 -> no Error)
784 *
785 */
iis2dh_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)786 int32_t iis2dh_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
787 {
788 iis2dh_ctrl_reg4_t ctrl_reg4;
789 int32_t ret;
790
791 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
792 *val = (uint8_t)ctrl_reg4.bdu;
793
794 return ret;
795 }
796
797 /**
798 * @brief Reference value for interrupt generation.[set]
799 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
800 *
801 * @param ctx read / write interface definitions
802 * @param buff buffer that contains data to write
803 * @retval interface status (MANDATORY: return 0 -> no Error)
804 *
805 */
iis2dh_filter_reference_set(stmdev_ctx_t * ctx,uint8_t * buff)806 int32_t iis2dh_filter_reference_set(stmdev_ctx_t *ctx, uint8_t *buff)
807 {
808 int32_t ret;
809
810 ret = iis2dh_write_reg(ctx, IIS2DH_REFERENCE, buff, 1);
811
812 return ret;
813 }
814
815 /**
816 * @brief Reference value for interrupt generation.[get]
817 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
818 *
819 * @param ctx read / write interface definitions
820 * @param buff buffer that stores data read
821 * @retval interface status (MANDATORY: return 0 -> no Error)
822 *
823 */
iis2dh_filter_reference_get(stmdev_ctx_t * ctx,uint8_t * buff)824 int32_t iis2dh_filter_reference_get(stmdev_ctx_t *ctx, uint8_t *buff)
825 {
826 int32_t ret;
827
828 ret = iis2dh_read_reg(ctx, IIS2DH_REFERENCE, buff, 1);
829
830 return ret;
831 }
832 /**
833 * @brief Acceleration set of data available.[get]
834 *
835 * @param ctx read / write interface definitions
836 * @param val change the values of zyxda in reg STATUS_REG
837 * @retval interface status (MANDATORY: return 0 -> no Error)
838 *
839 */
iis2dh_xl_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)840 int32_t iis2dh_xl_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
841 {
842 iis2dh_status_reg_t status_reg;
843 int32_t ret;
844
845 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1);
846 *val = status_reg.zyxda;
847
848 return ret;
849 }
850 /**
851 * @brief Acceleration set of data overrun.[get]
852 *
853 * @param ctx read / write interface definitions
854 * @param val change the values of zyxor in reg STATUS_REG
855 * @retval interface status (MANDATORY: return 0 -> no Error)
856 *
857 */
iis2dh_xl_data_ovr_get(stmdev_ctx_t * ctx,uint8_t * val)858 int32_t iis2dh_xl_data_ovr_get(stmdev_ctx_t *ctx, uint8_t *val)
859 {
860 iis2dh_status_reg_t status_reg;
861 int32_t ret;
862
863 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *)&status_reg, 1);
864 *val = status_reg.zyxor;
865
866 return ret;
867 }
868 /**
869 * @brief Acceleration output value.[get]
870 *
871 * @param ctx read / write interface definitions
872 * @param buff buffer that stores data read
873 * @retval interface status (MANDATORY: return 0 -> no Error)
874 *
875 */
iis2dh_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)876 int32_t iis2dh_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
877 {
878 uint8_t buff[6];
879 int32_t ret;
880
881 ret = iis2dh_read_reg(ctx, IIS2DH_OUT_X_L, buff, 6);
882 val[0] = (int16_t)buff[1];
883 val[0] = (val[0] * 256) + (int16_t)buff[0];
884 val[1] = (int16_t)buff[3];
885 val[1] = (val[1] * 256) + (int16_t)buff[2];
886 val[2] = (int16_t)buff[5];
887 val[2] = (val[2] * 256) + (int16_t)buff[4];
888
889 return ret;
890 }
891 /**
892 * @}
893 *
894 */
895
896 /**
897 * @defgroup IIS2DH_Common
898 * @brief This section group common useful functions
899 * @{
900 *
901 */
902
903 /**
904 * @brief DeviceWhoamI .[get]
905 *
906 * @param ctx read / write interface definitions
907 * @param buff buffer that stores data read
908 * @retval interface status (MANDATORY: return 0 -> no Error)
909 *
910 */
iis2dh_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)911 int32_t iis2dh_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
912 {
913 int32_t ret;
914
915 ret = iis2dh_read_reg(ctx, IIS2DH_WHO_AM_I, buff, 1);
916
917 return ret;
918 }
919 /**
920 * @brief Self Test.[set]
921 *
922 * @param ctx read / write interface definitions
923 * @param val change the values of st in reg CTRL_REG4
924 * @retval interface status (MANDATORY: return 0 -> no Error)
925 *
926 */
iis2dh_self_test_set(stmdev_ctx_t * ctx,iis2dh_st_t val)927 int32_t iis2dh_self_test_set(stmdev_ctx_t *ctx, iis2dh_st_t val)
928 {
929 iis2dh_ctrl_reg4_t ctrl_reg4;
930 int32_t ret;
931
932 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
933
934 if (ret == 0)
935 {
936 ctrl_reg4.st = (uint8_t)val;
937 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
938 }
939
940 return ret;
941 }
942
943 /**
944 * @brief Self Test.[get]
945 *
946 * @param ctx read / write interface definitions
947 * @param val Get the values of st in reg CTRL_REG4
948 * @retval interface status (MANDATORY: return 0 -> no Error)
949 *
950 */
iis2dh_self_test_get(stmdev_ctx_t * ctx,iis2dh_st_t * val)951 int32_t iis2dh_self_test_get(stmdev_ctx_t *ctx, iis2dh_st_t *val)
952 {
953 iis2dh_ctrl_reg4_t ctrl_reg4;
954 int32_t ret;
955
956 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
957
958 switch (ctrl_reg4.st)
959 {
960 case IIS2DH_ST_DISABLE:
961 *val = IIS2DH_ST_DISABLE;
962 break;
963
964 case IIS2DH_ST_POSITIVE:
965 *val = IIS2DH_ST_POSITIVE;
966 break;
967
968 case IIS2DH_ST_NEGATIVE:
969 *val = IIS2DH_ST_NEGATIVE;
970 break;
971
972 default:
973 *val = IIS2DH_ST_DISABLE;
974 break;
975 }
976
977 return ret;
978 }
979
980 /**
981 * @brief Big/Little Endian data selection.[set]
982 *
983 * @param ctx read / write interface definitions
984 * @param val change the values of ble in reg CTRL_REG4
985 * @retval interface status (MANDATORY: return 0 -> no Error)
986 *
987 */
iis2dh_data_format_set(stmdev_ctx_t * ctx,iis2dh_ble_t val)988 int32_t iis2dh_data_format_set(stmdev_ctx_t *ctx, iis2dh_ble_t val)
989 {
990 iis2dh_ctrl_reg4_t ctrl_reg4;
991 int32_t ret;
992
993 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
994
995 if (ret == 0)
996 {
997 ctrl_reg4.ble = (uint8_t)val;
998 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
999 }
1000
1001 return ret;
1002 }
1003
1004 /**
1005 * @brief Big/Little Endian data selection.[get]
1006 *
1007 * @param ctx read / write interface definitions
1008 * @param val get the values of ble in reg CTRL_REG4
1009 * @retval interface status (MANDATORY: return 0 -> no Error)
1010 *
1011 */
iis2dh_data_format_get(stmdev_ctx_t * ctx,iis2dh_ble_t * val)1012 int32_t iis2dh_data_format_get(stmdev_ctx_t *ctx, iis2dh_ble_t *val)
1013 {
1014 iis2dh_ctrl_reg4_t ctrl_reg4;
1015 int32_t ret;
1016
1017 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
1018
1019 switch (ctrl_reg4.ble)
1020 {
1021 case IIS2DH_LSB_AT_LOW_ADD:
1022 *val = IIS2DH_LSB_AT_LOW_ADD;
1023 break;
1024
1025 case IIS2DH_MSB_AT_LOW_ADD:
1026 *val = IIS2DH_MSB_AT_LOW_ADD;
1027 break;
1028
1029 default:
1030 *val = IIS2DH_LSB_AT_LOW_ADD;
1031 break;
1032 }
1033
1034 return ret;
1035 }
1036
1037 /**
1038 * @brief Reboot memory content. Reload the calibration parameters.[set]
1039 *
1040 * @param ctx read / write interface definitions
1041 * @param val change the values of boot in reg CTRL_REG5
1042 * @retval interface status (MANDATORY: return 0 -> no Error)
1043 *
1044 */
iis2dh_boot_set(stmdev_ctx_t * ctx,uint8_t val)1045 int32_t iis2dh_boot_set(stmdev_ctx_t *ctx, uint8_t val)
1046 {
1047 iis2dh_ctrl_reg5_t ctrl_reg5;
1048 int32_t ret;
1049
1050 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1051
1052 if (ret == 0)
1053 {
1054 ctrl_reg5.boot = val;
1055 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1056 }
1057
1058 return ret;
1059 }
1060
1061 /**
1062 * @brief Reboot memory content. Reload the calibration parameters.[get]
1063 *
1064 * @param ctx read / write interface definitions
1065 * @param val change the values of boot in reg CTRL_REG5
1066 * @retval interface status (MANDATORY: return 0 -> no Error)
1067 *
1068 */
iis2dh_boot_get(stmdev_ctx_t * ctx,uint8_t * val)1069 int32_t iis2dh_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
1070 {
1071 iis2dh_ctrl_reg5_t ctrl_reg5;
1072 int32_t ret;
1073
1074 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1075 *val = (uint8_t)ctrl_reg5.boot;
1076
1077 return ret;
1078 }
1079
1080 /**
1081 * @brief count the interrupt occurrencies.[get]
1082 *
1083 * @param ctx read / write interface definitions
1084 * @param val registers INT_COUNTER_REG
1085 * @retval interface status (MANDATORY: return 0 -> no Error)
1086 *
1087 */
iis2dh_int_occurrencies_get(stmdev_ctx_t * ctx,uint8_t * val)1088 int32_t iis2dh_int_occurrencies_get(stmdev_ctx_t *ctx, uint8_t *val)
1089 {
1090 int32_t ret;
1091
1092 ret = iis2dh_read_reg(ctx, IIS2DH_INT_COUNTER_REG, (uint8_t *) val, 1);
1093
1094 return ret;
1095 }
1096
1097 /**
1098 * @brief Info about device status.[get]
1099 *
1100 * @param ctx read / write interface definitions
1101 * @param val register STATUS_REG
1102 * @retval interface status (MANDATORY: return 0 -> no Error)
1103 *
1104 */
iis2dh_status_get(stmdev_ctx_t * ctx,iis2dh_status_reg_t * val)1105 int32_t iis2dh_status_get(stmdev_ctx_t *ctx, iis2dh_status_reg_t *val)
1106 {
1107 int32_t ret;
1108
1109 ret = iis2dh_read_reg(ctx, IIS2DH_STATUS_REG, (uint8_t *) val, 1);
1110
1111 return ret;
1112 }
1113 /**
1114 * @}
1115 *
1116 */
1117
1118 /**
1119 * @defgroup IIS2DH_Interrupts_generator_1
1120 * @brief This section group all the functions that manage the first
1121 * interrupts generator
1122 * @{
1123 *
1124 */
1125
1126 /**
1127 * @brief Interrupt generator 1 configuration register.[set]
1128 *
1129 * @param ctx read / write interface definitions
1130 * @param val register INT1_CFG
1131 * @retval interface status (MANDATORY: return 0 -> no Error)
1132 *
1133 */
iis2dh_int1_gen_conf_set(stmdev_ctx_t * ctx,iis2dh_int1_cfg_t * val)1134 int32_t iis2dh_int1_gen_conf_set(stmdev_ctx_t *ctx,
1135 iis2dh_int1_cfg_t *val)
1136 {
1137 int32_t ret;
1138
1139 ret = iis2dh_write_reg(ctx, IIS2DH_INT1_CFG, (uint8_t *) val, 1);
1140
1141 return ret;
1142 }
1143
1144 /**
1145 * @brief Interrupt generator 1 configuration register.[get]
1146 *
1147 * @param ctx read / write interface definitions
1148 * @param val register INT1_CFG
1149 * @retval interface status (MANDATORY: return 0 -> no Error)
1150 *
1151 */
iis2dh_int1_gen_conf_get(stmdev_ctx_t * ctx,iis2dh_int1_cfg_t * val)1152 int32_t iis2dh_int1_gen_conf_get(stmdev_ctx_t *ctx,
1153 iis2dh_int1_cfg_t *val)
1154 {
1155 int32_t ret;
1156
1157 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_CFG, (uint8_t *) val, 1);
1158
1159 return ret;
1160 }
1161
1162 /**
1163 * @brief Interrupt generator 1 source register.[get]
1164 *
1165 * @param ctx read / write interface definitions
1166 * @param val Registers INT1_SRC
1167 * @retval interface status (MANDATORY: return 0 -> no Error)
1168 *
1169 */
iis2dh_int1_gen_source_get(stmdev_ctx_t * ctx,iis2dh_int1_src_t * val)1170 int32_t iis2dh_int1_gen_source_get(stmdev_ctx_t *ctx,
1171 iis2dh_int1_src_t *val)
1172 {
1173 int32_t ret;
1174
1175 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_SRC, (uint8_t *) val, 1);
1176
1177 return ret;
1178 }
1179 /**
1180 * @brief User-defined threshold value for xl interrupt event on
1181 * generator 1.[set]
1182 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1183 *
1184 * @param ctx read / write interface definitions
1185 * @param val change the values of ths in reg INT1_THS
1186 * @retval interface status (MANDATORY: return 0 -> no Error)
1187 *
1188 */
iis2dh_int1_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1189 int32_t iis2dh_int1_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
1190 {
1191 iis2dh_int1_ths_t int1_ths;
1192 int32_t ret;
1193
1194 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1195
1196 if (ret == 0)
1197 {
1198 int1_ths.ths = val;
1199 ret = iis2dh_write_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1200 }
1201
1202 return ret;
1203 }
1204
1205 /**
1206 * @brief User-defined threshold value for xl interrupt event on
1207 * generator 1.[get]
1208 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1209 *
1210 * @param ctx read / write interface definitions
1211 * @param val change the values of ths in reg INT1_THS
1212 * @retval interface status (MANDATORY: return 0 -> no Error)
1213 *
1214 */
iis2dh_int1_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1215 int32_t iis2dh_int1_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1216 {
1217 iis2dh_int1_ths_t int1_ths;
1218 int32_t ret;
1219
1220 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_THS, (uint8_t *)&int1_ths, 1);
1221 *val = (uint8_t)int1_ths.ths;
1222
1223 return ret;
1224 }
1225
1226 /**
1227 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1228 * recognized.[set]
1229 *
1230 * @param ctx read / write interface definitions
1231 * @param val change the values of d in reg INT1_DURATION
1232 * @retval interface status (MANDATORY: return 0 -> no Error)
1233 *
1234 */
iis2dh_int1_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1235 int32_t iis2dh_int1_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1236 {
1237 iis2dh_int1_duration_t int1_duration;
1238 int32_t ret;
1239
1240 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_DURATION,
1241 (uint8_t *)&int1_duration, 1);
1242
1243 if (ret == 0)
1244 {
1245 int1_duration.d = val;
1246 ret = iis2dh_write_reg(ctx, IIS2DH_INT1_DURATION,
1247 (uint8_t *)&int1_duration, 1);
1248 }
1249
1250 return ret;
1251 }
1252
1253 /**
1254 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1255 * recognized.[get]
1256 *
1257 * @param ctx read / write interface definitions
1258 * @param val change the values of d in reg INT1_DURATION
1259 * @retval interface status (MANDATORY: return 0 -> no Error)
1260 *
1261 */
iis2dh_int1_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1262 int32_t iis2dh_int1_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
1263 {
1264 iis2dh_int1_duration_t int1_duration;
1265 int32_t ret;
1266
1267 ret = iis2dh_read_reg(ctx, IIS2DH_INT1_DURATION,
1268 (uint8_t *)&int1_duration, 1);
1269 *val = (uint8_t)int1_duration.d;
1270
1271 return ret;
1272 }
1273
1274 /**
1275 * @}
1276 *
1277 */
1278
1279 /**
1280 * @defgroup IIS2DH_Interrupts_generator_2
1281 * @brief This section group all the functions that manage the second
1282 * interrupts generator
1283 * @{
1284 *
1285 */
1286
1287 /**
1288 * @brief Interrupt generator 2 configuration register.[set]
1289 *
1290 * @param ctx read / write interface definitions
1291 * @param val registers INT2_CFG
1292 * @retval interface status (MANDATORY: return 0 -> no Error)
1293 *
1294 */
iis2dh_int2_gen_conf_set(stmdev_ctx_t * ctx,iis2dh_int2_cfg_t * val)1295 int32_t iis2dh_int2_gen_conf_set(stmdev_ctx_t *ctx,
1296 iis2dh_int2_cfg_t *val)
1297 {
1298 int32_t ret;
1299
1300 ret = iis2dh_write_reg(ctx, IIS2DH_INT2_CFG, (uint8_t *) val, 1);
1301
1302 return ret;
1303 }
1304
1305 /**
1306 * @brief Interrupt generator 2 configuration register.[get]
1307 *
1308 * @param ctx read / write interface definitions
1309 * @param val registers INT2_CFG
1310 * @retval interface status (MANDATORY: return 0 -> no Error)
1311 *
1312 */
iis2dh_int2_gen_conf_get(stmdev_ctx_t * ctx,iis2dh_int2_cfg_t * val)1313 int32_t iis2dh_int2_gen_conf_get(stmdev_ctx_t *ctx,
1314 iis2dh_int2_cfg_t *val)
1315 {
1316 int32_t ret;
1317
1318 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_CFG, (uint8_t *) val, 1);
1319
1320 return ret;
1321 }
1322 /**
1323 * @brief Interrupt generator 2 source register.[get]
1324 *
1325 * @param ctx read / write interface definitions
1326 * @param val registers INT2_SRC
1327 * @retval interface status (MANDATORY: return 0 -> no Error)
1328 *
1329 */
iis2dh_int2_gen_source_get(stmdev_ctx_t * ctx,iis2dh_int2_src_t * val)1330 int32_t iis2dh_int2_gen_source_get(stmdev_ctx_t *ctx,
1331 iis2dh_int2_src_t *val)
1332 {
1333 int32_t ret;
1334
1335 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_SRC, (uint8_t *) val, 1);
1336
1337 return ret;
1338 }
1339 /**
1340 * @brief User-defined threshold value for xl interrupt event on
1341 * generator 2.[set]
1342 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1343 *
1344 * @param ctx read / write interface definitions
1345 * @param val change the values of ths in reg INT2_THS
1346 * @retval interface status (MANDATORY: return 0 -> no Error)
1347 *
1348 */
iis2dh_int2_gen_threshold_set(stmdev_ctx_t * ctx,uint8_t val)1349 int32_t iis2dh_int2_gen_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
1350 {
1351 iis2dh_int2_ths_t int2_ths;
1352 int32_t ret;
1353
1354 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1355
1356 if (ret == 0)
1357 {
1358 int2_ths.ths = val;
1359 ret = iis2dh_write_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1360 }
1361
1362 return ret;
1363 }
1364
1365 /**
1366 * @brief User-defined threshold value for xl interrupt event on
1367 * generator 2.[get]
1368 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
1369 *
1370 * @param ctx read / write interface definitions
1371 * @param val change the values of ths in reg INT2_THS
1372 * @retval interface status (MANDATORY: return 0 -> no Error)
1373 *
1374 */
iis2dh_int2_gen_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)1375 int32_t iis2dh_int2_gen_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
1376 {
1377 iis2dh_int2_ths_t int2_ths;
1378 int32_t ret;
1379
1380 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_THS, (uint8_t *)&int2_ths, 1);
1381 *val = (uint8_t)int2_ths.ths;
1382
1383 return ret;
1384 }
1385
1386 /**
1387 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1388 * recognized .[set]
1389 *
1390 * @param ctx read / write interface definitions
1391 * @param val change the values of d in reg INT2_DURATION
1392 * @retval interface status (MANDATORY: return 0 -> no Error)
1393 *
1394 */
iis2dh_int2_gen_duration_set(stmdev_ctx_t * ctx,uint8_t val)1395 int32_t iis2dh_int2_gen_duration_set(stmdev_ctx_t *ctx, uint8_t val)
1396 {
1397 iis2dh_int2_duration_t int2_duration;
1398 int32_t ret;
1399
1400 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_DURATION,
1401 (uint8_t *)&int2_duration, 1);
1402
1403 if (ret == 0)
1404 {
1405 int2_duration.d = val;
1406 ret = iis2dh_write_reg(ctx, IIS2DH_INT2_DURATION,
1407 (uint8_t *)&int2_duration, 1);
1408 }
1409
1410 return ret;
1411 }
1412
1413 /**
1414 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
1415 * recognized.[get]
1416 *
1417 * @param ctx read / write interface definitions
1418 * @param val change the values of d in reg INT2_DURATION
1419 * @retval interface status (MANDATORY: return 0 -> no Error)
1420 *
1421 */
iis2dh_int2_gen_duration_get(stmdev_ctx_t * ctx,uint8_t * val)1422 int32_t iis2dh_int2_gen_duration_get(stmdev_ctx_t *ctx, uint8_t *val)
1423 {
1424 iis2dh_int2_duration_t int2_duration;
1425 int32_t ret;
1426
1427 ret = iis2dh_read_reg(ctx, IIS2DH_INT2_DURATION,
1428 (uint8_t *)&int2_duration, 1);
1429 *val = (uint8_t)int2_duration.d;
1430
1431 return ret;
1432 }
1433
1434 /**
1435 * @}
1436 *
1437 */
1438
1439 /**
1440 * @defgroup IIS2DH_Interrupt_pins
1441 * @brief This section group all the functions that manage interrupt pins
1442 * @{
1443 *
1444 */
1445
1446 /**
1447 * @brief High-pass filter on interrupts/tap generator.[set]
1448 *
1449 * @param ctx read / write interface definitions
1450 * @param val change the values of hp in reg CTRL_REG2
1451 * @retval interface status (MANDATORY: return 0 -> no Error)
1452 *
1453 */
iis2dh_high_pass_int_conf_set(stmdev_ctx_t * ctx,iis2dh_hp_t val)1454 int32_t iis2dh_high_pass_int_conf_set(stmdev_ctx_t *ctx,
1455 iis2dh_hp_t val)
1456 {
1457 iis2dh_ctrl_reg2_t ctrl_reg2;
1458 int32_t ret;
1459
1460 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1461
1462 if (ret == 0)
1463 {
1464 ctrl_reg2.hp = (uint8_t)val;
1465 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1466 }
1467
1468 return ret;
1469 }
1470
1471 /**
1472 * @brief High-pass filter on interrupts/tap generator.[get]
1473 *
1474 * @param ctx read / write interface definitions
1475 * @param val Get the values of hp in reg CTRL_REG2
1476 * @retval interface status (MANDATORY: return 0 -> no Error)
1477 *
1478 */
iis2dh_high_pass_int_conf_get(stmdev_ctx_t * ctx,iis2dh_hp_t * val)1479 int32_t iis2dh_high_pass_int_conf_get(stmdev_ctx_t *ctx,
1480 iis2dh_hp_t *val)
1481 {
1482 iis2dh_ctrl_reg2_t ctrl_reg2;
1483 int32_t ret;
1484
1485 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG2, (uint8_t *)&ctrl_reg2, 1);
1486
1487 switch (ctrl_reg2.hp)
1488 {
1489 case IIS2DH_DISC_FROM_INT_GENERATOR:
1490 *val = IIS2DH_DISC_FROM_INT_GENERATOR;
1491 break;
1492
1493 case IIS2DH_ON_INT1_GEN:
1494 *val = IIS2DH_ON_INT1_GEN;
1495 break;
1496
1497 case IIS2DH_ON_INT2_GEN:
1498 *val = IIS2DH_ON_INT2_GEN;
1499 break;
1500
1501 case IIS2DH_ON_TAP_GEN:
1502 *val = IIS2DH_ON_TAP_GEN;
1503 break;
1504
1505 case IIS2DH_ON_INT1_INT2_GEN:
1506 *val = IIS2DH_ON_INT1_INT2_GEN;
1507 break;
1508
1509 case IIS2DH_ON_INT1_TAP_GEN:
1510 *val = IIS2DH_ON_INT1_TAP_GEN;
1511 break;
1512
1513 case IIS2DH_ON_INT2_TAP_GEN:
1514 *val = IIS2DH_ON_INT2_TAP_GEN;
1515 break;
1516
1517 case IIS2DH_ON_INT1_INT2_TAP_GEN:
1518 *val = IIS2DH_ON_INT1_INT2_TAP_GEN;
1519 break;
1520
1521 default:
1522 *val = IIS2DH_DISC_FROM_INT_GENERATOR;
1523 break;
1524 }
1525
1526 return ret;
1527 }
1528
1529 /**
1530 * @brief Int1 pin routing configuration register.[set]
1531 *
1532 * @param ctx read / write interface definitions
1533 * @param val registers CTRL_REG3
1534 * @retval interface status (MANDATORY: return 0 -> no Error)
1535 *
1536 */
iis2dh_pin_int1_config_set(stmdev_ctx_t * ctx,iis2dh_ctrl_reg3_t * val)1537 int32_t iis2dh_pin_int1_config_set(stmdev_ctx_t *ctx,
1538 iis2dh_ctrl_reg3_t *val)
1539 {
1540 int32_t ret;
1541
1542 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t *) val, 1);
1543
1544 return ret;
1545 }
1546
1547 /**
1548 * @brief Int1 pin routing configuration register.[get]
1549 *
1550 * @param ctx read / write interface definitions
1551 * @param val registers CTRL_REG3
1552 * @retval interface status (MANDATORY: return 0 -> no Error)
1553 *
1554 */
iis2dh_pin_int1_config_get(stmdev_ctx_t * ctx,iis2dh_ctrl_reg3_t * val)1555 int32_t iis2dh_pin_int1_config_get(stmdev_ctx_t *ctx,
1556 iis2dh_ctrl_reg3_t *val)
1557 {
1558 int32_t ret;
1559
1560 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG3, (uint8_t *) val, 1);
1561
1562 return ret;
1563 }
1564 /**
1565 * @brief int2_pin_detect_4d: [set] 4D enable: 4D detection is enabled
1566 * on INT2 pin when 6D bit on
1567 * INT2_CFG (34h) is set to 1.
1568 *
1569 * @param ctx read / write interface definitions
1570 * @param val change the values of d4d_int2 in reg CTRL_REG5
1571 * @retval interface status (MANDATORY: return 0 -> no Error)
1572 *
1573 */
iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1574 int32_t iis2dh_int2_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
1575 {
1576 iis2dh_ctrl_reg5_t ctrl_reg5;
1577 int32_t ret;
1578
1579 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1580
1581 if (ret == 0)
1582 {
1583 ctrl_reg5.d4d_int2 = val;
1584 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1585 }
1586
1587 return ret;
1588 }
1589
1590 /**
1591 * @brief 4D enable: 4D detection is enabled on INT2 pin when 6D bit on
1592 * INT2_CFG (34h) is set to 1.[get]
1593 *
1594 * @param ctx read / write interface definitions
1595 * @param val change the values of d4d_int2 in reg CTRL_REG5
1596 * @retval interface status (MANDATORY: return 0 -> no Error)
1597 *
1598 */
iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1599 int32_t iis2dh_int2_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
1600 {
1601 iis2dh_ctrl_reg5_t ctrl_reg5;
1602 int32_t ret;
1603
1604 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1605 *val = (uint8_t)ctrl_reg5.d4d_int2;
1606
1607 return ret;
1608 }
1609
1610 /**
1611 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1612 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1613 * itself.[set]
1614 *
1615 * @param ctx read / write interface definitions
1616 * @param val change the values of lir_int2 in reg CTRL_REG5
1617 * @retval interface status (MANDATORY: return 0 -> no Error)
1618 *
1619 */
iis2dh_int2_pin_notification_mode_set(stmdev_ctx_t * ctx,iis2dh_lir_int2_t val)1620 int32_t iis2dh_int2_pin_notification_mode_set(stmdev_ctx_t *ctx,
1621 iis2dh_lir_int2_t val)
1622 {
1623 iis2dh_ctrl_reg5_t ctrl_reg5;
1624 int32_t ret;
1625
1626 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1627
1628 if (ret == 0)
1629 {
1630 ctrl_reg5.lir_int2 = (uint8_t)val;
1631 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1632 }
1633
1634 return ret;
1635 }
1636
1637 /**
1638 * @brief Latch interrupt request on INT2_SRC (35h) register, with
1639 * INT2_SRC (35h) register cleared by reading INT2_SRC(35h)
1640 * itself.[get]
1641 *
1642 * @param ctx read / write interface definitions
1643 * @param val Get the values of lir_int2 in reg CTRL_REG5
1644 * @retval interface status (MANDATORY: return 0 -> no Error)
1645 *
1646 */
iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t * ctx,iis2dh_lir_int2_t * val)1647 int32_t iis2dh_int2_pin_notification_mode_get(stmdev_ctx_t *ctx,
1648 iis2dh_lir_int2_t *val)
1649 {
1650 iis2dh_ctrl_reg5_t ctrl_reg5;
1651 int32_t ret;
1652
1653 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1654
1655 switch (ctrl_reg5.lir_int2)
1656 {
1657 case IIS2DH_INT2_PULSED:
1658 *val = IIS2DH_INT2_PULSED;
1659 break;
1660
1661 case IIS2DH_INT2_LATCHED:
1662 *val = IIS2DH_INT2_LATCHED;
1663 break;
1664
1665 default:
1666 *val = IIS2DH_INT2_PULSED;
1667 break;
1668 }
1669
1670 return ret;
1671 }
1672
1673 /**
1674 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit
1675 * on INT1_CFG(30h) is set to 1.[set]
1676 *
1677 * @param ctx read / write interface definitions
1678 * @param val change the values of d4d_int1 in reg CTRL_REG5
1679 * @retval interface status (MANDATORY: return 0 -> no Error)
1680 *
1681 */
iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t * ctx,uint8_t val)1682 int32_t iis2dh_int1_pin_detect_4d_set(stmdev_ctx_t *ctx, uint8_t val)
1683 {
1684 iis2dh_ctrl_reg5_t ctrl_reg5;
1685 int32_t ret;
1686
1687 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1688
1689 if (ret == 0)
1690 {
1691 ctrl_reg5.d4d_int1 = val;
1692 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1693 }
1694
1695 return ret;
1696 }
1697
1698 /**
1699 * @brief 4D enable: 4D detection is enabled on INT1 pin when 6D bit on
1700 * INT1_CFG(30h) is set to 1.[get]
1701 *
1702 * @param ctx read / write interface definitions
1703 * @param val change the values of d4d_int1 in reg CTRL_REG5
1704 * @retval interface status (MANDATORY: return 0 -> no Error)
1705 *
1706 */
iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t * ctx,uint8_t * val)1707 int32_t iis2dh_int1_pin_detect_4d_get(stmdev_ctx_t *ctx, uint8_t *val)
1708 {
1709 iis2dh_ctrl_reg5_t ctrl_reg5;
1710 int32_t ret;
1711
1712 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1713 *val = (uint8_t)ctrl_reg5.d4d_int1;
1714
1715 return ret;
1716 }
1717
1718 /**
1719 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1720 * register cleared by reading INT1_SRC (31h) itself.[set]
1721 *
1722 * @param ctx read / write interface definitions
1723 * @param val change the values of lir_int1 in reg CTRL_REG5
1724 * @retval interface status (MANDATORY: return 0 -> no Error)
1725 *
1726 */
iis2dh_int1_pin_notification_mode_set(stmdev_ctx_t * ctx,iis2dh_lir_int1_t val)1727 int32_t iis2dh_int1_pin_notification_mode_set(stmdev_ctx_t *ctx,
1728 iis2dh_lir_int1_t val)
1729 {
1730 iis2dh_ctrl_reg5_t ctrl_reg5;
1731 int32_t ret;
1732
1733 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1734
1735 if (ret == 0)
1736 {
1737 ctrl_reg5.lir_int1 = (uint8_t)val;
1738 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1739 }
1740
1741 return ret;
1742 }
1743
1744 /**
1745 * @brief Latch interrupt request on INT1_SRC (31h), with INT1_SRC(31h)
1746 * register cleared by reading INT1_SRC (31h) itself.[get]
1747 *
1748 * @param ctx read / write interface definitions
1749 * @param val Get the values of lir_int1 in reg CTRL_REG5
1750 * @retval interface status (MANDATORY: return 0 -> no Error)
1751 *
1752 */
iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t * ctx,iis2dh_lir_int1_t * val)1753 int32_t iis2dh_int1_pin_notification_mode_get(stmdev_ctx_t *ctx,
1754 iis2dh_lir_int1_t *val)
1755 {
1756 iis2dh_ctrl_reg5_t ctrl_reg5;
1757 int32_t ret;
1758
1759 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1760
1761 switch (ctrl_reg5.lir_int1)
1762 {
1763 case IIS2DH_INT1_PULSED:
1764 *val = IIS2DH_INT1_PULSED;
1765 break;
1766
1767 case IIS2DH_INT1_LATCHED:
1768 *val = IIS2DH_INT1_LATCHED;
1769 break;
1770
1771 default:
1772 *val = IIS2DH_INT1_PULSED;
1773 break;
1774 }
1775
1776 return ret;
1777 }
1778
1779 /**
1780 * @brief Int2 pin routing configuration register.[set]
1781 *
1782 * @param ctx read / write interface definitions
1783 * @param val registers CTRL_REG6
1784 * @retval interface status (MANDATORY: return 0 -> no Error)
1785 *
1786 */
iis2dh_pin_int2_config_set(stmdev_ctx_t * ctx,iis2dh_ctrl_reg6_t * val)1787 int32_t iis2dh_pin_int2_config_set(stmdev_ctx_t *ctx,
1788 iis2dh_ctrl_reg6_t *val)
1789 {
1790 int32_t ret;
1791
1792 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t *) val, 1);
1793
1794 return ret;
1795 }
1796
1797 /**
1798 * @brief Int2 pin routing configuration register.[get]
1799 *
1800 * @param ctx read / write interface definitions
1801 * @param val registers CTRL_REG6
1802 * @retval interface status (MANDATORY: return 0 -> no Error)
1803 *
1804 */
iis2dh_pin_int2_config_get(stmdev_ctx_t * ctx,iis2dh_ctrl_reg6_t * val)1805 int32_t iis2dh_pin_int2_config_get(stmdev_ctx_t *ctx,
1806 iis2dh_ctrl_reg6_t *val)
1807 {
1808 int32_t ret;
1809
1810 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG6, (uint8_t *) val, 1);
1811
1812 return ret;
1813 }
1814
1815 /**
1816 * @}
1817 *
1818 */
1819
1820 /**
1821 * @defgroup IIS2DH_Fifo
1822 * @brief This section group all the functions concerning the fifo usage
1823 * @{
1824 *
1825 */
1826
1827 /**
1828 * @brief FIFO enable.[set]
1829 *
1830 * @param ctx read / write interface definitions
1831 * @param val change the values of fifo_en in reg CTRL_REG5
1832 * @retval interface status (MANDATORY: return 0 -> no Error)
1833 *
1834 */
iis2dh_fifo_set(stmdev_ctx_t * ctx,uint8_t val)1835 int32_t iis2dh_fifo_set(stmdev_ctx_t *ctx, uint8_t val)
1836 {
1837 iis2dh_ctrl_reg5_t ctrl_reg5;
1838 int32_t ret;
1839
1840 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1841
1842 if (ret == 0)
1843 {
1844 ctrl_reg5.fifo_en = val;
1845 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1846 }
1847
1848 return ret;
1849 }
1850
1851 /**
1852 * @brief FIFO enable.[get]
1853 *
1854 * @param ctx read / write interface definitions
1855 * @param val change the values of fifo_en in reg CTRL_REG5
1856 * @retval interface status (MANDATORY: return 0 -> no Error)
1857 *
1858 */
iis2dh_fifo_get(stmdev_ctx_t * ctx,uint8_t * val)1859 int32_t iis2dh_fifo_get(stmdev_ctx_t *ctx, uint8_t *val)
1860 {
1861 iis2dh_ctrl_reg5_t ctrl_reg5;
1862 int32_t ret;
1863
1864 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG5, (uint8_t *)&ctrl_reg5, 1);
1865 *val = (uint8_t)ctrl_reg5.fifo_en;
1866
1867 return ret;
1868 }
1869
1870 /**
1871 * @brief FIFO watermark level selection.[set]
1872 *
1873 * @param ctx read / write interface definitions
1874 * @param val change the values of fth in reg FIFO_CTRL_REG
1875 * @retval interface status (MANDATORY: return 0 -> no Error)
1876 *
1877 */
iis2dh_fifo_watermark_set(stmdev_ctx_t * ctx,uint8_t val)1878 int32_t iis2dh_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
1879 {
1880 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1881 int32_t ret;
1882
1883 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1884 (uint8_t *)&fifo_ctrl_reg, 1);
1885
1886 if (ret == 0)
1887 {
1888 fifo_ctrl_reg.fth = val;
1889 ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1890 (uint8_t *)&fifo_ctrl_reg, 1);
1891 }
1892
1893 return ret;
1894 }
1895
1896 /**
1897 * @brief FIFO watermark level selection.[get]
1898 *
1899 * @param ctx read / write interface definitions
1900 * @param val change the values of fth in reg FIFO_CTRL_REG
1901 * @retval interface status (MANDATORY: return 0 -> no Error)
1902 *
1903 */
iis2dh_fifo_watermark_get(stmdev_ctx_t * ctx,uint8_t * val)1904 int32_t iis2dh_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
1905 {
1906 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1907 int32_t ret;
1908
1909 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1910 (uint8_t *)&fifo_ctrl_reg, 1);
1911 *val = (uint8_t)fifo_ctrl_reg.fth;
1912
1913 return ret;
1914 }
1915
1916 /**
1917 * @brief Trigger FIFO selection.[set]
1918 *
1919 * @param ctx read / write interface definitions
1920 * @param val change the values of tr in reg FIFO_CTRL_REG
1921 * @retval interface status (MANDATORY: return 0 -> no Error)
1922 *
1923 */
iis2dh_fifo_trigger_event_set(stmdev_ctx_t * ctx,iis2dh_tr_t val)1924 int32_t iis2dh_fifo_trigger_event_set(stmdev_ctx_t *ctx,
1925 iis2dh_tr_t val)
1926 {
1927 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1928 int32_t ret;
1929
1930 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1931 (uint8_t *)&fifo_ctrl_reg, 1);
1932
1933 if (ret == 0)
1934 {
1935 fifo_ctrl_reg.tr = (uint8_t)val;
1936 ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1937 (uint8_t *)&fifo_ctrl_reg, 1);
1938 }
1939
1940 return ret;
1941 }
1942
1943 /**
1944 * @brief Trigger FIFO selection.[get]
1945 *
1946 * @param ctx read / write interface definitions
1947 * @param val Get the values of tr in reg FIFO_CTRL_REG
1948 * @retval interface status (MANDATORY: return 0 -> no Error)
1949 *
1950 */
iis2dh_fifo_trigger_event_get(stmdev_ctx_t * ctx,iis2dh_tr_t * val)1951 int32_t iis2dh_fifo_trigger_event_get(stmdev_ctx_t *ctx,
1952 iis2dh_tr_t *val)
1953 {
1954 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1955 int32_t ret;
1956
1957 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1958 (uint8_t *)&fifo_ctrl_reg, 1);
1959
1960 switch (fifo_ctrl_reg.tr)
1961 {
1962 case IIS2DH_INT1_GEN:
1963 *val = IIS2DH_INT1_GEN;
1964 break;
1965
1966 case IIS2DH_INT2_GEN:
1967 *val = IIS2DH_INT2_GEN;
1968 break;
1969
1970 default:
1971 *val = IIS2DH_INT1_GEN;
1972 break;
1973 }
1974
1975 return ret;
1976 }
1977
1978 /**
1979 * @brief FIFO mode selection.[set]
1980 *
1981 * @param ctx read / write interface definitions
1982 * @param val change the values of fm in reg FIFO_CTRL_REG
1983 * @retval interface status (MANDATORY: return 0 -> no Error)
1984 *
1985 */
iis2dh_fifo_mode_set(stmdev_ctx_t * ctx,iis2dh_fm_t val)1986 int32_t iis2dh_fifo_mode_set(stmdev_ctx_t *ctx, iis2dh_fm_t val)
1987 {
1988 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
1989 int32_t ret;
1990
1991 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1992 (uint8_t *)&fifo_ctrl_reg, 1);
1993
1994 if (ret == 0)
1995 {
1996 fifo_ctrl_reg.fm = (uint8_t)val;
1997 ret = iis2dh_write_reg(ctx, IIS2DH_FIFO_CTRL_REG,
1998 (uint8_t *)&fifo_ctrl_reg, 1);
1999 }
2000
2001 return ret;
2002 }
2003
2004 /**
2005 * @brief FIFO mode selection.[get]
2006 *
2007 * @param ctx read / write interface definitions
2008 * @param val Get the values of fm in reg FIFO_CTRL_REG
2009 * @retval interface status (MANDATORY: return 0 -> no Error)
2010 *
2011 */
iis2dh_fifo_mode_get(stmdev_ctx_t * ctx,iis2dh_fm_t * val)2012 int32_t iis2dh_fifo_mode_get(stmdev_ctx_t *ctx, iis2dh_fm_t *val)
2013 {
2014 iis2dh_fifo_ctrl_reg_t fifo_ctrl_reg;
2015 int32_t ret;
2016
2017 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_CTRL_REG,
2018 (uint8_t *)&fifo_ctrl_reg, 1);
2019
2020 switch (fifo_ctrl_reg.fm)
2021 {
2022 case IIS2DH_BYPASS_MODE:
2023 *val = IIS2DH_BYPASS_MODE;
2024 break;
2025
2026 case IIS2DH_FIFO_MODE:
2027 *val = IIS2DH_FIFO_MODE;
2028 break;
2029
2030 case IIS2DH_DYNAMIC_STREAM_MODE:
2031 *val = IIS2DH_DYNAMIC_STREAM_MODE;
2032 break;
2033
2034 case IIS2DH_STREAM_TO_FIFO_MODE:
2035 *val = IIS2DH_STREAM_TO_FIFO_MODE;
2036 break;
2037
2038 default:
2039 *val = IIS2DH_BYPASS_MODE;
2040 break;
2041 }
2042
2043 return ret;
2044 }
2045
2046 /**
2047 * @brief FIFO status register.[get]
2048 *
2049 * @param ctx read / write interface definitions
2050 * @param val registers FIFO_SRC_REG
2051 * @retval interface status (MANDATORY: return 0 -> no Error)
2052 *
2053 */
iis2dh_fifo_status_get(stmdev_ctx_t * ctx,iis2dh_fifo_src_reg_t * val)2054 int32_t iis2dh_fifo_status_get(stmdev_ctx_t *ctx,
2055 iis2dh_fifo_src_reg_t *val)
2056 {
2057 int32_t ret;
2058
2059 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG, (uint8_t *) val, 1);
2060
2061 return ret;
2062 }
2063 /**
2064 * @brief FIFO stored data level.[get]
2065 *
2066 * @param ctx read / write interface definitions
2067 * @param val change the values of fss in reg FIFO_SRC_REG
2068 * @retval interface status (MANDATORY: return 0 -> no Error)
2069 *
2070 */
iis2dh_fifo_data_level_get(stmdev_ctx_t * ctx,uint8_t * val)2071 int32_t iis2dh_fifo_data_level_get(stmdev_ctx_t *ctx, uint8_t *val)
2072 {
2073 iis2dh_fifo_src_reg_t fifo_src_reg;
2074 int32_t ret;
2075
2076 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2077 (uint8_t *)&fifo_src_reg, 1);
2078 *val = (uint8_t)fifo_src_reg.fss;
2079
2080 return ret;
2081 }
2082 /**
2083 * @brief Empty FIFO status flag.[get]
2084 *
2085 * @param ctx read / write interface definitions
2086 * @param val change the values of empty in reg FIFO_SRC_REG
2087 * @retval interface status (MANDATORY: return 0 -> no Error)
2088 *
2089 */
iis2dh_fifo_empty_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2090 int32_t iis2dh_fifo_empty_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2091 {
2092 iis2dh_fifo_src_reg_t fifo_src_reg;
2093 int32_t ret;
2094
2095 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2096 (uint8_t *)&fifo_src_reg, 1);
2097 *val = (uint8_t)fifo_src_reg.empty;
2098
2099 return ret;
2100 }
2101 /**
2102 * @brief FIFO overrun status flag.[get]
2103 *
2104 * @param ctx read / write interface definitions
2105 * @param val change the values of ovrn_fifo in reg FIFO_SRC_REG
2106 * @retval interface status (MANDATORY: return 0 -> no Error)
2107 *
2108 */
iis2dh_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2109 int32_t iis2dh_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2110 {
2111 iis2dh_fifo_src_reg_t fifo_src_reg;
2112 int32_t ret;
2113
2114 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2115 (uint8_t *)&fifo_src_reg, 1);
2116 *val = (uint8_t)fifo_src_reg.ovrn_fifo;
2117
2118 return ret;
2119 }
2120 /**
2121 * @brief FIFO watermark status.[get]
2122 *
2123 * @param ctx read / write interface definitions
2124 * @param val change the values of wtm in reg FIFO_SRC_REG
2125 * @retval interface status (MANDATORY: return 0 -> no Error)
2126 *
2127 */
iis2dh_fifo_fth_flag_get(stmdev_ctx_t * ctx,uint8_t * val)2128 int32_t iis2dh_fifo_fth_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
2129 {
2130 iis2dh_fifo_src_reg_t fifo_src_reg;
2131 int32_t ret;
2132
2133 ret = iis2dh_read_reg(ctx, IIS2DH_FIFO_SRC_REG,
2134 (uint8_t *)&fifo_src_reg, 1);
2135 *val = (uint8_t)fifo_src_reg.wtm;
2136
2137 return ret;
2138 }
2139 /**
2140 * @}
2141 *
2142 */
2143
2144 /**
2145 * @defgroup IIS2DH_Tap_generator
2146 * @brief This section group all the functions that manage the tap and
2147 * double tap event generation
2148 * @{
2149 *
2150 */
2151
2152 /**
2153 * @brief Tap/Double Tap generator configuration register.[set]
2154 *
2155 * @param ctx read / write interface definitions
2156 * @param val registers CLICK_CFG
2157 * @retval interface status (MANDATORY: return 0 -> no Error)
2158 *
2159 */
iis2dh_tap_conf_set(stmdev_ctx_t * ctx,iis2dh_click_cfg_t * val)2160 int32_t iis2dh_tap_conf_set(stmdev_ctx_t *ctx,
2161 iis2dh_click_cfg_t *val)
2162 {
2163 int32_t ret;
2164
2165 ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t *) val, 1);
2166
2167 return ret;
2168 }
2169
2170 /**
2171 * @brief Tap/Double Tap generator configuration register.[get]
2172 *
2173 * @param ctx read / write interface definitions
2174 * @param val registers CLICK_CFG
2175 * @retval interface status (MANDATORY: return 0 -> no Error)
2176 *
2177 */
iis2dh_tap_conf_get(stmdev_ctx_t * ctx,iis2dh_click_cfg_t * val)2178 int32_t iis2dh_tap_conf_get(stmdev_ctx_t *ctx,
2179 iis2dh_click_cfg_t *val)
2180 {
2181 int32_t ret;
2182
2183 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_CFG, (uint8_t *) val, 1);
2184
2185 return ret;
2186 }
2187 /**
2188 * @brief Tap/Double Tap generator source register.[get]
2189 *
2190 * @param ctx read / write interface definitions
2191 * @param val registers CLICK_SRC
2192 * @retval interface status (MANDATORY: return 0 -> no Error)
2193 *
2194 */
iis2dh_tap_source_get(stmdev_ctx_t * ctx,iis2dh_click_src_t * val)2195 int32_t iis2dh_tap_source_get(stmdev_ctx_t *ctx,
2196 iis2dh_click_src_t *val)
2197 {
2198 int32_t ret;
2199
2200 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_SRC, (uint8_t *) val, 1);
2201
2202 return ret;
2203 }
2204 /**
2205 * @brief User-defined threshold value for Tap/Double Tap event.[set]
2206 * 1 LSB = full scale/128
2207 *
2208 * @param ctx read / write interface definitions
2209 * @param val change the values of ths in reg CLICK_THS
2210 * @retval interface status (MANDATORY: return 0 -> no Error)
2211 *
2212 */
iis2dh_tap_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2213 int32_t iis2dh_tap_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2214 {
2215 iis2dh_click_ths_t click_ths;
2216 int32_t ret;
2217
2218 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2219
2220 if (ret == 0)
2221 {
2222 click_ths.ths = val;
2223 ret = iis2dh_write_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2224 }
2225
2226 return ret;
2227 }
2228
2229 /**
2230 * @brief User-defined threshold value for Tap/Double Tap event.[get]
2231 * 1 LSB = full scale/128
2232 *
2233 * @param ctx read / write interface definitions
2234 * @param val change the values of ths in reg CLICK_THS
2235 * @retval interface status (MANDATORY: return 0 -> no Error)
2236 *
2237 */
iis2dh_tap_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2238 int32_t iis2dh_tap_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2239 {
2240 iis2dh_click_ths_t click_ths;
2241 int32_t ret;
2242
2243 ret = iis2dh_read_reg(ctx, IIS2DH_CLICK_THS, (uint8_t *)&click_ths, 1);
2244 *val = (uint8_t)click_ths.ths;
2245
2246 return ret;
2247 }
2248
2249 /**
2250 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse
2251 * between the start of the click-detection procedure and when the
2252 * acceleration falls back below the threshold.[set]
2253 *
2254 * @param ctx read / write interface definitions
2255 * @param val change the values of tli in reg TIME_LIMIT
2256 * @retval interface status (MANDATORY: return 0 -> no Error)
2257 *
2258 */
iis2dh_shock_dur_set(stmdev_ctx_t * ctx,uint8_t val)2259 int32_t iis2dh_shock_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2260 {
2261 iis2dh_time_limit_t time_limit;
2262 int32_t ret;
2263
2264 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2265
2266 if (ret == 0)
2267 {
2268 time_limit.tli = val;
2269 ret = iis2dh_write_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2270 }
2271
2272 return ret;
2273 }
2274
2275 /**
2276 * @brief The maximum time (1 LSB = 1/ODR) interval that can elapse between
2277 * the start of the click-detection procedure and when the
2278 * acceleration falls back below the threshold.[get]
2279 *
2280 * @param ctx read / write interface definitions
2281 * @param val change the values of tli in reg TIME_LIMIT
2282 * @retval interface status (MANDATORY: return 0 -> no Error)
2283 *
2284 */
iis2dh_shock_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2285 int32_t iis2dh_shock_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2286 {
2287 iis2dh_time_limit_t time_limit;
2288 int32_t ret;
2289
2290 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LIMIT, (uint8_t *)&time_limit, 1);
2291 *val = (uint8_t)time_limit.tli;
2292
2293 return ret;
2294 }
2295
2296 /**
2297 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2298 * click detection where the click-detection procedure is
2299 * disabled, in cases where the device is configured for
2300 * double-click detection.[set]
2301 *
2302 * @param ctx read / write interface definitions
2303 * @param val change the values of tla in reg TIME_LATENCY
2304 * @retval interface status (MANDATORY: return 0 -> no Error)
2305 *
2306 */
iis2dh_quiet_dur_set(stmdev_ctx_t * ctx,uint8_t val)2307 int32_t iis2dh_quiet_dur_set(stmdev_ctx_t *ctx, uint8_t val)
2308 {
2309 iis2dh_time_latency_t time_latency;
2310 int32_t ret;
2311
2312 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY,
2313 (uint8_t *)&time_latency, 1);
2314
2315 if (ret == 0)
2316 {
2317 time_latency.tla = val;
2318 ret = iis2dh_write_reg(ctx, IIS2DH_TIME_LATENCY,
2319 (uint8_t *)&time_latency, 1);
2320 }
2321
2322 return ret;
2323 }
2324
2325 /**
2326 * @brief The time (1 LSB = 1/ODR) interval that starts after the first
2327 * click detection where the click-detection procedure is
2328 * disabled, in cases where the device is configured for
2329 * double-click detection.[get]
2330 *
2331 * @param ctx read / write interface definitions
2332 * @param val change the values of tla in reg TIME_LATENCY
2333 * @retval interface status (MANDATORY: return 0 -> no Error)
2334 *
2335 */
iis2dh_quiet_dur_get(stmdev_ctx_t * ctx,uint8_t * val)2336 int32_t iis2dh_quiet_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
2337 {
2338 iis2dh_time_latency_t time_latency;
2339 int32_t ret;
2340
2341 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_LATENCY,
2342 (uint8_t *)&time_latency, 1);
2343 *val = (uint8_t)time_latency.tla;
2344
2345 return ret;
2346 }
2347
2348 /**
2349 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2350 * after the end of the latency interval in which the click-detection
2351 * procedure can start, in cases where the device is configured
2352 * for double-click detection.[set]
2353 *
2354 * @param ctx read / write interface definitions
2355 * @param val change the values of tw in reg TIME_WINDOW
2356 * @retval interface status (MANDATORY: return 0 -> no Error)
2357 *
2358 */
iis2dh_double_tap_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2359 int32_t iis2dh_double_tap_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
2360 {
2361 iis2dh_time_window_t time_window;
2362 int32_t ret;
2363
2364 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW,
2365 (uint8_t *)&time_window, 1);
2366
2367 if (ret == 0)
2368 {
2369 time_window.tw = val;
2370 ret = iis2dh_write_reg(ctx, IIS2DH_TIME_WINDOW,
2371 (uint8_t *)&time_window, 1);
2372 }
2373
2374 return ret;
2375 }
2376
2377 /**
2378 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse
2379 * after the end of the latency interval in which the
2380 * click-detection procedure can start, in cases where the device
2381 * is configured for double-click detection.[get]
2382 *
2383 * @param ctx read / write interface definitions
2384 * @param val change the values of tw in reg TIME_WINDOW
2385 * @retval interface status (MANDATORY: return 0 -> no Error)
2386 *
2387 */
iis2dh_double_tap_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2388 int32_t iis2dh_double_tap_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
2389 {
2390 iis2dh_time_window_t time_window;
2391 int32_t ret;
2392
2393 ret = iis2dh_read_reg(ctx, IIS2DH_TIME_WINDOW,
2394 (uint8_t *)&time_window, 1);
2395 *val = (uint8_t)time_window.tw;
2396
2397 return ret;
2398 }
2399
2400 /**
2401 * @}
2402 *
2403 */
2404
2405 /**
2406 * @defgroup IIS2DH_Activity_inactivity
2407 * @brief This section group all the functions concerning activity
2408 * inactivity functionality
2409 * @{
2410 *
2411 */
2412
2413 /**
2414 * @brief Sleep-to-wake, return-to-sleep activation threshold in
2415 * low-power mode.[set]
2416 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2417 *
2418 * @param ctx read / write interface definitions
2419 * @param val change the values of acth in reg ACT_THS
2420 * @retval interface status (MANDATORY: return 0 -> no Error)
2421 *
2422 */
iis2dh_act_threshold_set(stmdev_ctx_t * ctx,uint8_t val)2423 int32_t iis2dh_act_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
2424 {
2425 iis2dh_act_ths_t act_ths;
2426 int32_t ret;
2427
2428 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2429
2430 if (ret == 0)
2431 {
2432 act_ths.acth = val;
2433 ret = iis2dh_write_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2434 }
2435
2436 return ret;
2437 }
2438
2439 /**
2440 * @brief Sleep-to-wake, return-to-sleep activation threshold in low-power
2441 * mode.[get]
2442 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2443 *
2444 * @param ctx read / write interface definitions
2445 * @param val change the values of acth in reg ACT_THS
2446 * @retval interface status (MANDATORY: return 0 -> no Error)
2447 *
2448 */
iis2dh_act_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)2449 int32_t iis2dh_act_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
2450 {
2451 iis2dh_act_ths_t act_ths;
2452 int32_t ret;
2453
2454 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_THS, (uint8_t *)&act_ths, 1);
2455 *val = (uint8_t)act_ths.acth;
2456
2457 return ret;
2458 }
2459
2460 /**
2461 * @brief Sleep-to-wake, return-to-sleep.[set]
2462 * duration = (8*1[LSb]+1)/ODR
2463 *
2464 * @param ctx read / write interface definitions
2465 * @param val change the values of actd in reg ACT_DUR
2466 * @retval interface status (MANDATORY: return 0 -> no Error)
2467 *
2468 */
iis2dh_act_timeout_set(stmdev_ctx_t * ctx,uint8_t val)2469 int32_t iis2dh_act_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
2470 {
2471 iis2dh_act_dur_t act_dur;
2472 int32_t ret;
2473
2474 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2475
2476 if (ret == 0)
2477 {
2478 act_dur.actd = val;
2479 ret = iis2dh_write_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2480 }
2481
2482 return ret;
2483 }
2484
2485 /**
2486 * @brief Sleep-to-wake, return-to-sleep.[get]
2487 * duration = (8*1[LSb]+1)/ODR
2488 *
2489 * @param ctx read / write interface definitions
2490 * @param val change the values of actd in reg ACT_DUR
2491 * @retval interface status (MANDATORY: return 0 -> no Error)
2492 *
2493 */
iis2dh_act_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)2494 int32_t iis2dh_act_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
2495 {
2496 iis2dh_act_dur_t act_dur;
2497 int32_t ret;
2498
2499 ret = iis2dh_read_reg(ctx, IIS2DH_ACT_DUR, (uint8_t *)&act_dur, 1);
2500 *val = (uint8_t)act_dur.actd;
2501
2502 return ret;
2503 }
2504
2505 /**
2506 * @}
2507 *
2508 */
2509
2510 /**
2511 * @defgroup IIS2DH_Serial_interface
2512 * @brief This section group all the functions concerning serial
2513 * interface management
2514 * @{
2515 *
2516 */
2517
2518 /**
2519 * @brief SPI Serial Interface Mode selection.[set]
2520 *
2521 * @param ctx read / write interface definitions
2522 * @param val change the values of sim in reg CTRL_REG4
2523 * @retval interface status (MANDATORY: return 0 -> no Error)
2524 *
2525 */
iis2dh_spi_mode_set(stmdev_ctx_t * ctx,iis2dh_sim_t val)2526 int32_t iis2dh_spi_mode_set(stmdev_ctx_t *ctx, iis2dh_sim_t val)
2527 {
2528 iis2dh_ctrl_reg4_t ctrl_reg4;
2529 int32_t ret;
2530
2531 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2532
2533 if (ret == 0)
2534 {
2535 ctrl_reg4.sim = (uint8_t)val;
2536 ret = iis2dh_write_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2537 }
2538
2539 return ret;
2540 }
2541
2542 /**
2543 * @brief SPI Serial Interface Mode selection.[get]
2544 *
2545 * @param ctx read / write interface definitions
2546 * @param val Get the values of sim in reg CTRL_REG4
2547 * @retval interface status (MANDATORY: return 0 -> no Error)
2548 *
2549 */
iis2dh_spi_mode_get(stmdev_ctx_t * ctx,iis2dh_sim_t * val)2550 int32_t iis2dh_spi_mode_get(stmdev_ctx_t *ctx, iis2dh_sim_t *val)
2551 {
2552 iis2dh_ctrl_reg4_t ctrl_reg4;
2553 int32_t ret;
2554
2555 ret = iis2dh_read_reg(ctx, IIS2DH_CTRL_REG4, (uint8_t *)&ctrl_reg4, 1);
2556
2557 switch (ctrl_reg4.sim)
2558 {
2559 case IIS2DH_SPI_4_WIRE:
2560 *val = IIS2DH_SPI_4_WIRE;
2561 break;
2562
2563 case IIS2DH_SPI_3_WIRE:
2564 *val = IIS2DH_SPI_3_WIRE;
2565 break;
2566
2567 default:
2568 *val = IIS2DH_SPI_4_WIRE;
2569 break;
2570 }
2571
2572 return ret;
2573 }
2574
2575 /**
2576 * @}
2577 *
2578 */
2579
2580 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2581
