1 /** 2 ****************************************************************************** 3 * @file i3g4250d_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * i3g4250d_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef I3G4250D_REGS_H 23 #define I3G4250D_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup I3G4250D 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef __BYTE_ORDER__ 45 46 #define DRV_LITTLE_ENDIAN 1234 47 #define DRV_BIG_ENDIAN 4321 48 49 /** if DRV_BYTE_ORDER is not defined, choose the endianness of your architecture 50 * by uncommenting the define which fits your platform endianness 51 */ 52 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 53 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 54 55 #else /* defined __BYTE_ORDER__ */ 56 57 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 58 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 59 #define DRV_BYTE_ORDER __BYTE_ORDER__ 60 61 #endif /* DRV_BYTE_ORDER */ 62 63 /** 64 * @} 65 * 66 */ 67 68 /** @defgroup STMicroelectronics sensors common types 69 * @{ 70 * 71 */ 72 73 #ifndef MEMS_SHARED_TYPES 74 #define MEMS_SHARED_TYPES 75 76 typedef struct 77 { 78 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 79 uint8_t bit0 : 1; 80 uint8_t bit1 : 1; 81 uint8_t bit2 : 1; 82 uint8_t bit3 : 1; 83 uint8_t bit4 : 1; 84 uint8_t bit5 : 1; 85 uint8_t bit6 : 1; 86 uint8_t bit7 : 1; 87 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 88 uint8_t bit7 : 1; 89 uint8_t bit6 : 1; 90 uint8_t bit5 : 1; 91 uint8_t bit4 : 1; 92 uint8_t bit3 : 1; 93 uint8_t bit2 : 1; 94 uint8_t bit1 : 1; 95 uint8_t bit0 : 1; 96 #endif /* DRV_BYTE_ORDER */ 97 } bitwise_t; 98 99 #define PROPERTY_DISABLE (0U) 100 #define PROPERTY_ENABLE (1U) 101 102 /** @addtogroup Interfaces_Functions 103 * @brief This section provide a set of functions used to read and 104 * write a generic register of the device. 105 * MANDATORY: return 0 -> no Error. 106 * @{ 107 * 108 */ 109 110 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 111 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 112 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 113 114 typedef struct 115 { 116 /** Component mandatory fields **/ 117 stmdev_write_ptr write_reg; 118 stmdev_read_ptr read_reg; 119 /** Component optional fields **/ 120 stmdev_mdelay_ptr mdelay; 121 /** Customizable optional pointer **/ 122 void *handle; 123 } stmdev_ctx_t; 124 125 /** 126 * @} 127 * 128 */ 129 130 #endif /* MEMS_SHARED_TYPES */ 131 132 #ifndef MEMS_UCF_SHARED_TYPES 133 #define MEMS_UCF_SHARED_TYPES 134 135 /** @defgroup Generic address-data structure definition 136 * @brief This structure is useful to load a predefined configuration 137 * of a sensor. 138 * You can create a sensor configuration by your own or using 139 * Unico / Unicleo tools available on STMicroelectronics 140 * web site. 141 * 142 * @{ 143 * 144 */ 145 146 typedef struct 147 { 148 uint8_t address; 149 uint8_t data; 150 } ucf_line_t; 151 152 /** 153 * @} 154 * 155 */ 156 157 #endif /* MEMS_UCF_SHARED_TYPES */ 158 159 /** 160 * @} 161 * 162 */ 163 164 /** 165 * @defgroup i3g4250d_Infos 166 * @{ 167 * 168 */ 169 170 /** I2C Device Address 8 bit format if SA0=0 -> 0xD1 if SA0=1 -> 0xD3 **/ 171 #define I3G4250D_I2C_ADD_L 0xD1U 172 #define I3G4250D_I2C_ADD_H 0xD3U 173 174 /** Device Identification (Who am I) **/ 175 #define I3G4250D_ID 0xD3U 176 177 /** 178 * @} 179 * 180 */ 181 182 #define I3G4250D_WHO_AM_I 0x0FU 183 #define I3G4250D_CTRL_REG1 0x20U 184 typedef struct 185 { 186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 187 uint8_t pd : 4; /* xen yen zen pd */ 188 uint8_t bw : 2; 189 uint8_t dr : 2; 190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 191 uint8_t dr : 2; 192 uint8_t bw : 2; 193 uint8_t pd : 4; /* xen yen zen pd */ 194 #endif /* DRV_BYTE_ORDER */ 195 } i3g4250d_ctrl_reg1_t; 196 197 #define I3G4250D_CTRL_REG2 0x21U 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t hpcf : 4; 202 uint8_t hpm : 2; 203 uint8_t not_used_01 : 2; 204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 205 uint8_t not_used_01 : 2; 206 uint8_t hpm : 2; 207 uint8_t hpcf : 4; 208 #endif /* DRV_BYTE_ORDER */ 209 } i3g4250d_ctrl_reg2_t; 210 211 #define I3G4250D_CTRL_REG3 0x22U 212 typedef struct 213 { 214 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 215 uint8_t i2_empty : 1; 216 uint8_t i2_orun : 1; 217 uint8_t i2_wtm : 1; 218 uint8_t i2_drdy : 1; 219 uint8_t pp_od : 1; 220 uint8_t h_lactive : 1; 221 uint8_t i1_boot : 1; 222 uint8_t i1_int1 : 1; 223 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 224 uint8_t i1_int1 : 1; 225 uint8_t i1_boot : 1; 226 uint8_t h_lactive : 1; 227 uint8_t pp_od : 1; 228 uint8_t i2_drdy : 1; 229 uint8_t i2_wtm : 1; 230 uint8_t i2_orun : 1; 231 uint8_t i2_empty : 1; 232 #endif /* DRV_BYTE_ORDER */ 233 } i3g4250d_ctrl_reg3_t; 234 235 #define I3G4250D_CTRL_REG4 0x23U 236 typedef struct 237 { 238 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 239 uint8_t sim : 1; 240 uint8_t st : 2; 241 uint8_t not_used_01 : 1; 242 uint8_t fs : 2; 243 uint8_t ble : 1; 244 uint8_t not_used_02 : 1; 245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 246 uint8_t not_used_02 : 1; 247 uint8_t ble : 1; 248 uint8_t fs : 2; 249 uint8_t not_used_01 : 1; 250 uint8_t st : 2; 251 uint8_t sim : 1; 252 #endif /* DRV_BYTE_ORDER */ 253 } i3g4250d_ctrl_reg4_t; 254 255 #define I3G4250D_CTRL_REG5 0x24U 256 typedef struct 257 { 258 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 259 uint8_t out_sel : 2; 260 uint8_t int1_sel : 2; 261 uint8_t hpen : 1; 262 uint8_t not_used_01 : 1; 263 uint8_t fifo_en : 1; 264 uint8_t boot : 1; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t boot : 1; 267 uint8_t fifo_en : 1; 268 uint8_t not_used_01 : 1; 269 uint8_t hpen : 1; 270 uint8_t int1_sel : 2; 271 uint8_t out_sel : 2; 272 #endif /* DRV_BYTE_ORDER */ 273 } i3g4250d_ctrl_reg5_t; 274 275 #define I3G4250D_REFERENCE 0x25U 276 typedef struct 277 { 278 uint8_t ref : 8; 279 } i3g4250d_reference_t; 280 281 #define I3G4250D_OUT_TEMP 0x26U 282 #define I3G4250D_STATUS_REG 0x27U 283 typedef struct 284 { 285 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 286 uint8_t xda : 1; 287 uint8_t yda : 1; 288 uint8_t zda : 1; 289 uint8_t zyxda : 1; 290 uint8_t _xor : 1; 291 uint8_t yor : 1; 292 uint8_t zor : 1; 293 uint8_t zyxor : 1; 294 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 295 uint8_t zyxor : 1; 296 uint8_t zor : 1; 297 uint8_t yor : 1; 298 uint8_t _xor : 1; 299 uint8_t zyxda : 1; 300 uint8_t zda : 1; 301 uint8_t yda : 1; 302 uint8_t xda : 1; 303 #endif /* DRV_BYTE_ORDER */ 304 } i3g4250d_status_reg_t; 305 306 #define I3G4250D_OUT_X_L 0x28U 307 #define I3G4250D_OUT_X_H 0x29U 308 #define I3G4250D_OUT_Y_L 0x2AU 309 #define I3G4250D_OUT_Y_H 0x2BU 310 #define I3G4250D_OUT_Z_L 0x2CU 311 #define I3G4250D_OUT_Z_H 0x2DU 312 #define I3G4250D_FIFO_CTRL_REG 0x2EU 313 typedef struct 314 { 315 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 316 uint8_t wtm : 5; 317 uint8_t fm : 3; 318 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 319 uint8_t fm : 3; 320 uint8_t wtm : 5; 321 #endif /* DRV_BYTE_ORDER */ 322 } i3g4250d_fifo_ctrl_reg_t; 323 324 #define I3G4250D_FIFO_SRC_REG 0x2FU 325 typedef struct 326 { 327 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 328 uint8_t fss : 5; 329 uint8_t empty : 1; 330 uint8_t ovrn : 1; 331 uint8_t wtm : 1; 332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 333 uint8_t wtm : 1; 334 uint8_t ovrn : 1; 335 uint8_t empty : 1; 336 uint8_t fss : 5; 337 #endif /* DRV_BYTE_ORDER */ 338 } i3g4250d_fifo_src_reg_t; 339 340 #define I3G4250D_INT1_CFG 0x30U 341 typedef struct 342 { 343 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 344 uint8_t xlie : 1; 345 uint8_t xhie : 1; 346 uint8_t ylie : 1; 347 uint8_t yhie : 1; 348 uint8_t zlie : 1; 349 uint8_t zhie : 1; 350 uint8_t lir : 1; 351 uint8_t and_or : 1; 352 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 353 uint8_t and_or : 1; 354 uint8_t lir : 1; 355 uint8_t zhie : 1; 356 uint8_t zlie : 1; 357 uint8_t yhie : 1; 358 uint8_t ylie : 1; 359 uint8_t xhie : 1; 360 uint8_t xlie : 1; 361 #endif /* DRV_BYTE_ORDER */ 362 } i3g4250d_int1_cfg_t; 363 364 #define I3G4250D_INT1_SRC 0x31U 365 typedef struct 366 { 367 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 368 uint8_t xl : 1; 369 uint8_t xh : 1; 370 uint8_t yl : 1; 371 uint8_t yh : 1; 372 uint8_t zl : 1; 373 uint8_t zh : 1; 374 uint8_t ia : 1; 375 uint8_t not_used_01 : 1; 376 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 377 uint8_t not_used_01 : 1; 378 uint8_t ia : 1; 379 uint8_t zh : 1; 380 uint8_t zl : 1; 381 uint8_t yh : 1; 382 uint8_t yl : 1; 383 uint8_t xh : 1; 384 uint8_t xl : 1; 385 #endif /* DRV_BYTE_ORDER */ 386 } i3g4250d_int1_src_t; 387 388 #define I3G4250D_INT1_TSH_XH 0x32U 389 typedef struct 390 { 391 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 392 uint8_t thsx : 7; 393 uint8_t not_used_01 : 1; 394 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 395 uint8_t not_used_01 : 1; 396 uint8_t thsx : 7; 397 #endif /* DRV_BYTE_ORDER */ 398 } i3g4250d_int1_tsh_xh_t; 399 400 #define I3G4250D_INT1_TSH_XL 0x33U 401 typedef struct 402 { 403 uint8_t thsx : 8; 404 } i3g4250d_int1_tsh_xl_t; 405 406 #define I3G4250D_INT1_TSH_YH 0x34U 407 typedef struct 408 { 409 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 410 uint8_t thsy : 7; 411 uint8_t not_used_01 : 1; 412 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 413 uint8_t not_used_01 : 1; 414 uint8_t thsy : 7; 415 #endif /* DRV_BYTE_ORDER */ 416 } i3g4250d_int1_tsh_yh_t; 417 418 #define I3G4250D_INT1_TSH_YL 0x35U 419 typedef struct 420 { 421 uint8_t thsy : 8; 422 } i3g4250d_int1_tsh_yl_t; 423 424 #define I3G4250D_INT1_TSH_ZH 0x36U 425 typedef struct 426 { 427 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 428 uint8_t thsz : 7; 429 uint8_t not_used_01 : 1; 430 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 431 uint8_t not_used_01 : 1; 432 uint8_t thsz : 7; 433 #endif /* DRV_BYTE_ORDER */ 434 } i3g4250d_int1_tsh_zh_t; 435 436 #define I3G4250D_INT1_TSH_ZL 0x37U 437 typedef struct 438 { 439 uint8_t thsz : 8; 440 } i3g4250d_int1_tsh_zl_t; 441 442 #define I3G4250D_INT1_DURATION 0x38U 443 typedef struct 444 { 445 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 446 uint8_t d : 7; 447 uint8_t wait : 1; 448 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 449 uint8_t wait : 1; 450 uint8_t d : 7; 451 #endif /* DRV_BYTE_ORDER */ 452 } i3g4250d_int1_duration_t; 453 454 /** 455 * @defgroup LSM9DS1_Register_Union 456 * @brief This union group all the registers having a bit-field 457 * description. 458 * This union is useful but it's not needed by the driver. 459 * 460 * REMOVING this union you are compliant with: 461 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 462 * 463 * @{ 464 * 465 */ 466 467 typedef union 468 { 469 i3g4250d_ctrl_reg1_t ctrl_reg1; 470 i3g4250d_ctrl_reg2_t ctrl_reg2; 471 i3g4250d_ctrl_reg3_t ctrl_reg3; 472 i3g4250d_ctrl_reg4_t ctrl_reg4; 473 i3g4250d_ctrl_reg5_t ctrl_reg5; 474 i3g4250d_reference_t reference; 475 i3g4250d_status_reg_t status_reg; 476 i3g4250d_fifo_ctrl_reg_t fifo_ctrl_reg; 477 i3g4250d_fifo_src_reg_t fifo_src_reg; 478 i3g4250d_int1_cfg_t int1_cfg; 479 i3g4250d_int1_src_t int1_src; 480 i3g4250d_int1_tsh_xh_t int1_tsh_xh; 481 i3g4250d_int1_tsh_xl_t int1_tsh_xl; 482 i3g4250d_int1_tsh_yh_t int1_tsh_yh; 483 i3g4250d_int1_tsh_yl_t int1_tsh_yl; 484 i3g4250d_int1_tsh_zh_t int1_tsh_zh; 485 i3g4250d_int1_tsh_zl_t int1_tsh_zl; 486 i3g4250d_int1_duration_t int1_duration; 487 bitwise_t bitwise; 488 uint8_t byte; 489 } i3g4250d_reg_t; 490 491 /** 492 * @} 493 * 494 */ 495 496 #ifndef __weak 497 #define __weak __attribute__((weak)) 498 #endif /* __weak */ 499 500 /* 501 * These are the basic platform dependent I/O routines to read 502 * and write device registers connected on a standard bus. 503 * The driver keeps offering a default implementation based on function 504 * pointers to read/write routines for backward compatibility. 505 * The __weak directive allows the final application to overwrite 506 * them with a custom implementation. 507 */ 508 509 int32_t i3g4250d_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 510 uint8_t *data, 511 uint16_t len); 512 int32_t i3g4250d_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 513 uint8_t *data, 514 uint16_t len); 515 516 float_t i3g4250d_from_fs245dps_to_mdps(int16_t lsb); 517 float_t i3g4250d_from_lsb_to_celsius(int16_t lsb); 518 519 int32_t i3g4250d_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); 520 int32_t i3g4250d_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 521 522 int32_t i3g4250d_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); 523 int32_t i3g4250d_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 524 525 int32_t i3g4250d_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); 526 int32_t i3g4250d_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 527 528 typedef enum 529 { 530 I3G4250D_ODR_OFF = 0x00, 531 I3G4250D_ODR_SLEEP = 0x08, 532 I3G4250D_ODR_100Hz = 0x0F, 533 I3G4250D_ODR_200Hz = 0x1F, 534 I3G4250D_ODR_400Hz = 0x2F, 535 I3G4250D_ODR_800Hz = 0x3F, 536 } i3g4250d_dr_t; 537 int32_t i3g4250d_data_rate_set(const stmdev_ctx_t *ctx, i3g4250d_dr_t val); 538 int32_t i3g4250d_data_rate_get(const stmdev_ctx_t *ctx, i3g4250d_dr_t *val); 539 540 typedef enum 541 { 542 I3G4250D_245dps = 0x00, 543 I3G4250D_500dps = 0x01, 544 I3G4250D_2000dps = 0x02, 545 } i3g4250d_fs_t; 546 int32_t i3g4250d_full_scale_set(const stmdev_ctx_t *ctx, i3g4250d_fs_t val); 547 int32_t i3g4250d_full_scale_get(const stmdev_ctx_t *ctx, 548 i3g4250d_fs_t *val); 549 550 int32_t i3g4250d_status_reg_get(const stmdev_ctx_t *ctx, 551 i3g4250d_status_reg_t *val); 552 553 int32_t i3g4250d_flag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 554 555 int32_t i3g4250d_temperature_raw_get(const stmdev_ctx_t *ctx, 556 uint8_t *buff); 557 558 int32_t i3g4250d_angular_rate_raw_get(const stmdev_ctx_t *ctx, 559 int16_t *val); 560 561 int32_t i3g4250d_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 562 563 typedef enum 564 { 565 I3G4250D_GY_ST_DISABLE = 0, 566 I3G4250D_GY_ST_POSITIVE = 1, 567 I3G4250D_GY_ST_NEGATIVE = 3, 568 } i3g4250d_st_t; 569 int32_t i3g4250d_self_test_set(const stmdev_ctx_t *ctx, i3g4250d_st_t val); 570 int32_t i3g4250d_self_test_get(const stmdev_ctx_t *ctx, i3g4250d_st_t *val); 571 572 typedef enum 573 { 574 I3G4250D_AUX_LSB_AT_LOW_ADD = 0, 575 I3G4250D_AUX_MSB_AT_LOW_ADD = 1, 576 } i3g4250d_ble_t; 577 int32_t i3g4250d_data_format_set(const stmdev_ctx_t *ctx, 578 i3g4250d_ble_t val); 579 int32_t i3g4250d_data_format_get(const stmdev_ctx_t *ctx, 580 i3g4250d_ble_t *val); 581 582 int32_t i3g4250d_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 583 int32_t i3g4250d_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 584 585 typedef enum 586 { 587 I3G4250D_CUT_OFF_LOW = 0, 588 I3G4250D_CUT_OFF_MEDIUM = 1, 589 I3G4250D_CUT_OFF_HIGH = 2, 590 I3G4250D_CUT_OFF_VERY_HIGH = 3, 591 } i3g4250d_bw_t; 592 int32_t i3g4250d_lp_bandwidth_set(const stmdev_ctx_t *ctx, 593 i3g4250d_bw_t val); 594 int32_t i3g4250d_lp_bandwidth_get(const stmdev_ctx_t *ctx, 595 i3g4250d_bw_t *val); 596 597 typedef enum 598 { 599 I3G4250D_HP_LEVEL_0 = 0, 600 I3G4250D_HP_LEVEL_1 = 1, 601 I3G4250D_HP_LEVEL_2 = 2, 602 I3G4250D_HP_LEVEL_3 = 3, 603 I3G4250D_HP_LEVEL_4 = 4, 604 I3G4250D_HP_LEVEL_5 = 5, 605 I3G4250D_HP_LEVEL_6 = 6, 606 I3G4250D_HP_LEVEL_7 = 7, 607 I3G4250D_HP_LEVEL_8 = 8, 608 I3G4250D_HP_LEVEL_9 = 9, 609 } i3g4250d_hpcf_t; 610 int32_t i3g4250d_hp_bandwidth_set(const stmdev_ctx_t *ctx, 611 i3g4250d_hpcf_t val); 612 int32_t i3g4250d_hp_bandwidth_get(const stmdev_ctx_t *ctx, 613 i3g4250d_hpcf_t *val); 614 615 typedef enum 616 { 617 I3G4250D_HP_NORMAL_MODE_WITH_RST = 0, 618 I3G4250D_HP_REFERENCE_SIGNAL = 1, 619 I3G4250D_HP_NORMAL_MODE = 2, 620 I3G4250D_HP_AUTO_RESET_ON_INT = 3, 621 } i3g4250d_hpm_t; 622 int32_t i3g4250d_hp_mode_set(const stmdev_ctx_t *ctx, i3g4250d_hpm_t val); 623 int32_t i3g4250d_hp_mode_get(const stmdev_ctx_t *ctx, i3g4250d_hpm_t *val); 624 625 typedef enum 626 { 627 I3G4250D_ONLY_LPF1_ON_OUT = 0, 628 I3G4250D_LPF1_HP_ON_OUT = 1, 629 I3G4250D_LPF1_LPF2_ON_OUT = 2, 630 I3G4250D_LPF1_HP_LPF2_ON_OUT = 6, 631 } i3g4250d_out_sel_t; 632 int32_t i3g4250d_filter_path_set(const stmdev_ctx_t *ctx, 633 i3g4250d_out_sel_t val); 634 int32_t i3g4250d_filter_path_get(const stmdev_ctx_t *ctx, 635 i3g4250d_out_sel_t *val); 636 637 typedef enum 638 { 639 I3G4250D_ONLY_LPF1_ON_INT = 0, 640 I3G4250D_LPF1_HP_ON_INT = 1, 641 I3G4250D_LPF1_LPF2_ON_INT = 2, 642 I3G4250D_LPF1_HP_LPF2_ON_INT = 6, 643 } i3g4250d_int1_sel_t; 644 int32_t i3g4250d_filter_path_internal_set(const stmdev_ctx_t *ctx, 645 i3g4250d_int1_sel_t val); 646 int32_t i3g4250d_filter_path_internal_get(const stmdev_ctx_t *ctx, 647 i3g4250d_int1_sel_t *val); 648 649 int32_t i3g4250d_hp_reference_value_set(const stmdev_ctx_t *ctx, 650 uint8_t val); 651 int32_t i3g4250d_hp_reference_value_get(const stmdev_ctx_t *ctx, 652 uint8_t *val); 653 654 typedef enum 655 { 656 I3G4250D_SPI_4_WIRE = 0, 657 I3G4250D_SPI_3_WIRE = 1, 658 } i3g4250d_sim_t; 659 int32_t i3g4250d_spi_mode_set(const stmdev_ctx_t *ctx, i3g4250d_sim_t val); 660 int32_t i3g4250d_spi_mode_get(const stmdev_ctx_t *ctx, i3g4250d_sim_t *val); 661 662 typedef struct 663 { 664 uint8_t i1_int1 : 1; 665 uint8_t i1_boot : 1; 666 } i3g4250d_int1_route_t; 667 int32_t i3g4250d_pin_int1_route_set(const stmdev_ctx_t *ctx, 668 i3g4250d_int1_route_t val); 669 int32_t i3g4250d_pin_int1_route_get(const stmdev_ctx_t *ctx, 670 i3g4250d_int1_route_t *val); 671 672 typedef struct 673 { 674 uint8_t i2_empty : 1; 675 uint8_t i2_orun : 1; 676 uint8_t i2_wtm : 1; 677 uint8_t i2_drdy : 1; 678 } i3g4250d_int2_route_t; 679 int32_t i3g4250d_pin_int2_route_set(const stmdev_ctx_t *ctx, 680 i3g4250d_int2_route_t val); 681 int32_t i3g4250d_pin_int2_route_get(const stmdev_ctx_t *ctx, 682 i3g4250d_int2_route_t *val); 683 684 typedef enum 685 { 686 I3G4250D_PUSH_PULL = 0, 687 I3G4250D_OPEN_DRAIN = 1, 688 } i3g4250d_pp_od_t; 689 int32_t i3g4250d_pin_mode_set(const stmdev_ctx_t *ctx, 690 i3g4250d_pp_od_t val); 691 int32_t i3g4250d_pin_mode_get(const stmdev_ctx_t *ctx, 692 i3g4250d_pp_od_t *val); 693 694 typedef enum 695 { 696 I3G4250D_ACTIVE_HIGH = 0, 697 I3G4250D_ACTIVE_LOW = 1, 698 } i3g4250d_h_lactive_t; 699 int32_t i3g4250d_pin_polarity_set(const stmdev_ctx_t *ctx, 700 i3g4250d_h_lactive_t val); 701 int32_t i3g4250d_pin_polarity_get(const stmdev_ctx_t *ctx, 702 i3g4250d_h_lactive_t *val); 703 704 typedef enum 705 { 706 I3G4250D_INT_PULSED = 0, 707 I3G4250D_INT_LATCHED = 1, 708 } i3g4250d_lir_t; 709 int32_t i3g4250d_int_notification_set(const stmdev_ctx_t *ctx, 710 i3g4250d_lir_t val); 711 int32_t i3g4250d_int_notification_get(const stmdev_ctx_t *ctx, 712 i3g4250d_lir_t *val); 713 714 int32_t i3g4250d_int_on_threshold_conf_set(const stmdev_ctx_t *ctx, 715 i3g4250d_int1_cfg_t *val); 716 int32_t i3g4250d_int_on_threshold_conf_get(const stmdev_ctx_t *ctx, 717 i3g4250d_int1_cfg_t *val); 718 719 typedef enum 720 { 721 I3G4250D_INT1_ON_TH_AND = 1, 722 I3G4250D_INT1_ON_TH_OR = 0, 723 } i3g4250d_and_or_t; 724 int32_t i3g4250d_int_on_threshold_mode_set(const stmdev_ctx_t *ctx, 725 i3g4250d_and_or_t val); 726 int32_t i3g4250d_int_on_threshold_mode_get(const stmdev_ctx_t *ctx, 727 i3g4250d_and_or_t *val); 728 729 int32_t i3g4250d_int_on_threshold_src_get(const stmdev_ctx_t *ctx, 730 i3g4250d_int1_src_t *val); 731 732 int32_t i3g4250d_int_x_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 733 int32_t i3g4250d_int_x_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 734 735 int32_t i3g4250d_int_y_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 736 int32_t i3g4250d_int_y_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 737 738 int32_t i3g4250d_int_z_threshold_set(const stmdev_ctx_t *ctx, uint16_t val); 739 int32_t i3g4250d_int_z_threshold_get(const stmdev_ctx_t *ctx, uint16_t *val); 740 741 int32_t i3g4250d_int_on_threshold_dur_set(const stmdev_ctx_t *ctx, 742 uint8_t val); 743 int32_t i3g4250d_int_on_threshold_dur_get(const stmdev_ctx_t *ctx, 744 uint8_t *val); 745 746 int32_t i3g4250d_fifo_enable_set(const stmdev_ctx_t *ctx, uint8_t val); 747 int32_t i3g4250d_fifo_enable_get(const stmdev_ctx_t *ctx, uint8_t *val); 748 749 int32_t i3g4250d_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 750 int32_t i3g4250d_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 751 752 typedef enum 753 { 754 I3G4250D_FIFO_BYPASS_MODE = 0x00, 755 I3G4250D_FIFO_MODE = 0x01, 756 I3G4250D_FIFO_STREAM_MODE = 0x02, 757 } i3g4250d_fifo_mode_t; 758 int32_t i3g4250d_fifo_mode_set(const stmdev_ctx_t *ctx, 759 i3g4250d_fifo_mode_t val); 760 int32_t i3g4250d_fifo_mode_get(const stmdev_ctx_t *ctx, 761 i3g4250d_fifo_mode_t *val); 762 763 int32_t i3g4250d_fifo_data_level_get(const stmdev_ctx_t *ctx, uint8_t *val); 764 765 int32_t i3g4250d_fifo_empty_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 766 767 int32_t i3g4250d_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 768 769 int32_t i3g4250d_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 770 771 /** 772 * @} 773 * 774 */ 775 776 #ifdef __cplusplus 777 } 778 #endif 779 780 #endif /* I3G4250D_REGS_H */ 781 782 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 783
