1 /*
2 * Copyright (c) 2016 BayLibre, SAS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/pm/device.h>
11 #include <zephyr/pm/device_runtime.h>
12 #include <zephyr/sys/util.h>
13 #include <zephyr/kernel.h>
14 #include <soc.h>
15 #include <stm32_ll_i2c.h>
16 #include <stm32_ll_rcc.h>
17 #include <errno.h>
18 #include <zephyr/drivers/i2c.h>
19 #include <zephyr/drivers/pinctrl.h>
20 #include "i2c_ll_stm32.h"
21
22 #ifdef CONFIG_I2C_STM32_BUS_RECOVERY
23 #include "i2c_bitbang.h"
24 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
25
26 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
27 #include <zephyr/logging/log.h>
28 #include <zephyr/irq.h>
29 LOG_MODULE_REGISTER(i2c_ll_stm32);
30
31 #include "i2c-priv.h"
32
33 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
34 #define DT_DRV_COMPAT st_stm32_i2c_v2
35 #else
36 #define DT_DRV_COMPAT st_stm32_i2c_v1
37 #endif
38
39 /* This symbol takes the value 1 if one of the device instances */
40 /* is configured in dts with a domain clock */
41 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
42 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
43 #else
44 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
45 #endif
46
i2c_stm32_runtime_configure(const struct device * dev,uint32_t config)47 int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
48 {
49 const struct i2c_stm32_config *cfg = dev->config;
50 struct i2c_stm32_data *data = dev->data;
51 I2C_TypeDef *i2c = cfg->i2c;
52 uint32_t clock = 0U;
53 int ret;
54
55 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
56 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
57 (clock_control_subsys_t)&cfg->pclken[1],
58 &clock) < 0) {
59 LOG_ERR("Failed call clock_control_get_rate(pclken[1])");
60 return -EIO;
61 }
62 } else {
63 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
64 (clock_control_subsys_t) &cfg->pclken[0],
65 &clock) < 0) {
66 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
67 return -EIO;
68 }
69 }
70
71 data->dev_config = config;
72
73 k_sem_take(&data->bus_mutex, K_FOREVER);
74
75 #ifdef CONFIG_PM_DEVICE_RUNTIME
76 (void)pm_device_runtime_get(dev);
77 #else
78 pm_device_busy_set(dev);
79 #endif
80
81 LL_I2C_Disable(i2c);
82 LL_I2C_SetMode(i2c, LL_I2C_MODE_I2C);
83 ret = stm32_i2c_configure_timing(dev, clock);
84
85 #ifdef CONFIG_PM_DEVICE_RUNTIME
86 (void)pm_device_runtime_put(dev);
87 #else
88 pm_device_busy_clear(dev);
89 #endif
90
91 k_sem_give(&data->bus_mutex);
92
93 return ret;
94 }
95
96 static inline int
i2c_stm32_transaction(const struct device * dev,struct i2c_msg msg,uint8_t * next_msg_flags,uint16_t periph)97 i2c_stm32_transaction(const struct device *dev,
98 struct i2c_msg msg, uint8_t *next_msg_flags,
99 uint16_t periph)
100 {
101 /*
102 * Perform a I2C transaction, while taking into account the STM32 I2C
103 * peripheral has a limited maximum chunk size. Take appropriate action
104 * if the message to send exceeds that limit.
105 *
106 * The last chunk of a transmission uses this function's next_msg_flags
107 * parameter for its backend calls (_write/_read). Any previous chunks
108 * use a copy of the current message's flags, with the STOP and RESTART
109 * bits turned off. This will cause the backend to use reload-mode,
110 * which will make the combination of all chunks to look like one big
111 * transaction on the wire.
112 */
113 const uint32_t i2c_stm32_maxchunk = 255U;
114 const uint8_t saved_flags = msg.flags;
115 uint8_t combine_flags =
116 saved_flags & ~(I2C_MSG_STOP | I2C_MSG_RESTART);
117 uint8_t *flagsp = NULL;
118 uint32_t rest = msg.len;
119 int ret = 0;
120
121 do { /* do ... while to allow zero-length transactions */
122 if (msg.len > i2c_stm32_maxchunk) {
123 msg.len = i2c_stm32_maxchunk;
124 msg.flags &= ~I2C_MSG_STOP;
125 flagsp = &combine_flags;
126 } else {
127 msg.flags = saved_flags;
128 flagsp = next_msg_flags;
129 }
130 if ((msg.flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
131 ret = stm32_i2c_msg_write(dev, &msg, flagsp, periph);
132 } else {
133 ret = stm32_i2c_msg_read(dev, &msg, flagsp, periph);
134 }
135 if (ret < 0) {
136 break;
137 }
138 rest -= msg.len;
139 msg.buf += msg.len;
140 msg.len = rest;
141 } while (rest > 0U);
142
143 return ret;
144 }
145
146 #define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK)
147
i2c_stm32_transfer(const struct device * dev,struct i2c_msg * msg,uint8_t num_msgs,uint16_t slave)148 static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
149 uint8_t num_msgs, uint16_t slave)
150 {
151 struct i2c_stm32_data *data = dev->data;
152 struct i2c_msg *current, *next;
153 int ret = 0;
154
155 /* Check for validity of all messages, to prevent having to abort
156 * in the middle of a transfer
157 */
158 current = msg;
159
160 /*
161 * Set I2C_MSG_RESTART flag on first message in order to send start
162 * condition
163 */
164 current->flags |= I2C_MSG_RESTART;
165
166 for (uint8_t i = 1; i <= num_msgs; i++) {
167
168 if (i < num_msgs) {
169 next = current + 1;
170
171 /*
172 * Restart condition between messages
173 * of different directions is required
174 */
175 if (OPERATION(current) != OPERATION(next)) {
176 if (!(next->flags & I2C_MSG_RESTART)) {
177 ret = -EINVAL;
178 break;
179 }
180 }
181
182 /* Stop condition is only allowed on last message */
183 if (current->flags & I2C_MSG_STOP) {
184 ret = -EINVAL;
185 break;
186 }
187 } else {
188 /* Stop condition is required for the last message */
189 current->flags |= I2C_MSG_STOP;
190 }
191
192 current++;
193 }
194
195 if (ret) {
196 return ret;
197 }
198
199 ret = pm_device_runtime_get(dev);
200 if (ret < 0) {
201 return ret;
202 }
203
204 /* Send out messages */
205 k_sem_take(&data->bus_mutex, K_FOREVER);
206
207 /* Prevent driver from being suspended by PM until I2C transaction is complete */
208 #ifdef CONFIG_PM_DEVICE_RUNTIME
209 (void)pm_device_runtime_get(dev);
210 #else
211 pm_device_busy_set(dev);
212 #endif
213
214 current = msg;
215
216 while (num_msgs > 0) {
217 uint8_t *next_msg_flags = NULL;
218
219 if (num_msgs > 1) {
220 next = current + 1;
221 next_msg_flags = &(next->flags);
222 }
223 ret = i2c_stm32_transaction(dev, *current, next_msg_flags, slave);
224 if (ret < 0) {
225 break;
226 }
227 current++;
228 num_msgs--;
229 }
230
231 #ifdef CONFIG_PM_DEVICE_RUNTIME
232 (void)pm_device_runtime_put(dev);
233 #else
234 pm_device_busy_clear(dev);
235 #endif
236
237 k_sem_give(&data->bus_mutex);
238
239 return ret;
240 }
241
242 #if CONFIG_I2C_STM32_BUS_RECOVERY
i2c_stm32_bitbang_set_scl(void * io_context,int state)243 static void i2c_stm32_bitbang_set_scl(void *io_context, int state)
244 {
245 const struct i2c_stm32_config *config = io_context;
246
247 gpio_pin_set_dt(&config->scl, state);
248 }
249
i2c_stm32_bitbang_set_sda(void * io_context,int state)250 static void i2c_stm32_bitbang_set_sda(void *io_context, int state)
251 {
252 const struct i2c_stm32_config *config = io_context;
253
254 gpio_pin_set_dt(&config->sda, state);
255 }
256
i2c_stm32_bitbang_get_sda(void * io_context)257 static int i2c_stm32_bitbang_get_sda(void *io_context)
258 {
259 const struct i2c_stm32_config *config = io_context;
260
261 return gpio_pin_get_dt(&config->sda) == 0 ? 0 : 1;
262 }
263
i2c_stm32_recover_bus(const struct device * dev)264 static int i2c_stm32_recover_bus(const struct device *dev)
265 {
266 const struct i2c_stm32_config *config = dev->config;
267 struct i2c_stm32_data *data = dev->data;
268 struct i2c_bitbang bitbang_ctx;
269 struct i2c_bitbang_io bitbang_io = {
270 .set_scl = i2c_stm32_bitbang_set_scl,
271 .set_sda = i2c_stm32_bitbang_set_sda,
272 .get_sda = i2c_stm32_bitbang_get_sda,
273 };
274 uint32_t bitrate_cfg;
275 int error = 0;
276
277 LOG_ERR("attempting to recover bus");
278
279 if (!device_is_ready(config->scl.port)) {
280 LOG_ERR("SCL GPIO device not ready");
281 return -EIO;
282 }
283
284 if (!device_is_ready(config->sda.port)) {
285 LOG_ERR("SDA GPIO device not ready");
286 return -EIO;
287 }
288
289 k_sem_take(&data->bus_mutex, K_FOREVER);
290
291 error = gpio_pin_configure_dt(&config->scl, GPIO_OUTPUT_HIGH);
292 if (error != 0) {
293 LOG_ERR("failed to configure SCL GPIO (err %d)", error);
294 goto restore;
295 }
296
297 error = gpio_pin_configure_dt(&config->sda, GPIO_OUTPUT_HIGH);
298 if (error != 0) {
299 LOG_ERR("failed to configure SDA GPIO (err %d)", error);
300 goto restore;
301 }
302
303 i2c_bitbang_init(&bitbang_ctx, &bitbang_io, (void *)config);
304
305 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate) | I2C_MODE_CONTROLLER;
306 error = i2c_bitbang_configure(&bitbang_ctx, bitrate_cfg);
307 if (error != 0) {
308 LOG_ERR("failed to configure I2C bitbang (err %d)", error);
309 goto restore;
310 }
311
312 error = i2c_bitbang_recover_bus(&bitbang_ctx);
313 if (error != 0) {
314 LOG_ERR("failed to recover bus (err %d)", error);
315 }
316
317 restore:
318 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
319
320 k_sem_give(&data->bus_mutex);
321
322 return error;
323 }
324 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
325
326
327 static const struct i2c_driver_api api_funcs = {
328 .configure = i2c_stm32_runtime_configure,
329 .transfer = i2c_stm32_transfer,
330 #if CONFIG_I2C_STM32_BUS_RECOVERY
331 .recover_bus = i2c_stm32_recover_bus,
332 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
333 #if defined(CONFIG_I2C_TARGET)
334 .target_register = i2c_stm32_target_register,
335 .target_unregister = i2c_stm32_target_unregister,
336 #endif
337 };
338
339 #ifdef CONFIG_PM_DEVICE
340
i2c_stm32_suspend(const struct device * dev)341 static int i2c_stm32_suspend(const struct device *dev)
342 {
343 int ret;
344 const struct i2c_stm32_config *cfg = dev->config;
345 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
346
347 /* Disable device clock. */
348 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
349 if (ret < 0) {
350 LOG_ERR("failure disabling I2C clock");
351 return ret;
352 }
353
354 /* Move pins to sleep state */
355 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
356 if (ret == -ENOENT) {
357 /* Warn but don't block suspend */
358 LOG_WRN("I2C pinctrl sleep state not available ");
359 } else if (ret < 0) {
360 return ret;
361 }
362
363 return 0;
364 }
365
366 #endif
367
i2c_stm32_activate(const struct device * dev)368 static int i2c_stm32_activate(const struct device *dev)
369 {
370 int ret;
371 const struct i2c_stm32_config *cfg = dev->config;
372 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
373
374 /* Move pins to active/default state */
375 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
376 if (ret < 0) {
377 LOG_ERR("I2C pinctrl setup failed (%d)", ret);
378 return ret;
379 }
380
381 /* Enable device clock. */
382 if (clock_control_on(clk,
383 (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
384 LOG_ERR("i2c: failure enabling clock");
385 return -EIO;
386 }
387
388 return 0;
389 }
390
391
i2c_stm32_init(const struct device * dev)392 static int i2c_stm32_init(const struct device *dev)
393 {
394 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
395 const struct i2c_stm32_config *cfg = dev->config;
396 uint32_t bitrate_cfg;
397 int ret;
398 struct i2c_stm32_data *data = dev->data;
399 #ifdef CONFIG_I2C_STM32_INTERRUPT
400 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
401 cfg->irq_config_func(dev);
402 #endif
403
404 /*
405 * initialize mutex used when multiple transfers
406 * are taking place to guarantee that each one is
407 * atomic and has exclusive access to the I2C bus.
408 */
409 k_sem_init(&data->bus_mutex, 1, 1);
410
411 if (!device_is_ready(clk)) {
412 LOG_ERR("clock control device not ready");
413 return -ENODEV;
414 }
415
416 i2c_stm32_activate(dev);
417
418 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
419 /* Enable I2C clock source */
420 ret = clock_control_configure(clk,
421 (clock_control_subsys_t) &cfg->pclken[1],
422 NULL);
423 if (ret < 0) {
424 return -EIO;
425 }
426 }
427
428 #if defined(CONFIG_SOC_SERIES_STM32F1X)
429 /*
430 * Force i2c reset for STM32F1 series.
431 * So that they can enter master mode properly.
432 * Issue described in ES096 2.14.7
433 */
434 I2C_TypeDef *i2c = cfg->i2c;
435
436 LL_I2C_EnableReset(i2c);
437 LL_I2C_DisableReset(i2c);
438 #endif
439
440 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
441
442 ret = i2c_stm32_runtime_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
443 if (ret < 0) {
444 LOG_ERR("i2c: failure initializing");
445 return ret;
446 }
447
448 #ifdef CONFIG_PM_DEVICE_RUNTIME
449 i2c_stm32_suspend(dev);
450 pm_device_init_suspended(dev);
451 (void)pm_device_runtime_enable(dev);
452 #endif
453
454 return 0;
455 }
456
457 #ifdef CONFIG_PM_DEVICE
458
i2c_stm32_pm_action(const struct device * dev,enum pm_device_action action)459 static int i2c_stm32_pm_action(const struct device *dev, enum pm_device_action action)
460 {
461 int err;
462
463 switch (action) {
464 case PM_DEVICE_ACTION_RESUME:
465 err = i2c_stm32_activate(dev);
466 break;
467 case PM_DEVICE_ACTION_SUSPEND:
468 err = i2c_stm32_suspend(dev);
469 break;
470 default:
471 return -ENOTSUP;
472 }
473
474 return err;
475 }
476
477 #endif
478
479 /* Macros for I2C instance declaration */
480
481 #ifdef CONFIG_I2C_STM32_INTERRUPT
482
483 #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
484 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
485 do { \
486 IRQ_CONNECT(DT_INST_IRQN(index), \
487 DT_INST_IRQ(index, priority), \
488 stm32_i2c_combined_isr, \
489 DEVICE_DT_INST_GET(index), 0); \
490 irq_enable(DT_INST_IRQN(index)); \
491 } while (false)
492 #else
493 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
494 do { \
495 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
496 DT_INST_IRQ_BY_NAME(index, event, priority),\
497 stm32_i2c_event_isr, \
498 DEVICE_DT_INST_GET(index), 0); \
499 irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
500 \
501 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
502 DT_INST_IRQ_BY_NAME(index, error, priority),\
503 stm32_i2c_error_isr, \
504 DEVICE_DT_INST_GET(index), 0); \
505 irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
506 } while (false)
507 #endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
508
509 #define STM32_I2C_IRQ_HANDLER_DECL(index) \
510 static void i2c_stm32_irq_config_func_##index(const struct device *dev)
511 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
512 .irq_config_func = i2c_stm32_irq_config_func_##index,
513 #define STM32_I2C_IRQ_HANDLER(index) \
514 static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
515 { \
516 STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
517 }
518 #else
519
520 #define STM32_I2C_IRQ_HANDLER_DECL(index)
521 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index)
522 #define STM32_I2C_IRQ_HANDLER(index)
523
524 #endif /* CONFIG_I2C_STM32_INTERRUPT */
525
526 #if CONFIG_I2C_STM32_BUS_RECOVERY
527 #define I2C_STM32_SCL_INIT(n) .scl = GPIO_DT_SPEC_INST_GET_OR(n, scl_gpios, {0}),
528 #define I2C_STM32_SDA_INIT(n) .sda = GPIO_DT_SPEC_INST_GET_OR(n, sda_gpios, {0}),
529 #else
530 #define I2C_STM32_SCL_INIT(n)
531 #define I2C_STM32_SDA_INIT(n)
532 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
533
534 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
535 #define DEFINE_TIMINGS(index) \
536 static const uint32_t i2c_timings_##index[] = \
537 DT_INST_PROP_OR(index, timings, {});
538 #define USE_TIMINGS(index) \
539 .timings = (const struct i2c_config_timing *) i2c_timings_##index, \
540 .n_timings = ARRAY_SIZE(i2c_timings_##index),
541 #else /* V2 */
542 #define DEFINE_TIMINGS(index)
543 #define USE_TIMINGS(index)
544 #endif /* V2 */
545
546 #define STM32_I2C_INIT(index) \
547 STM32_I2C_IRQ_HANDLER_DECL(index); \
548 \
549 DEFINE_TIMINGS(index) \
550 \
551 PINCTRL_DT_INST_DEFINE(index); \
552 \
553 static const struct stm32_pclken pclken_##index[] = \
554 STM32_DT_INST_CLOCKS(index); \
555 \
556 static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
557 .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
558 .pclken = pclken_##index, \
559 .pclk_len = DT_INST_NUM_CLOCKS(index), \
560 STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
561 .bitrate = DT_INST_PROP(index, clock_frequency), \
562 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
563 I2C_STM32_SCL_INIT(index) \
564 I2C_STM32_SDA_INIT(index) \
565 USE_TIMINGS(index) \
566 }; \
567 \
568 static struct i2c_stm32_data i2c_stm32_dev_data_##index; \
569 \
570 PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
571 \
572 I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
573 PM_DEVICE_DT_INST_GET(index), \
574 &i2c_stm32_dev_data_##index, \
575 &i2c_stm32_cfg_##index, \
576 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
577 &api_funcs); \
578 \
579 STM32_I2C_IRQ_HANDLER(index)
580
581 DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT)
582
