1 /*
2 * Copyright (c) 2016 BayLibre, SAS
3 * Copyright (c) 2017 Linaro Ltd
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
9 #include <zephyr/drivers/clock_control.h>
10 #include <zephyr/pm/device.h>
11 #include <zephyr/pm/device_runtime.h>
12 #include <zephyr/pm/policy.h>
13 #include <zephyr/sys/util.h>
14 #include <zephyr/kernel.h>
15 #include <soc.h>
16 #include <stm32_ll_i2c.h>
17 #include <stm32_ll_rcc.h>
18 #include <errno.h>
19 #include <zephyr/drivers/i2c.h>
20 #include <zephyr/drivers/pinctrl.h>
21 #include "i2c_ll_stm32.h"
22
23 #ifdef CONFIG_I2C_STM32_BUS_RECOVERY
24 #include "i2c_bitbang.h"
25 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
26
27 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
28 #include <zephyr/logging/log.h>
29 #include <zephyr/irq.h>
30 LOG_MODULE_REGISTER(i2c_ll_stm32);
31
32 #include "i2c-priv.h"
33
34 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
35 #define DT_DRV_COMPAT st_stm32_i2c_v2
36 #else
37 #define DT_DRV_COMPAT st_stm32_i2c_v1
38 #endif
39
40 /* This symbol takes the value 1 if one of the device instances */
41 /* is configured in dts with a domain clock */
42 #if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
43 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 1
44 #else
45 #define STM32_I2C_DOMAIN_CLOCK_SUPPORT 0
46 #endif
47
i2c_stm32_get_config(const struct device * dev,uint32_t * config)48 int i2c_stm32_get_config(const struct device *dev, uint32_t *config)
49 {
50 struct i2c_stm32_data *data = dev->data;
51
52 if (!data->is_configured) {
53 LOG_ERR("I2C controller not configured");
54 return -EIO;
55 }
56
57 *config = data->dev_config;
58
59 #if CONFIG_I2C_STM32_V2_TIMING
60 /* Print the timing parameter of device data */
61 LOG_INF("I2C timing value, report to the DTS :");
62
63 /* I2C BIT RATE */
64 if (data->current_timing.i2c_speed == 100000) {
65 LOG_INF("timings = <%d I2C_BITRATE_STANDARD 0x%X>;",
66 data->current_timing.periph_clock,
67 data->current_timing.timing_setting);
68 } else if (data->current_timing.i2c_speed == 400000) {
69 LOG_INF("timings = <%d I2C_BITRATE_FAST 0x%X>;",
70 data->current_timing.periph_clock,
71 data->current_timing.timing_setting);
72 } else if (data->current_timing.i2c_speed == 1000000) {
73 LOG_INF("timings = <%d I2C_SPEED_FAST_PLUS 0x%X>;",
74 data->current_timing.periph_clock,
75 data->current_timing.timing_setting);
76 }
77 #endif /* CONFIG_I2C_STM32_V2_TIMING */
78
79 return 0;
80 }
81
i2c_stm32_runtime_configure(const struct device * dev,uint32_t config)82 int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config)
83 {
84 const struct i2c_stm32_config *cfg = dev->config;
85 struct i2c_stm32_data *data = dev->data;
86 const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
87 I2C_TypeDef *i2c = cfg->i2c;
88 uint32_t i2c_clock = 0U;
89 int ret;
90
91 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
92 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[1],
93 &i2c_clock) < 0) {
94 LOG_ERR("Failed call clock_control_get_rate(pclken[1])");
95 return -EIO;
96 }
97 } else {
98 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[0],
99 &i2c_clock) < 0) {
100 LOG_ERR("Failed call clock_control_get_rate(pclken[0])");
101 return -EIO;
102 }
103 }
104
105 data->dev_config = config;
106
107 k_sem_take(&data->bus_mutex, K_FOREVER);
108
109 #ifdef CONFIG_PM_DEVICE_RUNTIME
110 ret = clock_control_on(clk, (clock_control_subsys_t)&cfg->pclken[0]);
111 if (ret < 0) {
112 LOG_ERR("failure Enabling I2C clock");
113 return ret;
114 }
115 #endif
116
117 LL_I2C_Disable(i2c);
118 i2c_stm32_set_smbus_mode(dev, data->mode);
119 ret = stm32_i2c_configure_timing(dev, i2c_clock);
120
121 if (data->smbalert_active) {
122 LL_I2C_Enable(i2c);
123 }
124
125 #ifdef CONFIG_PM_DEVICE_RUNTIME
126 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
127 if (ret < 0) {
128 LOG_ERR("failure disabling I2C clock");
129 return ret;
130 }
131 #endif
132
133 k_sem_give(&data->bus_mutex);
134
135 return ret;
136 }
137
138 #define OPERATION(msg) (((struct i2c_msg *) msg)->flags & I2C_MSG_RW_MASK)
139
i2c_stm32_transfer(const struct device * dev,struct i2c_msg * msg,uint8_t num_msgs,uint16_t slave)140 static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
141 uint8_t num_msgs, uint16_t slave)
142 {
143 struct i2c_stm32_data *data = dev->data;
144 struct i2c_msg *current, *next;
145 int ret = 0;
146
147 /* Check for validity of all messages, to prevent having to abort
148 * in the middle of a transfer
149 */
150 current = msg;
151
152 /*
153 * Set I2C_MSG_RESTART flag on first message in order to send start
154 * condition
155 */
156 current->flags |= I2C_MSG_RESTART;
157
158 for (uint8_t i = 1; i <= num_msgs; i++) {
159
160 if (i < num_msgs) {
161 next = current + 1;
162
163 /*
164 * Restart condition between messages
165 * of different directions is required
166 */
167 if (OPERATION(current) != OPERATION(next)) {
168 if (!(next->flags & I2C_MSG_RESTART)) {
169 ret = -EINVAL;
170 break;
171 }
172 }
173
174 /* Stop condition is only allowed on last message */
175 if (current->flags & I2C_MSG_STOP) {
176 ret = -EINVAL;
177 break;
178 }
179 }
180
181 current++;
182 }
183
184 if (ret) {
185 return ret;
186 }
187
188 /* Send out messages */
189 k_sem_take(&data->bus_mutex, K_FOREVER);
190
191 /* Prevent driver from being suspended by PM until I2C transaction is complete */
192 #ifdef CONFIG_PM_DEVICE_RUNTIME
193 (void)pm_device_runtime_get(dev);
194 #endif
195
196 /* Prevent the clocks to be stopped during the i2c transaction */
197 pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
198
199 current = msg;
200
201 while (num_msgs > 0) {
202 uint8_t *next_msg_flags = NULL;
203
204 if (num_msgs > 1) {
205 next = current + 1;
206 next_msg_flags = &(next->flags);
207 }
208 ret = stm32_i2c_transaction(dev, *current, next_msg_flags, slave);
209 if (ret < 0) {
210 break;
211 }
212 current++;
213 num_msgs--;
214 }
215
216 pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
217
218 #ifdef CONFIG_PM_DEVICE_RUNTIME
219 (void)pm_device_runtime_put(dev);
220 #endif
221
222 k_sem_give(&data->bus_mutex);
223
224 return ret;
225 }
226
227 #if CONFIG_I2C_STM32_BUS_RECOVERY
i2c_stm32_bitbang_set_scl(void * io_context,int state)228 static void i2c_stm32_bitbang_set_scl(void *io_context, int state)
229 {
230 const struct i2c_stm32_config *config = io_context;
231
232 gpio_pin_set_dt(&config->scl, state);
233 }
234
i2c_stm32_bitbang_set_sda(void * io_context,int state)235 static void i2c_stm32_bitbang_set_sda(void *io_context, int state)
236 {
237 const struct i2c_stm32_config *config = io_context;
238
239 gpio_pin_set_dt(&config->sda, state);
240 }
241
i2c_stm32_bitbang_get_sda(void * io_context)242 static int i2c_stm32_bitbang_get_sda(void *io_context)
243 {
244 const struct i2c_stm32_config *config = io_context;
245
246 return gpio_pin_get_dt(&config->sda) == 0 ? 0 : 1;
247 }
248
i2c_stm32_recover_bus(const struct device * dev)249 static int i2c_stm32_recover_bus(const struct device *dev)
250 {
251 const struct i2c_stm32_config *config = dev->config;
252 struct i2c_stm32_data *data = dev->data;
253 struct i2c_bitbang bitbang_ctx;
254 struct i2c_bitbang_io bitbang_io = {
255 .set_scl = i2c_stm32_bitbang_set_scl,
256 .set_sda = i2c_stm32_bitbang_set_sda,
257 .get_sda = i2c_stm32_bitbang_get_sda,
258 };
259 uint32_t bitrate_cfg;
260 int error = 0;
261
262 LOG_ERR("attempting to recover bus");
263
264 if (!gpio_is_ready_dt(&config->scl)) {
265 LOG_ERR("SCL GPIO device not ready");
266 return -EIO;
267 }
268
269 if (!gpio_is_ready_dt(&config->sda)) {
270 LOG_ERR("SDA GPIO device not ready");
271 return -EIO;
272 }
273
274 k_sem_take(&data->bus_mutex, K_FOREVER);
275
276 error = gpio_pin_configure_dt(&config->scl, GPIO_OUTPUT_HIGH);
277 if (error != 0) {
278 LOG_ERR("failed to configure SCL GPIO (err %d)", error);
279 goto restore;
280 }
281
282 error = gpio_pin_configure_dt(&config->sda, GPIO_OUTPUT_HIGH);
283 if (error != 0) {
284 LOG_ERR("failed to configure SDA GPIO (err %d)", error);
285 goto restore;
286 }
287
288 i2c_bitbang_init(&bitbang_ctx, &bitbang_io, (void *)config);
289
290 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate) | I2C_MODE_CONTROLLER;
291 error = i2c_bitbang_configure(&bitbang_ctx, bitrate_cfg);
292 if (error != 0) {
293 LOG_ERR("failed to configure I2C bitbang (err %d)", error);
294 goto restore;
295 }
296
297 error = i2c_bitbang_recover_bus(&bitbang_ctx);
298 if (error != 0) {
299 LOG_ERR("failed to recover bus (err %d)", error);
300 }
301
302 restore:
303 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
304
305 k_sem_give(&data->bus_mutex);
306
307 return error;
308 }
309 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
310
311
312 static const struct i2c_driver_api api_funcs = {
313 .configure = i2c_stm32_runtime_configure,
314 .transfer = i2c_stm32_transfer,
315 .get_config = i2c_stm32_get_config,
316 #if CONFIG_I2C_STM32_BUS_RECOVERY
317 .recover_bus = i2c_stm32_recover_bus,
318 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
319 #if defined(CONFIG_I2C_TARGET)
320 .target_register = i2c_stm32_target_register,
321 .target_unregister = i2c_stm32_target_unregister,
322 #endif
323 };
324
325 #ifdef CONFIG_PM_DEVICE
326
i2c_stm32_suspend(const struct device * dev)327 static int i2c_stm32_suspend(const struct device *dev)
328 {
329 int ret;
330 const struct i2c_stm32_config *cfg = dev->config;
331 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
332
333 /* Disable device clock. */
334 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]);
335 if (ret < 0) {
336 LOG_ERR("failure disabling I2C clock");
337 return ret;
338 }
339
340 /* Move pins to sleep state */
341 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
342 if (ret == -ENOENT) {
343 /* Warn but don't block suspend */
344 LOG_WRN("I2C pinctrl sleep state not available ");
345 } else if (ret < 0) {
346 return ret;
347 }
348
349 return 0;
350 }
351
352 #endif
353
i2c_stm32_activate(const struct device * dev)354 static int i2c_stm32_activate(const struct device *dev)
355 {
356 int ret;
357 const struct i2c_stm32_config *cfg = dev->config;
358 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
359
360 /* Move pins to active/default state */
361 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
362 if (ret < 0) {
363 LOG_ERR("I2C pinctrl setup failed (%d)", ret);
364 return ret;
365 }
366
367 /* Enable device clock. */
368 if (clock_control_on(clk,
369 (clock_control_subsys_t) &cfg->pclken[0]) != 0) {
370 LOG_ERR("i2c: failure enabling clock");
371 return -EIO;
372 }
373
374 return 0;
375 }
376
377
i2c_stm32_init(const struct device * dev)378 static int i2c_stm32_init(const struct device *dev)
379 {
380 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
381 const struct i2c_stm32_config *cfg = dev->config;
382 uint32_t bitrate_cfg;
383 int ret;
384 struct i2c_stm32_data *data = dev->data;
385 #ifdef CONFIG_I2C_STM32_INTERRUPT
386 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
387 cfg->irq_config_func(dev);
388 #endif
389
390 data->is_configured = false;
391 data->mode = I2CSTM32MODE_I2C;
392
393 /*
394 * initialize mutex used when multiple transfers
395 * are taking place to guarantee that each one is
396 * atomic and has exclusive access to the I2C bus.
397 */
398 k_sem_init(&data->bus_mutex, 1, 1);
399
400 if (!device_is_ready(clk)) {
401 LOG_ERR("clock control device not ready");
402 return -ENODEV;
403 }
404
405 i2c_stm32_activate(dev);
406
407 if (IS_ENABLED(STM32_I2C_DOMAIN_CLOCK_SUPPORT) && (cfg->pclk_len > 1)) {
408 /* Enable I2C clock source */
409 ret = clock_control_configure(clk,
410 (clock_control_subsys_t) &cfg->pclken[1],
411 NULL);
412 if (ret < 0) {
413 return -EIO;
414 }
415 }
416
417 #if defined(CONFIG_SOC_SERIES_STM32F1X)
418 /*
419 * Force i2c reset for STM32F1 series.
420 * So that they can enter master mode properly.
421 * Issue described in ES096 2.14.7
422 */
423 I2C_TypeDef *i2c = cfg->i2c;
424
425 LL_I2C_EnableReset(i2c);
426 LL_I2C_DisableReset(i2c);
427 #endif
428
429 bitrate_cfg = i2c_map_dt_bitrate(cfg->bitrate);
430
431 ret = i2c_stm32_runtime_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
432 if (ret < 0) {
433 LOG_ERR("i2c: failure initializing");
434 return ret;
435 }
436
437 #ifdef CONFIG_PM_DEVICE_RUNTIME
438 (void)pm_device_runtime_enable(dev);
439 #endif
440
441 data->is_configured = true;
442
443 return 0;
444 }
445
446 #ifdef CONFIG_PM_DEVICE
447
i2c_stm32_pm_action(const struct device * dev,enum pm_device_action action)448 static int i2c_stm32_pm_action(const struct device *dev, enum pm_device_action action)
449 {
450 int err;
451
452 switch (action) {
453 case PM_DEVICE_ACTION_RESUME:
454 err = i2c_stm32_activate(dev);
455 break;
456 case PM_DEVICE_ACTION_SUSPEND:
457 err = i2c_stm32_suspend(dev);
458 break;
459 default:
460 return -ENOTSUP;
461 }
462
463 return err;
464 }
465
466 #endif
467
468 #ifdef CONFIG_SMBUS_STM32_SMBALERT
i2c_stm32_smbalert_set_callback(const struct device * dev,i2c_stm32_smbalert_cb_func_t func,const struct device * cb_dev)469 void i2c_stm32_smbalert_set_callback(const struct device *dev, i2c_stm32_smbalert_cb_func_t func,
470 const struct device *cb_dev)
471 {
472 struct i2c_stm32_data *data = dev->data;
473
474 data->smbalert_cb_func = func;
475 data->smbalert_cb_dev = cb_dev;
476 }
477 #endif /* CONFIG_SMBUS_STM32_SMBALERT */
478
i2c_stm32_set_smbus_mode(const struct device * dev,enum i2c_stm32_mode mode)479 void i2c_stm32_set_smbus_mode(const struct device *dev, enum i2c_stm32_mode mode)
480 {
481 const struct i2c_stm32_config *cfg = dev->config;
482 struct i2c_stm32_data *data = dev->data;
483 I2C_TypeDef *i2c = cfg->i2c;
484
485 data->mode = mode;
486
487 switch (mode) {
488 case I2CSTM32MODE_I2C:
489 LL_I2C_SetMode(i2c, LL_I2C_MODE_I2C);
490 return;
491 #ifdef CONFIG_SMBUS_STM32
492 case I2CSTM32MODE_SMBUSHOST:
493 LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_HOST);
494 return;
495 case I2CSTM32MODE_SMBUSDEVICE:
496 LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_DEVICE);
497 return;
498 case I2CSTM32MODE_SMBUSDEVICEARP:
499 LL_I2C_SetMode(i2c, LL_I2C_MODE_SMBUS_DEVICE_ARP);
500 return;
501 #endif
502 default:
503 LOG_ERR("%s: invalid mode %i", dev->name, mode);
504 return;
505 }
506 }
507
508 #ifdef CONFIG_SMBUS_STM32
i2c_stm32_smbalert_enable(const struct device * dev)509 void i2c_stm32_smbalert_enable(const struct device *dev)
510 {
511 struct i2c_stm32_data *data = dev->data;
512 const struct i2c_stm32_config *cfg = dev->config;
513
514 data->smbalert_active = true;
515 LL_I2C_EnableSMBusAlert(cfg->i2c);
516 LL_I2C_EnableIT_ERR(cfg->i2c);
517 LL_I2C_Enable(cfg->i2c);
518 }
519
i2c_stm32_smbalert_disable(const struct device * dev)520 void i2c_stm32_smbalert_disable(const struct device *dev)
521 {
522 struct i2c_stm32_data *data = dev->data;
523 const struct i2c_stm32_config *cfg = dev->config;
524
525 data->smbalert_active = false;
526 LL_I2C_DisableSMBusAlert(cfg->i2c);
527 LL_I2C_DisableIT_ERR(cfg->i2c);
528 LL_I2C_Disable(cfg->i2c);
529 }
530 #endif /* CONFIG_SMBUS_STM32 */
531
532 /* Macros for I2C instance declaration */
533
534 #ifdef CONFIG_I2C_STM32_INTERRUPT
535
536 #ifdef CONFIG_I2C_STM32_COMBINED_INTERRUPT
537 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
538 do { \
539 IRQ_CONNECT(DT_INST_IRQN(index), \
540 DT_INST_IRQ(index, priority), \
541 stm32_i2c_combined_isr, \
542 DEVICE_DT_INST_GET(index), 0); \
543 irq_enable(DT_INST_IRQN(index)); \
544 } while (false)
545 #else
546 #define STM32_I2C_IRQ_CONNECT_AND_ENABLE(index) \
547 do { \
548 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, event, irq), \
549 DT_INST_IRQ_BY_NAME(index, event, priority),\
550 stm32_i2c_event_isr, \
551 DEVICE_DT_INST_GET(index), 0); \
552 irq_enable(DT_INST_IRQ_BY_NAME(index, event, irq)); \
553 \
554 IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, error, irq), \
555 DT_INST_IRQ_BY_NAME(index, error, priority),\
556 stm32_i2c_error_isr, \
557 DEVICE_DT_INST_GET(index), 0); \
558 irq_enable(DT_INST_IRQ_BY_NAME(index, error, irq)); \
559 } while (false)
560 #endif /* CONFIG_I2C_STM32_COMBINED_INTERRUPT */
561
562 #define STM32_I2C_IRQ_HANDLER_DECL(index) \
563 static void i2c_stm32_irq_config_func_##index(const struct device *dev)
564 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
565 .irq_config_func = i2c_stm32_irq_config_func_##index,
566 #define STM32_I2C_IRQ_HANDLER(index) \
567 static void i2c_stm32_irq_config_func_##index(const struct device *dev) \
568 { \
569 STM32_I2C_IRQ_CONNECT_AND_ENABLE(index); \
570 }
571 #else
572
573 #define STM32_I2C_IRQ_HANDLER_DECL(index)
574 #define STM32_I2C_IRQ_HANDLER_FUNCTION(index)
575 #define STM32_I2C_IRQ_HANDLER(index)
576
577 #endif /* CONFIG_I2C_STM32_INTERRUPT */
578
579 #define STM32_I2C_INIT(index) \
580 STM32_I2C_IRQ_HANDLER_DECL(index); \
581 \
582 IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
583 (static const uint32_t i2c_timings_##index[] = \
584 DT_INST_PROP_OR(index, timings, {});)) \
585 \
586 PINCTRL_DT_INST_DEFINE(index); \
587 \
588 static const struct stm32_pclken pclken_##index[] = \
589 STM32_DT_INST_CLOCKS(index); \
590 \
591 static const struct i2c_stm32_config i2c_stm32_cfg_##index = { \
592 .i2c = (I2C_TypeDef *)DT_INST_REG_ADDR(index), \
593 .pclken = pclken_##index, \
594 .pclk_len = DT_INST_NUM_CLOCKS(index), \
595 STM32_I2C_IRQ_HANDLER_FUNCTION(index) \
596 .bitrate = DT_INST_PROP(index, clock_frequency), \
597 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
598 IF_ENABLED(CONFIG_I2C_STM32_BUS_RECOVERY, \
599 (.scl = GPIO_DT_SPEC_INST_GET_OR(index, scl_gpios, {0}),\
600 .sda = GPIO_DT_SPEC_INST_GET_OR(index, sda_gpios, {0}),))\
601 IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2), \
602 (.timings = (const struct i2c_config_timing *) i2c_timings_##index,\
603 .n_timings = ARRAY_SIZE(i2c_timings_##index),)) \
604 }; \
605 \
606 static struct i2c_stm32_data i2c_stm32_dev_data_##index; \
607 \
608 PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action); \
609 \
610 I2C_DEVICE_DT_INST_DEFINE(index, i2c_stm32_init, \
611 PM_DEVICE_DT_INST_GET(index), \
612 &i2c_stm32_dev_data_##index, \
613 &i2c_stm32_cfg_##index, \
614 POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
615 &api_funcs); \
616 \
617 STM32_I2C_IRQ_HANDLER(index)
618
619 DT_INST_FOREACH_STATUS_OKAY(STM32_I2C_INIT)
620
