1 /*
2 * Copyright (c) 2017 Linaro Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief Software driven 'bit-banging' library for I2C
10 *
11 * This code implements the I2C single master protocol in software by directly
12 * manipulating the levels of the SCL and SDA lines of an I2C bus. It supports
13 * the Standard-mode and Fast-mode speeds and doesn't support optional
14 * protocol feature like 10-bit addresses or clock stretching.
15 *
16 * Timings and protocol are based Rev. 6 of the I2C specification:
17 * http://www.nxp.com/documents/user_manual/UM10204.pdf
18 */
19
20 #include <errno.h>
21 #include <zephyr/kernel.h>
22 #include <zephyr/drivers/i2c.h>
23 #include "i2c_bitbang.h"
24
25 /*
26 * Indexes into delay table for each part of I2C timing waveform we are
27 * interested in. In practice, for Standard and Fast modes, there are only two
28 * different numerical values (T_LOW and T_HIGH) so we alias the others to
29 * these. (Actually, we're simplifying a little, T_SU_STA could be T_HIGH on
30 * Fast mode)
31 */
32 #define T_LOW 0
33 #define T_HIGH 1
34 #define T_SU_STA T_LOW
35 #define T_HD_STA T_HIGH
36 #define T_SU_STP T_HIGH
37 #define T_BUF T_LOW
38
39 #define NS_TO_SYS_CLOCK_HW_CYCLES(ns) \
40 ((uint64_t)sys_clock_hw_cycles_per_sec() * (ns) / NSEC_PER_SEC + 1)
41
i2c_bitbang_configure(struct i2c_bitbang * context,uint32_t dev_config)42 int i2c_bitbang_configure(struct i2c_bitbang *context, uint32_t dev_config)
43 {
44 /* Check for features we don't support */
45 if (I2C_ADDR_10_BITS & dev_config) {
46 return -ENOTSUP;
47 }
48
49 /* Setup speed to use */
50 switch (I2C_SPEED_GET(dev_config)) {
51 case I2C_SPEED_STANDARD:
52 context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700);
53 context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000);
54 break;
55 case I2C_SPEED_FAST:
56 context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300);
57 context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(600);
58 break;
59 default:
60 return -ENOTSUP;
61 }
62
63 context->dev_config = dev_config;
64
65 return 0;
66 }
67
i2c_bitbang_get_config(struct i2c_bitbang * context,uint32_t * config)68 int i2c_bitbang_get_config(struct i2c_bitbang *context, uint32_t *config)
69 {
70 if (context->dev_config == 0) {
71 return -EIO;
72 }
73
74 *config = context->dev_config;
75
76 return 0;
77 }
78
i2c_set_scl(struct i2c_bitbang * context,int state)79 static void i2c_set_scl(struct i2c_bitbang *context, int state)
80 {
81 context->io->set_scl(context->io_context, state);
82 }
83
i2c_set_sda(struct i2c_bitbang * context,int state)84 static void i2c_set_sda(struct i2c_bitbang *context, int state)
85 {
86 context->io->set_sda(context->io_context, state);
87 }
88
i2c_get_sda(struct i2c_bitbang * context)89 static int i2c_get_sda(struct i2c_bitbang *context)
90 {
91 return context->io->get_sda(context->io_context);
92 }
93
i2c_delay(unsigned int cycles_to_wait)94 static void i2c_delay(unsigned int cycles_to_wait)
95 {
96 uint32_t start = k_cycle_get_32();
97
98 /* Wait until the given number of cycles have passed */
99 while (k_cycle_get_32() - start < cycles_to_wait) {
100 }
101 }
102
i2c_start(struct i2c_bitbang * context)103 static void i2c_start(struct i2c_bitbang *context)
104 {
105 if (!i2c_get_sda(context)) {
106 /*
107 * SDA is already low, so we need to do something to make it
108 * high. Try pulsing clock low to get slave to release SDA.
109 */
110 i2c_set_scl(context, 0);
111 i2c_delay(context->delays[T_LOW]);
112 i2c_set_scl(context, 1);
113 i2c_delay(context->delays[T_SU_STA]);
114 }
115 i2c_set_sda(context, 0);
116 i2c_delay(context->delays[T_HD_STA]);
117
118 i2c_set_scl(context, 0);
119 i2c_delay(context->delays[T_LOW]);
120 }
121
i2c_repeated_start(struct i2c_bitbang * context)122 static void i2c_repeated_start(struct i2c_bitbang *context)
123 {
124 i2c_set_sda(context, 1);
125 i2c_set_scl(context, 1);
126 i2c_delay(context->delays[T_HIGH]);
127
128 i2c_delay(context->delays[T_SU_STA]);
129 i2c_start(context);
130 }
131
i2c_stop(struct i2c_bitbang * context)132 static void i2c_stop(struct i2c_bitbang *context)
133 {
134 i2c_set_sda(context, 0);
135 i2c_delay(context->delays[T_LOW]);
136
137 i2c_set_scl(context, 1);
138 i2c_delay(context->delays[T_HIGH]);
139
140 i2c_delay(context->delays[T_SU_STP]);
141 i2c_set_sda(context, 1);
142 i2c_delay(context->delays[T_BUF]); /* In case we start again too soon */
143 }
144
i2c_write_bit(struct i2c_bitbang * context,int bit)145 static void i2c_write_bit(struct i2c_bitbang *context, int bit)
146 {
147 /* SDA hold time is zero, so no need for a delay here */
148 i2c_set_sda(context, bit);
149 i2c_set_scl(context, 1);
150 i2c_delay(context->delays[T_HIGH]);
151 i2c_set_scl(context, 0);
152 i2c_delay(context->delays[T_LOW]);
153 }
154
i2c_read_bit(struct i2c_bitbang * context)155 static bool i2c_read_bit(struct i2c_bitbang *context)
156 {
157 bool bit;
158
159 /* SDA hold time is zero, so no need for a delay here */
160 i2c_set_sda(context, 1); /* Stop driving low, so slave has control */
161
162 i2c_set_scl(context, 1);
163 i2c_delay(context->delays[T_HIGH]);
164
165 bit = i2c_get_sda(context);
166
167 i2c_set_scl(context, 0);
168 i2c_delay(context->delays[T_LOW]);
169 return bit;
170 }
171
i2c_write_byte(struct i2c_bitbang * context,uint8_t byte)172 static bool i2c_write_byte(struct i2c_bitbang *context, uint8_t byte)
173 {
174 uint8_t mask = 1 << 7;
175
176 do {
177 i2c_write_bit(context, byte & mask);
178 } while (mask >>= 1);
179
180 /* Return inverted ACK bit, i.e. 'true' for ACK, 'false' for NACK */
181 return !i2c_read_bit(context);
182 }
183
i2c_read_byte(struct i2c_bitbang * context)184 static uint8_t i2c_read_byte(struct i2c_bitbang *context)
185 {
186 unsigned int byte = 1U;
187
188 do {
189 byte <<= 1;
190 byte |= i2c_read_bit(context);
191 } while (!(byte & (1 << 8)));
192
193 return byte;
194 }
195
i2c_bitbang_transfer(struct i2c_bitbang * context,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t slave_address)196 int i2c_bitbang_transfer(struct i2c_bitbang *context,
197 struct i2c_msg *msgs, uint8_t num_msgs,
198 uint16_t slave_address)
199 {
200 uint8_t *buf, *buf_end;
201 unsigned int flags;
202 int result = -EIO;
203
204 if (!num_msgs) {
205 return 0;
206 }
207
208 /* We want an initial Start condition */
209 flags = I2C_MSG_RESTART;
210
211 /* Make sure we're in a good state so slave recognises the Start */
212 i2c_set_scl(context, 1);
213 flags |= I2C_MSG_STOP;
214
215 do {
216 /* Stop flag from previous message? */
217 if (flags & I2C_MSG_STOP) {
218 i2c_stop(context);
219 }
220
221 /* Forget old flags except start flag */
222 flags &= I2C_MSG_RESTART;
223
224 /* Start condition? */
225 if (flags & I2C_MSG_RESTART) {
226 i2c_start(context);
227 } else if (msgs->flags & I2C_MSG_RESTART) {
228 i2c_repeated_start(context);
229 }
230
231 /* Get flags for new message */
232 flags |= msgs->flags;
233
234 /* Send address after any Start condition */
235 if (flags & I2C_MSG_RESTART) {
236 unsigned int byte0 = slave_address << 1;
237
238 byte0 |= (flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
239 if (!i2c_write_byte(context, byte0)) {
240 goto finish; /* No ACK received */
241 }
242 flags &= ~I2C_MSG_RESTART;
243 }
244
245 /* Transfer data */
246 buf = msgs->buf;
247 buf_end = buf + msgs->len;
248 if ((flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
249 /* Read */
250 while (buf < buf_end) {
251 *buf++ = i2c_read_byte(context);
252 /* ACK the byte, except for the last one */
253 i2c_write_bit(context, buf == buf_end);
254 }
255 } else {
256 /* Write */
257 while (buf < buf_end) {
258 if (!i2c_write_byte(context, *buf++)) {
259 goto finish; /* No ACK received */
260 }
261 }
262 }
263
264 /* Next message */
265 msgs++;
266 num_msgs--;
267 } while (num_msgs);
268
269 /* Complete without error */
270 result = 0;
271 finish:
272 i2c_stop(context);
273
274 return result;
275 }
276
i2c_bitbang_recover_bus(struct i2c_bitbang * context)277 int i2c_bitbang_recover_bus(struct i2c_bitbang *context)
278 {
279 int i;
280
281 /*
282 * The I2C-bus specification and user manual (NXP UM10204
283 * rev. 6, section 3.1.16) suggests the master emit 9 SCL
284 * clock pulses to recover the bus.
285 *
286 * The Linux kernel I2C bitbang recovery functionality issues
287 * a START condition followed by 9 STOP conditions.
288 *
289 * Other I2C slave devices (e.g. Microchip ATSHA204a) suggest
290 * issuing a START condition followed by 9 SCL clock pulses
291 * with SDA held high/floating, a REPEATED START condition,
292 * and a STOP condition.
293 *
294 * The latter is what is implemented here.
295 */
296
297 /* Start condition */
298 i2c_start(context);
299
300 /* 9 cycles of SCL with SDA held high */
301 for (i = 0; i < 9; i++) {
302 i2c_write_bit(context, 1);
303 }
304
305 /* Another start condition followed by a stop condition */
306 i2c_repeated_start(context);
307 i2c_stop(context);
308
309 /* Check if bus is clear */
310 if (i2c_get_sda(context)) {
311 return 0;
312 } else {
313 return -EBUSY;
314 }
315 }
316
i2c_bitbang_init(struct i2c_bitbang * context,const struct i2c_bitbang_io * io,void * io_context)317 void i2c_bitbang_init(struct i2c_bitbang *context,
318 const struct i2c_bitbang_io *io, void *io_context)
319 {
320 context->io = io;
321 context->io_context = io_context;
322 i2c_bitbang_configure(context, I2C_SPEED_STANDARD << I2C_SPEED_SHIFT);
323 }
324
