1 /*
2 * Copyright (c) 2017 Linaro Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief Software driven 'bit-banging' library for I2C
10 *
11 * This code implements the I2C single master protocol in software by directly
12 * manipulating the levels of the SCL and SDA lines of an I2C bus. It supports
13 * the Standard-mode and Fast-mode speeds and doesn't support optional
14 * protocol feature like 10-bit addresses or clock stretching.
15 *
16 * Timings and protocol are based Rev. 6 of the I2C specification:
17 * http://www.nxp.com/documents/user_manual/UM10204.pdf
18 */
19
20 #include <errno.h>
21 #include <zephyr/kernel.h>
22 #include <zephyr/drivers/i2c.h>
23 #include "i2c_bitbang.h"
24
25 /*
26 * Indexes into delay table for each part of I2C timing waveform we are
27 * interested in. In practice, for Standard and Fast modes, there are only two
28 * different numerical values (T_LOW and T_HIGH) so we alias the others to
29 * these. (Actually, we're simplifying a little, T_SU_STA could be T_HIGH on
30 * Fast mode)
31 */
32 #define T_LOW 0
33 #define T_HIGH 1
34 #define T_SU_STA T_LOW
35 #define T_HD_STA T_HIGH
36 #define T_SU_STP T_HIGH
37 #define T_BUF T_LOW
38
39 #define NS_TO_SYS_CLOCK_HW_CYCLES(ns) \
40 ((uint64_t)sys_clock_hw_cycles_per_sec() * (ns) / NSEC_PER_SEC + 1)
41
i2c_bitbang_configure(struct i2c_bitbang * context,uint32_t dev_config)42 int i2c_bitbang_configure(struct i2c_bitbang *context, uint32_t dev_config)
43 {
44 /* Check for features we don't support */
45 if (I2C_ADDR_10_BITS & dev_config) {
46 return -ENOTSUP;
47 }
48
49 /* Setup speed to use */
50 switch (I2C_SPEED_GET(dev_config)) {
51 case I2C_SPEED_STANDARD:
52 context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(4700);
53 context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(4000);
54 break;
55 case I2C_SPEED_FAST:
56 context->delays[T_LOW] = NS_TO_SYS_CLOCK_HW_CYCLES(1300);
57 context->delays[T_HIGH] = NS_TO_SYS_CLOCK_HW_CYCLES(600);
58 break;
59 default:
60 return -ENOTSUP;
61 }
62
63 return 0;
64 }
65
i2c_set_scl(struct i2c_bitbang * context,int state)66 static void i2c_set_scl(struct i2c_bitbang *context, int state)
67 {
68 context->io->set_scl(context->io_context, state);
69 }
70
i2c_set_sda(struct i2c_bitbang * context,int state)71 static void i2c_set_sda(struct i2c_bitbang *context, int state)
72 {
73 context->io->set_sda(context->io_context, state);
74 }
75
i2c_get_sda(struct i2c_bitbang * context)76 static int i2c_get_sda(struct i2c_bitbang *context)
77 {
78 return context->io->get_sda(context->io_context);
79 }
80
i2c_delay(unsigned int cycles_to_wait)81 static void i2c_delay(unsigned int cycles_to_wait)
82 {
83 uint32_t start = k_cycle_get_32();
84
85 /* Wait until the given number of cycles have passed */
86 while (k_cycle_get_32() - start < cycles_to_wait) {
87 }
88 }
89
i2c_start(struct i2c_bitbang * context)90 static void i2c_start(struct i2c_bitbang *context)
91 {
92 if (!i2c_get_sda(context)) {
93 /*
94 * SDA is already low, so we need to do something to make it
95 * high. Try pulsing clock low to get slave to release SDA.
96 */
97 i2c_set_scl(context, 0);
98 i2c_delay(context->delays[T_LOW]);
99 i2c_set_scl(context, 1);
100 i2c_delay(context->delays[T_SU_STA]);
101 }
102 i2c_set_sda(context, 0);
103 i2c_delay(context->delays[T_HD_STA]);
104
105 i2c_set_scl(context, 0);
106 i2c_delay(context->delays[T_LOW]);
107 }
108
i2c_repeated_start(struct i2c_bitbang * context)109 static void i2c_repeated_start(struct i2c_bitbang *context)
110 {
111 i2c_set_sda(context, 1);
112 i2c_set_scl(context, 1);
113 i2c_delay(context->delays[T_HIGH]);
114
115 i2c_delay(context->delays[T_SU_STA]);
116 i2c_start(context);
117 }
118
i2c_stop(struct i2c_bitbang * context)119 static void i2c_stop(struct i2c_bitbang *context)
120 {
121 i2c_set_sda(context, 0);
122 i2c_delay(context->delays[T_LOW]);
123
124 i2c_set_scl(context, 1);
125 i2c_delay(context->delays[T_HIGH]);
126
127 i2c_delay(context->delays[T_SU_STP]);
128 i2c_set_sda(context, 1);
129 i2c_delay(context->delays[T_BUF]); /* In case we start again too soon */
130 }
131
i2c_write_bit(struct i2c_bitbang * context,int bit)132 static void i2c_write_bit(struct i2c_bitbang *context, int bit)
133 {
134 /* SDA hold time is zero, so no need for a delay here */
135 i2c_set_sda(context, bit);
136 i2c_set_scl(context, 1);
137 i2c_delay(context->delays[T_HIGH]);
138 i2c_set_scl(context, 0);
139 i2c_delay(context->delays[T_LOW]);
140 }
141
i2c_read_bit(struct i2c_bitbang * context)142 static bool i2c_read_bit(struct i2c_bitbang *context)
143 {
144 bool bit;
145
146 /* SDA hold time is zero, so no need for a delay here */
147 i2c_set_sda(context, 1); /* Stop driving low, so slave has control */
148
149 i2c_set_scl(context, 1);
150 i2c_delay(context->delays[T_HIGH]);
151
152 bit = i2c_get_sda(context);
153
154 i2c_set_scl(context, 0);
155 i2c_delay(context->delays[T_LOW]);
156 return bit;
157 }
158
i2c_write_byte(struct i2c_bitbang * context,uint8_t byte)159 static bool i2c_write_byte(struct i2c_bitbang *context, uint8_t byte)
160 {
161 uint8_t mask = 1 << 7;
162
163 do {
164 i2c_write_bit(context, byte & mask);
165 } while (mask >>= 1);
166
167 /* Return inverted ACK bit, i.e. 'true' for ACK, 'false' for NACK */
168 return !i2c_read_bit(context);
169 }
170
i2c_read_byte(struct i2c_bitbang * context)171 static uint8_t i2c_read_byte(struct i2c_bitbang *context)
172 {
173 unsigned int byte = 1U;
174
175 do {
176 byte <<= 1;
177 byte |= i2c_read_bit(context);
178 } while (!(byte & (1 << 8)));
179
180 return byte;
181 }
182
i2c_bitbang_transfer(struct i2c_bitbang * context,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t slave_address)183 int i2c_bitbang_transfer(struct i2c_bitbang *context,
184 struct i2c_msg *msgs, uint8_t num_msgs,
185 uint16_t slave_address)
186 {
187 uint8_t *buf, *buf_end;
188 unsigned int flags;
189 int result = -EIO;
190
191 if (!num_msgs) {
192 return 0;
193 }
194
195 /* We want an initial Start condition */
196 flags = I2C_MSG_RESTART;
197
198 /* Make sure we're in a good state so slave recognises the Start */
199 i2c_set_scl(context, 1);
200 flags |= I2C_MSG_STOP;
201
202 do {
203 /* Stop flag from previous message? */
204 if (flags & I2C_MSG_STOP) {
205 i2c_stop(context);
206 }
207
208 /* Forget old flags except start flag */
209 flags &= I2C_MSG_RESTART;
210
211 /* Start condition? */
212 if (flags & I2C_MSG_RESTART) {
213 i2c_start(context);
214 } else if (msgs->flags & I2C_MSG_RESTART) {
215 i2c_repeated_start(context);
216 }
217
218 /* Get flags for new message */
219 flags |= msgs->flags;
220
221 /* Send address after any Start condition */
222 if (flags & I2C_MSG_RESTART) {
223 unsigned int byte0 = slave_address << 1;
224
225 byte0 |= (flags & I2C_MSG_RW_MASK) == I2C_MSG_READ;
226 if (!i2c_write_byte(context, byte0)) {
227 goto finish; /* No ACK received */
228 }
229 flags &= ~I2C_MSG_RESTART;
230 }
231
232 /* Transfer data */
233 buf = msgs->buf;
234 buf_end = buf + msgs->len;
235 if ((flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
236 /* Read */
237 while (buf < buf_end) {
238 *buf++ = i2c_read_byte(context);
239 /* ACK the byte, except for the last one */
240 i2c_write_bit(context, buf == buf_end);
241 }
242 } else {
243 /* Write */
244 while (buf < buf_end) {
245 if (!i2c_write_byte(context, *buf++)) {
246 goto finish; /* No ACK received */
247 }
248 }
249 }
250
251 /* Next message */
252 msgs++;
253 num_msgs--;
254 } while (num_msgs);
255
256 /* Complete without error */
257 result = 0;
258 finish:
259 i2c_stop(context);
260
261 return result;
262 }
263
i2c_bitbang_recover_bus(struct i2c_bitbang * context)264 int i2c_bitbang_recover_bus(struct i2c_bitbang *context)
265 {
266 int i;
267
268 /*
269 * The I2C-bus specification and user manual (NXP UM10204
270 * rev. 6, section 3.1.16) suggests the master emit 9 SCL
271 * clock pulses to recover the bus.
272 *
273 * The Linux kernel I2C bitbang recovery functionality issues
274 * a START condition followed by 9 STOP conditions.
275 *
276 * Other I2C slave devices (e.g. Microchip ATSHA204a) suggest
277 * issuing a START condition followed by 9 SCL clock pulses
278 * with SDA held high/floating, a REPEATED START condition,
279 * and a STOP condition.
280 *
281 * The latter is what is implemented here.
282 */
283
284 /* Start condition */
285 i2c_start(context);
286
287 /* 9 cycles of SCL with SDA held high */
288 for (i = 0; i < 9; i++) {
289 i2c_write_bit(context, 1);
290 }
291
292 /* Another start condition followed by a stop condition */
293 i2c_repeated_start(context);
294 i2c_stop(context);
295
296 /* Check if bus is clear */
297 if (i2c_get_sda(context)) {
298 return 0;
299 } else {
300 return -EBUSY;
301 }
302 }
303
i2c_bitbang_init(struct i2c_bitbang * context,const struct i2c_bitbang_io * io,void * io_context)304 void i2c_bitbang_init(struct i2c_bitbang *context,
305 const struct i2c_bitbang_io *io, void *io_context)
306 {
307 context->io = io;
308 context->io_context = io_context;
309 i2c_bitbang_configure(context, I2C_SPEED_STANDARD << I2C_SPEED_SHIFT);
310 }
311
