1 /*
2 * Copyright (c) 2023 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stddef.h>
8 #include <stdint.h>
9 #include "bs_tracing.h"
10 #include "NHW_config.h"
11 #include "NHW_peri_types.h"
12 #include "NHW_virt_RAM.h"
13 #include "nrf_bsim_redef.h"
14
15 /*
16 * Get the name of a core/domain
17 *
18 * Only for debugging/logging/tracing purposes.
19 */
nhw_get_core_name(unsigned int core_n)20 const char *nhw_get_core_name(unsigned int core_n)
21 {
22 static const char *corenames[NHW_INTCTRL_TOTAL_INST] = NHW_CORE_NAMES;
23
24 if (core_n < sizeof(corenames)/sizeof(corenames[0])) {
25 return corenames[core_n];
26 } else {
27 return NULL;
28 }
29 }
30
31 /*
32 * Convert an address to the real embedded device RAM into an addresses
33 * in the models buffer which is used in place of the RAM.
34 * Note the input is a pointer to the pointer/address, which will be modified in the call.
35 *
36 * This function will only modify the address if it was inside an embedded RAM known to it.
37 * In that case it returns true.
38 * Otherwise the address is unmodified and false is returned.
39 */
nhw_convert_RAM_addr(void ** addr)40 bool nhw_convert_RAM_addr(void **addr)
41 {
42 #if defined(NRF5340) || defined(NRF5340_XXAA_NETWORK) || defined(NRF5340_XXAA_APPLICATION)
43 if (((intptr_t)*addr >= NHW_APPCORE_RAM_ADDR) && ((intptr_t)*addr < (intptr_t)*addr + NHW_APPCORE_RAM_SIZE)) {
44 *addr = (intptr_t)*addr - NHW_APPCORE_RAM_ADDR + NHW_appcore_RAM;
45 return true;
46 }
47 #else
48 (void) addr;
49 bs_trace_warning_time_line("%s not supported yet in this device\n", __func__);
50 #endif
51 return false;
52 }
53
54 /**
55 * Convert a real peripheral base address (like 0x4000F000UL)
56 * into the corresponding simulation peripheral base address
57 *
58 * Note: In general it is recommended to refer to peripherals
59 * using the MDK macros (like NRF_TIMER0), this function
60 * exists to cover the cases in which this is not possible.
61 */
nhw_convert_periph_base_addr(void * hw_addr)62 void *nhw_convert_periph_base_addr(void *hw_addr) {
63
64 #if defined(NRF5340)
65 /* The nrf_bsim_redef.h header which is meant to hack the
66 * nrf definitions only provides declarations for the
67 * registers structures for a given core. So we need to declare
68 * the ones that are exclusive for either core here.
69 *
70 * If at some point we have more uses for a bulk peripheral definitions
71 * of all peripherals in a SOC consider moving it to a separate header
72 */
73 extern NRF_AAR_Type NRF_AAR_regs;
74 extern NRF_CCM_Type NRF_CCM_regs;
75 extern NRF_ECB_Type NRF_ECB_regs;
76 extern NRF_RADIO_Type NRF_RADIO_regs;
77 extern NRF_RNG_Type NRF_RNG_regs;
78 extern int NRF_SWI_regs[];
79 extern NRF_TEMP_Type NRF_TEMP_regs;
80 extern NRF_VREQCTRL_Type NRF_VREQCTRL_regs;
81 #endif
82
83 struct {
84 void* simu_addr;
85 uint32_t real_add;
86 } conv_table[] = {
87 #if defined(NRF52833)
88 {(void *)NRF_FICR_BASE , 0x10000000UL},
89 {(void *)NRF_UICR_BASE , 0x10001000UL},
90 // {(void *)NRF_APPROTECT_BASE , 0x40000000UL},
91 {(void *)NRF_CLOCK_BASE , 0x40000000UL},
92 {(void *)NRF_POWER_BASE , 0x40000000UL},
93 {(void *)NRF_P0_BASE , 0x50000000UL},
94 {(void *)NRF_P1_BASE , 0x50000300UL},
95 {(void *)NRF_RADIO_BASE , 0x40001000UL},
96 {(void *)NRF_UART0_BASE , 0x40002000UL},
97 {(void *)NRF_UARTE0_BASE , 0x40002000UL},
98 // {(void *)NRF_SPI0_BASE , 0x40003000UL},
99 // {(void *)NRF_SPIM0_BASE , 0x40003000UL},
100 // {(void *)NRF_SPIS0_BASE , 0x40003000UL},
101 // {(void *)NRF_TWI0_BASE , 0x40003000UL},
102 // {(void *)NRF_TWIM0_BASE , 0x40003000UL},
103 // {(void *)NRF_TWIS0_BASE , 0x40003000UL},
104 // {(void *)NRF_SPI1_BASE , 0x40004000UL},
105 // {(void *)NRF_SPIM1_BASE , 0x40004000UL},
106 // {(void *)NRF_SPIS1_BASE , 0x40004000UL},
107 // {(void *)NRF_TWI1_BASE , 0x40004000UL},
108 // {(void *)NRF_TWIM1_BASE , 0x40004000UL},
109 // {(void *)NRF_TWIS1_BASE , 0x40004000UL},
110 // {(void *)NRF_NFCT_BASE , 0x40005000UL},
111 {(void *)NRF_GPIOTE_BASE , 0x40006000UL},
112 // {(void *)NRF_SAADC_BASE , 0x40007000UL},
113 {(void *)NRF_TIMER0_BASE , 0x40008000UL},
114 {(void *)NRF_TIMER1_BASE , 0x40009000UL},
115 {(void *)NRF_TIMER2_BASE , 0x4000A000UL},
116 {(void *)NRF_RTC0_BASE , 0x4000B000UL},
117 {(void *)NRF_TEMP_BASE , 0x4000C000UL},
118 {(void *)NRF_RNG_BASE , 0x4000D000UL},
119 {(void *)NRF_ECB_BASE , 0x4000E000UL},
120 {(void *)NRF_AAR_BASE , 0x4000F000UL},
121 {(void *)NRF_CCM_BASE , 0x4000F000UL},
122 // {(void *)NRF_WDT_BASE , 0x40010000UL},
123 {(void *)NRF_RTC1_BASE , 0x40011000UL},
124 // {(void *)NRF_QDEC_BASE , 0x40012000UL},
125 // {(void *)NRF_COMP_BASE , 0x40013000UL},
126 // {(void *)NRF_LPCOMP_BASE , 0x40013000UL},
127 {(void *)NRF_EGU0_BASE , 0x40014000UL},
128 // {(void *)NRF_SWI0_BASE , 0x40014000UL},
129 {(void *)NRF_EGU1_BASE , 0x40015000UL},
130 // {(void *)NRF_SWI1_BASE , 0x40015000UL},
131 {(void *)NRF_EGU2_BASE , 0x40016000UL},
132 // {(void *)NRF_SWI2_BASE , 0x40016000UL},
133 {(void *)NRF_EGU3_BASE , 0x40017000UL},
134 // {(void *)NRF_SWI3_BASE , 0x40017000UL},
135 {(void *)NRF_EGU4_BASE , 0x40018000UL},
136 // {(void *)NRF_SWI4_BASE , 0x40018000UL},
137 {(void *)NRF_EGU5_BASE , 0x40019000UL},
138 // {(void *)NRF_SWI5_BASE , 0x40019000UL},
139 {(void *)NRF_TIMER3_BASE , 0x4001A000UL},
140 {(void *)NRF_TIMER4_BASE , 0x4001B000UL},
141 // {(void *)NRF_PWM0_BASE , 0x4001C000UL},
142 // {(void *)NRF_PDM_BASE , 0x4001D000UL},
143 // {(void *)NRF_ACL_BASE , 0x4001E000UL},
144 {(void *)NRF_NVMC_BASE , 0x4001E000UL},
145 {(void *)NRF_PPI_BASE , 0x4001F000UL},
146 // {(void *)NRF_MWU_BASE , 0x40020000UL},
147 // {(void *)NRF_PWM1_BASE , 0x40021000UL},
148 // {(void *)NRF_PWM2_BASE , 0x40022000UL},
149 // {(void *)NRF_SPI2_BASE , 0x40023000UL},
150 // {(void *)NRF_SPIM2_BASE , 0x40023000UL},
151 // {(void *)NRF_SPIS2_BASE , 0x40023000UL},
152 {(void *)NRF_RTC2_BASE , 0x40024000UL},
153 // {(void *)NRF_I2S_BASE , 0x40025000UL},
154 // {(void *)NRF_FPU_BASE , 0x40026000UL},
155 // {(void *)NRF_USBD_BASE , 0x40027000UL},
156 {(void *)NRF_UARTE1_BASE , 0x40028000UL},
157 // {(void *)NRF_PWM3_BASE , 0x4002D000UL},
158 // {(void *)NRF_SPIM3_BASE , 0x4002F000UL},
159 #elif defined(NRF5340)
160 /*Application core */
161 //{(void *)NRF_CACHEDATA_S_BASE ,0x00F00000UL},
162 //{(void *)NRF_CACHEINFO_S_BASE ,0x00F08000UL},
163 {(void *)(NRF_FICR_regs_p[NHW_FICR_APP]) ,0x00FF0000UL},
164 {(void *)(NRF_UICR_regs_p[NHW_UICR_APP0]) ,0x00FF8000UL},
165 //{(void *)NRF_CTI_S_BASE ,0xE0042000UL},
166 //{(void *)NRF_TAD_S_BASE ,0xE0080000UL},
167 //{(void *)NRF_DCNF_NS_BASE ,0x40000000UL},
168 //{(void *)NRF_FPU_NS_BASE ,0x40000000UL},
169 //{(void *)NRF_DCNF_S_BASE ,0x50000000UL},
170 //{(void *)NRF_FPU_S_BASE ,0x50000000UL},
171 //{(void *)NRF_CACHE_S_BASE ,0x50001000UL},
172 //{(void *)NRF_SPU_S_BASE ,0x50003000UL},
173 //{(void *)NRF_OSCILLATORS_NS_BASE ,0x40004000UL},
174 //{(void *)NRF_REGULATORS_NS_BASE ,0x40004000UL},
175 //{(void *)NRF_OSCILLATORS_S_BASE ,0x50004000UL},
176 //{(void *)NRF_REGULATORS_S_BASE ,0x50004000UL},
177 {(void *)(NRF_CLOCK_regs[NHW_CLKPWR_APP0]) ,0x40005000UL},
178 {(void *)(NRF_POWER_regs[NHW_CLKPWR_APP0]) ,0x40005000UL},
179 {(void *)(NRF_RESET_regs[NHW_CLKPWR_APP0]) ,0x40005000UL},
180 {(void *)(NRF_CLOCK_regs[NHW_CLKPWR_APP0]) ,0x50005000UL},
181 {(void *)(NRF_POWER_regs[NHW_CLKPWR_APP0]) ,0x50005000UL},
182 {(void *)(NRF_RESET_regs[NHW_CLKPWR_APP0]) ,0x50005000UL},
183 //{(void *)NRF_CTRLAP_NS_BASE ,0x40006000UL},
184 //{(void *)NRF_CTRLAP_S_BASE ,0x50006000UL},
185 //{(void *)NRF_SPIM0_NS_BASE ,0x40008000UL},
186 //{(void *)NRF_SPIS0_NS_BASE ,0x40008000UL},
187 //{(void *)NRF_TWIM0_NS_BASE ,0x40008000UL},
188 //{(void *)NRF_TWIS0_NS_BASE ,0x40008000UL},
189 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP0]) ,0x40008000UL},
190 //{(void *)NRF_SPIM0_S_BASE ,0x50008000UL},
191 //{(void *)NRF_SPIS0_S_BASE ,0x50008000UL},
192 //{(void *)NRF_TWIM0_S_BASE ,0x50008000UL},
193 //{(void *)NRF_TWIS0_S_BASE ,0x50008000UL},
194 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP0]) ,0x50008000UL},
195 //{(void *)NRF_SPIM1_NS_BASE ,0x40009000UL},
196 //{(void *)NRF_SPIS1_NS_BASE ,0x40009000UL},
197 //{(void *)NRF_TWIM1_NS_BASE ,0x40009000UL},
198 //{(void *)NRF_TWIS1_NS_BASE ,0x40009000UL},
199 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP1]) ,0x40009000UL},
200 //{(void *)NRF_SPIM1_S_BASE ,0x50009000UL},
201 //{(void *)NRF_SPIS1_S_BASE ,0x50009000UL},
202 //{(void *)NRF_TWIM1_S_BASE ,0x50009000UL},
203 //{(void *)NRF_TWIS1_S_BASE ,0x50009000UL},
204 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP1]) ,0x50009000UL},
205 //{(void *)NRF_SPIM4_NS_BASE ,0x4000A000UL},
206 //{(void *)NRF_SPIM4_S_BASE ,0x5000A000UL},
207 //{(void *)NRF_SPIM2_NS_BASE ,0x4000B000UL},
208 //{(void *)NRF_SPIS2_NS_BASE ,0x4000B000UL},
209 //{(void *)NRF_TWIM2_NS_BASE ,0x4000B000UL},
210 //{(void *)NRF_TWIS2_NS_BASE ,0x4000B000UL},
211 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP2]) ,0x4000B000UL},
212 //{(void *)NRF_SPIM2_S_BASE ,0x5000B000UL},
213 //{(void *)NRF_SPIS2_S_BASE ,0x5000B000UL},
214 //{(void *)NRF_TWIM2_S_BASE ,0x5000B000UL},
215 //{(void *)NRF_TWIS2_S_BASE ,0x5000B000UL},
216 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP2]) ,0x5000B000UL},
217 //{(void *)NRF_SPIM3_NS_BASE ,0x4000C000UL},
218 //{(void *)NRF_SPIS3_NS_BASE ,0x4000C000UL},
219 //{(void *)NRF_TWIM3_NS_BASE ,0x4000C000UL},
220 //{(void *)NRF_TWIS3_NS_BASE ,0x4000C000UL},
221 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP3]) ,0x4000C000UL},
222 //{(void *)NRF_SPIM3_S_BASE ,0x5000C000UL},
223 //{(void *)NRF_SPIS3_S_BASE ,0x5000C000UL},
224 //{(void *)NRF_TWIM3_S_BASE ,0x5000C000UL},
225 //{(void *)NRF_TWIS3_S_BASE ,0x5000C000UL},
226 {(void *)(&NRF_UARTE_regs[NHW_UARTE_APP3]) ,0x5000C000UL},
227 //{(void *)NRF_GPIOTE0_S_BASE ,0x5000D000UL},
228 //{(void *)NRF_SAADC_NS_BASE ,0x4000E000UL},
229 //{(void *)NRF_SAADC_S_BASE ,0x5000E000UL},
230 {(void *)(&NRF_TIMER_regs[NHW_TIMER_APP0]) ,0x4000F000UL},
231 {(void *)(&NRF_TIMER_regs[NHW_TIMER_APP0]) ,0x5000F000UL},
232 {(void *)(&NRF_TIMER_regs[NHW_TIMER_APP1]) ,0x40010000UL},
233 {(void *)(&NRF_TIMER_regs[NHW_TIMER_APP1]) ,0x50010000UL},
234 {(void *)(&NRF_TIMER_regs[NHW_TIMER_APP2]) ,0x40011000UL},
235 {(void *)(&NRF_TIMER_regs[NHW_TIMER_APP2]) ,0x50011000UL},
236 {(void *)(&NRF_RTC_regs[NHW_RTC_APP0]) ,0x40014000UL},
237 {(void *)(&NRF_RTC_regs[NHW_RTC_APP0]) ,0x50014000UL},
238 {(void *)(&NRF_RTC_regs[NHW_RTC_APP1]) ,0x40015000UL},
239 {(void *)(&NRF_RTC_regs[NHW_RTC_APP1]) ,0x50015000UL},
240 {(void *)(&NRF_DPPIC_regs[NHW_DPPI_APP_0]) ,0x40017000UL},
241 {(void *)(&NRF_DPPIC_regs[NHW_DPPI_APP_0]) ,0x50017000UL},
242 //{(void *)NRF_WDT0_NS_BASE ,0x40018000UL},
243 //{(void *)NRF_WDT0_S_BASE ,0x50018000UL},
244 //{(void *)NRF_WDT1_NS_BASE ,0x40019000UL},
245 //{(void *)NRF_WDT1_S_BASE ,0x50019000UL},
246 //{(void *)NRF_COMP_NS_BASE ,0x4001A000UL},
247 //{(void *)NRF_LPCOMP_NS_BASE ,0x4001A000UL},
248 //{(void *)NRF_COMP_S_BASE ,0x5001A000UL},
249 //{(void *)NRF_LPCOMP_S_BASE ,0x5001A000UL},
250 {(void *)(&NRF_EGU_regs[NHW_EGU_APP0]) ,0x4001B000UL},
251 {(void *)(&NRF_EGU_regs[NHW_EGU_APP0]) ,0x5001B000UL},
252 {(void *)(&NRF_EGU_regs[NHW_EGU_APP1]) ,0x4001C000UL},
253 {(void *)(&NRF_EGU_regs[NHW_EGU_APP1]) ,0x5001C000UL},
254 {(void *)(&NRF_EGU_regs[NHW_EGU_APP2]) ,0x4001D000UL},
255 {(void *)(&NRF_EGU_regs[NHW_EGU_APP2]) ,0x5001D000UL},
256 {(void *)(&NRF_EGU_regs[NHW_EGU_APP3]) ,0x4001E000UL},
257 {(void *)(&NRF_EGU_regs[NHW_EGU_APP3]) ,0x5001E000UL},
258 {(void *)(&NRF_EGU_regs[NHW_EGU_APP4]) ,0x4001F000UL},
259 {(void *)(&NRF_EGU_regs[NHW_EGU_APP4]) ,0x5001F000UL},
260 {(void *)(&NRF_EGU_regs[NHW_EGU_APP5]) ,0x40020000UL},
261 {(void *)(&NRF_EGU_regs[NHW_EGU_APP5]) ,0x50020000UL},
262 //{(void *)NRF_PWM0_NS_BASE ,0x40021000UL},
263 //{(void *)NRF_PWM0_S_BASE ,0x50021000UL},
264 //{(void *)NRF_PWM1_NS_BASE ,0x40022000UL},
265 //{(void *)NRF_PWM1_S_BASE ,0x50022000UL},
266 //{(void *)NRF_PWM2_NS_BASE ,0x40023000UL},
267 //{(void *)NRF_PWM2_S_BASE ,0x50023000UL},
268 //{(void *)NRF_PWM3_NS_BASE ,0x40024000UL},
269 //{(void *)NRF_PWM3_S_BASE ,0x50024000UL},
270 //{(void *)NRF_PDM0_NS_BASE ,0x40026000UL},
271 //{(void *)NRF_PDM0_S_BASE ,0x50026000UL},
272 //{(void *)NRF_I2S0_NS_BASE ,0x40028000UL},
273 //{(void *)NRF_I2S0_S_BASE ,0x50028000UL},
274 {(void *)(&NRF_IPC_regs[NHW_IPC_APP0]) ,0x4002A000UL},
275 {(void *)(&NRF_IPC_regs[NHW_IPC_APP0]) ,0x5002A000UL},
276 //{(void *)NRF_QSPI_NS_BASE ,0x4002B000UL},
277 //{(void *)NRF_QSPI_S_BASE ,0x5002B000UL},
278 //{(void *)NRF_NFCT_NS_BASE ,0x4002D000UL},
279 //{(void *)NRF_NFCT_S_BASE ,0x5002D000UL},
280 //{(void *)NRF_GPIOTE1_NS_BASE ,0x4002F000UL},
281 {(void *)(&NRF_MUTEX_regs) ,0x40030000UL},
282 {(void *)(&NRF_MUTEX_regs) ,0x50030000UL},
283 //{(void *)NRF_QDEC0_NS_BASE ,0x40033000UL},
284 //{(void *)NRF_QDEC0_S_BASE ,0x50033000UL},
285 //{(void *)NRF_QDEC1_NS_BASE ,0x40034000UL},
286 //{(void *)NRF_QDEC1_S_BASE ,0x50034000UL},
287 //{(void *)NRF_USBD_NS_BASE ,0x40036000UL},
288 //{(void *)NRF_USBD_S_BASE ,0x50036000UL},
289 //{(void *)NRF_USBREGULATOR_NS_BASE,0x40037000UL},
290 //{(void *)NRF_USBREGULATOR_S_BASE ,0x50037000UL},
291 //{(void *)NRF_KMU_NS_BASE ,0x40039000UL},
292 {(void *)(NRF_NVMC_regs_p[NHW_NVMC_APP0]) ,0x40039000UL},
293 //{(void *)NRF_KMU_S_BASE ,0x50039000UL},
294 {(void *)(NRF_NVMC_regs_p[NHW_NVMC_APP0]) ,0x50039000UL},
295 //{(void *)NRF_P0_NS_BASE ,0x40842500UL},
296 //{(void *)NRF_P1_NS_BASE ,0x40842800UL},
297 //{(void *)NRF_P0_S_BASE ,0x50842500UL},
298 //{(void *)NRF_P1_S_BASE ,0x50842800UL},
299 //{(void *)NRF_CRYPTOCELL_S_BASE ,0x50844000UL},
300 //{(void *)NRF_VMC_NS_BASE ,0x40081000UL},
301 //{(void *)NRF_VMC_S_BASE ,0x50081000UL},
302 /* Network core: */
303 {(void *)(NRF_FICR_regs_p[NHW_FICR_NET]) ,0x01FF0000UL},
304 {(void *)(NRF_UICR_regs_p[NHW_UICR_NET0]) ,0x01FF8000UL},
305 //{(void *)NRF_CTI_NS_BASE ,0xE0042000UL},
306 //{(void *)NRF_DCNF_NS_BASE ,0x41000000UL},
307 {(void *)(&NRF_VREQCTRL_regs) ,0x41004000UL},
308 {(void *)(NRF_CLOCK_regs[NHW_CLKPWR_NET0]) ,0x41005000UL},
309 {(void *)(NRF_POWER_regs[NHW_CLKPWR_NET0]) ,0x41005000UL},
310 {(void *)(NRF_RESET_regs[NHW_CLKPWR_NET0]) ,0x41005000UL},
311 //{(void *)NRF_CTRLAP_NS_BASE ,0x41006000UL},
312 {(void *)(&NRF_RADIO_regs) ,0x41008000UL},
313 {(void *)(&NRF_RNG_regs) ,0x41009000UL},
314 //{(void *)NRF_GPIOTE_NS_BASE ,0x4100A000UL},
315 //{(void *)NRF_WDT_NS_BASE ,0x4100B000UL},
316 {(void *)(&NRF_TIMER_regs[NHW_TIMER_NET0]) ,0x4100C000UL},
317 {(void *)(&NRF_ECB_regs) ,0x4100D000UL},
318 {(void *)(&NRF_AAR_regs) ,0x4100E000UL},
319 {(void *)(&NRF_CCM_regs) ,0x4100E000UL},
320 {(void *)(&NRF_DPPIC_regs[NHW_DPPI_NET_0]) ,0x4100F000UL},
321 {(void *)(&NRF_TEMP_regs) ,0x41010000UL},
322 {(void *)(&NRF_RTC_regs[NHW_RTC_NET0]) ,0x41011000UL},
323 {(void *)(&NRF_IPC_regs[NHW_IPC_NET0]) ,0x41012000UL},
324 //{(void *)NRF_SPIM0_NS_BASE ,0x41013000UL},
325 //{(void *)NRF_SPIS0_NS_BASE ,0x41013000UL},
326 //{(void *)NRF_TWIM0_NS_BASE ,0x41013000UL},
327 //{(void *)NRF_TWIS0_NS_BASE ,0x41013000UL},
328 {(void *)(&NRF_UARTE_regs[NHW_UARTE_NET0]) ,0x41013000UL},
329 {(void *)(&NRF_EGU_regs[NHW_EGU_NET0]) ,0x41014000UL},
330 {(void *)(&NRF_RTC_regs[NHW_RTC_NET1]) ,0x41016000UL},
331 {(void *)(&NRF_TIMER_regs[NHW_TIMER_NET1]) ,0x41018000UL},
332 {(void *)(&NRF_TIMER_regs[NHW_TIMER_NET2]) ,0x41019000UL},
333 {(void *)(&NRF_SWI_regs[NHW_SWI_NET0]) ,0x4101A000UL},
334 {(void *)(&NRF_SWI_regs[NHW_SWI_NET1]) ,0x4101B000UL},
335 {(void *)(&NRF_SWI_regs[NHW_SWI_NET2]) ,0x4101C000UL},
336 {(void *)(&NRF_SWI_regs[NHW_SWI_NET3]) ,0x4101D000UL},
337 {(void *)(&NRF_MUTEX_regs) ,0x40030000UL},
338 {(void *)(&NRF_MUTEX_regs) ,0x50030000UL},
339 //{(void *)NRF_ACL_NS_BASE ,0x41080000UL},
340 {(void *)(NRF_NVMC_regs_p[NHW_NVMC_NET0]) ,0x41080000UL},
341 //{(void *)NRF_VMC_NS_BASE ,0x41081000UL},
342 //{(void *)NRF_P0_NS_BASE ,0x418C0500UL},
343 //{(void *)NRF_P1_NS_BASE ,0x418C0800UL},
344 #elif defined(NRF54L15)
345 {(void*)NRF_FICR_NS_BASE , 0x00FFC000UL},
346 {(void*)NRF_UICR_S_BASE , 0x00FFD000UL},
347 {(void*)NRF_SICR_S_BASE , 0x00FFE000UL},
348 {(void*)NRF_CRACENCORE_S_BASE , 0x51800000UL},
349 {(void*)NRF_SPU00_S_BASE , 0x50040000UL},
350 {(void*)NRF_MPC00_S_BASE , 0x50041000UL},
351 {(void*)NRF_DPPIC00_NS_BASE , 0x40042000UL},
352 {(void*)NRF_DPPIC00_S_BASE , 0x50042000UL},
353 {(void*)NRF_PPIB00_NS_BASE , 0x40043000UL},
354 {(void*)NRF_PPIB00_S_BASE , 0x50043000UL},
355 {(void*)NRF_PPIB01_NS_BASE , 0x40044000UL},
356 {(void*)NRF_PPIB01_S_BASE , 0x50044000UL},
357 {(void*)NRF_KMU_S_BASE , 0x50045000UL},
358 {(void*)NRF_AAR00_NS_BASE , 0x40046000UL},
359 {(void*)NRF_CCM00_NS_BASE , 0x40046000UL},
360 {(void*)NRF_AAR00_S_BASE , 0x50046000UL},
361 {(void*)NRF_CCM00_S_BASE , 0x50046000UL},
362 {(void*)NRF_ECB00_NS_BASE , 0x40047000UL},
363 {(void*)NRF_ECB00_S_BASE , 0x50047000UL},
364 {(void*)NRF_CRACEN_S_BASE , 0x50048000UL},
365 {(void*)NRF_SPIM00_NS_BASE , 0x4004A000UL},
366 {(void*)NRF_SPIS00_NS_BASE , 0x4004A000UL},
367 {(void*)NRF_UARTE00_NS_BASE , 0x4004A000UL},
368 {(void*)NRF_SPIM00_S_BASE , 0x5004A000UL},
369 {(void*)NRF_SPIS00_S_BASE , 0x5004A000UL},
370 {(void*)NRF_UARTE00_S_BASE , 0x5004A000UL},
371 {(void*)NRF_GLITCHDET_S_BASE , 0x5004B000UL},
372 {(void*)NRF_RRAMC_S_BASE , 0x5004B000UL},
373 {(void*)NRF_VPR00_NS_BASE , 0x4004C000UL},
374 {(void*)NRF_VPR00_S_BASE , 0x5004C000UL},
375 {(void*)NRF_P2_NS_BASE , 0x40050400UL},
376 {(void*)NRF_P2_S_BASE , 0x50050400UL},
377 {(void*)NRF_CTRLAP_NS_BASE , 0x40052000UL},
378 {(void*)NRF_CTRLAP_S_BASE , 0x50052000UL},
379 {(void*)NRF_TAD_NS_BASE , 0x40053000UL},
380 {(void*)NRF_TAD_S_BASE , 0x50053000UL},
381 {(void*)NRF_TIMER00_NS_BASE , 0x40055000UL},
382 {(void*)NRF_TIMER00_S_BASE , 0x50055000UL},
383 {(void*)NRF_SPU10_S_BASE , 0x50080000UL},
384 {(void*)NRF_DPPIC10_NS_BASE , 0x40082000UL},
385 {(void*)NRF_DPPIC10_S_BASE , 0x50082000UL},
386 {(void*)NRF_PPIB10_NS_BASE , 0x40083000UL},
387 {(void*)NRF_PPIB10_S_BASE , 0x50083000UL},
388 {(void*)NRF_PPIB11_NS_BASE , 0x40084000UL},
389 {(void*)NRF_PPIB11_S_BASE , 0x50084000UL},
390 {(void*)NRF_TIMER10_NS_BASE , 0x40085000UL},
391 {(void*)NRF_TIMER10_S_BASE , 0x50085000UL},
392 {(void*)NRF_EGU10_NS_BASE , 0x40087000UL},
393 {(void*)NRF_EGU10_S_BASE , 0x50087000UL},
394 {(void*)NRF_RADIO_NS_BASE , 0x4008A000UL},
395 {(void*)NRF_RADIO_S_BASE , 0x5008A000UL},
396 {(void*)NRF_SPU20_S_BASE , 0x500C0000UL},
397 {(void*)NRF_DPPIC20_NS_BASE , 0x400C2000UL},
398 {(void*)NRF_DPPIC20_S_BASE , 0x500C2000UL},
399 {(void*)NRF_PPIB20_NS_BASE , 0x400C3000UL},
400 {(void*)NRF_PPIB20_S_BASE , 0x500C3000UL},
401 {(void*)NRF_PPIB21_NS_BASE , 0x400C4000UL},
402 {(void*)NRF_PPIB21_S_BASE , 0x500C4000UL},
403 {(void*)NRF_PPIB22_NS_BASE , 0x400C5000UL},
404 {(void*)NRF_PPIB22_S_BASE , 0x500C5000UL},
405 {(void*)NRF_SPIM20_NS_BASE , 0x400C6000UL},
406 {(void*)NRF_SPIS20_NS_BASE , 0x400C6000UL},
407 {(void*)NRF_TWIM20_NS_BASE , 0x400C6000UL},
408 {(void*)NRF_TWIS20_NS_BASE , 0x400C6000UL},
409 {(void*)NRF_UARTE20_NS_BASE , 0x400C6000UL},
410 {(void*)NRF_SPIM20_S_BASE , 0x500C6000UL},
411 {(void*)NRF_SPIS20_S_BASE , 0x500C6000UL},
412 {(void*)NRF_TWIM20_S_BASE , 0x500C6000UL},
413 {(void*)NRF_TWIS20_S_BASE , 0x500C6000UL},
414 {(void*)NRF_UARTE20_S_BASE , 0x500C6000UL},
415 {(void*)NRF_SPIM21_NS_BASE , 0x400C7000UL},
416 {(void*)NRF_SPIS21_NS_BASE , 0x400C7000UL},
417 {(void*)NRF_TWIM21_NS_BASE , 0x400C7000UL},
418 {(void*)NRF_TWIS21_NS_BASE , 0x400C7000UL},
419 {(void*)NRF_UARTE21_NS_BASE , 0x400C7000UL},
420 {(void*)NRF_SPIM21_S_BASE , 0x500C7000UL},
421 {(void*)NRF_SPIS21_S_BASE , 0x500C7000UL},
422 {(void*)NRF_TWIM21_S_BASE , 0x500C7000UL},
423 {(void*)NRF_TWIS21_S_BASE , 0x500C7000UL},
424 {(void*)NRF_UARTE21_S_BASE , 0x500C7000UL},
425 {(void*)NRF_SPIM22_NS_BASE , 0x400C8000UL},
426 {(void*)NRF_SPIS22_NS_BASE , 0x400C8000UL},
427 {(void*)NRF_TWIM22_NS_BASE , 0x400C8000UL},
428 {(void*)NRF_TWIS22_NS_BASE , 0x400C8000UL},
429 {(void*)NRF_UARTE22_NS_BASE , 0x400C8000UL},
430 {(void*)NRF_SPIM22_S_BASE , 0x500C8000UL},
431 {(void*)NRF_SPIS22_S_BASE , 0x500C8000UL},
432 {(void*)NRF_TWIM22_S_BASE , 0x500C8000UL},
433 {(void*)NRF_TWIS22_S_BASE , 0x500C8000UL},
434 {(void*)NRF_UARTE22_S_BASE , 0x500C8000UL},
435 {(void*)NRF_EGU20_NS_BASE , 0x400C9000UL},
436 {(void*)NRF_EGU20_S_BASE , 0x500C9000UL},
437 {(void*)NRF_TIMER20_NS_BASE , 0x400CA000UL},
438 {(void*)NRF_TIMER20_S_BASE , 0x500CA000UL},
439 {(void*)NRF_TIMER21_NS_BASE , 0x400CB000UL},
440 {(void*)NRF_TIMER21_S_BASE , 0x500CB000UL},
441 {(void*)NRF_TIMER22_NS_BASE , 0x400CC000UL},
442 {(void*)NRF_TIMER22_S_BASE , 0x500CC000UL},
443 {(void*)NRF_TIMER23_NS_BASE , 0x400CD000UL},
444 {(void*)NRF_TIMER23_S_BASE , 0x500CD000UL},
445 {(void*)NRF_TIMER24_NS_BASE , 0x400CE000UL},
446 {(void*)NRF_TIMER24_S_BASE , 0x500CE000UL},
447 {(void*)NRF_MEMCONF_NS_BASE , 0x400CF000UL},
448 {(void*)NRF_MEMCONF_S_BASE , 0x500CF000UL},
449 {(void*)NRF_PDM20_NS_BASE , 0x400D0000UL},
450 {(void*)NRF_PDM20_S_BASE , 0x500D0000UL},
451 {(void*)NRF_PDM21_NS_BASE , 0x400D1000UL},
452 {(void*)NRF_PDM21_S_BASE , 0x500D1000UL},
453 {(void*)NRF_PWM20_NS_BASE , 0x400D2000UL},
454 {(void*)NRF_PWM20_S_BASE , 0x500D2000UL},
455 {(void*)NRF_PWM21_NS_BASE , 0x400D3000UL},
456 {(void*)NRF_PWM21_S_BASE , 0x500D3000UL},
457 {(void*)NRF_PWM22_NS_BASE , 0x400D4000UL},
458 {(void*)NRF_PWM22_S_BASE , 0x500D4000UL},
459 {(void*)NRF_SAADC_NS_BASE , 0x400D5000UL},
460 {(void*)NRF_SAADC_S_BASE , 0x500D5000UL},
461 {(void*)NRF_NFCT_NS_BASE , 0x400D6000UL},
462 {(void*)NRF_NFCT_S_BASE , 0x500D6000UL},
463 {(void*)NRF_TEMP_NS_BASE , 0x400D7000UL},
464 {(void*)NRF_TEMP_S_BASE , 0x500D7000UL},
465 {(void*)NRF_P1_NS_BASE , 0x400D8200UL},
466 {(void*)NRF_P1_S_BASE , 0x500D8200UL},
467 {(void*)NRF_GPIOTE20_NS_BASE , 0x400DA000UL},
468 {(void*)NRF_GPIOTE20_S_BASE , 0x500DA000UL},
469 {(void*)NRF_TAMPC_S_BASE , 0x500DC000UL},
470 {(void*)NRF_I2S20_NS_BASE , 0x400DD000UL},
471 {(void*)NRF_I2S20_S_BASE , 0x500DD000UL},
472 {(void*)NRF_QDEC20_NS_BASE , 0x400E0000UL},
473 {(void*)NRF_QDEC20_S_BASE , 0x500E0000UL},
474 {(void*)NRF_QDEC21_NS_BASE , 0x400E1000UL},
475 {(void*)NRF_QDEC21_S_BASE , 0x500E1000UL},
476 {(void*)NRF_GRTC_NS_BASE , 0x400E2000UL},
477 {(void*)NRF_GRTC_S_BASE , 0x500E2000UL},
478 {(void*)NRF_SPU30_S_BASE , 0x50100000UL},
479 {(void*)NRF_DPPIC30_NS_BASE , 0x40102000UL},
480 {(void*)NRF_DPPIC30_S_BASE , 0x50102000UL},
481 {(void*)NRF_PPIB30_NS_BASE , 0x40103000UL},
482 {(void*)NRF_PPIB30_S_BASE , 0x50103000UL},
483 {(void*)NRF_SPIM30_NS_BASE , 0x40104000UL},
484 {(void*)NRF_SPIS30_NS_BASE , 0x40104000UL},
485 {(void*)NRF_TWIM30_NS_BASE , 0x40104000UL},
486 {(void*)NRF_TWIS30_NS_BASE , 0x40104000UL},
487 {(void*)NRF_UARTE30_NS_BASE , 0x40104000UL},
488 {(void*)NRF_SPIM30_S_BASE , 0x50104000UL},
489 {(void*)NRF_SPIS30_S_BASE , 0x50104000UL},
490 {(void*)NRF_TWIM30_S_BASE , 0x50104000UL},
491 {(void*)NRF_TWIS30_S_BASE , 0x50104000UL},
492 {(void*)NRF_UARTE30_S_BASE , 0x50104000UL},
493 {(void*)NRF_COMP_NS_BASE , 0x40106000UL},
494 {(void*)NRF_LPCOMP_NS_BASE , 0x40106000UL},
495 {(void*)NRF_COMP_S_BASE , 0x50106000UL},
496 {(void*)NRF_LPCOMP_S_BASE , 0x50106000UL},
497 {(void*)NRF_WDT30_S_BASE , 0x50108000UL},
498 {(void*)NRF_WDT31_NS_BASE , 0x40109000UL},
499 {(void*)NRF_WDT31_S_BASE , 0x50109000UL},
500 {(void*)NRF_P0_NS_BASE , 0x4010A000UL},
501 {(void*)NRF_P0_S_BASE , 0x5010A000UL},
502 {(void*)NRF_GPIOTE30_NS_BASE , 0x4010C000UL},
503 {(void*)NRF_GPIOTE30_S_BASE , 0x5010C000UL},
504 {(void*)NRF_CLOCK_NS_BASE , 0x4010E000UL},
505 {(void*)NRF_POWER_NS_BASE , 0x4010E000UL},
506 {(void*)NRF_RESET_NS_BASE , 0x4010E000UL},
507 {(void*)NRF_CLOCK_S_BASE , 0x5010E000UL},
508 {(void*)NRF_POWER_S_BASE , 0x5010E000UL},
509 {(void*)NRF_RESET_S_BASE , 0x5010E000UL},
510 {(void*)NRF_OSCILLATORS_NS_BASE , 0x40120000UL},
511 {(void*)NRF_REGULATORS_NS_BASE , 0x40120000UL},
512 {(void*)NRF_OSCILLATORS_S_BASE , 0x50120000UL},
513 {(void*)NRF_REGULATORS_S_BASE , 0x50120000UL},
514 #else
515 #error "No valid platform was selected"
516 #endif
517 };
518
519 for (unsigned int i = 0; i < sizeof(conv_table)/sizeof(conv_table[0]); i++) {
520 if (conv_table[i].real_add == (uint32_t)hw_addr) {
521 return conv_table[i].simu_addr;
522 }
523 }
524 bs_trace_error_time_line("Could not find real peripheral addr %p\n", hw_addr);
525 return NULL;
526 }
527
