1 /**
2 * \file
3 *
4 * \brief SAM PM
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_PM_COMPONENT_
44 #ifndef _HRI_PM_L21_H_INCLUDED_
45 #define _HRI_PM_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_PM_CRITICAL_SECTIONS)
55 #define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define PM_CRITICAL_SECTION_ENTER()
59 #define PM_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_pm_stdbycfg_reg_t;
63 typedef uint8_t hri_pm_ctrla_reg_t;
64 typedef uint8_t hri_pm_intenset_reg_t;
65 typedef uint8_t hri_pm_intflag_reg_t;
66 typedef uint8_t hri_pm_plcfg_reg_t;
67 typedef uint8_t hri_pm_pwsakdly_reg_t;
68 typedef uint8_t hri_pm_sleepcfg_reg_t;
69
hri_pm_set_INTEN_PLRDY_bit(const void * const hw)70 static inline void hri_pm_set_INTEN_PLRDY_bit(const void *const hw)
71 {
72 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
73 }
74
hri_pm_get_INTEN_PLRDY_bit(const void * const hw)75 static inline bool hri_pm_get_INTEN_PLRDY_bit(const void *const hw)
76 {
77 return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos;
78 }
79
hri_pm_write_INTEN_PLRDY_bit(const void * const hw,bool value)80 static inline void hri_pm_write_INTEN_PLRDY_bit(const void *const hw, bool value)
81 {
82 if (value == 0x0) {
83 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
84 } else {
85 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY;
86 }
87 }
88
hri_pm_clear_INTEN_PLRDY_bit(const void * const hw)89 static inline void hri_pm_clear_INTEN_PLRDY_bit(const void *const hw)
90 {
91 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY;
92 }
93
hri_pm_set_INTEN_reg(const void * const hw,hri_pm_intenset_reg_t mask)94 static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
95 {
96 ((Pm *)hw)->INTENSET.reg = mask;
97 }
98
hri_pm_get_INTEN_reg(const void * const hw,hri_pm_intenset_reg_t mask)99 static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
100 {
101 uint8_t tmp;
102 tmp = ((Pm *)hw)->INTENSET.reg;
103 tmp &= mask;
104 return tmp;
105 }
106
hri_pm_read_INTEN_reg(const void * const hw)107 static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw)
108 {
109 return ((Pm *)hw)->INTENSET.reg;
110 }
111
hri_pm_write_INTEN_reg(const void * const hw,hri_pm_intenset_reg_t data)112 static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data)
113 {
114 ((Pm *)hw)->INTENSET.reg = data;
115 ((Pm *)hw)->INTENCLR.reg = ~data;
116 }
117
hri_pm_clear_INTEN_reg(const void * const hw,hri_pm_intenset_reg_t mask)118 static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask)
119 {
120 ((Pm *)hw)->INTENCLR.reg = mask;
121 }
122
hri_pm_get_INTFLAG_PLRDY_bit(const void * const hw)123 static inline bool hri_pm_get_INTFLAG_PLRDY_bit(const void *const hw)
124 {
125 return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
126 }
127
hri_pm_clear_INTFLAG_PLRDY_bit(const void * const hw)128 static inline void hri_pm_clear_INTFLAG_PLRDY_bit(const void *const hw)
129 {
130 ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
131 }
132
hri_pm_get_interrupt_PLRDY_bit(const void * const hw)133 static inline bool hri_pm_get_interrupt_PLRDY_bit(const void *const hw)
134 {
135 return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_PLRDY) >> PM_INTFLAG_PLRDY_Pos;
136 }
137
hri_pm_clear_interrupt_PLRDY_bit(const void * const hw)138 static inline void hri_pm_clear_interrupt_PLRDY_bit(const void *const hw)
139 {
140 ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_PLRDY;
141 }
142
hri_pm_get_INTFLAG_reg(const void * const hw,hri_pm_intflag_reg_t mask)143 static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
144 {
145 uint8_t tmp;
146 tmp = ((Pm *)hw)->INTFLAG.reg;
147 tmp &= mask;
148 return tmp;
149 }
150
hri_pm_read_INTFLAG_reg(const void * const hw)151 static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw)
152 {
153 return ((Pm *)hw)->INTFLAG.reg;
154 }
155
hri_pm_clear_INTFLAG_reg(const void * const hw,hri_pm_intflag_reg_t mask)156 static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask)
157 {
158 ((Pm *)hw)->INTFLAG.reg = mask;
159 }
160
hri_pm_set_CTRLA_IORET_bit(const void * const hw)161 static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw)
162 {
163 PM_CRITICAL_SECTION_ENTER();
164 ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET;
165 PM_CRITICAL_SECTION_LEAVE();
166 }
167
hri_pm_get_CTRLA_IORET_bit(const void * const hw)168 static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw)
169 {
170 uint8_t tmp;
171 tmp = ((Pm *)hw)->CTRLA.reg;
172 tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos;
173 return (bool)tmp;
174 }
175
hri_pm_write_CTRLA_IORET_bit(const void * const hw,bool value)176 static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value)
177 {
178 uint8_t tmp;
179 PM_CRITICAL_SECTION_ENTER();
180 tmp = ((Pm *)hw)->CTRLA.reg;
181 tmp &= ~PM_CTRLA_IORET;
182 tmp |= value << PM_CTRLA_IORET_Pos;
183 ((Pm *)hw)->CTRLA.reg = tmp;
184 PM_CRITICAL_SECTION_LEAVE();
185 }
186
hri_pm_clear_CTRLA_IORET_bit(const void * const hw)187 static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw)
188 {
189 PM_CRITICAL_SECTION_ENTER();
190 ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET;
191 PM_CRITICAL_SECTION_LEAVE();
192 }
193
hri_pm_toggle_CTRLA_IORET_bit(const void * const hw)194 static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw)
195 {
196 PM_CRITICAL_SECTION_ENTER();
197 ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET;
198 PM_CRITICAL_SECTION_LEAVE();
199 }
200
hri_pm_set_CTRLA_reg(const void * const hw,hri_pm_ctrla_reg_t mask)201 static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
202 {
203 PM_CRITICAL_SECTION_ENTER();
204 ((Pm *)hw)->CTRLA.reg |= mask;
205 PM_CRITICAL_SECTION_LEAVE();
206 }
207
hri_pm_get_CTRLA_reg(const void * const hw,hri_pm_ctrla_reg_t mask)208 static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
209 {
210 uint8_t tmp;
211 tmp = ((Pm *)hw)->CTRLA.reg;
212 tmp &= mask;
213 return tmp;
214 }
215
hri_pm_write_CTRLA_reg(const void * const hw,hri_pm_ctrla_reg_t data)216 static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data)
217 {
218 PM_CRITICAL_SECTION_ENTER();
219 ((Pm *)hw)->CTRLA.reg = data;
220 PM_CRITICAL_SECTION_LEAVE();
221 }
222
hri_pm_clear_CTRLA_reg(const void * const hw,hri_pm_ctrla_reg_t mask)223 static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
224 {
225 PM_CRITICAL_SECTION_ENTER();
226 ((Pm *)hw)->CTRLA.reg &= ~mask;
227 PM_CRITICAL_SECTION_LEAVE();
228 }
229
hri_pm_toggle_CTRLA_reg(const void * const hw,hri_pm_ctrla_reg_t mask)230 static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask)
231 {
232 PM_CRITICAL_SECTION_ENTER();
233 ((Pm *)hw)->CTRLA.reg ^= mask;
234 PM_CRITICAL_SECTION_LEAVE();
235 }
236
hri_pm_read_CTRLA_reg(const void * const hw)237 static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw)
238 {
239 return ((Pm *)hw)->CTRLA.reg;
240 }
241
hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void * const hw,hri_pm_sleepcfg_reg_t mask)242 static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
243 {
244 PM_CRITICAL_SECTION_ENTER();
245 ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask);
246 PM_CRITICAL_SECTION_LEAVE();
247 }
248
hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void * const hw,hri_pm_sleepcfg_reg_t mask)249 static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
250 {
251 uint8_t tmp;
252 tmp = ((Pm *)hw)->SLEEPCFG.reg;
253 tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos;
254 return tmp;
255 }
256
hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void * const hw,hri_pm_sleepcfg_reg_t data)257 static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data)
258 {
259 uint8_t tmp;
260 PM_CRITICAL_SECTION_ENTER();
261 tmp = ((Pm *)hw)->SLEEPCFG.reg;
262 tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk;
263 tmp |= PM_SLEEPCFG_SLEEPMODE(data);
264 ((Pm *)hw)->SLEEPCFG.reg = tmp;
265 PM_CRITICAL_SECTION_LEAVE();
266 }
267
hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void * const hw,hri_pm_sleepcfg_reg_t mask)268 static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
269 {
270 PM_CRITICAL_SECTION_ENTER();
271 ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask);
272 PM_CRITICAL_SECTION_LEAVE();
273 }
274
hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void * const hw,hri_pm_sleepcfg_reg_t mask)275 static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask)
276 {
277 PM_CRITICAL_SECTION_ENTER();
278 ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask);
279 PM_CRITICAL_SECTION_LEAVE();
280 }
281
hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void * const hw)282 static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw)
283 {
284 uint8_t tmp;
285 tmp = ((Pm *)hw)->SLEEPCFG.reg;
286 tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos;
287 return tmp;
288 }
289
hri_pm_set_SLEEPCFG_reg(const void * const hw,hri_pm_sleepcfg_reg_t mask)290 static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
291 {
292 PM_CRITICAL_SECTION_ENTER();
293 ((Pm *)hw)->SLEEPCFG.reg |= mask;
294 PM_CRITICAL_SECTION_LEAVE();
295 }
296
hri_pm_get_SLEEPCFG_reg(const void * const hw,hri_pm_sleepcfg_reg_t mask)297 static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
298 {
299 uint8_t tmp;
300 tmp = ((Pm *)hw)->SLEEPCFG.reg;
301 tmp &= mask;
302 return tmp;
303 }
304
hri_pm_write_SLEEPCFG_reg(const void * const hw,hri_pm_sleepcfg_reg_t data)305 static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data)
306 {
307 PM_CRITICAL_SECTION_ENTER();
308 ((Pm *)hw)->SLEEPCFG.reg = data;
309 PM_CRITICAL_SECTION_LEAVE();
310 }
311
hri_pm_clear_SLEEPCFG_reg(const void * const hw,hri_pm_sleepcfg_reg_t mask)312 static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
313 {
314 PM_CRITICAL_SECTION_ENTER();
315 ((Pm *)hw)->SLEEPCFG.reg &= ~mask;
316 PM_CRITICAL_SECTION_LEAVE();
317 }
318
hri_pm_toggle_SLEEPCFG_reg(const void * const hw,hri_pm_sleepcfg_reg_t mask)319 static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask)
320 {
321 PM_CRITICAL_SECTION_ENTER();
322 ((Pm *)hw)->SLEEPCFG.reg ^= mask;
323 PM_CRITICAL_SECTION_LEAVE();
324 }
325
hri_pm_read_SLEEPCFG_reg(const void * const hw)326 static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw)
327 {
328 return ((Pm *)hw)->SLEEPCFG.reg;
329 }
330
hri_pm_set_PLCFG_PLDIS_bit(const void * const hw)331 static inline void hri_pm_set_PLCFG_PLDIS_bit(const void *const hw)
332 {
333 PM_CRITICAL_SECTION_ENTER();
334 ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLDIS;
335 PM_CRITICAL_SECTION_LEAVE();
336 }
337
hri_pm_get_PLCFG_PLDIS_bit(const void * const hw)338 static inline bool hri_pm_get_PLCFG_PLDIS_bit(const void *const hw)
339 {
340 uint8_t tmp;
341 tmp = ((Pm *)hw)->PLCFG.reg;
342 tmp = (tmp & PM_PLCFG_PLDIS) >> PM_PLCFG_PLDIS_Pos;
343 return (bool)tmp;
344 }
345
hri_pm_write_PLCFG_PLDIS_bit(const void * const hw,bool value)346 static inline void hri_pm_write_PLCFG_PLDIS_bit(const void *const hw, bool value)
347 {
348 uint8_t tmp;
349 PM_CRITICAL_SECTION_ENTER();
350 tmp = ((Pm *)hw)->PLCFG.reg;
351 tmp &= ~PM_PLCFG_PLDIS;
352 tmp |= value << PM_PLCFG_PLDIS_Pos;
353 ((Pm *)hw)->PLCFG.reg = tmp;
354 PM_CRITICAL_SECTION_LEAVE();
355 }
356
hri_pm_clear_PLCFG_PLDIS_bit(const void * const hw)357 static inline void hri_pm_clear_PLCFG_PLDIS_bit(const void *const hw)
358 {
359 PM_CRITICAL_SECTION_ENTER();
360 ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLDIS;
361 PM_CRITICAL_SECTION_LEAVE();
362 }
363
hri_pm_toggle_PLCFG_PLDIS_bit(const void * const hw)364 static inline void hri_pm_toggle_PLCFG_PLDIS_bit(const void *const hw)
365 {
366 PM_CRITICAL_SECTION_ENTER();
367 ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLDIS;
368 PM_CRITICAL_SECTION_LEAVE();
369 }
370
hri_pm_set_PLCFG_PLSEL_bf(const void * const hw,hri_pm_plcfg_reg_t mask)371 static inline void hri_pm_set_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
372 {
373 PM_CRITICAL_SECTION_ENTER();
374 ((Pm *)hw)->PLCFG.reg |= PM_PLCFG_PLSEL(mask);
375 PM_CRITICAL_SECTION_LEAVE();
376 }
377
hri_pm_get_PLCFG_PLSEL_bf(const void * const hw,hri_pm_plcfg_reg_t mask)378 static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
379 {
380 uint8_t tmp;
381 tmp = ((Pm *)hw)->PLCFG.reg;
382 tmp = (tmp & PM_PLCFG_PLSEL(mask)) >> PM_PLCFG_PLSEL_Pos;
383 return tmp;
384 }
385
hri_pm_write_PLCFG_PLSEL_bf(const void * const hw,hri_pm_plcfg_reg_t data)386 static inline void hri_pm_write_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t data)
387 {
388 uint8_t tmp;
389 PM_CRITICAL_SECTION_ENTER();
390 tmp = ((Pm *)hw)->PLCFG.reg;
391 tmp &= ~PM_PLCFG_PLSEL_Msk;
392 tmp |= PM_PLCFG_PLSEL(data);
393 ((Pm *)hw)->PLCFG.reg = tmp;
394 PM_CRITICAL_SECTION_LEAVE();
395 }
396
hri_pm_clear_PLCFG_PLSEL_bf(const void * const hw,hri_pm_plcfg_reg_t mask)397 static inline void hri_pm_clear_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
398 {
399 PM_CRITICAL_SECTION_ENTER();
400 ((Pm *)hw)->PLCFG.reg &= ~PM_PLCFG_PLSEL(mask);
401 PM_CRITICAL_SECTION_LEAVE();
402 }
403
hri_pm_toggle_PLCFG_PLSEL_bf(const void * const hw,hri_pm_plcfg_reg_t mask)404 static inline void hri_pm_toggle_PLCFG_PLSEL_bf(const void *const hw, hri_pm_plcfg_reg_t mask)
405 {
406 PM_CRITICAL_SECTION_ENTER();
407 ((Pm *)hw)->PLCFG.reg ^= PM_PLCFG_PLSEL(mask);
408 PM_CRITICAL_SECTION_LEAVE();
409 }
410
hri_pm_read_PLCFG_PLSEL_bf(const void * const hw)411 static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_PLSEL_bf(const void *const hw)
412 {
413 uint8_t tmp;
414 tmp = ((Pm *)hw)->PLCFG.reg;
415 tmp = (tmp & PM_PLCFG_PLSEL_Msk) >> PM_PLCFG_PLSEL_Pos;
416 return tmp;
417 }
418
hri_pm_set_PLCFG_reg(const void * const hw,hri_pm_plcfg_reg_t mask)419 static inline void hri_pm_set_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
420 {
421 PM_CRITICAL_SECTION_ENTER();
422 ((Pm *)hw)->PLCFG.reg |= mask;
423 PM_CRITICAL_SECTION_LEAVE();
424 }
425
hri_pm_get_PLCFG_reg(const void * const hw,hri_pm_plcfg_reg_t mask)426 static inline hri_pm_plcfg_reg_t hri_pm_get_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
427 {
428 uint8_t tmp;
429 tmp = ((Pm *)hw)->PLCFG.reg;
430 tmp &= mask;
431 return tmp;
432 }
433
hri_pm_write_PLCFG_reg(const void * const hw,hri_pm_plcfg_reg_t data)434 static inline void hri_pm_write_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t data)
435 {
436 PM_CRITICAL_SECTION_ENTER();
437 ((Pm *)hw)->PLCFG.reg = data;
438 PM_CRITICAL_SECTION_LEAVE();
439 }
440
hri_pm_clear_PLCFG_reg(const void * const hw,hri_pm_plcfg_reg_t mask)441 static inline void hri_pm_clear_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
442 {
443 PM_CRITICAL_SECTION_ENTER();
444 ((Pm *)hw)->PLCFG.reg &= ~mask;
445 PM_CRITICAL_SECTION_LEAVE();
446 }
447
hri_pm_toggle_PLCFG_reg(const void * const hw,hri_pm_plcfg_reg_t mask)448 static inline void hri_pm_toggle_PLCFG_reg(const void *const hw, hri_pm_plcfg_reg_t mask)
449 {
450 PM_CRITICAL_SECTION_ENTER();
451 ((Pm *)hw)->PLCFG.reg ^= mask;
452 PM_CRITICAL_SECTION_LEAVE();
453 }
454
hri_pm_read_PLCFG_reg(const void * const hw)455 static inline hri_pm_plcfg_reg_t hri_pm_read_PLCFG_reg(const void *const hw)
456 {
457 return ((Pm *)hw)->PLCFG.reg;
458 }
459
hri_pm_set_STDBYCFG_DPGPD0_bit(const void * const hw)460 static inline void hri_pm_set_STDBYCFG_DPGPD0_bit(const void *const hw)
461 {
462 PM_CRITICAL_SECTION_ENTER();
463 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_DPGPD0;
464 PM_CRITICAL_SECTION_LEAVE();
465 }
466
hri_pm_get_STDBYCFG_DPGPD0_bit(const void * const hw)467 static inline bool hri_pm_get_STDBYCFG_DPGPD0_bit(const void *const hw)
468 {
469 uint16_t tmp;
470 tmp = ((Pm *)hw)->STDBYCFG.reg;
471 tmp = (tmp & PM_STDBYCFG_DPGPD0) >> PM_STDBYCFG_DPGPD0_Pos;
472 return (bool)tmp;
473 }
474
hri_pm_write_STDBYCFG_DPGPD0_bit(const void * const hw,bool value)475 static inline void hri_pm_write_STDBYCFG_DPGPD0_bit(const void *const hw, bool value)
476 {
477 uint16_t tmp;
478 PM_CRITICAL_SECTION_ENTER();
479 tmp = ((Pm *)hw)->STDBYCFG.reg;
480 tmp &= ~PM_STDBYCFG_DPGPD0;
481 tmp |= value << PM_STDBYCFG_DPGPD0_Pos;
482 ((Pm *)hw)->STDBYCFG.reg = tmp;
483 PM_CRITICAL_SECTION_LEAVE();
484 }
485
hri_pm_clear_STDBYCFG_DPGPD0_bit(const void * const hw)486 static inline void hri_pm_clear_STDBYCFG_DPGPD0_bit(const void *const hw)
487 {
488 PM_CRITICAL_SECTION_ENTER();
489 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_DPGPD0;
490 PM_CRITICAL_SECTION_LEAVE();
491 }
492
hri_pm_toggle_STDBYCFG_DPGPD0_bit(const void * const hw)493 static inline void hri_pm_toggle_STDBYCFG_DPGPD0_bit(const void *const hw)
494 {
495 PM_CRITICAL_SECTION_ENTER();
496 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_DPGPD0;
497 PM_CRITICAL_SECTION_LEAVE();
498 }
499
hri_pm_set_STDBYCFG_DPGPD1_bit(const void * const hw)500 static inline void hri_pm_set_STDBYCFG_DPGPD1_bit(const void *const hw)
501 {
502 PM_CRITICAL_SECTION_ENTER();
503 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_DPGPD1;
504 PM_CRITICAL_SECTION_LEAVE();
505 }
506
hri_pm_get_STDBYCFG_DPGPD1_bit(const void * const hw)507 static inline bool hri_pm_get_STDBYCFG_DPGPD1_bit(const void *const hw)
508 {
509 uint16_t tmp;
510 tmp = ((Pm *)hw)->STDBYCFG.reg;
511 tmp = (tmp & PM_STDBYCFG_DPGPD1) >> PM_STDBYCFG_DPGPD1_Pos;
512 return (bool)tmp;
513 }
514
hri_pm_write_STDBYCFG_DPGPD1_bit(const void * const hw,bool value)515 static inline void hri_pm_write_STDBYCFG_DPGPD1_bit(const void *const hw, bool value)
516 {
517 uint16_t tmp;
518 PM_CRITICAL_SECTION_ENTER();
519 tmp = ((Pm *)hw)->STDBYCFG.reg;
520 tmp &= ~PM_STDBYCFG_DPGPD1;
521 tmp |= value << PM_STDBYCFG_DPGPD1_Pos;
522 ((Pm *)hw)->STDBYCFG.reg = tmp;
523 PM_CRITICAL_SECTION_LEAVE();
524 }
525
hri_pm_clear_STDBYCFG_DPGPD1_bit(const void * const hw)526 static inline void hri_pm_clear_STDBYCFG_DPGPD1_bit(const void *const hw)
527 {
528 PM_CRITICAL_SECTION_ENTER();
529 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_DPGPD1;
530 PM_CRITICAL_SECTION_LEAVE();
531 }
532
hri_pm_toggle_STDBYCFG_DPGPD1_bit(const void * const hw)533 static inline void hri_pm_toggle_STDBYCFG_DPGPD1_bit(const void *const hw)
534 {
535 PM_CRITICAL_SECTION_ENTER();
536 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_DPGPD1;
537 PM_CRITICAL_SECTION_LEAVE();
538 }
539
hri_pm_set_STDBYCFG_PDCFG_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)540 static inline void hri_pm_set_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
541 {
542 PM_CRITICAL_SECTION_ENTER();
543 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_PDCFG(mask);
544 PM_CRITICAL_SECTION_LEAVE();
545 }
546
hri_pm_get_STDBYCFG_PDCFG_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)547 static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
548 {
549 uint16_t tmp;
550 tmp = ((Pm *)hw)->STDBYCFG.reg;
551 tmp = (tmp & PM_STDBYCFG_PDCFG(mask)) >> PM_STDBYCFG_PDCFG_Pos;
552 return tmp;
553 }
554
hri_pm_write_STDBYCFG_PDCFG_bf(const void * const hw,hri_pm_stdbycfg_reg_t data)555 static inline void hri_pm_write_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
556 {
557 uint16_t tmp;
558 PM_CRITICAL_SECTION_ENTER();
559 tmp = ((Pm *)hw)->STDBYCFG.reg;
560 tmp &= ~PM_STDBYCFG_PDCFG_Msk;
561 tmp |= PM_STDBYCFG_PDCFG(data);
562 ((Pm *)hw)->STDBYCFG.reg = tmp;
563 PM_CRITICAL_SECTION_LEAVE();
564 }
565
hri_pm_clear_STDBYCFG_PDCFG_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)566 static inline void hri_pm_clear_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
567 {
568 PM_CRITICAL_SECTION_ENTER();
569 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_PDCFG(mask);
570 PM_CRITICAL_SECTION_LEAVE();
571 }
572
hri_pm_toggle_STDBYCFG_PDCFG_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)573 static inline void hri_pm_toggle_STDBYCFG_PDCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
574 {
575 PM_CRITICAL_SECTION_ENTER();
576 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_PDCFG(mask);
577 PM_CRITICAL_SECTION_LEAVE();
578 }
579
hri_pm_read_STDBYCFG_PDCFG_bf(const void * const hw)580 static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_PDCFG_bf(const void *const hw)
581 {
582 uint16_t tmp;
583 tmp = ((Pm *)hw)->STDBYCFG.reg;
584 tmp = (tmp & PM_STDBYCFG_PDCFG_Msk) >> PM_STDBYCFG_PDCFG_Pos;
585 return tmp;
586 }
587
hri_pm_set_STDBYCFG_VREGSMOD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)588 static inline void hri_pm_set_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
589 {
590 PM_CRITICAL_SECTION_ENTER();
591 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_VREGSMOD(mask);
592 PM_CRITICAL_SECTION_LEAVE();
593 }
594
hri_pm_get_STDBYCFG_VREGSMOD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)595 static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
596 {
597 uint16_t tmp;
598 tmp = ((Pm *)hw)->STDBYCFG.reg;
599 tmp = (tmp & PM_STDBYCFG_VREGSMOD(mask)) >> PM_STDBYCFG_VREGSMOD_Pos;
600 return tmp;
601 }
602
hri_pm_write_STDBYCFG_VREGSMOD_bf(const void * const hw,hri_pm_stdbycfg_reg_t data)603 static inline void hri_pm_write_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
604 {
605 uint16_t tmp;
606 PM_CRITICAL_SECTION_ENTER();
607 tmp = ((Pm *)hw)->STDBYCFG.reg;
608 tmp &= ~PM_STDBYCFG_VREGSMOD_Msk;
609 tmp |= PM_STDBYCFG_VREGSMOD(data);
610 ((Pm *)hw)->STDBYCFG.reg = tmp;
611 PM_CRITICAL_SECTION_LEAVE();
612 }
613
hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)614 static inline void hri_pm_clear_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
615 {
616 PM_CRITICAL_SECTION_ENTER();
617 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_VREGSMOD(mask);
618 PM_CRITICAL_SECTION_LEAVE();
619 }
620
hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)621 static inline void hri_pm_toggle_STDBYCFG_VREGSMOD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
622 {
623 PM_CRITICAL_SECTION_ENTER();
624 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_VREGSMOD(mask);
625 PM_CRITICAL_SECTION_LEAVE();
626 }
627
hri_pm_read_STDBYCFG_VREGSMOD_bf(const void * const hw)628 static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_VREGSMOD_bf(const void *const hw)
629 {
630 uint16_t tmp;
631 tmp = ((Pm *)hw)->STDBYCFG.reg;
632 tmp = (tmp & PM_STDBYCFG_VREGSMOD_Msk) >> PM_STDBYCFG_VREGSMOD_Pos;
633 return tmp;
634 }
635
hri_pm_set_STDBYCFG_LINKPD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)636 static inline void hri_pm_set_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
637 {
638 PM_CRITICAL_SECTION_ENTER();
639 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_LINKPD(mask);
640 PM_CRITICAL_SECTION_LEAVE();
641 }
642
hri_pm_get_STDBYCFG_LINKPD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)643 static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
644 {
645 uint16_t tmp;
646 tmp = ((Pm *)hw)->STDBYCFG.reg;
647 tmp = (tmp & PM_STDBYCFG_LINKPD(mask)) >> PM_STDBYCFG_LINKPD_Pos;
648 return tmp;
649 }
650
hri_pm_write_STDBYCFG_LINKPD_bf(const void * const hw,hri_pm_stdbycfg_reg_t data)651 static inline void hri_pm_write_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
652 {
653 uint16_t tmp;
654 PM_CRITICAL_SECTION_ENTER();
655 tmp = ((Pm *)hw)->STDBYCFG.reg;
656 tmp &= ~PM_STDBYCFG_LINKPD_Msk;
657 tmp |= PM_STDBYCFG_LINKPD(data);
658 ((Pm *)hw)->STDBYCFG.reg = tmp;
659 PM_CRITICAL_SECTION_LEAVE();
660 }
661
hri_pm_clear_STDBYCFG_LINKPD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)662 static inline void hri_pm_clear_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
663 {
664 PM_CRITICAL_SECTION_ENTER();
665 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_LINKPD(mask);
666 PM_CRITICAL_SECTION_LEAVE();
667 }
668
hri_pm_toggle_STDBYCFG_LINKPD_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)669 static inline void hri_pm_toggle_STDBYCFG_LINKPD_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
670 {
671 PM_CRITICAL_SECTION_ENTER();
672 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_LINKPD(mask);
673 PM_CRITICAL_SECTION_LEAVE();
674 }
675
hri_pm_read_STDBYCFG_LINKPD_bf(const void * const hw)676 static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_LINKPD_bf(const void *const hw)
677 {
678 uint16_t tmp;
679 tmp = ((Pm *)hw)->STDBYCFG.reg;
680 tmp = (tmp & PM_STDBYCFG_LINKPD_Msk) >> PM_STDBYCFG_LINKPD_Pos;
681 return tmp;
682 }
683
hri_pm_set_STDBYCFG_BBIASHS_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)684 static inline void hri_pm_set_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
685 {
686 PM_CRITICAL_SECTION_ENTER();
687 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASHS(mask);
688 PM_CRITICAL_SECTION_LEAVE();
689 }
690
hri_pm_get_STDBYCFG_BBIASHS_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)691 static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
692 {
693 uint16_t tmp;
694 tmp = ((Pm *)hw)->STDBYCFG.reg;
695 tmp = (tmp & PM_STDBYCFG_BBIASHS(mask)) >> PM_STDBYCFG_BBIASHS_Pos;
696 return tmp;
697 }
698
hri_pm_write_STDBYCFG_BBIASHS_bf(const void * const hw,hri_pm_stdbycfg_reg_t data)699 static inline void hri_pm_write_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
700 {
701 uint16_t tmp;
702 PM_CRITICAL_SECTION_ENTER();
703 tmp = ((Pm *)hw)->STDBYCFG.reg;
704 tmp &= ~PM_STDBYCFG_BBIASHS_Msk;
705 tmp |= PM_STDBYCFG_BBIASHS(data);
706 ((Pm *)hw)->STDBYCFG.reg = tmp;
707 PM_CRITICAL_SECTION_LEAVE();
708 }
709
hri_pm_clear_STDBYCFG_BBIASHS_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)710 static inline void hri_pm_clear_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
711 {
712 PM_CRITICAL_SECTION_ENTER();
713 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASHS(mask);
714 PM_CRITICAL_SECTION_LEAVE();
715 }
716
hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)717 static inline void hri_pm_toggle_STDBYCFG_BBIASHS_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
718 {
719 PM_CRITICAL_SECTION_ENTER();
720 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASHS(mask);
721 PM_CRITICAL_SECTION_LEAVE();
722 }
723
hri_pm_read_STDBYCFG_BBIASHS_bf(const void * const hw)724 static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASHS_bf(const void *const hw)
725 {
726 uint16_t tmp;
727 tmp = ((Pm *)hw)->STDBYCFG.reg;
728 tmp = (tmp & PM_STDBYCFG_BBIASHS_Msk) >> PM_STDBYCFG_BBIASHS_Pos;
729 return tmp;
730 }
731
hri_pm_set_STDBYCFG_BBIASLP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)732 static inline void hri_pm_set_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
733 {
734 PM_CRITICAL_SECTION_ENTER();
735 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASLP(mask);
736 PM_CRITICAL_SECTION_LEAVE();
737 }
738
hri_pm_get_STDBYCFG_BBIASLP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)739 static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
740 {
741 uint16_t tmp;
742 tmp = ((Pm *)hw)->STDBYCFG.reg;
743 tmp = (tmp & PM_STDBYCFG_BBIASLP(mask)) >> PM_STDBYCFG_BBIASLP_Pos;
744 return tmp;
745 }
746
hri_pm_write_STDBYCFG_BBIASLP_bf(const void * const hw,hri_pm_stdbycfg_reg_t data)747 static inline void hri_pm_write_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
748 {
749 uint16_t tmp;
750 PM_CRITICAL_SECTION_ENTER();
751 tmp = ((Pm *)hw)->STDBYCFG.reg;
752 tmp &= ~PM_STDBYCFG_BBIASLP_Msk;
753 tmp |= PM_STDBYCFG_BBIASLP(data);
754 ((Pm *)hw)->STDBYCFG.reg = tmp;
755 PM_CRITICAL_SECTION_LEAVE();
756 }
757
hri_pm_clear_STDBYCFG_BBIASLP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)758 static inline void hri_pm_clear_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
759 {
760 PM_CRITICAL_SECTION_ENTER();
761 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASLP(mask);
762 PM_CRITICAL_SECTION_LEAVE();
763 }
764
hri_pm_toggle_STDBYCFG_BBIASLP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)765 static inline void hri_pm_toggle_STDBYCFG_BBIASLP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
766 {
767 PM_CRITICAL_SECTION_ENTER();
768 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASLP(mask);
769 PM_CRITICAL_SECTION_LEAVE();
770 }
771
hri_pm_read_STDBYCFG_BBIASLP_bf(const void * const hw)772 static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASLP_bf(const void *const hw)
773 {
774 uint16_t tmp;
775 tmp = ((Pm *)hw)->STDBYCFG.reg;
776 tmp = (tmp & PM_STDBYCFG_BBIASLP_Msk) >> PM_STDBYCFG_BBIASLP_Pos;
777 return tmp;
778 }
779
hri_pm_set_STDBYCFG_BBIASPP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)780 static inline void hri_pm_set_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
781 {
782 PM_CRITICAL_SECTION_ENTER();
783 ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_BBIASPP(mask);
784 PM_CRITICAL_SECTION_LEAVE();
785 }
786
hri_pm_get_STDBYCFG_BBIASPP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)787 static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
788 {
789 uint16_t tmp;
790 tmp = ((Pm *)hw)->STDBYCFG.reg;
791 tmp = (tmp & PM_STDBYCFG_BBIASPP(mask)) >> PM_STDBYCFG_BBIASPP_Pos;
792 return tmp;
793 }
794
hri_pm_write_STDBYCFG_BBIASPP_bf(const void * const hw,hri_pm_stdbycfg_reg_t data)795 static inline void hri_pm_write_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data)
796 {
797 uint16_t tmp;
798 PM_CRITICAL_SECTION_ENTER();
799 tmp = ((Pm *)hw)->STDBYCFG.reg;
800 tmp &= ~PM_STDBYCFG_BBIASPP_Msk;
801 tmp |= PM_STDBYCFG_BBIASPP(data);
802 ((Pm *)hw)->STDBYCFG.reg = tmp;
803 PM_CRITICAL_SECTION_LEAVE();
804 }
805
hri_pm_clear_STDBYCFG_BBIASPP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)806 static inline void hri_pm_clear_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
807 {
808 PM_CRITICAL_SECTION_ENTER();
809 ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_BBIASPP(mask);
810 PM_CRITICAL_SECTION_LEAVE();
811 }
812
hri_pm_toggle_STDBYCFG_BBIASPP_bf(const void * const hw,hri_pm_stdbycfg_reg_t mask)813 static inline void hri_pm_toggle_STDBYCFG_BBIASPP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask)
814 {
815 PM_CRITICAL_SECTION_ENTER();
816 ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_BBIASPP(mask);
817 PM_CRITICAL_SECTION_LEAVE();
818 }
819
hri_pm_read_STDBYCFG_BBIASPP_bf(const void * const hw)820 static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_BBIASPP_bf(const void *const hw)
821 {
822 uint16_t tmp;
823 tmp = ((Pm *)hw)->STDBYCFG.reg;
824 tmp = (tmp & PM_STDBYCFG_BBIASPP_Msk) >> PM_STDBYCFG_BBIASPP_Pos;
825 return tmp;
826 }
827
hri_pm_set_STDBYCFG_reg(const void * const hw,hri_pm_stdbycfg_reg_t mask)828 static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
829 {
830 PM_CRITICAL_SECTION_ENTER();
831 ((Pm *)hw)->STDBYCFG.reg |= mask;
832 PM_CRITICAL_SECTION_LEAVE();
833 }
834
hri_pm_get_STDBYCFG_reg(const void * const hw,hri_pm_stdbycfg_reg_t mask)835 static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
836 {
837 uint16_t tmp;
838 tmp = ((Pm *)hw)->STDBYCFG.reg;
839 tmp &= mask;
840 return tmp;
841 }
842
hri_pm_write_STDBYCFG_reg(const void * const hw,hri_pm_stdbycfg_reg_t data)843 static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data)
844 {
845 PM_CRITICAL_SECTION_ENTER();
846 ((Pm *)hw)->STDBYCFG.reg = data;
847 PM_CRITICAL_SECTION_LEAVE();
848 }
849
hri_pm_clear_STDBYCFG_reg(const void * const hw,hri_pm_stdbycfg_reg_t mask)850 static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
851 {
852 PM_CRITICAL_SECTION_ENTER();
853 ((Pm *)hw)->STDBYCFG.reg &= ~mask;
854 PM_CRITICAL_SECTION_LEAVE();
855 }
856
hri_pm_toggle_STDBYCFG_reg(const void * const hw,hri_pm_stdbycfg_reg_t mask)857 static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask)
858 {
859 PM_CRITICAL_SECTION_ENTER();
860 ((Pm *)hw)->STDBYCFG.reg ^= mask;
861 PM_CRITICAL_SECTION_LEAVE();
862 }
863
hri_pm_read_STDBYCFG_reg(const void * const hw)864 static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw)
865 {
866 return ((Pm *)hw)->STDBYCFG.reg;
867 }
868
hri_pm_set_PWSAKDLY_IGNACK_bit(const void * const hw)869 static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw)
870 {
871 PM_CRITICAL_SECTION_ENTER();
872 ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK;
873 PM_CRITICAL_SECTION_LEAVE();
874 }
875
hri_pm_get_PWSAKDLY_IGNACK_bit(const void * const hw)876 static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw)
877 {
878 uint8_t tmp;
879 tmp = ((Pm *)hw)->PWSAKDLY.reg;
880 tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos;
881 return (bool)tmp;
882 }
883
hri_pm_write_PWSAKDLY_IGNACK_bit(const void * const hw,bool value)884 static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value)
885 {
886 uint8_t tmp;
887 PM_CRITICAL_SECTION_ENTER();
888 tmp = ((Pm *)hw)->PWSAKDLY.reg;
889 tmp &= ~PM_PWSAKDLY_IGNACK;
890 tmp |= value << PM_PWSAKDLY_IGNACK_Pos;
891 ((Pm *)hw)->PWSAKDLY.reg = tmp;
892 PM_CRITICAL_SECTION_LEAVE();
893 }
894
hri_pm_clear_PWSAKDLY_IGNACK_bit(const void * const hw)895 static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw)
896 {
897 PM_CRITICAL_SECTION_ENTER();
898 ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK;
899 PM_CRITICAL_SECTION_LEAVE();
900 }
901
hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void * const hw)902 static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw)
903 {
904 PM_CRITICAL_SECTION_ENTER();
905 ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK;
906 PM_CRITICAL_SECTION_LEAVE();
907 }
908
hri_pm_set_PWSAKDLY_DLYVAL_bf(const void * const hw,hri_pm_pwsakdly_reg_t mask)909 static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
910 {
911 PM_CRITICAL_SECTION_ENTER();
912 ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask);
913 PM_CRITICAL_SECTION_LEAVE();
914 }
915
hri_pm_get_PWSAKDLY_DLYVAL_bf(const void * const hw,hri_pm_pwsakdly_reg_t mask)916 static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
917 {
918 uint8_t tmp;
919 tmp = ((Pm *)hw)->PWSAKDLY.reg;
920 tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos;
921 return tmp;
922 }
923
hri_pm_write_PWSAKDLY_DLYVAL_bf(const void * const hw,hri_pm_pwsakdly_reg_t data)924 static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data)
925 {
926 uint8_t tmp;
927 PM_CRITICAL_SECTION_ENTER();
928 tmp = ((Pm *)hw)->PWSAKDLY.reg;
929 tmp &= ~PM_PWSAKDLY_DLYVAL_Msk;
930 tmp |= PM_PWSAKDLY_DLYVAL(data);
931 ((Pm *)hw)->PWSAKDLY.reg = tmp;
932 PM_CRITICAL_SECTION_LEAVE();
933 }
934
hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void * const hw,hri_pm_pwsakdly_reg_t mask)935 static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
936 {
937 PM_CRITICAL_SECTION_ENTER();
938 ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask);
939 PM_CRITICAL_SECTION_LEAVE();
940 }
941
hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void * const hw,hri_pm_pwsakdly_reg_t mask)942 static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask)
943 {
944 PM_CRITICAL_SECTION_ENTER();
945 ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask);
946 PM_CRITICAL_SECTION_LEAVE();
947 }
948
hri_pm_read_PWSAKDLY_DLYVAL_bf(const void * const hw)949 static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw)
950 {
951 uint8_t tmp;
952 tmp = ((Pm *)hw)->PWSAKDLY.reg;
953 tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos;
954 return tmp;
955 }
956
hri_pm_set_PWSAKDLY_reg(const void * const hw,hri_pm_pwsakdly_reg_t mask)957 static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
958 {
959 PM_CRITICAL_SECTION_ENTER();
960 ((Pm *)hw)->PWSAKDLY.reg |= mask;
961 PM_CRITICAL_SECTION_LEAVE();
962 }
963
hri_pm_get_PWSAKDLY_reg(const void * const hw,hri_pm_pwsakdly_reg_t mask)964 static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
965 {
966 uint8_t tmp;
967 tmp = ((Pm *)hw)->PWSAKDLY.reg;
968 tmp &= mask;
969 return tmp;
970 }
971
hri_pm_write_PWSAKDLY_reg(const void * const hw,hri_pm_pwsakdly_reg_t data)972 static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data)
973 {
974 PM_CRITICAL_SECTION_ENTER();
975 ((Pm *)hw)->PWSAKDLY.reg = data;
976 PM_CRITICAL_SECTION_LEAVE();
977 }
978
hri_pm_clear_PWSAKDLY_reg(const void * const hw,hri_pm_pwsakdly_reg_t mask)979 static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
980 {
981 PM_CRITICAL_SECTION_ENTER();
982 ((Pm *)hw)->PWSAKDLY.reg &= ~mask;
983 PM_CRITICAL_SECTION_LEAVE();
984 }
985
hri_pm_toggle_PWSAKDLY_reg(const void * const hw,hri_pm_pwsakdly_reg_t mask)986 static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask)
987 {
988 PM_CRITICAL_SECTION_ENTER();
989 ((Pm *)hw)->PWSAKDLY.reg ^= mask;
990 PM_CRITICAL_SECTION_LEAVE();
991 }
992
hri_pm_read_PWSAKDLY_reg(const void * const hw)993 static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw)
994 {
995 return ((Pm *)hw)->PWSAKDLY.reg;
996 }
997
998 #ifdef __cplusplus
999 }
1000 #endif
1001
1002 #endif /* _HRI_PM_L21_H_INCLUDED */
1003 #endif /* _SAML21_PM_COMPONENT_ */
1004
