1 /**
2 * \file
3 *
4 * \brief SAM MCLK
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_MCLK_COMPONENT_
44 #ifndef _HRI_MCLK_L21_H_INCLUDED_
45 #define _HRI_MCLK_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_MCLK_CRITICAL_SECTIONS)
55 #define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define MCLK_CRITICAL_SECTION_ENTER()
59 #define MCLK_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint32_t hri_mclk_ahbmask_reg_t;
63 typedef uint32_t hri_mclk_apbamask_reg_t;
64 typedef uint32_t hri_mclk_apbbmask_reg_t;
65 typedef uint32_t hri_mclk_apbcmask_reg_t;
66 typedef uint32_t hri_mclk_apbdmask_reg_t;
67 typedef uint32_t hri_mclk_apbemask_reg_t;
68 typedef uint8_t hri_mclk_bupdiv_reg_t;
69 typedef uint8_t hri_mclk_cpudiv_reg_t;
70 typedef uint8_t hri_mclk_ctrla_reg_t;
71 typedef uint8_t hri_mclk_intenset_reg_t;
72 typedef uint8_t hri_mclk_intflag_reg_t;
73 typedef uint8_t hri_mclk_lpdiv_reg_t;
74
hri_mclk_set_INTEN_CKRDY_bit(const void * const hw)75 static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw)
76 {
77 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
78 }
79
hri_mclk_get_INTEN_CKRDY_bit(const void * const hw)80 static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw)
81 {
82 return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos;
83 }
84
hri_mclk_write_INTEN_CKRDY_bit(const void * const hw,bool value)85 static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value)
86 {
87 if (value == 0x0) {
88 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
89 } else {
90 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY;
91 }
92 }
93
hri_mclk_clear_INTEN_CKRDY_bit(const void * const hw)94 static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw)
95 {
96 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY;
97 }
98
hri_mclk_set_INTEN_reg(const void * const hw,hri_mclk_intenset_reg_t mask)99 static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
100 {
101 ((Mclk *)hw)->INTENSET.reg = mask;
102 }
103
hri_mclk_get_INTEN_reg(const void * const hw,hri_mclk_intenset_reg_t mask)104 static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
105 {
106 uint8_t tmp;
107 tmp = ((Mclk *)hw)->INTENSET.reg;
108 tmp &= mask;
109 return tmp;
110 }
111
hri_mclk_read_INTEN_reg(const void * const hw)112 static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw)
113 {
114 return ((Mclk *)hw)->INTENSET.reg;
115 }
116
hri_mclk_write_INTEN_reg(const void * const hw,hri_mclk_intenset_reg_t data)117 static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data)
118 {
119 ((Mclk *)hw)->INTENSET.reg = data;
120 ((Mclk *)hw)->INTENCLR.reg = ~data;
121 }
122
hri_mclk_clear_INTEN_reg(const void * const hw,hri_mclk_intenset_reg_t mask)123 static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask)
124 {
125 ((Mclk *)hw)->INTENCLR.reg = mask;
126 }
127
hri_mclk_get_INTFLAG_CKRDY_bit(const void * const hw)128 static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw)
129 {
130 return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
131 }
132
hri_mclk_clear_INTFLAG_CKRDY_bit(const void * const hw)133 static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw)
134 {
135 ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
136 }
137
hri_mclk_get_interrupt_CKRDY_bit(const void * const hw)138 static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw)
139 {
140 return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos;
141 }
142
hri_mclk_clear_interrupt_CKRDY_bit(const void * const hw)143 static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw)
144 {
145 ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY;
146 }
147
hri_mclk_get_INTFLAG_reg(const void * const hw,hri_mclk_intflag_reg_t mask)148 static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
149 {
150 uint8_t tmp;
151 tmp = ((Mclk *)hw)->INTFLAG.reg;
152 tmp &= mask;
153 return tmp;
154 }
155
hri_mclk_read_INTFLAG_reg(const void * const hw)156 static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw)
157 {
158 return ((Mclk *)hw)->INTFLAG.reg;
159 }
160
hri_mclk_clear_INTFLAG_reg(const void * const hw,hri_mclk_intflag_reg_t mask)161 static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask)
162 {
163 ((Mclk *)hw)->INTFLAG.reg = mask;
164 }
165
hri_mclk_set_CTRLA_reg(const void * const hw,hri_mclk_ctrla_reg_t mask)166 static inline void hri_mclk_set_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask)
167 {
168 MCLK_CRITICAL_SECTION_ENTER();
169 ((Mclk *)hw)->CTRLA.reg |= mask;
170 MCLK_CRITICAL_SECTION_LEAVE();
171 }
172
hri_mclk_get_CTRLA_reg(const void * const hw,hri_mclk_ctrla_reg_t mask)173 static inline hri_mclk_ctrla_reg_t hri_mclk_get_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask)
174 {
175 uint8_t tmp;
176 tmp = ((Mclk *)hw)->CTRLA.reg;
177 tmp &= mask;
178 return tmp;
179 }
180
hri_mclk_write_CTRLA_reg(const void * const hw,hri_mclk_ctrla_reg_t data)181 static inline void hri_mclk_write_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t data)
182 {
183 MCLK_CRITICAL_SECTION_ENTER();
184 ((Mclk *)hw)->CTRLA.reg = data;
185 MCLK_CRITICAL_SECTION_LEAVE();
186 }
187
hri_mclk_clear_CTRLA_reg(const void * const hw,hri_mclk_ctrla_reg_t mask)188 static inline void hri_mclk_clear_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask)
189 {
190 MCLK_CRITICAL_SECTION_ENTER();
191 ((Mclk *)hw)->CTRLA.reg &= ~mask;
192 MCLK_CRITICAL_SECTION_LEAVE();
193 }
194
hri_mclk_toggle_CTRLA_reg(const void * const hw,hri_mclk_ctrla_reg_t mask)195 static inline void hri_mclk_toggle_CTRLA_reg(const void *const hw, hri_mclk_ctrla_reg_t mask)
196 {
197 MCLK_CRITICAL_SECTION_ENTER();
198 ((Mclk *)hw)->CTRLA.reg ^= mask;
199 MCLK_CRITICAL_SECTION_LEAVE();
200 }
201
hri_mclk_read_CTRLA_reg(const void * const hw)202 static inline hri_mclk_ctrla_reg_t hri_mclk_read_CTRLA_reg(const void *const hw)
203 {
204 return ((Mclk *)hw)->CTRLA.reg;
205 }
206
hri_mclk_set_CPUDIV_CPUDIV_bf(const void * const hw,hri_mclk_cpudiv_reg_t mask)207 static inline void hri_mclk_set_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
208 {
209 MCLK_CRITICAL_SECTION_ENTER();
210 ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_CPUDIV(mask);
211 MCLK_CRITICAL_SECTION_LEAVE();
212 }
213
hri_mclk_get_CPUDIV_CPUDIV_bf(const void * const hw,hri_mclk_cpudiv_reg_t mask)214 static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
215 {
216 uint8_t tmp;
217 tmp = ((Mclk *)hw)->CPUDIV.reg;
218 tmp = (tmp & MCLK_CPUDIV_CPUDIV(mask)) >> MCLK_CPUDIV_CPUDIV_Pos;
219 return tmp;
220 }
221
hri_mclk_write_CPUDIV_CPUDIV_bf(const void * const hw,hri_mclk_cpudiv_reg_t data)222 static inline void hri_mclk_write_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data)
223 {
224 uint8_t tmp;
225 MCLK_CRITICAL_SECTION_ENTER();
226 tmp = ((Mclk *)hw)->CPUDIV.reg;
227 tmp &= ~MCLK_CPUDIV_CPUDIV_Msk;
228 tmp |= MCLK_CPUDIV_CPUDIV(data);
229 ((Mclk *)hw)->CPUDIV.reg = tmp;
230 MCLK_CRITICAL_SECTION_LEAVE();
231 }
232
hri_mclk_clear_CPUDIV_CPUDIV_bf(const void * const hw,hri_mclk_cpudiv_reg_t mask)233 static inline void hri_mclk_clear_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
234 {
235 MCLK_CRITICAL_SECTION_ENTER();
236 ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_CPUDIV(mask);
237 MCLK_CRITICAL_SECTION_LEAVE();
238 }
239
hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void * const hw,hri_mclk_cpudiv_reg_t mask)240 static inline void hri_mclk_toggle_CPUDIV_CPUDIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask)
241 {
242 MCLK_CRITICAL_SECTION_ENTER();
243 ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_CPUDIV(mask);
244 MCLK_CRITICAL_SECTION_LEAVE();
245 }
246
hri_mclk_read_CPUDIV_CPUDIV_bf(const void * const hw)247 static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_CPUDIV_bf(const void *const hw)
248 {
249 uint8_t tmp;
250 tmp = ((Mclk *)hw)->CPUDIV.reg;
251 tmp = (tmp & MCLK_CPUDIV_CPUDIV_Msk) >> MCLK_CPUDIV_CPUDIV_Pos;
252 return tmp;
253 }
254
hri_mclk_set_CPUDIV_reg(const void * const hw,hri_mclk_cpudiv_reg_t mask)255 static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
256 {
257 MCLK_CRITICAL_SECTION_ENTER();
258 ((Mclk *)hw)->CPUDIV.reg |= mask;
259 MCLK_CRITICAL_SECTION_LEAVE();
260 }
261
hri_mclk_get_CPUDIV_reg(const void * const hw,hri_mclk_cpudiv_reg_t mask)262 static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
263 {
264 uint8_t tmp;
265 tmp = ((Mclk *)hw)->CPUDIV.reg;
266 tmp &= mask;
267 return tmp;
268 }
269
hri_mclk_write_CPUDIV_reg(const void * const hw,hri_mclk_cpudiv_reg_t data)270 static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data)
271 {
272 MCLK_CRITICAL_SECTION_ENTER();
273 ((Mclk *)hw)->CPUDIV.reg = data;
274 MCLK_CRITICAL_SECTION_LEAVE();
275 }
276
hri_mclk_clear_CPUDIV_reg(const void * const hw,hri_mclk_cpudiv_reg_t mask)277 static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
278 {
279 MCLK_CRITICAL_SECTION_ENTER();
280 ((Mclk *)hw)->CPUDIV.reg &= ~mask;
281 MCLK_CRITICAL_SECTION_LEAVE();
282 }
283
hri_mclk_toggle_CPUDIV_reg(const void * const hw,hri_mclk_cpudiv_reg_t mask)284 static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask)
285 {
286 MCLK_CRITICAL_SECTION_ENTER();
287 ((Mclk *)hw)->CPUDIV.reg ^= mask;
288 MCLK_CRITICAL_SECTION_LEAVE();
289 }
290
hri_mclk_read_CPUDIV_reg(const void * const hw)291 static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw)
292 {
293 return ((Mclk *)hw)->CPUDIV.reg;
294 }
295
hri_mclk_set_LPDIV_LPDIV_bf(const void * const hw,hri_mclk_lpdiv_reg_t mask)296 static inline void hri_mclk_set_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask)
297 {
298 MCLK_CRITICAL_SECTION_ENTER();
299 ((Mclk *)hw)->LPDIV.reg |= MCLK_LPDIV_LPDIV(mask);
300 MCLK_CRITICAL_SECTION_LEAVE();
301 }
302
hri_mclk_get_LPDIV_LPDIV_bf(const void * const hw,hri_mclk_lpdiv_reg_t mask)303 static inline hri_mclk_lpdiv_reg_t hri_mclk_get_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask)
304 {
305 uint8_t tmp;
306 tmp = ((Mclk *)hw)->LPDIV.reg;
307 tmp = (tmp & MCLK_LPDIV_LPDIV(mask)) >> MCLK_LPDIV_LPDIV_Pos;
308 return tmp;
309 }
310
hri_mclk_write_LPDIV_LPDIV_bf(const void * const hw,hri_mclk_lpdiv_reg_t data)311 static inline void hri_mclk_write_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t data)
312 {
313 uint8_t tmp;
314 MCLK_CRITICAL_SECTION_ENTER();
315 tmp = ((Mclk *)hw)->LPDIV.reg;
316 tmp &= ~MCLK_LPDIV_LPDIV_Msk;
317 tmp |= MCLK_LPDIV_LPDIV(data);
318 ((Mclk *)hw)->LPDIV.reg = tmp;
319 MCLK_CRITICAL_SECTION_LEAVE();
320 }
321
hri_mclk_clear_LPDIV_LPDIV_bf(const void * const hw,hri_mclk_lpdiv_reg_t mask)322 static inline void hri_mclk_clear_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask)
323 {
324 MCLK_CRITICAL_SECTION_ENTER();
325 ((Mclk *)hw)->LPDIV.reg &= ~MCLK_LPDIV_LPDIV(mask);
326 MCLK_CRITICAL_SECTION_LEAVE();
327 }
328
hri_mclk_toggle_LPDIV_LPDIV_bf(const void * const hw,hri_mclk_lpdiv_reg_t mask)329 static inline void hri_mclk_toggle_LPDIV_LPDIV_bf(const void *const hw, hri_mclk_lpdiv_reg_t mask)
330 {
331 MCLK_CRITICAL_SECTION_ENTER();
332 ((Mclk *)hw)->LPDIV.reg ^= MCLK_LPDIV_LPDIV(mask);
333 MCLK_CRITICAL_SECTION_LEAVE();
334 }
335
hri_mclk_read_LPDIV_LPDIV_bf(const void * const hw)336 static inline hri_mclk_lpdiv_reg_t hri_mclk_read_LPDIV_LPDIV_bf(const void *const hw)
337 {
338 uint8_t tmp;
339 tmp = ((Mclk *)hw)->LPDIV.reg;
340 tmp = (tmp & MCLK_LPDIV_LPDIV_Msk) >> MCLK_LPDIV_LPDIV_Pos;
341 return tmp;
342 }
343
hri_mclk_set_LPDIV_reg(const void * const hw,hri_mclk_lpdiv_reg_t mask)344 static inline void hri_mclk_set_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask)
345 {
346 MCLK_CRITICAL_SECTION_ENTER();
347 ((Mclk *)hw)->LPDIV.reg |= mask;
348 MCLK_CRITICAL_SECTION_LEAVE();
349 }
350
hri_mclk_get_LPDIV_reg(const void * const hw,hri_mclk_lpdiv_reg_t mask)351 static inline hri_mclk_lpdiv_reg_t hri_mclk_get_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask)
352 {
353 uint8_t tmp;
354 tmp = ((Mclk *)hw)->LPDIV.reg;
355 tmp &= mask;
356 return tmp;
357 }
358
hri_mclk_write_LPDIV_reg(const void * const hw,hri_mclk_lpdiv_reg_t data)359 static inline void hri_mclk_write_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t data)
360 {
361 MCLK_CRITICAL_SECTION_ENTER();
362 ((Mclk *)hw)->LPDIV.reg = data;
363 MCLK_CRITICAL_SECTION_LEAVE();
364 }
365
hri_mclk_clear_LPDIV_reg(const void * const hw,hri_mclk_lpdiv_reg_t mask)366 static inline void hri_mclk_clear_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask)
367 {
368 MCLK_CRITICAL_SECTION_ENTER();
369 ((Mclk *)hw)->LPDIV.reg &= ~mask;
370 MCLK_CRITICAL_SECTION_LEAVE();
371 }
372
hri_mclk_toggle_LPDIV_reg(const void * const hw,hri_mclk_lpdiv_reg_t mask)373 static inline void hri_mclk_toggle_LPDIV_reg(const void *const hw, hri_mclk_lpdiv_reg_t mask)
374 {
375 MCLK_CRITICAL_SECTION_ENTER();
376 ((Mclk *)hw)->LPDIV.reg ^= mask;
377 MCLK_CRITICAL_SECTION_LEAVE();
378 }
379
hri_mclk_read_LPDIV_reg(const void * const hw)380 static inline hri_mclk_lpdiv_reg_t hri_mclk_read_LPDIV_reg(const void *const hw)
381 {
382 return ((Mclk *)hw)->LPDIV.reg;
383 }
384
hri_mclk_set_BUPDIV_BUPDIV_bf(const void * const hw,hri_mclk_bupdiv_reg_t mask)385 static inline void hri_mclk_set_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
386 {
387 MCLK_CRITICAL_SECTION_ENTER();
388 ((Mclk *)hw)->BUPDIV.reg |= MCLK_BUPDIV_BUPDIV(mask);
389 MCLK_CRITICAL_SECTION_LEAVE();
390 }
391
hri_mclk_get_BUPDIV_BUPDIV_bf(const void * const hw,hri_mclk_bupdiv_reg_t mask)392 static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
393 {
394 uint8_t tmp;
395 tmp = ((Mclk *)hw)->BUPDIV.reg;
396 tmp = (tmp & MCLK_BUPDIV_BUPDIV(mask)) >> MCLK_BUPDIV_BUPDIV_Pos;
397 return tmp;
398 }
399
hri_mclk_write_BUPDIV_BUPDIV_bf(const void * const hw,hri_mclk_bupdiv_reg_t data)400 static inline void hri_mclk_write_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t data)
401 {
402 uint8_t tmp;
403 MCLK_CRITICAL_SECTION_ENTER();
404 tmp = ((Mclk *)hw)->BUPDIV.reg;
405 tmp &= ~MCLK_BUPDIV_BUPDIV_Msk;
406 tmp |= MCLK_BUPDIV_BUPDIV(data);
407 ((Mclk *)hw)->BUPDIV.reg = tmp;
408 MCLK_CRITICAL_SECTION_LEAVE();
409 }
410
hri_mclk_clear_BUPDIV_BUPDIV_bf(const void * const hw,hri_mclk_bupdiv_reg_t mask)411 static inline void hri_mclk_clear_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
412 {
413 MCLK_CRITICAL_SECTION_ENTER();
414 ((Mclk *)hw)->BUPDIV.reg &= ~MCLK_BUPDIV_BUPDIV(mask);
415 MCLK_CRITICAL_SECTION_LEAVE();
416 }
417
hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void * const hw,hri_mclk_bupdiv_reg_t mask)418 static inline void hri_mclk_toggle_BUPDIV_BUPDIV_bf(const void *const hw, hri_mclk_bupdiv_reg_t mask)
419 {
420 MCLK_CRITICAL_SECTION_ENTER();
421 ((Mclk *)hw)->BUPDIV.reg ^= MCLK_BUPDIV_BUPDIV(mask);
422 MCLK_CRITICAL_SECTION_LEAVE();
423 }
424
hri_mclk_read_BUPDIV_BUPDIV_bf(const void * const hw)425 static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_BUPDIV_bf(const void *const hw)
426 {
427 uint8_t tmp;
428 tmp = ((Mclk *)hw)->BUPDIV.reg;
429 tmp = (tmp & MCLK_BUPDIV_BUPDIV_Msk) >> MCLK_BUPDIV_BUPDIV_Pos;
430 return tmp;
431 }
432
hri_mclk_set_BUPDIV_reg(const void * const hw,hri_mclk_bupdiv_reg_t mask)433 static inline void hri_mclk_set_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
434 {
435 MCLK_CRITICAL_SECTION_ENTER();
436 ((Mclk *)hw)->BUPDIV.reg |= mask;
437 MCLK_CRITICAL_SECTION_LEAVE();
438 }
439
hri_mclk_get_BUPDIV_reg(const void * const hw,hri_mclk_bupdiv_reg_t mask)440 static inline hri_mclk_bupdiv_reg_t hri_mclk_get_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
441 {
442 uint8_t tmp;
443 tmp = ((Mclk *)hw)->BUPDIV.reg;
444 tmp &= mask;
445 return tmp;
446 }
447
hri_mclk_write_BUPDIV_reg(const void * const hw,hri_mclk_bupdiv_reg_t data)448 static inline void hri_mclk_write_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t data)
449 {
450 MCLK_CRITICAL_SECTION_ENTER();
451 ((Mclk *)hw)->BUPDIV.reg = data;
452 MCLK_CRITICAL_SECTION_LEAVE();
453 }
454
hri_mclk_clear_BUPDIV_reg(const void * const hw,hri_mclk_bupdiv_reg_t mask)455 static inline void hri_mclk_clear_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
456 {
457 MCLK_CRITICAL_SECTION_ENTER();
458 ((Mclk *)hw)->BUPDIV.reg &= ~mask;
459 MCLK_CRITICAL_SECTION_LEAVE();
460 }
461
hri_mclk_toggle_BUPDIV_reg(const void * const hw,hri_mclk_bupdiv_reg_t mask)462 static inline void hri_mclk_toggle_BUPDIV_reg(const void *const hw, hri_mclk_bupdiv_reg_t mask)
463 {
464 MCLK_CRITICAL_SECTION_ENTER();
465 ((Mclk *)hw)->BUPDIV.reg ^= mask;
466 MCLK_CRITICAL_SECTION_LEAVE();
467 }
468
hri_mclk_read_BUPDIV_reg(const void * const hw)469 static inline hri_mclk_bupdiv_reg_t hri_mclk_read_BUPDIV_reg(const void *const hw)
470 {
471 return ((Mclk *)hw)->BUPDIV.reg;
472 }
473
hri_mclk_set_AHBMASK_HPB0_bit(const void * const hw)474 static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw)
475 {
476 MCLK_CRITICAL_SECTION_ENTER();
477 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0;
478 MCLK_CRITICAL_SECTION_LEAVE();
479 }
480
hri_mclk_get_AHBMASK_HPB0_bit(const void * const hw)481 static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw)
482 {
483 uint32_t tmp;
484 tmp = ((Mclk *)hw)->AHBMASK.reg;
485 tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos;
486 return (bool)tmp;
487 }
488
hri_mclk_write_AHBMASK_HPB0_bit(const void * const hw,bool value)489 static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value)
490 {
491 uint32_t tmp;
492 MCLK_CRITICAL_SECTION_ENTER();
493 tmp = ((Mclk *)hw)->AHBMASK.reg;
494 tmp &= ~MCLK_AHBMASK_HPB0;
495 tmp |= value << MCLK_AHBMASK_HPB0_Pos;
496 ((Mclk *)hw)->AHBMASK.reg = tmp;
497 MCLK_CRITICAL_SECTION_LEAVE();
498 }
499
hri_mclk_clear_AHBMASK_HPB0_bit(const void * const hw)500 static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw)
501 {
502 MCLK_CRITICAL_SECTION_ENTER();
503 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0;
504 MCLK_CRITICAL_SECTION_LEAVE();
505 }
506
hri_mclk_toggle_AHBMASK_HPB0_bit(const void * const hw)507 static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw)
508 {
509 MCLK_CRITICAL_SECTION_ENTER();
510 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0;
511 MCLK_CRITICAL_SECTION_LEAVE();
512 }
513
hri_mclk_set_AHBMASK_HPB1_bit(const void * const hw)514 static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw)
515 {
516 MCLK_CRITICAL_SECTION_ENTER();
517 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1;
518 MCLK_CRITICAL_SECTION_LEAVE();
519 }
520
hri_mclk_get_AHBMASK_HPB1_bit(const void * const hw)521 static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw)
522 {
523 uint32_t tmp;
524 tmp = ((Mclk *)hw)->AHBMASK.reg;
525 tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos;
526 return (bool)tmp;
527 }
528
hri_mclk_write_AHBMASK_HPB1_bit(const void * const hw,bool value)529 static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value)
530 {
531 uint32_t tmp;
532 MCLK_CRITICAL_SECTION_ENTER();
533 tmp = ((Mclk *)hw)->AHBMASK.reg;
534 tmp &= ~MCLK_AHBMASK_HPB1;
535 tmp |= value << MCLK_AHBMASK_HPB1_Pos;
536 ((Mclk *)hw)->AHBMASK.reg = tmp;
537 MCLK_CRITICAL_SECTION_LEAVE();
538 }
539
hri_mclk_clear_AHBMASK_HPB1_bit(const void * const hw)540 static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw)
541 {
542 MCLK_CRITICAL_SECTION_ENTER();
543 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1;
544 MCLK_CRITICAL_SECTION_LEAVE();
545 }
546
hri_mclk_toggle_AHBMASK_HPB1_bit(const void * const hw)547 static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw)
548 {
549 MCLK_CRITICAL_SECTION_ENTER();
550 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1;
551 MCLK_CRITICAL_SECTION_LEAVE();
552 }
553
hri_mclk_set_AHBMASK_HPB2_bit(const void * const hw)554 static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw)
555 {
556 MCLK_CRITICAL_SECTION_ENTER();
557 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2;
558 MCLK_CRITICAL_SECTION_LEAVE();
559 }
560
hri_mclk_get_AHBMASK_HPB2_bit(const void * const hw)561 static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw)
562 {
563 uint32_t tmp;
564 tmp = ((Mclk *)hw)->AHBMASK.reg;
565 tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos;
566 return (bool)tmp;
567 }
568
hri_mclk_write_AHBMASK_HPB2_bit(const void * const hw,bool value)569 static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value)
570 {
571 uint32_t tmp;
572 MCLK_CRITICAL_SECTION_ENTER();
573 tmp = ((Mclk *)hw)->AHBMASK.reg;
574 tmp &= ~MCLK_AHBMASK_HPB2;
575 tmp |= value << MCLK_AHBMASK_HPB2_Pos;
576 ((Mclk *)hw)->AHBMASK.reg = tmp;
577 MCLK_CRITICAL_SECTION_LEAVE();
578 }
579
hri_mclk_clear_AHBMASK_HPB2_bit(const void * const hw)580 static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw)
581 {
582 MCLK_CRITICAL_SECTION_ENTER();
583 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2;
584 MCLK_CRITICAL_SECTION_LEAVE();
585 }
586
hri_mclk_toggle_AHBMASK_HPB2_bit(const void * const hw)587 static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw)
588 {
589 MCLK_CRITICAL_SECTION_ENTER();
590 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2;
591 MCLK_CRITICAL_SECTION_LEAVE();
592 }
593
hri_mclk_set_AHBMASK_HPB3_bit(const void * const hw)594 static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw)
595 {
596 MCLK_CRITICAL_SECTION_ENTER();
597 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3;
598 MCLK_CRITICAL_SECTION_LEAVE();
599 }
600
hri_mclk_get_AHBMASK_HPB3_bit(const void * const hw)601 static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw)
602 {
603 uint32_t tmp;
604 tmp = ((Mclk *)hw)->AHBMASK.reg;
605 tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos;
606 return (bool)tmp;
607 }
608
hri_mclk_write_AHBMASK_HPB3_bit(const void * const hw,bool value)609 static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value)
610 {
611 uint32_t tmp;
612 MCLK_CRITICAL_SECTION_ENTER();
613 tmp = ((Mclk *)hw)->AHBMASK.reg;
614 tmp &= ~MCLK_AHBMASK_HPB3;
615 tmp |= value << MCLK_AHBMASK_HPB3_Pos;
616 ((Mclk *)hw)->AHBMASK.reg = tmp;
617 MCLK_CRITICAL_SECTION_LEAVE();
618 }
619
hri_mclk_clear_AHBMASK_HPB3_bit(const void * const hw)620 static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw)
621 {
622 MCLK_CRITICAL_SECTION_ENTER();
623 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3;
624 MCLK_CRITICAL_SECTION_LEAVE();
625 }
626
hri_mclk_toggle_AHBMASK_HPB3_bit(const void * const hw)627 static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw)
628 {
629 MCLK_CRITICAL_SECTION_ENTER();
630 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3;
631 MCLK_CRITICAL_SECTION_LEAVE();
632 }
633
hri_mclk_set_AHBMASK_HPB4_bit(const void * const hw)634 static inline void hri_mclk_set_AHBMASK_HPB4_bit(const void *const hw)
635 {
636 MCLK_CRITICAL_SECTION_ENTER();
637 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB4;
638 MCLK_CRITICAL_SECTION_LEAVE();
639 }
640
hri_mclk_get_AHBMASK_HPB4_bit(const void * const hw)641 static inline bool hri_mclk_get_AHBMASK_HPB4_bit(const void *const hw)
642 {
643 uint32_t tmp;
644 tmp = ((Mclk *)hw)->AHBMASK.reg;
645 tmp = (tmp & MCLK_AHBMASK_HPB4) >> MCLK_AHBMASK_HPB4_Pos;
646 return (bool)tmp;
647 }
648
hri_mclk_write_AHBMASK_HPB4_bit(const void * const hw,bool value)649 static inline void hri_mclk_write_AHBMASK_HPB4_bit(const void *const hw, bool value)
650 {
651 uint32_t tmp;
652 MCLK_CRITICAL_SECTION_ENTER();
653 tmp = ((Mclk *)hw)->AHBMASK.reg;
654 tmp &= ~MCLK_AHBMASK_HPB4;
655 tmp |= value << MCLK_AHBMASK_HPB4_Pos;
656 ((Mclk *)hw)->AHBMASK.reg = tmp;
657 MCLK_CRITICAL_SECTION_LEAVE();
658 }
659
hri_mclk_clear_AHBMASK_HPB4_bit(const void * const hw)660 static inline void hri_mclk_clear_AHBMASK_HPB4_bit(const void *const hw)
661 {
662 MCLK_CRITICAL_SECTION_ENTER();
663 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB4;
664 MCLK_CRITICAL_SECTION_LEAVE();
665 }
666
hri_mclk_toggle_AHBMASK_HPB4_bit(const void * const hw)667 static inline void hri_mclk_toggle_AHBMASK_HPB4_bit(const void *const hw)
668 {
669 MCLK_CRITICAL_SECTION_ENTER();
670 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB4;
671 MCLK_CRITICAL_SECTION_LEAVE();
672 }
673
hri_mclk_set_AHBMASK_DSU_bit(const void * const hw)674 static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw)
675 {
676 MCLK_CRITICAL_SECTION_ENTER();
677 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU;
678 MCLK_CRITICAL_SECTION_LEAVE();
679 }
680
hri_mclk_get_AHBMASK_DSU_bit(const void * const hw)681 static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw)
682 {
683 uint32_t tmp;
684 tmp = ((Mclk *)hw)->AHBMASK.reg;
685 tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos;
686 return (bool)tmp;
687 }
688
hri_mclk_write_AHBMASK_DSU_bit(const void * const hw,bool value)689 static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value)
690 {
691 uint32_t tmp;
692 MCLK_CRITICAL_SECTION_ENTER();
693 tmp = ((Mclk *)hw)->AHBMASK.reg;
694 tmp &= ~MCLK_AHBMASK_DSU;
695 tmp |= value << MCLK_AHBMASK_DSU_Pos;
696 ((Mclk *)hw)->AHBMASK.reg = tmp;
697 MCLK_CRITICAL_SECTION_LEAVE();
698 }
699
hri_mclk_clear_AHBMASK_DSU_bit(const void * const hw)700 static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw)
701 {
702 MCLK_CRITICAL_SECTION_ENTER();
703 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU;
704 MCLK_CRITICAL_SECTION_LEAVE();
705 }
706
hri_mclk_toggle_AHBMASK_DSU_bit(const void * const hw)707 static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw)
708 {
709 MCLK_CRITICAL_SECTION_ENTER();
710 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU;
711 MCLK_CRITICAL_SECTION_LEAVE();
712 }
713
hri_mclk_set_AHBMASK_NVMCTRL_bit(const void * const hw)714 static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw)
715 {
716 MCLK_CRITICAL_SECTION_ENTER();
717 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL;
718 MCLK_CRITICAL_SECTION_LEAVE();
719 }
720
hri_mclk_get_AHBMASK_NVMCTRL_bit(const void * const hw)721 static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw)
722 {
723 uint32_t tmp;
724 tmp = ((Mclk *)hw)->AHBMASK.reg;
725 tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos;
726 return (bool)tmp;
727 }
728
hri_mclk_write_AHBMASK_NVMCTRL_bit(const void * const hw,bool value)729 static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value)
730 {
731 uint32_t tmp;
732 MCLK_CRITICAL_SECTION_ENTER();
733 tmp = ((Mclk *)hw)->AHBMASK.reg;
734 tmp &= ~MCLK_AHBMASK_NVMCTRL;
735 tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos;
736 ((Mclk *)hw)->AHBMASK.reg = tmp;
737 MCLK_CRITICAL_SECTION_LEAVE();
738 }
739
hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void * const hw)740 static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw)
741 {
742 MCLK_CRITICAL_SECTION_ENTER();
743 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL;
744 MCLK_CRITICAL_SECTION_LEAVE();
745 }
746
hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void * const hw)747 static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw)
748 {
749 MCLK_CRITICAL_SECTION_ENTER();
750 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL;
751 MCLK_CRITICAL_SECTION_LEAVE();
752 }
753
hri_mclk_set_AHBMASK_HSRAM_bit(const void * const hw)754 static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw)
755 {
756 MCLK_CRITICAL_SECTION_ENTER();
757 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM;
758 MCLK_CRITICAL_SECTION_LEAVE();
759 }
760
hri_mclk_get_AHBMASK_HSRAM_bit(const void * const hw)761 static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw)
762 {
763 uint32_t tmp;
764 tmp = ((Mclk *)hw)->AHBMASK.reg;
765 tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos;
766 return (bool)tmp;
767 }
768
hri_mclk_write_AHBMASK_HSRAM_bit(const void * const hw,bool value)769 static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value)
770 {
771 uint32_t tmp;
772 MCLK_CRITICAL_SECTION_ENTER();
773 tmp = ((Mclk *)hw)->AHBMASK.reg;
774 tmp &= ~MCLK_AHBMASK_HSRAM;
775 tmp |= value << MCLK_AHBMASK_HSRAM_Pos;
776 ((Mclk *)hw)->AHBMASK.reg = tmp;
777 MCLK_CRITICAL_SECTION_LEAVE();
778 }
779
hri_mclk_clear_AHBMASK_HSRAM_bit(const void * const hw)780 static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw)
781 {
782 MCLK_CRITICAL_SECTION_ENTER();
783 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM;
784 MCLK_CRITICAL_SECTION_LEAVE();
785 }
786
hri_mclk_toggle_AHBMASK_HSRAM_bit(const void * const hw)787 static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw)
788 {
789 MCLK_CRITICAL_SECTION_ENTER();
790 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM;
791 MCLK_CRITICAL_SECTION_LEAVE();
792 }
793
hri_mclk_set_AHBMASK_LPRAM_bit(const void * const hw)794 static inline void hri_mclk_set_AHBMASK_LPRAM_bit(const void *const hw)
795 {
796 MCLK_CRITICAL_SECTION_ENTER();
797 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_LPRAM;
798 MCLK_CRITICAL_SECTION_LEAVE();
799 }
800
hri_mclk_get_AHBMASK_LPRAM_bit(const void * const hw)801 static inline bool hri_mclk_get_AHBMASK_LPRAM_bit(const void *const hw)
802 {
803 uint32_t tmp;
804 tmp = ((Mclk *)hw)->AHBMASK.reg;
805 tmp = (tmp & MCLK_AHBMASK_LPRAM) >> MCLK_AHBMASK_LPRAM_Pos;
806 return (bool)tmp;
807 }
808
hri_mclk_write_AHBMASK_LPRAM_bit(const void * const hw,bool value)809 static inline void hri_mclk_write_AHBMASK_LPRAM_bit(const void *const hw, bool value)
810 {
811 uint32_t tmp;
812 MCLK_CRITICAL_SECTION_ENTER();
813 tmp = ((Mclk *)hw)->AHBMASK.reg;
814 tmp &= ~MCLK_AHBMASK_LPRAM;
815 tmp |= value << MCLK_AHBMASK_LPRAM_Pos;
816 ((Mclk *)hw)->AHBMASK.reg = tmp;
817 MCLK_CRITICAL_SECTION_LEAVE();
818 }
819
hri_mclk_clear_AHBMASK_LPRAM_bit(const void * const hw)820 static inline void hri_mclk_clear_AHBMASK_LPRAM_bit(const void *const hw)
821 {
822 MCLK_CRITICAL_SECTION_ENTER();
823 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_LPRAM;
824 MCLK_CRITICAL_SECTION_LEAVE();
825 }
826
hri_mclk_toggle_AHBMASK_LPRAM_bit(const void * const hw)827 static inline void hri_mclk_toggle_AHBMASK_LPRAM_bit(const void *const hw)
828 {
829 MCLK_CRITICAL_SECTION_ENTER();
830 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_LPRAM;
831 MCLK_CRITICAL_SECTION_LEAVE();
832 }
833
hri_mclk_set_AHBMASK_DMAC_bit(const void * const hw)834 static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw)
835 {
836 MCLK_CRITICAL_SECTION_ENTER();
837 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC;
838 MCLK_CRITICAL_SECTION_LEAVE();
839 }
840
hri_mclk_get_AHBMASK_DMAC_bit(const void * const hw)841 static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw)
842 {
843 uint32_t tmp;
844 tmp = ((Mclk *)hw)->AHBMASK.reg;
845 tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos;
846 return (bool)tmp;
847 }
848
hri_mclk_write_AHBMASK_DMAC_bit(const void * const hw,bool value)849 static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value)
850 {
851 uint32_t tmp;
852 MCLK_CRITICAL_SECTION_ENTER();
853 tmp = ((Mclk *)hw)->AHBMASK.reg;
854 tmp &= ~MCLK_AHBMASK_DMAC;
855 tmp |= value << MCLK_AHBMASK_DMAC_Pos;
856 ((Mclk *)hw)->AHBMASK.reg = tmp;
857 MCLK_CRITICAL_SECTION_LEAVE();
858 }
859
hri_mclk_clear_AHBMASK_DMAC_bit(const void * const hw)860 static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw)
861 {
862 MCLK_CRITICAL_SECTION_ENTER();
863 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC;
864 MCLK_CRITICAL_SECTION_LEAVE();
865 }
866
hri_mclk_toggle_AHBMASK_DMAC_bit(const void * const hw)867 static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw)
868 {
869 MCLK_CRITICAL_SECTION_ENTER();
870 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC;
871 MCLK_CRITICAL_SECTION_LEAVE();
872 }
873
hri_mclk_set_AHBMASK_USB_bit(const void * const hw)874 static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw)
875 {
876 MCLK_CRITICAL_SECTION_ENTER();
877 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB;
878 MCLK_CRITICAL_SECTION_LEAVE();
879 }
880
hri_mclk_get_AHBMASK_USB_bit(const void * const hw)881 static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw)
882 {
883 uint32_t tmp;
884 tmp = ((Mclk *)hw)->AHBMASK.reg;
885 tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos;
886 return (bool)tmp;
887 }
888
hri_mclk_write_AHBMASK_USB_bit(const void * const hw,bool value)889 static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value)
890 {
891 uint32_t tmp;
892 MCLK_CRITICAL_SECTION_ENTER();
893 tmp = ((Mclk *)hw)->AHBMASK.reg;
894 tmp &= ~MCLK_AHBMASK_USB;
895 tmp |= value << MCLK_AHBMASK_USB_Pos;
896 ((Mclk *)hw)->AHBMASK.reg = tmp;
897 MCLK_CRITICAL_SECTION_LEAVE();
898 }
899
hri_mclk_clear_AHBMASK_USB_bit(const void * const hw)900 static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw)
901 {
902 MCLK_CRITICAL_SECTION_ENTER();
903 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB;
904 MCLK_CRITICAL_SECTION_LEAVE();
905 }
906
hri_mclk_toggle_AHBMASK_USB_bit(const void * const hw)907 static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw)
908 {
909 MCLK_CRITICAL_SECTION_ENTER();
910 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB;
911 MCLK_CRITICAL_SECTION_LEAVE();
912 }
913
hri_mclk_set_AHBMASK_PAC_bit(const void * const hw)914 static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw)
915 {
916 MCLK_CRITICAL_SECTION_ENTER();
917 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC;
918 MCLK_CRITICAL_SECTION_LEAVE();
919 }
920
hri_mclk_get_AHBMASK_PAC_bit(const void * const hw)921 static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw)
922 {
923 uint32_t tmp;
924 tmp = ((Mclk *)hw)->AHBMASK.reg;
925 tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos;
926 return (bool)tmp;
927 }
928
hri_mclk_write_AHBMASK_PAC_bit(const void * const hw,bool value)929 static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value)
930 {
931 uint32_t tmp;
932 MCLK_CRITICAL_SECTION_ENTER();
933 tmp = ((Mclk *)hw)->AHBMASK.reg;
934 tmp &= ~MCLK_AHBMASK_PAC;
935 tmp |= value << MCLK_AHBMASK_PAC_Pos;
936 ((Mclk *)hw)->AHBMASK.reg = tmp;
937 MCLK_CRITICAL_SECTION_LEAVE();
938 }
939
hri_mclk_clear_AHBMASK_PAC_bit(const void * const hw)940 static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw)
941 {
942 MCLK_CRITICAL_SECTION_ENTER();
943 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC;
944 MCLK_CRITICAL_SECTION_LEAVE();
945 }
946
hri_mclk_toggle_AHBMASK_PAC_bit(const void * const hw)947 static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw)
948 {
949 MCLK_CRITICAL_SECTION_ENTER();
950 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC;
951 MCLK_CRITICAL_SECTION_LEAVE();
952 }
953
hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void * const hw)954 static inline void hri_mclk_set_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
955 {
956 MCLK_CRITICAL_SECTION_ENTER();
957 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_PICACHU;
958 MCLK_CRITICAL_SECTION_LEAVE();
959 }
960
hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void * const hw)961 static inline bool hri_mclk_get_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
962 {
963 uint32_t tmp;
964 tmp = ((Mclk *)hw)->AHBMASK.reg;
965 tmp = (tmp & MCLK_AHBMASK_NVMCTRL_PICACHU) >> MCLK_AHBMASK_NVMCTRL_PICACHU_Pos;
966 return (bool)tmp;
967 }
968
hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void * const hw,bool value)969 static inline void hri_mclk_write_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw, bool value)
970 {
971 uint32_t tmp;
972 MCLK_CRITICAL_SECTION_ENTER();
973 tmp = ((Mclk *)hw)->AHBMASK.reg;
974 tmp &= ~MCLK_AHBMASK_NVMCTRL_PICACHU;
975 tmp |= value << MCLK_AHBMASK_NVMCTRL_PICACHU_Pos;
976 ((Mclk *)hw)->AHBMASK.reg = tmp;
977 MCLK_CRITICAL_SECTION_LEAVE();
978 }
979
hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void * const hw)980 static inline void hri_mclk_clear_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
981 {
982 MCLK_CRITICAL_SECTION_ENTER();
983 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_PICACHU;
984 MCLK_CRITICAL_SECTION_LEAVE();
985 }
986
hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void * const hw)987 static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_PICACHU_bit(const void *const hw)
988 {
989 MCLK_CRITICAL_SECTION_ENTER();
990 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_PICACHU;
991 MCLK_CRITICAL_SECTION_LEAVE();
992 }
993
hri_mclk_set_AHBMASK_L2HBRIDGES_H_bit(const void * const hw)994 static inline void hri_mclk_set_AHBMASK_L2HBRIDGES_H_bit(const void *const hw)
995 {
996 MCLK_CRITICAL_SECTION_ENTER();
997 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_L2HBRIDGES_H;
998 MCLK_CRITICAL_SECTION_LEAVE();
999 }
1000
hri_mclk_get_AHBMASK_L2HBRIDGES_H_bit(const void * const hw)1001 static inline bool hri_mclk_get_AHBMASK_L2HBRIDGES_H_bit(const void *const hw)
1002 {
1003 uint32_t tmp;
1004 tmp = ((Mclk *)hw)->AHBMASK.reg;
1005 tmp = (tmp & MCLK_AHBMASK_L2HBRIDGES_H) >> MCLK_AHBMASK_L2HBRIDGES_H_Pos;
1006 return (bool)tmp;
1007 }
1008
hri_mclk_write_AHBMASK_L2HBRIDGES_H_bit(const void * const hw,bool value)1009 static inline void hri_mclk_write_AHBMASK_L2HBRIDGES_H_bit(const void *const hw, bool value)
1010 {
1011 uint32_t tmp;
1012 MCLK_CRITICAL_SECTION_ENTER();
1013 tmp = ((Mclk *)hw)->AHBMASK.reg;
1014 tmp &= ~MCLK_AHBMASK_L2HBRIDGES_H;
1015 tmp |= value << MCLK_AHBMASK_L2HBRIDGES_H_Pos;
1016 ((Mclk *)hw)->AHBMASK.reg = tmp;
1017 MCLK_CRITICAL_SECTION_LEAVE();
1018 }
1019
hri_mclk_clear_AHBMASK_L2HBRIDGES_H_bit(const void * const hw)1020 static inline void hri_mclk_clear_AHBMASK_L2HBRIDGES_H_bit(const void *const hw)
1021 {
1022 MCLK_CRITICAL_SECTION_ENTER();
1023 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_L2HBRIDGES_H;
1024 MCLK_CRITICAL_SECTION_LEAVE();
1025 }
1026
hri_mclk_toggle_AHBMASK_L2HBRIDGES_H_bit(const void * const hw)1027 static inline void hri_mclk_toggle_AHBMASK_L2HBRIDGES_H_bit(const void *const hw)
1028 {
1029 MCLK_CRITICAL_SECTION_ENTER();
1030 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_L2HBRIDGES_H;
1031 MCLK_CRITICAL_SECTION_LEAVE();
1032 }
1033
hri_mclk_set_AHBMASK_H2LBRIDGES_H_bit(const void * const hw)1034 static inline void hri_mclk_set_AHBMASK_H2LBRIDGES_H_bit(const void *const hw)
1035 {
1036 MCLK_CRITICAL_SECTION_ENTER();
1037 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_H2LBRIDGES_H;
1038 MCLK_CRITICAL_SECTION_LEAVE();
1039 }
1040
hri_mclk_get_AHBMASK_H2LBRIDGES_H_bit(const void * const hw)1041 static inline bool hri_mclk_get_AHBMASK_H2LBRIDGES_H_bit(const void *const hw)
1042 {
1043 uint32_t tmp;
1044 tmp = ((Mclk *)hw)->AHBMASK.reg;
1045 tmp = (tmp & MCLK_AHBMASK_H2LBRIDGES_H) >> MCLK_AHBMASK_H2LBRIDGES_H_Pos;
1046 return (bool)tmp;
1047 }
1048
hri_mclk_write_AHBMASK_H2LBRIDGES_H_bit(const void * const hw,bool value)1049 static inline void hri_mclk_write_AHBMASK_H2LBRIDGES_H_bit(const void *const hw, bool value)
1050 {
1051 uint32_t tmp;
1052 MCLK_CRITICAL_SECTION_ENTER();
1053 tmp = ((Mclk *)hw)->AHBMASK.reg;
1054 tmp &= ~MCLK_AHBMASK_H2LBRIDGES_H;
1055 tmp |= value << MCLK_AHBMASK_H2LBRIDGES_H_Pos;
1056 ((Mclk *)hw)->AHBMASK.reg = tmp;
1057 MCLK_CRITICAL_SECTION_LEAVE();
1058 }
1059
hri_mclk_clear_AHBMASK_H2LBRIDGES_H_bit(const void * const hw)1060 static inline void hri_mclk_clear_AHBMASK_H2LBRIDGES_H_bit(const void *const hw)
1061 {
1062 MCLK_CRITICAL_SECTION_ENTER();
1063 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_H2LBRIDGES_H;
1064 MCLK_CRITICAL_SECTION_LEAVE();
1065 }
1066
hri_mclk_toggle_AHBMASK_H2LBRIDGES_H_bit(const void * const hw)1067 static inline void hri_mclk_toggle_AHBMASK_H2LBRIDGES_H_bit(const void *const hw)
1068 {
1069 MCLK_CRITICAL_SECTION_ENTER();
1070 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_H2LBRIDGES_H;
1071 MCLK_CRITICAL_SECTION_LEAVE();
1072 }
1073
hri_mclk_set_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void * const hw)1074 static inline void hri_mclk_set_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void *const hw)
1075 {
1076 MCLK_CRITICAL_SECTION_ENTER();
1077 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER;
1078 MCLK_CRITICAL_SECTION_LEAVE();
1079 }
1080
hri_mclk_get_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void * const hw)1081 static inline bool hri_mclk_get_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void *const hw)
1082 {
1083 uint32_t tmp;
1084 tmp = ((Mclk *)hw)->AHBMASK.reg;
1085 tmp = (tmp & MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER) >> MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_Pos;
1086 return (bool)tmp;
1087 }
1088
hri_mclk_write_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void * const hw,bool value)1089 static inline void hri_mclk_write_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void *const hw, bool value)
1090 {
1091 uint32_t tmp;
1092 MCLK_CRITICAL_SECTION_ENTER();
1093 tmp = ((Mclk *)hw)->AHBMASK.reg;
1094 tmp &= ~MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER;
1095 tmp |= value << MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_Pos;
1096 ((Mclk *)hw)->AHBMASK.reg = tmp;
1097 MCLK_CRITICAL_SECTION_LEAVE();
1098 }
1099
hri_mclk_clear_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void * const hw)1100 static inline void hri_mclk_clear_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void *const hw)
1101 {
1102 MCLK_CRITICAL_SECTION_ENTER();
1103 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER;
1104 MCLK_CRITICAL_SECTION_LEAVE();
1105 }
1106
hri_mclk_toggle_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void * const hw)1107 static inline void hri_mclk_toggle_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER_bit(const void *const hw)
1108 {
1109 MCLK_CRITICAL_SECTION_ENTER();
1110 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMCRAMCHS_AHBSETUPKEEPER;
1111 MCLK_CRITICAL_SECTION_LEAVE();
1112 }
1113
hri_mclk_set_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void * const hw)1114 static inline void hri_mclk_set_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw)
1115 {
1116 MCLK_CRITICAL_SECTION_ENTER();
1117 ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE;
1118 MCLK_CRITICAL_SECTION_LEAVE();
1119 }
1120
hri_mclk_get_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void * const hw)1121 static inline bool hri_mclk_get_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw)
1122 {
1123 uint32_t tmp;
1124 tmp = ((Mclk *)hw)->AHBMASK.reg;
1125 tmp = (tmp & MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE)
1126 >> MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_Pos;
1127 return (bool)tmp;
1128 }
1129
hri_mclk_write_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void * const hw,bool value)1130 static inline void hri_mclk_write_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw, bool value)
1131 {
1132 uint32_t tmp;
1133 MCLK_CRITICAL_SECTION_ENTER();
1134 tmp = ((Mclk *)hw)->AHBMASK.reg;
1135 tmp &= ~MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE;
1136 tmp |= value << MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_Pos;
1137 ((Mclk *)hw)->AHBMASK.reg = tmp;
1138 MCLK_CRITICAL_SECTION_LEAVE();
1139 }
1140
hri_mclk_clear_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void * const hw)1141 static inline void hri_mclk_clear_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw)
1142 {
1143 MCLK_CRITICAL_SECTION_ENTER();
1144 ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE;
1145 MCLK_CRITICAL_SECTION_LEAVE();
1146 }
1147
hri_mclk_toggle_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void * const hw)1148 static inline void hri_mclk_toggle_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE_bit(const void *const hw)
1149 {
1150 MCLK_CRITICAL_SECTION_ENTER();
1151 ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMCRAMCHS_HMATRIXLP2HMCRAMCHSBRIDGE;
1152 MCLK_CRITICAL_SECTION_LEAVE();
1153 }
1154
hri_mclk_set_AHBMASK_reg(const void * const hw,hri_mclk_ahbmask_reg_t mask)1155 static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1156 {
1157 MCLK_CRITICAL_SECTION_ENTER();
1158 ((Mclk *)hw)->AHBMASK.reg |= mask;
1159 MCLK_CRITICAL_SECTION_LEAVE();
1160 }
1161
hri_mclk_get_AHBMASK_reg(const void * const hw,hri_mclk_ahbmask_reg_t mask)1162 static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1163 {
1164 uint32_t tmp;
1165 tmp = ((Mclk *)hw)->AHBMASK.reg;
1166 tmp &= mask;
1167 return tmp;
1168 }
1169
hri_mclk_write_AHBMASK_reg(const void * const hw,hri_mclk_ahbmask_reg_t data)1170 static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data)
1171 {
1172 MCLK_CRITICAL_SECTION_ENTER();
1173 ((Mclk *)hw)->AHBMASK.reg = data;
1174 MCLK_CRITICAL_SECTION_LEAVE();
1175 }
1176
hri_mclk_clear_AHBMASK_reg(const void * const hw,hri_mclk_ahbmask_reg_t mask)1177 static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1178 {
1179 MCLK_CRITICAL_SECTION_ENTER();
1180 ((Mclk *)hw)->AHBMASK.reg &= ~mask;
1181 MCLK_CRITICAL_SECTION_LEAVE();
1182 }
1183
hri_mclk_toggle_AHBMASK_reg(const void * const hw,hri_mclk_ahbmask_reg_t mask)1184 static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask)
1185 {
1186 MCLK_CRITICAL_SECTION_ENTER();
1187 ((Mclk *)hw)->AHBMASK.reg ^= mask;
1188 MCLK_CRITICAL_SECTION_LEAVE();
1189 }
1190
hri_mclk_read_AHBMASK_reg(const void * const hw)1191 static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw)
1192 {
1193 return ((Mclk *)hw)->AHBMASK.reg;
1194 }
1195
hri_mclk_set_APBAMASK_PM_bit(const void * const hw)1196 static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw)
1197 {
1198 MCLK_CRITICAL_SECTION_ENTER();
1199 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM;
1200 MCLK_CRITICAL_SECTION_LEAVE();
1201 }
1202
hri_mclk_get_APBAMASK_PM_bit(const void * const hw)1203 static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw)
1204 {
1205 uint32_t tmp;
1206 tmp = ((Mclk *)hw)->APBAMASK.reg;
1207 tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos;
1208 return (bool)tmp;
1209 }
1210
hri_mclk_write_APBAMASK_PM_bit(const void * const hw,bool value)1211 static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value)
1212 {
1213 uint32_t tmp;
1214 MCLK_CRITICAL_SECTION_ENTER();
1215 tmp = ((Mclk *)hw)->APBAMASK.reg;
1216 tmp &= ~MCLK_APBAMASK_PM;
1217 tmp |= value << MCLK_APBAMASK_PM_Pos;
1218 ((Mclk *)hw)->APBAMASK.reg = tmp;
1219 MCLK_CRITICAL_SECTION_LEAVE();
1220 }
1221
hri_mclk_clear_APBAMASK_PM_bit(const void * const hw)1222 static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw)
1223 {
1224 MCLK_CRITICAL_SECTION_ENTER();
1225 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM;
1226 MCLK_CRITICAL_SECTION_LEAVE();
1227 }
1228
hri_mclk_toggle_APBAMASK_PM_bit(const void * const hw)1229 static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw)
1230 {
1231 MCLK_CRITICAL_SECTION_ENTER();
1232 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM;
1233 MCLK_CRITICAL_SECTION_LEAVE();
1234 }
1235
hri_mclk_set_APBAMASK_MCLK_bit(const void * const hw)1236 static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw)
1237 {
1238 MCLK_CRITICAL_SECTION_ENTER();
1239 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK;
1240 MCLK_CRITICAL_SECTION_LEAVE();
1241 }
1242
hri_mclk_get_APBAMASK_MCLK_bit(const void * const hw)1243 static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw)
1244 {
1245 uint32_t tmp;
1246 tmp = ((Mclk *)hw)->APBAMASK.reg;
1247 tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos;
1248 return (bool)tmp;
1249 }
1250
hri_mclk_write_APBAMASK_MCLK_bit(const void * const hw,bool value)1251 static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value)
1252 {
1253 uint32_t tmp;
1254 MCLK_CRITICAL_SECTION_ENTER();
1255 tmp = ((Mclk *)hw)->APBAMASK.reg;
1256 tmp &= ~MCLK_APBAMASK_MCLK;
1257 tmp |= value << MCLK_APBAMASK_MCLK_Pos;
1258 ((Mclk *)hw)->APBAMASK.reg = tmp;
1259 MCLK_CRITICAL_SECTION_LEAVE();
1260 }
1261
hri_mclk_clear_APBAMASK_MCLK_bit(const void * const hw)1262 static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw)
1263 {
1264 MCLK_CRITICAL_SECTION_ENTER();
1265 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK;
1266 MCLK_CRITICAL_SECTION_LEAVE();
1267 }
1268
hri_mclk_toggle_APBAMASK_MCLK_bit(const void * const hw)1269 static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw)
1270 {
1271 MCLK_CRITICAL_SECTION_ENTER();
1272 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK;
1273 MCLK_CRITICAL_SECTION_LEAVE();
1274 }
1275
hri_mclk_set_APBAMASK_RSTC_bit(const void * const hw)1276 static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw)
1277 {
1278 MCLK_CRITICAL_SECTION_ENTER();
1279 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC;
1280 MCLK_CRITICAL_SECTION_LEAVE();
1281 }
1282
hri_mclk_get_APBAMASK_RSTC_bit(const void * const hw)1283 static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw)
1284 {
1285 uint32_t tmp;
1286 tmp = ((Mclk *)hw)->APBAMASK.reg;
1287 tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos;
1288 return (bool)tmp;
1289 }
1290
hri_mclk_write_APBAMASK_RSTC_bit(const void * const hw,bool value)1291 static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value)
1292 {
1293 uint32_t tmp;
1294 MCLK_CRITICAL_SECTION_ENTER();
1295 tmp = ((Mclk *)hw)->APBAMASK.reg;
1296 tmp &= ~MCLK_APBAMASK_RSTC;
1297 tmp |= value << MCLK_APBAMASK_RSTC_Pos;
1298 ((Mclk *)hw)->APBAMASK.reg = tmp;
1299 MCLK_CRITICAL_SECTION_LEAVE();
1300 }
1301
hri_mclk_clear_APBAMASK_RSTC_bit(const void * const hw)1302 static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw)
1303 {
1304 MCLK_CRITICAL_SECTION_ENTER();
1305 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC;
1306 MCLK_CRITICAL_SECTION_LEAVE();
1307 }
1308
hri_mclk_toggle_APBAMASK_RSTC_bit(const void * const hw)1309 static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw)
1310 {
1311 MCLK_CRITICAL_SECTION_ENTER();
1312 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC;
1313 MCLK_CRITICAL_SECTION_LEAVE();
1314 }
1315
hri_mclk_set_APBAMASK_OSCCTRL_bit(const void * const hw)1316 static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw)
1317 {
1318 MCLK_CRITICAL_SECTION_ENTER();
1319 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL;
1320 MCLK_CRITICAL_SECTION_LEAVE();
1321 }
1322
hri_mclk_get_APBAMASK_OSCCTRL_bit(const void * const hw)1323 static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw)
1324 {
1325 uint32_t tmp;
1326 tmp = ((Mclk *)hw)->APBAMASK.reg;
1327 tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos;
1328 return (bool)tmp;
1329 }
1330
hri_mclk_write_APBAMASK_OSCCTRL_bit(const void * const hw,bool value)1331 static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value)
1332 {
1333 uint32_t tmp;
1334 MCLK_CRITICAL_SECTION_ENTER();
1335 tmp = ((Mclk *)hw)->APBAMASK.reg;
1336 tmp &= ~MCLK_APBAMASK_OSCCTRL;
1337 tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos;
1338 ((Mclk *)hw)->APBAMASK.reg = tmp;
1339 MCLK_CRITICAL_SECTION_LEAVE();
1340 }
1341
hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void * const hw)1342 static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw)
1343 {
1344 MCLK_CRITICAL_SECTION_ENTER();
1345 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL;
1346 MCLK_CRITICAL_SECTION_LEAVE();
1347 }
1348
hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void * const hw)1349 static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw)
1350 {
1351 MCLK_CRITICAL_SECTION_ENTER();
1352 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL;
1353 MCLK_CRITICAL_SECTION_LEAVE();
1354 }
1355
hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void * const hw)1356 static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1357 {
1358 MCLK_CRITICAL_SECTION_ENTER();
1359 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL;
1360 MCLK_CRITICAL_SECTION_LEAVE();
1361 }
1362
hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void * const hw)1363 static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1364 {
1365 uint32_t tmp;
1366 tmp = ((Mclk *)hw)->APBAMASK.reg;
1367 tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos;
1368 return (bool)tmp;
1369 }
1370
hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void * const hw,bool value)1371 static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value)
1372 {
1373 uint32_t tmp;
1374 MCLK_CRITICAL_SECTION_ENTER();
1375 tmp = ((Mclk *)hw)->APBAMASK.reg;
1376 tmp &= ~MCLK_APBAMASK_OSC32KCTRL;
1377 tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos;
1378 ((Mclk *)hw)->APBAMASK.reg = tmp;
1379 MCLK_CRITICAL_SECTION_LEAVE();
1380 }
1381
hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void * const hw)1382 static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1383 {
1384 MCLK_CRITICAL_SECTION_ENTER();
1385 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL;
1386 MCLK_CRITICAL_SECTION_LEAVE();
1387 }
1388
hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void * const hw)1389 static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw)
1390 {
1391 MCLK_CRITICAL_SECTION_ENTER();
1392 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL;
1393 MCLK_CRITICAL_SECTION_LEAVE();
1394 }
1395
hri_mclk_set_APBAMASK_SUPC_bit(const void * const hw)1396 static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw)
1397 {
1398 MCLK_CRITICAL_SECTION_ENTER();
1399 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC;
1400 MCLK_CRITICAL_SECTION_LEAVE();
1401 }
1402
hri_mclk_get_APBAMASK_SUPC_bit(const void * const hw)1403 static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw)
1404 {
1405 uint32_t tmp;
1406 tmp = ((Mclk *)hw)->APBAMASK.reg;
1407 tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos;
1408 return (bool)tmp;
1409 }
1410
hri_mclk_write_APBAMASK_SUPC_bit(const void * const hw,bool value)1411 static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value)
1412 {
1413 uint32_t tmp;
1414 MCLK_CRITICAL_SECTION_ENTER();
1415 tmp = ((Mclk *)hw)->APBAMASK.reg;
1416 tmp &= ~MCLK_APBAMASK_SUPC;
1417 tmp |= value << MCLK_APBAMASK_SUPC_Pos;
1418 ((Mclk *)hw)->APBAMASK.reg = tmp;
1419 MCLK_CRITICAL_SECTION_LEAVE();
1420 }
1421
hri_mclk_clear_APBAMASK_SUPC_bit(const void * const hw)1422 static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw)
1423 {
1424 MCLK_CRITICAL_SECTION_ENTER();
1425 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC;
1426 MCLK_CRITICAL_SECTION_LEAVE();
1427 }
1428
hri_mclk_toggle_APBAMASK_SUPC_bit(const void * const hw)1429 static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw)
1430 {
1431 MCLK_CRITICAL_SECTION_ENTER();
1432 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC;
1433 MCLK_CRITICAL_SECTION_LEAVE();
1434 }
1435
hri_mclk_set_APBAMASK_GCLK_bit(const void * const hw)1436 static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw)
1437 {
1438 MCLK_CRITICAL_SECTION_ENTER();
1439 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK;
1440 MCLK_CRITICAL_SECTION_LEAVE();
1441 }
1442
hri_mclk_get_APBAMASK_GCLK_bit(const void * const hw)1443 static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw)
1444 {
1445 uint32_t tmp;
1446 tmp = ((Mclk *)hw)->APBAMASK.reg;
1447 tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos;
1448 return (bool)tmp;
1449 }
1450
hri_mclk_write_APBAMASK_GCLK_bit(const void * const hw,bool value)1451 static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value)
1452 {
1453 uint32_t tmp;
1454 MCLK_CRITICAL_SECTION_ENTER();
1455 tmp = ((Mclk *)hw)->APBAMASK.reg;
1456 tmp &= ~MCLK_APBAMASK_GCLK;
1457 tmp |= value << MCLK_APBAMASK_GCLK_Pos;
1458 ((Mclk *)hw)->APBAMASK.reg = tmp;
1459 MCLK_CRITICAL_SECTION_LEAVE();
1460 }
1461
hri_mclk_clear_APBAMASK_GCLK_bit(const void * const hw)1462 static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw)
1463 {
1464 MCLK_CRITICAL_SECTION_ENTER();
1465 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK;
1466 MCLK_CRITICAL_SECTION_LEAVE();
1467 }
1468
hri_mclk_toggle_APBAMASK_GCLK_bit(const void * const hw)1469 static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw)
1470 {
1471 MCLK_CRITICAL_SECTION_ENTER();
1472 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK;
1473 MCLK_CRITICAL_SECTION_LEAVE();
1474 }
1475
hri_mclk_set_APBAMASK_WDT_bit(const void * const hw)1476 static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw)
1477 {
1478 MCLK_CRITICAL_SECTION_ENTER();
1479 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT;
1480 MCLK_CRITICAL_SECTION_LEAVE();
1481 }
1482
hri_mclk_get_APBAMASK_WDT_bit(const void * const hw)1483 static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw)
1484 {
1485 uint32_t tmp;
1486 tmp = ((Mclk *)hw)->APBAMASK.reg;
1487 tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos;
1488 return (bool)tmp;
1489 }
1490
hri_mclk_write_APBAMASK_WDT_bit(const void * const hw,bool value)1491 static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value)
1492 {
1493 uint32_t tmp;
1494 MCLK_CRITICAL_SECTION_ENTER();
1495 tmp = ((Mclk *)hw)->APBAMASK.reg;
1496 tmp &= ~MCLK_APBAMASK_WDT;
1497 tmp |= value << MCLK_APBAMASK_WDT_Pos;
1498 ((Mclk *)hw)->APBAMASK.reg = tmp;
1499 MCLK_CRITICAL_SECTION_LEAVE();
1500 }
1501
hri_mclk_clear_APBAMASK_WDT_bit(const void * const hw)1502 static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw)
1503 {
1504 MCLK_CRITICAL_SECTION_ENTER();
1505 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT;
1506 MCLK_CRITICAL_SECTION_LEAVE();
1507 }
1508
hri_mclk_toggle_APBAMASK_WDT_bit(const void * const hw)1509 static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw)
1510 {
1511 MCLK_CRITICAL_SECTION_ENTER();
1512 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT;
1513 MCLK_CRITICAL_SECTION_LEAVE();
1514 }
1515
hri_mclk_set_APBAMASK_RTC_bit(const void * const hw)1516 static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw)
1517 {
1518 MCLK_CRITICAL_SECTION_ENTER();
1519 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC;
1520 MCLK_CRITICAL_SECTION_LEAVE();
1521 }
1522
hri_mclk_get_APBAMASK_RTC_bit(const void * const hw)1523 static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw)
1524 {
1525 uint32_t tmp;
1526 tmp = ((Mclk *)hw)->APBAMASK.reg;
1527 tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos;
1528 return (bool)tmp;
1529 }
1530
hri_mclk_write_APBAMASK_RTC_bit(const void * const hw,bool value)1531 static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value)
1532 {
1533 uint32_t tmp;
1534 MCLK_CRITICAL_SECTION_ENTER();
1535 tmp = ((Mclk *)hw)->APBAMASK.reg;
1536 tmp &= ~MCLK_APBAMASK_RTC;
1537 tmp |= value << MCLK_APBAMASK_RTC_Pos;
1538 ((Mclk *)hw)->APBAMASK.reg = tmp;
1539 MCLK_CRITICAL_SECTION_LEAVE();
1540 }
1541
hri_mclk_clear_APBAMASK_RTC_bit(const void * const hw)1542 static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw)
1543 {
1544 MCLK_CRITICAL_SECTION_ENTER();
1545 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC;
1546 MCLK_CRITICAL_SECTION_LEAVE();
1547 }
1548
hri_mclk_toggle_APBAMASK_RTC_bit(const void * const hw)1549 static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw)
1550 {
1551 MCLK_CRITICAL_SECTION_ENTER();
1552 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC;
1553 MCLK_CRITICAL_SECTION_LEAVE();
1554 }
1555
hri_mclk_set_APBAMASK_EIC_bit(const void * const hw)1556 static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw)
1557 {
1558 MCLK_CRITICAL_SECTION_ENTER();
1559 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC;
1560 MCLK_CRITICAL_SECTION_LEAVE();
1561 }
1562
hri_mclk_get_APBAMASK_EIC_bit(const void * const hw)1563 static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw)
1564 {
1565 uint32_t tmp;
1566 tmp = ((Mclk *)hw)->APBAMASK.reg;
1567 tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos;
1568 return (bool)tmp;
1569 }
1570
hri_mclk_write_APBAMASK_EIC_bit(const void * const hw,bool value)1571 static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value)
1572 {
1573 uint32_t tmp;
1574 MCLK_CRITICAL_SECTION_ENTER();
1575 tmp = ((Mclk *)hw)->APBAMASK.reg;
1576 tmp &= ~MCLK_APBAMASK_EIC;
1577 tmp |= value << MCLK_APBAMASK_EIC_Pos;
1578 ((Mclk *)hw)->APBAMASK.reg = tmp;
1579 MCLK_CRITICAL_SECTION_LEAVE();
1580 }
1581
hri_mclk_clear_APBAMASK_EIC_bit(const void * const hw)1582 static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw)
1583 {
1584 MCLK_CRITICAL_SECTION_ENTER();
1585 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC;
1586 MCLK_CRITICAL_SECTION_LEAVE();
1587 }
1588
hri_mclk_toggle_APBAMASK_EIC_bit(const void * const hw)1589 static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw)
1590 {
1591 MCLK_CRITICAL_SECTION_ENTER();
1592 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC;
1593 MCLK_CRITICAL_SECTION_LEAVE();
1594 }
1595
hri_mclk_set_APBAMASK_PORT_bit(const void * const hw)1596 static inline void hri_mclk_set_APBAMASK_PORT_bit(const void *const hw)
1597 {
1598 MCLK_CRITICAL_SECTION_ENTER();
1599 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PORT;
1600 MCLK_CRITICAL_SECTION_LEAVE();
1601 }
1602
hri_mclk_get_APBAMASK_PORT_bit(const void * const hw)1603 static inline bool hri_mclk_get_APBAMASK_PORT_bit(const void *const hw)
1604 {
1605 uint32_t tmp;
1606 tmp = ((Mclk *)hw)->APBAMASK.reg;
1607 tmp = (tmp & MCLK_APBAMASK_PORT) >> MCLK_APBAMASK_PORT_Pos;
1608 return (bool)tmp;
1609 }
1610
hri_mclk_write_APBAMASK_PORT_bit(const void * const hw,bool value)1611 static inline void hri_mclk_write_APBAMASK_PORT_bit(const void *const hw, bool value)
1612 {
1613 uint32_t tmp;
1614 MCLK_CRITICAL_SECTION_ENTER();
1615 tmp = ((Mclk *)hw)->APBAMASK.reg;
1616 tmp &= ~MCLK_APBAMASK_PORT;
1617 tmp |= value << MCLK_APBAMASK_PORT_Pos;
1618 ((Mclk *)hw)->APBAMASK.reg = tmp;
1619 MCLK_CRITICAL_SECTION_LEAVE();
1620 }
1621
hri_mclk_clear_APBAMASK_PORT_bit(const void * const hw)1622 static inline void hri_mclk_clear_APBAMASK_PORT_bit(const void *const hw)
1623 {
1624 MCLK_CRITICAL_SECTION_ENTER();
1625 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PORT;
1626 MCLK_CRITICAL_SECTION_LEAVE();
1627 }
1628
hri_mclk_toggle_APBAMASK_PORT_bit(const void * const hw)1629 static inline void hri_mclk_toggle_APBAMASK_PORT_bit(const void *const hw)
1630 {
1631 MCLK_CRITICAL_SECTION_ENTER();
1632 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PORT;
1633 MCLK_CRITICAL_SECTION_LEAVE();
1634 }
1635
hri_mclk_set_APBAMASK_TAL_bit(const void * const hw)1636 static inline void hri_mclk_set_APBAMASK_TAL_bit(const void *const hw)
1637 {
1638 MCLK_CRITICAL_SECTION_ENTER();
1639 ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TAL;
1640 MCLK_CRITICAL_SECTION_LEAVE();
1641 }
1642
hri_mclk_get_APBAMASK_TAL_bit(const void * const hw)1643 static inline bool hri_mclk_get_APBAMASK_TAL_bit(const void *const hw)
1644 {
1645 uint32_t tmp;
1646 tmp = ((Mclk *)hw)->APBAMASK.reg;
1647 tmp = (tmp & MCLK_APBAMASK_TAL) >> MCLK_APBAMASK_TAL_Pos;
1648 return (bool)tmp;
1649 }
1650
hri_mclk_write_APBAMASK_TAL_bit(const void * const hw,bool value)1651 static inline void hri_mclk_write_APBAMASK_TAL_bit(const void *const hw, bool value)
1652 {
1653 uint32_t tmp;
1654 MCLK_CRITICAL_SECTION_ENTER();
1655 tmp = ((Mclk *)hw)->APBAMASK.reg;
1656 tmp &= ~MCLK_APBAMASK_TAL;
1657 tmp |= value << MCLK_APBAMASK_TAL_Pos;
1658 ((Mclk *)hw)->APBAMASK.reg = tmp;
1659 MCLK_CRITICAL_SECTION_LEAVE();
1660 }
1661
hri_mclk_clear_APBAMASK_TAL_bit(const void * const hw)1662 static inline void hri_mclk_clear_APBAMASK_TAL_bit(const void *const hw)
1663 {
1664 MCLK_CRITICAL_SECTION_ENTER();
1665 ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TAL;
1666 MCLK_CRITICAL_SECTION_LEAVE();
1667 }
1668
hri_mclk_toggle_APBAMASK_TAL_bit(const void * const hw)1669 static inline void hri_mclk_toggle_APBAMASK_TAL_bit(const void *const hw)
1670 {
1671 MCLK_CRITICAL_SECTION_ENTER();
1672 ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TAL;
1673 MCLK_CRITICAL_SECTION_LEAVE();
1674 }
1675
hri_mclk_set_APBAMASK_reg(const void * const hw,hri_mclk_apbamask_reg_t mask)1676 static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1677 {
1678 MCLK_CRITICAL_SECTION_ENTER();
1679 ((Mclk *)hw)->APBAMASK.reg |= mask;
1680 MCLK_CRITICAL_SECTION_LEAVE();
1681 }
1682
hri_mclk_get_APBAMASK_reg(const void * const hw,hri_mclk_apbamask_reg_t mask)1683 static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1684 {
1685 uint32_t tmp;
1686 tmp = ((Mclk *)hw)->APBAMASK.reg;
1687 tmp &= mask;
1688 return tmp;
1689 }
1690
hri_mclk_write_APBAMASK_reg(const void * const hw,hri_mclk_apbamask_reg_t data)1691 static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data)
1692 {
1693 MCLK_CRITICAL_SECTION_ENTER();
1694 ((Mclk *)hw)->APBAMASK.reg = data;
1695 MCLK_CRITICAL_SECTION_LEAVE();
1696 }
1697
hri_mclk_clear_APBAMASK_reg(const void * const hw,hri_mclk_apbamask_reg_t mask)1698 static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1699 {
1700 MCLK_CRITICAL_SECTION_ENTER();
1701 ((Mclk *)hw)->APBAMASK.reg &= ~mask;
1702 MCLK_CRITICAL_SECTION_LEAVE();
1703 }
1704
hri_mclk_toggle_APBAMASK_reg(const void * const hw,hri_mclk_apbamask_reg_t mask)1705 static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask)
1706 {
1707 MCLK_CRITICAL_SECTION_ENTER();
1708 ((Mclk *)hw)->APBAMASK.reg ^= mask;
1709 MCLK_CRITICAL_SECTION_LEAVE();
1710 }
1711
hri_mclk_read_APBAMASK_reg(const void * const hw)1712 static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw)
1713 {
1714 return ((Mclk *)hw)->APBAMASK.reg;
1715 }
1716
hri_mclk_set_APBBMASK_USB_bit(const void * const hw)1717 static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw)
1718 {
1719 MCLK_CRITICAL_SECTION_ENTER();
1720 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB;
1721 MCLK_CRITICAL_SECTION_LEAVE();
1722 }
1723
hri_mclk_get_APBBMASK_USB_bit(const void * const hw)1724 static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw)
1725 {
1726 uint32_t tmp;
1727 tmp = ((Mclk *)hw)->APBBMASK.reg;
1728 tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos;
1729 return (bool)tmp;
1730 }
1731
hri_mclk_write_APBBMASK_USB_bit(const void * const hw,bool value)1732 static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value)
1733 {
1734 uint32_t tmp;
1735 MCLK_CRITICAL_SECTION_ENTER();
1736 tmp = ((Mclk *)hw)->APBBMASK.reg;
1737 tmp &= ~MCLK_APBBMASK_USB;
1738 tmp |= value << MCLK_APBBMASK_USB_Pos;
1739 ((Mclk *)hw)->APBBMASK.reg = tmp;
1740 MCLK_CRITICAL_SECTION_LEAVE();
1741 }
1742
hri_mclk_clear_APBBMASK_USB_bit(const void * const hw)1743 static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw)
1744 {
1745 MCLK_CRITICAL_SECTION_ENTER();
1746 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB;
1747 MCLK_CRITICAL_SECTION_LEAVE();
1748 }
1749
hri_mclk_toggle_APBBMASK_USB_bit(const void * const hw)1750 static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw)
1751 {
1752 MCLK_CRITICAL_SECTION_ENTER();
1753 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB;
1754 MCLK_CRITICAL_SECTION_LEAVE();
1755 }
1756
hri_mclk_set_APBBMASK_DSU_bit(const void * const hw)1757 static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw)
1758 {
1759 MCLK_CRITICAL_SECTION_ENTER();
1760 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU;
1761 MCLK_CRITICAL_SECTION_LEAVE();
1762 }
1763
hri_mclk_get_APBBMASK_DSU_bit(const void * const hw)1764 static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw)
1765 {
1766 uint32_t tmp;
1767 tmp = ((Mclk *)hw)->APBBMASK.reg;
1768 tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos;
1769 return (bool)tmp;
1770 }
1771
hri_mclk_write_APBBMASK_DSU_bit(const void * const hw,bool value)1772 static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value)
1773 {
1774 uint32_t tmp;
1775 MCLK_CRITICAL_SECTION_ENTER();
1776 tmp = ((Mclk *)hw)->APBBMASK.reg;
1777 tmp &= ~MCLK_APBBMASK_DSU;
1778 tmp |= value << MCLK_APBBMASK_DSU_Pos;
1779 ((Mclk *)hw)->APBBMASK.reg = tmp;
1780 MCLK_CRITICAL_SECTION_LEAVE();
1781 }
1782
hri_mclk_clear_APBBMASK_DSU_bit(const void * const hw)1783 static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw)
1784 {
1785 MCLK_CRITICAL_SECTION_ENTER();
1786 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU;
1787 MCLK_CRITICAL_SECTION_LEAVE();
1788 }
1789
hri_mclk_toggle_APBBMASK_DSU_bit(const void * const hw)1790 static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw)
1791 {
1792 MCLK_CRITICAL_SECTION_ENTER();
1793 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU;
1794 MCLK_CRITICAL_SECTION_LEAVE();
1795 }
1796
hri_mclk_set_APBBMASK_NVMCTRL_bit(const void * const hw)1797 static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw)
1798 {
1799 MCLK_CRITICAL_SECTION_ENTER();
1800 ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL;
1801 MCLK_CRITICAL_SECTION_LEAVE();
1802 }
1803
hri_mclk_get_APBBMASK_NVMCTRL_bit(const void * const hw)1804 static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw)
1805 {
1806 uint32_t tmp;
1807 tmp = ((Mclk *)hw)->APBBMASK.reg;
1808 tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos;
1809 return (bool)tmp;
1810 }
1811
hri_mclk_write_APBBMASK_NVMCTRL_bit(const void * const hw,bool value)1812 static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value)
1813 {
1814 uint32_t tmp;
1815 MCLK_CRITICAL_SECTION_ENTER();
1816 tmp = ((Mclk *)hw)->APBBMASK.reg;
1817 tmp &= ~MCLK_APBBMASK_NVMCTRL;
1818 tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos;
1819 ((Mclk *)hw)->APBBMASK.reg = tmp;
1820 MCLK_CRITICAL_SECTION_LEAVE();
1821 }
1822
hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void * const hw)1823 static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw)
1824 {
1825 MCLK_CRITICAL_SECTION_ENTER();
1826 ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL;
1827 MCLK_CRITICAL_SECTION_LEAVE();
1828 }
1829
hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void * const hw)1830 static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw)
1831 {
1832 MCLK_CRITICAL_SECTION_ENTER();
1833 ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL;
1834 MCLK_CRITICAL_SECTION_LEAVE();
1835 }
1836
hri_mclk_set_APBBMASK_reg(const void * const hw,hri_mclk_apbbmask_reg_t mask)1837 static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
1838 {
1839 MCLK_CRITICAL_SECTION_ENTER();
1840 ((Mclk *)hw)->APBBMASK.reg |= mask;
1841 MCLK_CRITICAL_SECTION_LEAVE();
1842 }
1843
hri_mclk_get_APBBMASK_reg(const void * const hw,hri_mclk_apbbmask_reg_t mask)1844 static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
1845 {
1846 uint32_t tmp;
1847 tmp = ((Mclk *)hw)->APBBMASK.reg;
1848 tmp &= mask;
1849 return tmp;
1850 }
1851
hri_mclk_write_APBBMASK_reg(const void * const hw,hri_mclk_apbbmask_reg_t data)1852 static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data)
1853 {
1854 MCLK_CRITICAL_SECTION_ENTER();
1855 ((Mclk *)hw)->APBBMASK.reg = data;
1856 MCLK_CRITICAL_SECTION_LEAVE();
1857 }
1858
hri_mclk_clear_APBBMASK_reg(const void * const hw,hri_mclk_apbbmask_reg_t mask)1859 static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
1860 {
1861 MCLK_CRITICAL_SECTION_ENTER();
1862 ((Mclk *)hw)->APBBMASK.reg &= ~mask;
1863 MCLK_CRITICAL_SECTION_LEAVE();
1864 }
1865
hri_mclk_toggle_APBBMASK_reg(const void * const hw,hri_mclk_apbbmask_reg_t mask)1866 static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask)
1867 {
1868 MCLK_CRITICAL_SECTION_ENTER();
1869 ((Mclk *)hw)->APBBMASK.reg ^= mask;
1870 MCLK_CRITICAL_SECTION_LEAVE();
1871 }
1872
hri_mclk_read_APBBMASK_reg(const void * const hw)1873 static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw)
1874 {
1875 return ((Mclk *)hw)->APBBMASK.reg;
1876 }
1877
hri_mclk_set_APBCMASK_SERCOM0_bit(const void * const hw)1878 static inline void hri_mclk_set_APBCMASK_SERCOM0_bit(const void *const hw)
1879 {
1880 MCLK_CRITICAL_SECTION_ENTER();
1881 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM0;
1882 MCLK_CRITICAL_SECTION_LEAVE();
1883 }
1884
hri_mclk_get_APBCMASK_SERCOM0_bit(const void * const hw)1885 static inline bool hri_mclk_get_APBCMASK_SERCOM0_bit(const void *const hw)
1886 {
1887 uint32_t tmp;
1888 tmp = ((Mclk *)hw)->APBCMASK.reg;
1889 tmp = (tmp & MCLK_APBCMASK_SERCOM0) >> MCLK_APBCMASK_SERCOM0_Pos;
1890 return (bool)tmp;
1891 }
1892
hri_mclk_write_APBCMASK_SERCOM0_bit(const void * const hw,bool value)1893 static inline void hri_mclk_write_APBCMASK_SERCOM0_bit(const void *const hw, bool value)
1894 {
1895 uint32_t tmp;
1896 MCLK_CRITICAL_SECTION_ENTER();
1897 tmp = ((Mclk *)hw)->APBCMASK.reg;
1898 tmp &= ~MCLK_APBCMASK_SERCOM0;
1899 tmp |= value << MCLK_APBCMASK_SERCOM0_Pos;
1900 ((Mclk *)hw)->APBCMASK.reg = tmp;
1901 MCLK_CRITICAL_SECTION_LEAVE();
1902 }
1903
hri_mclk_clear_APBCMASK_SERCOM0_bit(const void * const hw)1904 static inline void hri_mclk_clear_APBCMASK_SERCOM0_bit(const void *const hw)
1905 {
1906 MCLK_CRITICAL_SECTION_ENTER();
1907 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM0;
1908 MCLK_CRITICAL_SECTION_LEAVE();
1909 }
1910
hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void * const hw)1911 static inline void hri_mclk_toggle_APBCMASK_SERCOM0_bit(const void *const hw)
1912 {
1913 MCLK_CRITICAL_SECTION_ENTER();
1914 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM0;
1915 MCLK_CRITICAL_SECTION_LEAVE();
1916 }
1917
hri_mclk_set_APBCMASK_SERCOM1_bit(const void * const hw)1918 static inline void hri_mclk_set_APBCMASK_SERCOM1_bit(const void *const hw)
1919 {
1920 MCLK_CRITICAL_SECTION_ENTER();
1921 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM1;
1922 MCLK_CRITICAL_SECTION_LEAVE();
1923 }
1924
hri_mclk_get_APBCMASK_SERCOM1_bit(const void * const hw)1925 static inline bool hri_mclk_get_APBCMASK_SERCOM1_bit(const void *const hw)
1926 {
1927 uint32_t tmp;
1928 tmp = ((Mclk *)hw)->APBCMASK.reg;
1929 tmp = (tmp & MCLK_APBCMASK_SERCOM1) >> MCLK_APBCMASK_SERCOM1_Pos;
1930 return (bool)tmp;
1931 }
1932
hri_mclk_write_APBCMASK_SERCOM1_bit(const void * const hw,bool value)1933 static inline void hri_mclk_write_APBCMASK_SERCOM1_bit(const void *const hw, bool value)
1934 {
1935 uint32_t tmp;
1936 MCLK_CRITICAL_SECTION_ENTER();
1937 tmp = ((Mclk *)hw)->APBCMASK.reg;
1938 tmp &= ~MCLK_APBCMASK_SERCOM1;
1939 tmp |= value << MCLK_APBCMASK_SERCOM1_Pos;
1940 ((Mclk *)hw)->APBCMASK.reg = tmp;
1941 MCLK_CRITICAL_SECTION_LEAVE();
1942 }
1943
hri_mclk_clear_APBCMASK_SERCOM1_bit(const void * const hw)1944 static inline void hri_mclk_clear_APBCMASK_SERCOM1_bit(const void *const hw)
1945 {
1946 MCLK_CRITICAL_SECTION_ENTER();
1947 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM1;
1948 MCLK_CRITICAL_SECTION_LEAVE();
1949 }
1950
hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void * const hw)1951 static inline void hri_mclk_toggle_APBCMASK_SERCOM1_bit(const void *const hw)
1952 {
1953 MCLK_CRITICAL_SECTION_ENTER();
1954 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM1;
1955 MCLK_CRITICAL_SECTION_LEAVE();
1956 }
1957
hri_mclk_set_APBCMASK_SERCOM2_bit(const void * const hw)1958 static inline void hri_mclk_set_APBCMASK_SERCOM2_bit(const void *const hw)
1959 {
1960 MCLK_CRITICAL_SECTION_ENTER();
1961 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM2;
1962 MCLK_CRITICAL_SECTION_LEAVE();
1963 }
1964
hri_mclk_get_APBCMASK_SERCOM2_bit(const void * const hw)1965 static inline bool hri_mclk_get_APBCMASK_SERCOM2_bit(const void *const hw)
1966 {
1967 uint32_t tmp;
1968 tmp = ((Mclk *)hw)->APBCMASK.reg;
1969 tmp = (tmp & MCLK_APBCMASK_SERCOM2) >> MCLK_APBCMASK_SERCOM2_Pos;
1970 return (bool)tmp;
1971 }
1972
hri_mclk_write_APBCMASK_SERCOM2_bit(const void * const hw,bool value)1973 static inline void hri_mclk_write_APBCMASK_SERCOM2_bit(const void *const hw, bool value)
1974 {
1975 uint32_t tmp;
1976 MCLK_CRITICAL_SECTION_ENTER();
1977 tmp = ((Mclk *)hw)->APBCMASK.reg;
1978 tmp &= ~MCLK_APBCMASK_SERCOM2;
1979 tmp |= value << MCLK_APBCMASK_SERCOM2_Pos;
1980 ((Mclk *)hw)->APBCMASK.reg = tmp;
1981 MCLK_CRITICAL_SECTION_LEAVE();
1982 }
1983
hri_mclk_clear_APBCMASK_SERCOM2_bit(const void * const hw)1984 static inline void hri_mclk_clear_APBCMASK_SERCOM2_bit(const void *const hw)
1985 {
1986 MCLK_CRITICAL_SECTION_ENTER();
1987 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM2;
1988 MCLK_CRITICAL_SECTION_LEAVE();
1989 }
1990
hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void * const hw)1991 static inline void hri_mclk_toggle_APBCMASK_SERCOM2_bit(const void *const hw)
1992 {
1993 MCLK_CRITICAL_SECTION_ENTER();
1994 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM2;
1995 MCLK_CRITICAL_SECTION_LEAVE();
1996 }
1997
hri_mclk_set_APBCMASK_SERCOM3_bit(const void * const hw)1998 static inline void hri_mclk_set_APBCMASK_SERCOM3_bit(const void *const hw)
1999 {
2000 MCLK_CRITICAL_SECTION_ENTER();
2001 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM3;
2002 MCLK_CRITICAL_SECTION_LEAVE();
2003 }
2004
hri_mclk_get_APBCMASK_SERCOM3_bit(const void * const hw)2005 static inline bool hri_mclk_get_APBCMASK_SERCOM3_bit(const void *const hw)
2006 {
2007 uint32_t tmp;
2008 tmp = ((Mclk *)hw)->APBCMASK.reg;
2009 tmp = (tmp & MCLK_APBCMASK_SERCOM3) >> MCLK_APBCMASK_SERCOM3_Pos;
2010 return (bool)tmp;
2011 }
2012
hri_mclk_write_APBCMASK_SERCOM3_bit(const void * const hw,bool value)2013 static inline void hri_mclk_write_APBCMASK_SERCOM3_bit(const void *const hw, bool value)
2014 {
2015 uint32_t tmp;
2016 MCLK_CRITICAL_SECTION_ENTER();
2017 tmp = ((Mclk *)hw)->APBCMASK.reg;
2018 tmp &= ~MCLK_APBCMASK_SERCOM3;
2019 tmp |= value << MCLK_APBCMASK_SERCOM3_Pos;
2020 ((Mclk *)hw)->APBCMASK.reg = tmp;
2021 MCLK_CRITICAL_SECTION_LEAVE();
2022 }
2023
hri_mclk_clear_APBCMASK_SERCOM3_bit(const void * const hw)2024 static inline void hri_mclk_clear_APBCMASK_SERCOM3_bit(const void *const hw)
2025 {
2026 MCLK_CRITICAL_SECTION_ENTER();
2027 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM3;
2028 MCLK_CRITICAL_SECTION_LEAVE();
2029 }
2030
hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void * const hw)2031 static inline void hri_mclk_toggle_APBCMASK_SERCOM3_bit(const void *const hw)
2032 {
2033 MCLK_CRITICAL_SECTION_ENTER();
2034 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM3;
2035 MCLK_CRITICAL_SECTION_LEAVE();
2036 }
2037
hri_mclk_set_APBCMASK_SERCOM4_bit(const void * const hw)2038 static inline void hri_mclk_set_APBCMASK_SERCOM4_bit(const void *const hw)
2039 {
2040 MCLK_CRITICAL_SECTION_ENTER();
2041 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_SERCOM4;
2042 MCLK_CRITICAL_SECTION_LEAVE();
2043 }
2044
hri_mclk_get_APBCMASK_SERCOM4_bit(const void * const hw)2045 static inline bool hri_mclk_get_APBCMASK_SERCOM4_bit(const void *const hw)
2046 {
2047 uint32_t tmp;
2048 tmp = ((Mclk *)hw)->APBCMASK.reg;
2049 tmp = (tmp & MCLK_APBCMASK_SERCOM4) >> MCLK_APBCMASK_SERCOM4_Pos;
2050 return (bool)tmp;
2051 }
2052
hri_mclk_write_APBCMASK_SERCOM4_bit(const void * const hw,bool value)2053 static inline void hri_mclk_write_APBCMASK_SERCOM4_bit(const void *const hw, bool value)
2054 {
2055 uint32_t tmp;
2056 MCLK_CRITICAL_SECTION_ENTER();
2057 tmp = ((Mclk *)hw)->APBCMASK.reg;
2058 tmp &= ~MCLK_APBCMASK_SERCOM4;
2059 tmp |= value << MCLK_APBCMASK_SERCOM4_Pos;
2060 ((Mclk *)hw)->APBCMASK.reg = tmp;
2061 MCLK_CRITICAL_SECTION_LEAVE();
2062 }
2063
hri_mclk_clear_APBCMASK_SERCOM4_bit(const void * const hw)2064 static inline void hri_mclk_clear_APBCMASK_SERCOM4_bit(const void *const hw)
2065 {
2066 MCLK_CRITICAL_SECTION_ENTER();
2067 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_SERCOM4;
2068 MCLK_CRITICAL_SECTION_LEAVE();
2069 }
2070
hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void * const hw)2071 static inline void hri_mclk_toggle_APBCMASK_SERCOM4_bit(const void *const hw)
2072 {
2073 MCLK_CRITICAL_SECTION_ENTER();
2074 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_SERCOM4;
2075 MCLK_CRITICAL_SECTION_LEAVE();
2076 }
2077
hri_mclk_set_APBCMASK_TCC0_bit(const void * const hw)2078 static inline void hri_mclk_set_APBCMASK_TCC0_bit(const void *const hw)
2079 {
2080 MCLK_CRITICAL_SECTION_ENTER();
2081 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC0;
2082 MCLK_CRITICAL_SECTION_LEAVE();
2083 }
2084
hri_mclk_get_APBCMASK_TCC0_bit(const void * const hw)2085 static inline bool hri_mclk_get_APBCMASK_TCC0_bit(const void *const hw)
2086 {
2087 uint32_t tmp;
2088 tmp = ((Mclk *)hw)->APBCMASK.reg;
2089 tmp = (tmp & MCLK_APBCMASK_TCC0) >> MCLK_APBCMASK_TCC0_Pos;
2090 return (bool)tmp;
2091 }
2092
hri_mclk_write_APBCMASK_TCC0_bit(const void * const hw,bool value)2093 static inline void hri_mclk_write_APBCMASK_TCC0_bit(const void *const hw, bool value)
2094 {
2095 uint32_t tmp;
2096 MCLK_CRITICAL_SECTION_ENTER();
2097 tmp = ((Mclk *)hw)->APBCMASK.reg;
2098 tmp &= ~MCLK_APBCMASK_TCC0;
2099 tmp |= value << MCLK_APBCMASK_TCC0_Pos;
2100 ((Mclk *)hw)->APBCMASK.reg = tmp;
2101 MCLK_CRITICAL_SECTION_LEAVE();
2102 }
2103
hri_mclk_clear_APBCMASK_TCC0_bit(const void * const hw)2104 static inline void hri_mclk_clear_APBCMASK_TCC0_bit(const void *const hw)
2105 {
2106 MCLK_CRITICAL_SECTION_ENTER();
2107 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC0;
2108 MCLK_CRITICAL_SECTION_LEAVE();
2109 }
2110
hri_mclk_toggle_APBCMASK_TCC0_bit(const void * const hw)2111 static inline void hri_mclk_toggle_APBCMASK_TCC0_bit(const void *const hw)
2112 {
2113 MCLK_CRITICAL_SECTION_ENTER();
2114 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC0;
2115 MCLK_CRITICAL_SECTION_LEAVE();
2116 }
2117
hri_mclk_set_APBCMASK_TCC1_bit(const void * const hw)2118 static inline void hri_mclk_set_APBCMASK_TCC1_bit(const void *const hw)
2119 {
2120 MCLK_CRITICAL_SECTION_ENTER();
2121 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC1;
2122 MCLK_CRITICAL_SECTION_LEAVE();
2123 }
2124
hri_mclk_get_APBCMASK_TCC1_bit(const void * const hw)2125 static inline bool hri_mclk_get_APBCMASK_TCC1_bit(const void *const hw)
2126 {
2127 uint32_t tmp;
2128 tmp = ((Mclk *)hw)->APBCMASK.reg;
2129 tmp = (tmp & MCLK_APBCMASK_TCC1) >> MCLK_APBCMASK_TCC1_Pos;
2130 return (bool)tmp;
2131 }
2132
hri_mclk_write_APBCMASK_TCC1_bit(const void * const hw,bool value)2133 static inline void hri_mclk_write_APBCMASK_TCC1_bit(const void *const hw, bool value)
2134 {
2135 uint32_t tmp;
2136 MCLK_CRITICAL_SECTION_ENTER();
2137 tmp = ((Mclk *)hw)->APBCMASK.reg;
2138 tmp &= ~MCLK_APBCMASK_TCC1;
2139 tmp |= value << MCLK_APBCMASK_TCC1_Pos;
2140 ((Mclk *)hw)->APBCMASK.reg = tmp;
2141 MCLK_CRITICAL_SECTION_LEAVE();
2142 }
2143
hri_mclk_clear_APBCMASK_TCC1_bit(const void * const hw)2144 static inline void hri_mclk_clear_APBCMASK_TCC1_bit(const void *const hw)
2145 {
2146 MCLK_CRITICAL_SECTION_ENTER();
2147 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC1;
2148 MCLK_CRITICAL_SECTION_LEAVE();
2149 }
2150
hri_mclk_toggle_APBCMASK_TCC1_bit(const void * const hw)2151 static inline void hri_mclk_toggle_APBCMASK_TCC1_bit(const void *const hw)
2152 {
2153 MCLK_CRITICAL_SECTION_ENTER();
2154 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC1;
2155 MCLK_CRITICAL_SECTION_LEAVE();
2156 }
2157
hri_mclk_set_APBCMASK_TCC2_bit(const void * const hw)2158 static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw)
2159 {
2160 MCLK_CRITICAL_SECTION_ENTER();
2161 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2;
2162 MCLK_CRITICAL_SECTION_LEAVE();
2163 }
2164
hri_mclk_get_APBCMASK_TCC2_bit(const void * const hw)2165 static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw)
2166 {
2167 uint32_t tmp;
2168 tmp = ((Mclk *)hw)->APBCMASK.reg;
2169 tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos;
2170 return (bool)tmp;
2171 }
2172
hri_mclk_write_APBCMASK_TCC2_bit(const void * const hw,bool value)2173 static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value)
2174 {
2175 uint32_t tmp;
2176 MCLK_CRITICAL_SECTION_ENTER();
2177 tmp = ((Mclk *)hw)->APBCMASK.reg;
2178 tmp &= ~MCLK_APBCMASK_TCC2;
2179 tmp |= value << MCLK_APBCMASK_TCC2_Pos;
2180 ((Mclk *)hw)->APBCMASK.reg = tmp;
2181 MCLK_CRITICAL_SECTION_LEAVE();
2182 }
2183
hri_mclk_clear_APBCMASK_TCC2_bit(const void * const hw)2184 static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw)
2185 {
2186 MCLK_CRITICAL_SECTION_ENTER();
2187 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2;
2188 MCLK_CRITICAL_SECTION_LEAVE();
2189 }
2190
hri_mclk_toggle_APBCMASK_TCC2_bit(const void * const hw)2191 static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw)
2192 {
2193 MCLK_CRITICAL_SECTION_ENTER();
2194 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2;
2195 MCLK_CRITICAL_SECTION_LEAVE();
2196 }
2197
hri_mclk_set_APBCMASK_TC0_bit(const void * const hw)2198 static inline void hri_mclk_set_APBCMASK_TC0_bit(const void *const hw)
2199 {
2200 MCLK_CRITICAL_SECTION_ENTER();
2201 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC0;
2202 MCLK_CRITICAL_SECTION_LEAVE();
2203 }
2204
hri_mclk_get_APBCMASK_TC0_bit(const void * const hw)2205 static inline bool hri_mclk_get_APBCMASK_TC0_bit(const void *const hw)
2206 {
2207 uint32_t tmp;
2208 tmp = ((Mclk *)hw)->APBCMASK.reg;
2209 tmp = (tmp & MCLK_APBCMASK_TC0) >> MCLK_APBCMASK_TC0_Pos;
2210 return (bool)tmp;
2211 }
2212
hri_mclk_write_APBCMASK_TC0_bit(const void * const hw,bool value)2213 static inline void hri_mclk_write_APBCMASK_TC0_bit(const void *const hw, bool value)
2214 {
2215 uint32_t tmp;
2216 MCLK_CRITICAL_SECTION_ENTER();
2217 tmp = ((Mclk *)hw)->APBCMASK.reg;
2218 tmp &= ~MCLK_APBCMASK_TC0;
2219 tmp |= value << MCLK_APBCMASK_TC0_Pos;
2220 ((Mclk *)hw)->APBCMASK.reg = tmp;
2221 MCLK_CRITICAL_SECTION_LEAVE();
2222 }
2223
hri_mclk_clear_APBCMASK_TC0_bit(const void * const hw)2224 static inline void hri_mclk_clear_APBCMASK_TC0_bit(const void *const hw)
2225 {
2226 MCLK_CRITICAL_SECTION_ENTER();
2227 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC0;
2228 MCLK_CRITICAL_SECTION_LEAVE();
2229 }
2230
hri_mclk_toggle_APBCMASK_TC0_bit(const void * const hw)2231 static inline void hri_mclk_toggle_APBCMASK_TC0_bit(const void *const hw)
2232 {
2233 MCLK_CRITICAL_SECTION_ENTER();
2234 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC0;
2235 MCLK_CRITICAL_SECTION_LEAVE();
2236 }
2237
hri_mclk_set_APBCMASK_TC1_bit(const void * const hw)2238 static inline void hri_mclk_set_APBCMASK_TC1_bit(const void *const hw)
2239 {
2240 MCLK_CRITICAL_SECTION_ENTER();
2241 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC1;
2242 MCLK_CRITICAL_SECTION_LEAVE();
2243 }
2244
hri_mclk_get_APBCMASK_TC1_bit(const void * const hw)2245 static inline bool hri_mclk_get_APBCMASK_TC1_bit(const void *const hw)
2246 {
2247 uint32_t tmp;
2248 tmp = ((Mclk *)hw)->APBCMASK.reg;
2249 tmp = (tmp & MCLK_APBCMASK_TC1) >> MCLK_APBCMASK_TC1_Pos;
2250 return (bool)tmp;
2251 }
2252
hri_mclk_write_APBCMASK_TC1_bit(const void * const hw,bool value)2253 static inline void hri_mclk_write_APBCMASK_TC1_bit(const void *const hw, bool value)
2254 {
2255 uint32_t tmp;
2256 MCLK_CRITICAL_SECTION_ENTER();
2257 tmp = ((Mclk *)hw)->APBCMASK.reg;
2258 tmp &= ~MCLK_APBCMASK_TC1;
2259 tmp |= value << MCLK_APBCMASK_TC1_Pos;
2260 ((Mclk *)hw)->APBCMASK.reg = tmp;
2261 MCLK_CRITICAL_SECTION_LEAVE();
2262 }
2263
hri_mclk_clear_APBCMASK_TC1_bit(const void * const hw)2264 static inline void hri_mclk_clear_APBCMASK_TC1_bit(const void *const hw)
2265 {
2266 MCLK_CRITICAL_SECTION_ENTER();
2267 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC1;
2268 MCLK_CRITICAL_SECTION_LEAVE();
2269 }
2270
hri_mclk_toggle_APBCMASK_TC1_bit(const void * const hw)2271 static inline void hri_mclk_toggle_APBCMASK_TC1_bit(const void *const hw)
2272 {
2273 MCLK_CRITICAL_SECTION_ENTER();
2274 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC1;
2275 MCLK_CRITICAL_SECTION_LEAVE();
2276 }
2277
hri_mclk_set_APBCMASK_TC2_bit(const void * const hw)2278 static inline void hri_mclk_set_APBCMASK_TC2_bit(const void *const hw)
2279 {
2280 MCLK_CRITICAL_SECTION_ENTER();
2281 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC2;
2282 MCLK_CRITICAL_SECTION_LEAVE();
2283 }
2284
hri_mclk_get_APBCMASK_TC2_bit(const void * const hw)2285 static inline bool hri_mclk_get_APBCMASK_TC2_bit(const void *const hw)
2286 {
2287 uint32_t tmp;
2288 tmp = ((Mclk *)hw)->APBCMASK.reg;
2289 tmp = (tmp & MCLK_APBCMASK_TC2) >> MCLK_APBCMASK_TC2_Pos;
2290 return (bool)tmp;
2291 }
2292
hri_mclk_write_APBCMASK_TC2_bit(const void * const hw,bool value)2293 static inline void hri_mclk_write_APBCMASK_TC2_bit(const void *const hw, bool value)
2294 {
2295 uint32_t tmp;
2296 MCLK_CRITICAL_SECTION_ENTER();
2297 tmp = ((Mclk *)hw)->APBCMASK.reg;
2298 tmp &= ~MCLK_APBCMASK_TC2;
2299 tmp |= value << MCLK_APBCMASK_TC2_Pos;
2300 ((Mclk *)hw)->APBCMASK.reg = tmp;
2301 MCLK_CRITICAL_SECTION_LEAVE();
2302 }
2303
hri_mclk_clear_APBCMASK_TC2_bit(const void * const hw)2304 static inline void hri_mclk_clear_APBCMASK_TC2_bit(const void *const hw)
2305 {
2306 MCLK_CRITICAL_SECTION_ENTER();
2307 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC2;
2308 MCLK_CRITICAL_SECTION_LEAVE();
2309 }
2310
hri_mclk_toggle_APBCMASK_TC2_bit(const void * const hw)2311 static inline void hri_mclk_toggle_APBCMASK_TC2_bit(const void *const hw)
2312 {
2313 MCLK_CRITICAL_SECTION_ENTER();
2314 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC2;
2315 MCLK_CRITICAL_SECTION_LEAVE();
2316 }
2317
hri_mclk_set_APBCMASK_TC3_bit(const void * const hw)2318 static inline void hri_mclk_set_APBCMASK_TC3_bit(const void *const hw)
2319 {
2320 MCLK_CRITICAL_SECTION_ENTER();
2321 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC3;
2322 MCLK_CRITICAL_SECTION_LEAVE();
2323 }
2324
hri_mclk_get_APBCMASK_TC3_bit(const void * const hw)2325 static inline bool hri_mclk_get_APBCMASK_TC3_bit(const void *const hw)
2326 {
2327 uint32_t tmp;
2328 tmp = ((Mclk *)hw)->APBCMASK.reg;
2329 tmp = (tmp & MCLK_APBCMASK_TC3) >> MCLK_APBCMASK_TC3_Pos;
2330 return (bool)tmp;
2331 }
2332
hri_mclk_write_APBCMASK_TC3_bit(const void * const hw,bool value)2333 static inline void hri_mclk_write_APBCMASK_TC3_bit(const void *const hw, bool value)
2334 {
2335 uint32_t tmp;
2336 MCLK_CRITICAL_SECTION_ENTER();
2337 tmp = ((Mclk *)hw)->APBCMASK.reg;
2338 tmp &= ~MCLK_APBCMASK_TC3;
2339 tmp |= value << MCLK_APBCMASK_TC3_Pos;
2340 ((Mclk *)hw)->APBCMASK.reg = tmp;
2341 MCLK_CRITICAL_SECTION_LEAVE();
2342 }
2343
hri_mclk_clear_APBCMASK_TC3_bit(const void * const hw)2344 static inline void hri_mclk_clear_APBCMASK_TC3_bit(const void *const hw)
2345 {
2346 MCLK_CRITICAL_SECTION_ENTER();
2347 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC3;
2348 MCLK_CRITICAL_SECTION_LEAVE();
2349 }
2350
hri_mclk_toggle_APBCMASK_TC3_bit(const void * const hw)2351 static inline void hri_mclk_toggle_APBCMASK_TC3_bit(const void *const hw)
2352 {
2353 MCLK_CRITICAL_SECTION_ENTER();
2354 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC3;
2355 MCLK_CRITICAL_SECTION_LEAVE();
2356 }
2357
hri_mclk_set_APBCMASK_DAC_bit(const void * const hw)2358 static inline void hri_mclk_set_APBCMASK_DAC_bit(const void *const hw)
2359 {
2360 MCLK_CRITICAL_SECTION_ENTER();
2361 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_DAC;
2362 MCLK_CRITICAL_SECTION_LEAVE();
2363 }
2364
hri_mclk_get_APBCMASK_DAC_bit(const void * const hw)2365 static inline bool hri_mclk_get_APBCMASK_DAC_bit(const void *const hw)
2366 {
2367 uint32_t tmp;
2368 tmp = ((Mclk *)hw)->APBCMASK.reg;
2369 tmp = (tmp & MCLK_APBCMASK_DAC) >> MCLK_APBCMASK_DAC_Pos;
2370 return (bool)tmp;
2371 }
2372
hri_mclk_write_APBCMASK_DAC_bit(const void * const hw,bool value)2373 static inline void hri_mclk_write_APBCMASK_DAC_bit(const void *const hw, bool value)
2374 {
2375 uint32_t tmp;
2376 MCLK_CRITICAL_SECTION_ENTER();
2377 tmp = ((Mclk *)hw)->APBCMASK.reg;
2378 tmp &= ~MCLK_APBCMASK_DAC;
2379 tmp |= value << MCLK_APBCMASK_DAC_Pos;
2380 ((Mclk *)hw)->APBCMASK.reg = tmp;
2381 MCLK_CRITICAL_SECTION_LEAVE();
2382 }
2383
hri_mclk_clear_APBCMASK_DAC_bit(const void * const hw)2384 static inline void hri_mclk_clear_APBCMASK_DAC_bit(const void *const hw)
2385 {
2386 MCLK_CRITICAL_SECTION_ENTER();
2387 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_DAC;
2388 MCLK_CRITICAL_SECTION_LEAVE();
2389 }
2390
hri_mclk_toggle_APBCMASK_DAC_bit(const void * const hw)2391 static inline void hri_mclk_toggle_APBCMASK_DAC_bit(const void *const hw)
2392 {
2393 MCLK_CRITICAL_SECTION_ENTER();
2394 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_DAC;
2395 MCLK_CRITICAL_SECTION_LEAVE();
2396 }
2397
hri_mclk_set_APBCMASK_AES_bit(const void * const hw)2398 static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw)
2399 {
2400 MCLK_CRITICAL_SECTION_ENTER();
2401 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES;
2402 MCLK_CRITICAL_SECTION_LEAVE();
2403 }
2404
hri_mclk_get_APBCMASK_AES_bit(const void * const hw)2405 static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw)
2406 {
2407 uint32_t tmp;
2408 tmp = ((Mclk *)hw)->APBCMASK.reg;
2409 tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos;
2410 return (bool)tmp;
2411 }
2412
hri_mclk_write_APBCMASK_AES_bit(const void * const hw,bool value)2413 static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value)
2414 {
2415 uint32_t tmp;
2416 MCLK_CRITICAL_SECTION_ENTER();
2417 tmp = ((Mclk *)hw)->APBCMASK.reg;
2418 tmp &= ~MCLK_APBCMASK_AES;
2419 tmp |= value << MCLK_APBCMASK_AES_Pos;
2420 ((Mclk *)hw)->APBCMASK.reg = tmp;
2421 MCLK_CRITICAL_SECTION_LEAVE();
2422 }
2423
hri_mclk_clear_APBCMASK_AES_bit(const void * const hw)2424 static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw)
2425 {
2426 MCLK_CRITICAL_SECTION_ENTER();
2427 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES;
2428 MCLK_CRITICAL_SECTION_LEAVE();
2429 }
2430
hri_mclk_toggle_APBCMASK_AES_bit(const void * const hw)2431 static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw)
2432 {
2433 MCLK_CRITICAL_SECTION_ENTER();
2434 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES;
2435 MCLK_CRITICAL_SECTION_LEAVE();
2436 }
2437
hri_mclk_set_APBCMASK_TRNG_bit(const void * const hw)2438 static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw)
2439 {
2440 MCLK_CRITICAL_SECTION_ENTER();
2441 ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG;
2442 MCLK_CRITICAL_SECTION_LEAVE();
2443 }
2444
hri_mclk_get_APBCMASK_TRNG_bit(const void * const hw)2445 static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw)
2446 {
2447 uint32_t tmp;
2448 tmp = ((Mclk *)hw)->APBCMASK.reg;
2449 tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos;
2450 return (bool)tmp;
2451 }
2452
hri_mclk_write_APBCMASK_TRNG_bit(const void * const hw,bool value)2453 static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value)
2454 {
2455 uint32_t tmp;
2456 MCLK_CRITICAL_SECTION_ENTER();
2457 tmp = ((Mclk *)hw)->APBCMASK.reg;
2458 tmp &= ~MCLK_APBCMASK_TRNG;
2459 tmp |= value << MCLK_APBCMASK_TRNG_Pos;
2460 ((Mclk *)hw)->APBCMASK.reg = tmp;
2461 MCLK_CRITICAL_SECTION_LEAVE();
2462 }
2463
hri_mclk_clear_APBCMASK_TRNG_bit(const void * const hw)2464 static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw)
2465 {
2466 MCLK_CRITICAL_SECTION_ENTER();
2467 ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG;
2468 MCLK_CRITICAL_SECTION_LEAVE();
2469 }
2470
hri_mclk_toggle_APBCMASK_TRNG_bit(const void * const hw)2471 static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw)
2472 {
2473 MCLK_CRITICAL_SECTION_ENTER();
2474 ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG;
2475 MCLK_CRITICAL_SECTION_LEAVE();
2476 }
2477
hri_mclk_set_APBCMASK_reg(const void * const hw,hri_mclk_apbcmask_reg_t mask)2478 static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
2479 {
2480 MCLK_CRITICAL_SECTION_ENTER();
2481 ((Mclk *)hw)->APBCMASK.reg |= mask;
2482 MCLK_CRITICAL_SECTION_LEAVE();
2483 }
2484
hri_mclk_get_APBCMASK_reg(const void * const hw,hri_mclk_apbcmask_reg_t mask)2485 static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
2486 {
2487 uint32_t tmp;
2488 tmp = ((Mclk *)hw)->APBCMASK.reg;
2489 tmp &= mask;
2490 return tmp;
2491 }
2492
hri_mclk_write_APBCMASK_reg(const void * const hw,hri_mclk_apbcmask_reg_t data)2493 static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data)
2494 {
2495 MCLK_CRITICAL_SECTION_ENTER();
2496 ((Mclk *)hw)->APBCMASK.reg = data;
2497 MCLK_CRITICAL_SECTION_LEAVE();
2498 }
2499
hri_mclk_clear_APBCMASK_reg(const void * const hw,hri_mclk_apbcmask_reg_t mask)2500 static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
2501 {
2502 MCLK_CRITICAL_SECTION_ENTER();
2503 ((Mclk *)hw)->APBCMASK.reg &= ~mask;
2504 MCLK_CRITICAL_SECTION_LEAVE();
2505 }
2506
hri_mclk_toggle_APBCMASK_reg(const void * const hw,hri_mclk_apbcmask_reg_t mask)2507 static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask)
2508 {
2509 MCLK_CRITICAL_SECTION_ENTER();
2510 ((Mclk *)hw)->APBCMASK.reg ^= mask;
2511 MCLK_CRITICAL_SECTION_LEAVE();
2512 }
2513
hri_mclk_read_APBCMASK_reg(const void * const hw)2514 static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw)
2515 {
2516 return ((Mclk *)hw)->APBCMASK.reg;
2517 }
2518
hri_mclk_set_APBDMASK_EVSYS_bit(const void * const hw)2519 static inline void hri_mclk_set_APBDMASK_EVSYS_bit(const void *const hw)
2520 {
2521 MCLK_CRITICAL_SECTION_ENTER();
2522 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_EVSYS;
2523 MCLK_CRITICAL_SECTION_LEAVE();
2524 }
2525
hri_mclk_get_APBDMASK_EVSYS_bit(const void * const hw)2526 static inline bool hri_mclk_get_APBDMASK_EVSYS_bit(const void *const hw)
2527 {
2528 uint32_t tmp;
2529 tmp = ((Mclk *)hw)->APBDMASK.reg;
2530 tmp = (tmp & MCLK_APBDMASK_EVSYS) >> MCLK_APBDMASK_EVSYS_Pos;
2531 return (bool)tmp;
2532 }
2533
hri_mclk_write_APBDMASK_EVSYS_bit(const void * const hw,bool value)2534 static inline void hri_mclk_write_APBDMASK_EVSYS_bit(const void *const hw, bool value)
2535 {
2536 uint32_t tmp;
2537 MCLK_CRITICAL_SECTION_ENTER();
2538 tmp = ((Mclk *)hw)->APBDMASK.reg;
2539 tmp &= ~MCLK_APBDMASK_EVSYS;
2540 tmp |= value << MCLK_APBDMASK_EVSYS_Pos;
2541 ((Mclk *)hw)->APBDMASK.reg = tmp;
2542 MCLK_CRITICAL_SECTION_LEAVE();
2543 }
2544
hri_mclk_clear_APBDMASK_EVSYS_bit(const void * const hw)2545 static inline void hri_mclk_clear_APBDMASK_EVSYS_bit(const void *const hw)
2546 {
2547 MCLK_CRITICAL_SECTION_ENTER();
2548 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_EVSYS;
2549 MCLK_CRITICAL_SECTION_LEAVE();
2550 }
2551
hri_mclk_toggle_APBDMASK_EVSYS_bit(const void * const hw)2552 static inline void hri_mclk_toggle_APBDMASK_EVSYS_bit(const void *const hw)
2553 {
2554 MCLK_CRITICAL_SECTION_ENTER();
2555 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_EVSYS;
2556 MCLK_CRITICAL_SECTION_LEAVE();
2557 }
2558
hri_mclk_set_APBDMASK_SERCOM5_bit(const void * const hw)2559 static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw)
2560 {
2561 MCLK_CRITICAL_SECTION_ENTER();
2562 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5;
2563 MCLK_CRITICAL_SECTION_LEAVE();
2564 }
2565
hri_mclk_get_APBDMASK_SERCOM5_bit(const void * const hw)2566 static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw)
2567 {
2568 uint32_t tmp;
2569 tmp = ((Mclk *)hw)->APBDMASK.reg;
2570 tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos;
2571 return (bool)tmp;
2572 }
2573
hri_mclk_write_APBDMASK_SERCOM5_bit(const void * const hw,bool value)2574 static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value)
2575 {
2576 uint32_t tmp;
2577 MCLK_CRITICAL_SECTION_ENTER();
2578 tmp = ((Mclk *)hw)->APBDMASK.reg;
2579 tmp &= ~MCLK_APBDMASK_SERCOM5;
2580 tmp |= value << MCLK_APBDMASK_SERCOM5_Pos;
2581 ((Mclk *)hw)->APBDMASK.reg = tmp;
2582 MCLK_CRITICAL_SECTION_LEAVE();
2583 }
2584
hri_mclk_clear_APBDMASK_SERCOM5_bit(const void * const hw)2585 static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw)
2586 {
2587 MCLK_CRITICAL_SECTION_ENTER();
2588 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5;
2589 MCLK_CRITICAL_SECTION_LEAVE();
2590 }
2591
hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void * const hw)2592 static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw)
2593 {
2594 MCLK_CRITICAL_SECTION_ENTER();
2595 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5;
2596 MCLK_CRITICAL_SECTION_LEAVE();
2597 }
2598
hri_mclk_set_APBDMASK_TC4_bit(const void * const hw)2599 static inline void hri_mclk_set_APBDMASK_TC4_bit(const void *const hw)
2600 {
2601 MCLK_CRITICAL_SECTION_ENTER();
2602 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC4;
2603 MCLK_CRITICAL_SECTION_LEAVE();
2604 }
2605
hri_mclk_get_APBDMASK_TC4_bit(const void * const hw)2606 static inline bool hri_mclk_get_APBDMASK_TC4_bit(const void *const hw)
2607 {
2608 uint32_t tmp;
2609 tmp = ((Mclk *)hw)->APBDMASK.reg;
2610 tmp = (tmp & MCLK_APBDMASK_TC4) >> MCLK_APBDMASK_TC4_Pos;
2611 return (bool)tmp;
2612 }
2613
hri_mclk_write_APBDMASK_TC4_bit(const void * const hw,bool value)2614 static inline void hri_mclk_write_APBDMASK_TC4_bit(const void *const hw, bool value)
2615 {
2616 uint32_t tmp;
2617 MCLK_CRITICAL_SECTION_ENTER();
2618 tmp = ((Mclk *)hw)->APBDMASK.reg;
2619 tmp &= ~MCLK_APBDMASK_TC4;
2620 tmp |= value << MCLK_APBDMASK_TC4_Pos;
2621 ((Mclk *)hw)->APBDMASK.reg = tmp;
2622 MCLK_CRITICAL_SECTION_LEAVE();
2623 }
2624
hri_mclk_clear_APBDMASK_TC4_bit(const void * const hw)2625 static inline void hri_mclk_clear_APBDMASK_TC4_bit(const void *const hw)
2626 {
2627 MCLK_CRITICAL_SECTION_ENTER();
2628 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC4;
2629 MCLK_CRITICAL_SECTION_LEAVE();
2630 }
2631
hri_mclk_toggle_APBDMASK_TC4_bit(const void * const hw)2632 static inline void hri_mclk_toggle_APBDMASK_TC4_bit(const void *const hw)
2633 {
2634 MCLK_CRITICAL_SECTION_ENTER();
2635 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC4;
2636 MCLK_CRITICAL_SECTION_LEAVE();
2637 }
2638
hri_mclk_set_APBDMASK_ADC_bit(const void * const hw)2639 static inline void hri_mclk_set_APBDMASK_ADC_bit(const void *const hw)
2640 {
2641 MCLK_CRITICAL_SECTION_ENTER();
2642 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC;
2643 MCLK_CRITICAL_SECTION_LEAVE();
2644 }
2645
hri_mclk_get_APBDMASK_ADC_bit(const void * const hw)2646 static inline bool hri_mclk_get_APBDMASK_ADC_bit(const void *const hw)
2647 {
2648 uint32_t tmp;
2649 tmp = ((Mclk *)hw)->APBDMASK.reg;
2650 tmp = (tmp & MCLK_APBDMASK_ADC) >> MCLK_APBDMASK_ADC_Pos;
2651 return (bool)tmp;
2652 }
2653
hri_mclk_write_APBDMASK_ADC_bit(const void * const hw,bool value)2654 static inline void hri_mclk_write_APBDMASK_ADC_bit(const void *const hw, bool value)
2655 {
2656 uint32_t tmp;
2657 MCLK_CRITICAL_SECTION_ENTER();
2658 tmp = ((Mclk *)hw)->APBDMASK.reg;
2659 tmp &= ~MCLK_APBDMASK_ADC;
2660 tmp |= value << MCLK_APBDMASK_ADC_Pos;
2661 ((Mclk *)hw)->APBDMASK.reg = tmp;
2662 MCLK_CRITICAL_SECTION_LEAVE();
2663 }
2664
hri_mclk_clear_APBDMASK_ADC_bit(const void * const hw)2665 static inline void hri_mclk_clear_APBDMASK_ADC_bit(const void *const hw)
2666 {
2667 MCLK_CRITICAL_SECTION_ENTER();
2668 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC;
2669 MCLK_CRITICAL_SECTION_LEAVE();
2670 }
2671
hri_mclk_toggle_APBDMASK_ADC_bit(const void * const hw)2672 static inline void hri_mclk_toggle_APBDMASK_ADC_bit(const void *const hw)
2673 {
2674 MCLK_CRITICAL_SECTION_ENTER();
2675 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC;
2676 MCLK_CRITICAL_SECTION_LEAVE();
2677 }
2678
hri_mclk_set_APBDMASK_AC_bit(const void * const hw)2679 static inline void hri_mclk_set_APBDMASK_AC_bit(const void *const hw)
2680 {
2681 MCLK_CRITICAL_SECTION_ENTER();
2682 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_AC;
2683 MCLK_CRITICAL_SECTION_LEAVE();
2684 }
2685
hri_mclk_get_APBDMASK_AC_bit(const void * const hw)2686 static inline bool hri_mclk_get_APBDMASK_AC_bit(const void *const hw)
2687 {
2688 uint32_t tmp;
2689 tmp = ((Mclk *)hw)->APBDMASK.reg;
2690 tmp = (tmp & MCLK_APBDMASK_AC) >> MCLK_APBDMASK_AC_Pos;
2691 return (bool)tmp;
2692 }
2693
hri_mclk_write_APBDMASK_AC_bit(const void * const hw,bool value)2694 static inline void hri_mclk_write_APBDMASK_AC_bit(const void *const hw, bool value)
2695 {
2696 uint32_t tmp;
2697 MCLK_CRITICAL_SECTION_ENTER();
2698 tmp = ((Mclk *)hw)->APBDMASK.reg;
2699 tmp &= ~MCLK_APBDMASK_AC;
2700 tmp |= value << MCLK_APBDMASK_AC_Pos;
2701 ((Mclk *)hw)->APBDMASK.reg = tmp;
2702 MCLK_CRITICAL_SECTION_LEAVE();
2703 }
2704
hri_mclk_clear_APBDMASK_AC_bit(const void * const hw)2705 static inline void hri_mclk_clear_APBDMASK_AC_bit(const void *const hw)
2706 {
2707 MCLK_CRITICAL_SECTION_ENTER();
2708 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_AC;
2709 MCLK_CRITICAL_SECTION_LEAVE();
2710 }
2711
hri_mclk_toggle_APBDMASK_AC_bit(const void * const hw)2712 static inline void hri_mclk_toggle_APBDMASK_AC_bit(const void *const hw)
2713 {
2714 MCLK_CRITICAL_SECTION_ENTER();
2715 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_AC;
2716 MCLK_CRITICAL_SECTION_LEAVE();
2717 }
2718
hri_mclk_set_APBDMASK_PTC_bit(const void * const hw)2719 static inline void hri_mclk_set_APBDMASK_PTC_bit(const void *const hw)
2720 {
2721 MCLK_CRITICAL_SECTION_ENTER();
2722 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PTC;
2723 MCLK_CRITICAL_SECTION_LEAVE();
2724 }
2725
hri_mclk_get_APBDMASK_PTC_bit(const void * const hw)2726 static inline bool hri_mclk_get_APBDMASK_PTC_bit(const void *const hw)
2727 {
2728 uint32_t tmp;
2729 tmp = ((Mclk *)hw)->APBDMASK.reg;
2730 tmp = (tmp & MCLK_APBDMASK_PTC) >> MCLK_APBDMASK_PTC_Pos;
2731 return (bool)tmp;
2732 }
2733
hri_mclk_write_APBDMASK_PTC_bit(const void * const hw,bool value)2734 static inline void hri_mclk_write_APBDMASK_PTC_bit(const void *const hw, bool value)
2735 {
2736 uint32_t tmp;
2737 MCLK_CRITICAL_SECTION_ENTER();
2738 tmp = ((Mclk *)hw)->APBDMASK.reg;
2739 tmp &= ~MCLK_APBDMASK_PTC;
2740 tmp |= value << MCLK_APBDMASK_PTC_Pos;
2741 ((Mclk *)hw)->APBDMASK.reg = tmp;
2742 MCLK_CRITICAL_SECTION_LEAVE();
2743 }
2744
hri_mclk_clear_APBDMASK_PTC_bit(const void * const hw)2745 static inline void hri_mclk_clear_APBDMASK_PTC_bit(const void *const hw)
2746 {
2747 MCLK_CRITICAL_SECTION_ENTER();
2748 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PTC;
2749 MCLK_CRITICAL_SECTION_LEAVE();
2750 }
2751
hri_mclk_toggle_APBDMASK_PTC_bit(const void * const hw)2752 static inline void hri_mclk_toggle_APBDMASK_PTC_bit(const void *const hw)
2753 {
2754 MCLK_CRITICAL_SECTION_ENTER();
2755 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PTC;
2756 MCLK_CRITICAL_SECTION_LEAVE();
2757 }
2758
hri_mclk_set_APBDMASK_OPAMP_bit(const void * const hw)2759 static inline void hri_mclk_set_APBDMASK_OPAMP_bit(const void *const hw)
2760 {
2761 MCLK_CRITICAL_SECTION_ENTER();
2762 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_OPAMP;
2763 MCLK_CRITICAL_SECTION_LEAVE();
2764 }
2765
hri_mclk_get_APBDMASK_OPAMP_bit(const void * const hw)2766 static inline bool hri_mclk_get_APBDMASK_OPAMP_bit(const void *const hw)
2767 {
2768 uint32_t tmp;
2769 tmp = ((Mclk *)hw)->APBDMASK.reg;
2770 tmp = (tmp & MCLK_APBDMASK_OPAMP) >> MCLK_APBDMASK_OPAMP_Pos;
2771 return (bool)tmp;
2772 }
2773
hri_mclk_write_APBDMASK_OPAMP_bit(const void * const hw,bool value)2774 static inline void hri_mclk_write_APBDMASK_OPAMP_bit(const void *const hw, bool value)
2775 {
2776 uint32_t tmp;
2777 MCLK_CRITICAL_SECTION_ENTER();
2778 tmp = ((Mclk *)hw)->APBDMASK.reg;
2779 tmp &= ~MCLK_APBDMASK_OPAMP;
2780 tmp |= value << MCLK_APBDMASK_OPAMP_Pos;
2781 ((Mclk *)hw)->APBDMASK.reg = tmp;
2782 MCLK_CRITICAL_SECTION_LEAVE();
2783 }
2784
hri_mclk_clear_APBDMASK_OPAMP_bit(const void * const hw)2785 static inline void hri_mclk_clear_APBDMASK_OPAMP_bit(const void *const hw)
2786 {
2787 MCLK_CRITICAL_SECTION_ENTER();
2788 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_OPAMP;
2789 MCLK_CRITICAL_SECTION_LEAVE();
2790 }
2791
hri_mclk_toggle_APBDMASK_OPAMP_bit(const void * const hw)2792 static inline void hri_mclk_toggle_APBDMASK_OPAMP_bit(const void *const hw)
2793 {
2794 MCLK_CRITICAL_SECTION_ENTER();
2795 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_OPAMP;
2796 MCLK_CRITICAL_SECTION_LEAVE();
2797 }
2798
hri_mclk_set_APBDMASK_CCL_bit(const void * const hw)2799 static inline void hri_mclk_set_APBDMASK_CCL_bit(const void *const hw)
2800 {
2801 MCLK_CRITICAL_SECTION_ENTER();
2802 ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_CCL;
2803 MCLK_CRITICAL_SECTION_LEAVE();
2804 }
2805
hri_mclk_get_APBDMASK_CCL_bit(const void * const hw)2806 static inline bool hri_mclk_get_APBDMASK_CCL_bit(const void *const hw)
2807 {
2808 uint32_t tmp;
2809 tmp = ((Mclk *)hw)->APBDMASK.reg;
2810 tmp = (tmp & MCLK_APBDMASK_CCL) >> MCLK_APBDMASK_CCL_Pos;
2811 return (bool)tmp;
2812 }
2813
hri_mclk_write_APBDMASK_CCL_bit(const void * const hw,bool value)2814 static inline void hri_mclk_write_APBDMASK_CCL_bit(const void *const hw, bool value)
2815 {
2816 uint32_t tmp;
2817 MCLK_CRITICAL_SECTION_ENTER();
2818 tmp = ((Mclk *)hw)->APBDMASK.reg;
2819 tmp &= ~MCLK_APBDMASK_CCL;
2820 tmp |= value << MCLK_APBDMASK_CCL_Pos;
2821 ((Mclk *)hw)->APBDMASK.reg = tmp;
2822 MCLK_CRITICAL_SECTION_LEAVE();
2823 }
2824
hri_mclk_clear_APBDMASK_CCL_bit(const void * const hw)2825 static inline void hri_mclk_clear_APBDMASK_CCL_bit(const void *const hw)
2826 {
2827 MCLK_CRITICAL_SECTION_ENTER();
2828 ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_CCL;
2829 MCLK_CRITICAL_SECTION_LEAVE();
2830 }
2831
hri_mclk_toggle_APBDMASK_CCL_bit(const void * const hw)2832 static inline void hri_mclk_toggle_APBDMASK_CCL_bit(const void *const hw)
2833 {
2834 MCLK_CRITICAL_SECTION_ENTER();
2835 ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_CCL;
2836 MCLK_CRITICAL_SECTION_LEAVE();
2837 }
2838
hri_mclk_set_APBDMASK_reg(const void * const hw,hri_mclk_apbdmask_reg_t mask)2839 static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
2840 {
2841 MCLK_CRITICAL_SECTION_ENTER();
2842 ((Mclk *)hw)->APBDMASK.reg |= mask;
2843 MCLK_CRITICAL_SECTION_LEAVE();
2844 }
2845
hri_mclk_get_APBDMASK_reg(const void * const hw,hri_mclk_apbdmask_reg_t mask)2846 static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
2847 {
2848 uint32_t tmp;
2849 tmp = ((Mclk *)hw)->APBDMASK.reg;
2850 tmp &= mask;
2851 return tmp;
2852 }
2853
hri_mclk_write_APBDMASK_reg(const void * const hw,hri_mclk_apbdmask_reg_t data)2854 static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data)
2855 {
2856 MCLK_CRITICAL_SECTION_ENTER();
2857 ((Mclk *)hw)->APBDMASK.reg = data;
2858 MCLK_CRITICAL_SECTION_LEAVE();
2859 }
2860
hri_mclk_clear_APBDMASK_reg(const void * const hw,hri_mclk_apbdmask_reg_t mask)2861 static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
2862 {
2863 MCLK_CRITICAL_SECTION_ENTER();
2864 ((Mclk *)hw)->APBDMASK.reg &= ~mask;
2865 MCLK_CRITICAL_SECTION_LEAVE();
2866 }
2867
hri_mclk_toggle_APBDMASK_reg(const void * const hw,hri_mclk_apbdmask_reg_t mask)2868 static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask)
2869 {
2870 MCLK_CRITICAL_SECTION_ENTER();
2871 ((Mclk *)hw)->APBDMASK.reg ^= mask;
2872 MCLK_CRITICAL_SECTION_LEAVE();
2873 }
2874
hri_mclk_read_APBDMASK_reg(const void * const hw)2875 static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw)
2876 {
2877 return ((Mclk *)hw)->APBDMASK.reg;
2878 }
2879
hri_mclk_set_APBEMASK_PAC_bit(const void * const hw)2880 static inline void hri_mclk_set_APBEMASK_PAC_bit(const void *const hw)
2881 {
2882 MCLK_CRITICAL_SECTION_ENTER();
2883 ((Mclk *)hw)->APBEMASK.reg |= MCLK_APBEMASK_PAC;
2884 MCLK_CRITICAL_SECTION_LEAVE();
2885 }
2886
hri_mclk_get_APBEMASK_PAC_bit(const void * const hw)2887 static inline bool hri_mclk_get_APBEMASK_PAC_bit(const void *const hw)
2888 {
2889 uint32_t tmp;
2890 tmp = ((Mclk *)hw)->APBEMASK.reg;
2891 tmp = (tmp & MCLK_APBEMASK_PAC) >> MCLK_APBEMASK_PAC_Pos;
2892 return (bool)tmp;
2893 }
2894
hri_mclk_write_APBEMASK_PAC_bit(const void * const hw,bool value)2895 static inline void hri_mclk_write_APBEMASK_PAC_bit(const void *const hw, bool value)
2896 {
2897 uint32_t tmp;
2898 MCLK_CRITICAL_SECTION_ENTER();
2899 tmp = ((Mclk *)hw)->APBEMASK.reg;
2900 tmp &= ~MCLK_APBEMASK_PAC;
2901 tmp |= value << MCLK_APBEMASK_PAC_Pos;
2902 ((Mclk *)hw)->APBEMASK.reg = tmp;
2903 MCLK_CRITICAL_SECTION_LEAVE();
2904 }
2905
hri_mclk_clear_APBEMASK_PAC_bit(const void * const hw)2906 static inline void hri_mclk_clear_APBEMASK_PAC_bit(const void *const hw)
2907 {
2908 MCLK_CRITICAL_SECTION_ENTER();
2909 ((Mclk *)hw)->APBEMASK.reg &= ~MCLK_APBEMASK_PAC;
2910 MCLK_CRITICAL_SECTION_LEAVE();
2911 }
2912
hri_mclk_toggle_APBEMASK_PAC_bit(const void * const hw)2913 static inline void hri_mclk_toggle_APBEMASK_PAC_bit(const void *const hw)
2914 {
2915 MCLK_CRITICAL_SECTION_ENTER();
2916 ((Mclk *)hw)->APBEMASK.reg ^= MCLK_APBEMASK_PAC;
2917 MCLK_CRITICAL_SECTION_LEAVE();
2918 }
2919
hri_mclk_set_APBEMASK_reg(const void * const hw,hri_mclk_apbemask_reg_t mask)2920 static inline void hri_mclk_set_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask)
2921 {
2922 MCLK_CRITICAL_SECTION_ENTER();
2923 ((Mclk *)hw)->APBEMASK.reg |= mask;
2924 MCLK_CRITICAL_SECTION_LEAVE();
2925 }
2926
hri_mclk_get_APBEMASK_reg(const void * const hw,hri_mclk_apbemask_reg_t mask)2927 static inline hri_mclk_apbemask_reg_t hri_mclk_get_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask)
2928 {
2929 uint32_t tmp;
2930 tmp = ((Mclk *)hw)->APBEMASK.reg;
2931 tmp &= mask;
2932 return tmp;
2933 }
2934
hri_mclk_write_APBEMASK_reg(const void * const hw,hri_mclk_apbemask_reg_t data)2935 static inline void hri_mclk_write_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t data)
2936 {
2937 MCLK_CRITICAL_SECTION_ENTER();
2938 ((Mclk *)hw)->APBEMASK.reg = data;
2939 MCLK_CRITICAL_SECTION_LEAVE();
2940 }
2941
hri_mclk_clear_APBEMASK_reg(const void * const hw,hri_mclk_apbemask_reg_t mask)2942 static inline void hri_mclk_clear_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask)
2943 {
2944 MCLK_CRITICAL_SECTION_ENTER();
2945 ((Mclk *)hw)->APBEMASK.reg &= ~mask;
2946 MCLK_CRITICAL_SECTION_LEAVE();
2947 }
2948
hri_mclk_toggle_APBEMASK_reg(const void * const hw,hri_mclk_apbemask_reg_t mask)2949 static inline void hri_mclk_toggle_APBEMASK_reg(const void *const hw, hri_mclk_apbemask_reg_t mask)
2950 {
2951 MCLK_CRITICAL_SECTION_ENTER();
2952 ((Mclk *)hw)->APBEMASK.reg ^= mask;
2953 MCLK_CRITICAL_SECTION_LEAVE();
2954 }
2955
hri_mclk_read_APBEMASK_reg(const void * const hw)2956 static inline hri_mclk_apbemask_reg_t hri_mclk_read_APBEMASK_reg(const void *const hw)
2957 {
2958 return ((Mclk *)hw)->APBEMASK.reg;
2959 }
2960
2961 #ifdef __cplusplus
2962 }
2963 #endif
2964
2965 #endif /* _HRI_MCLK_L21_H_INCLUDED */
2966 #endif /* _SAML21_MCLK_COMPONENT_ */
2967
