1 /**
2 * \file
3 *
4 * \brief SAM DMAC
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_DMAC_COMPONENT_
44 #ifndef _HRI_DMAC_L21_H_INCLUDED_
45 #define _HRI_DMAC_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_DMAC_CRITICAL_SECTIONS)
55 #define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define DMAC_CRITICAL_SECTION_ENTER()
59 #define DMAC_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_dmac_crcctrl_reg_t;
63 typedef uint16_t hri_dmac_ctrl_reg_t;
64 typedef uint16_t hri_dmac_intpend_reg_t;
65 typedef uint16_t hri_dmacdescriptor_btcnt_reg_t;
66 typedef uint16_t hri_dmacdescriptor_btctrl_reg_t;
67 typedef uint32_t hri_dmac_active_reg_t;
68 typedef uint32_t hri_dmac_baseaddr_reg_t;
69 typedef uint32_t hri_dmac_busych_reg_t;
70 typedef uint32_t hri_dmac_chctrlb_reg_t;
71 typedef uint32_t hri_dmac_crcchksum_reg_t;
72 typedef uint32_t hri_dmac_crcdatain_reg_t;
73 typedef uint32_t hri_dmac_intstatus_reg_t;
74 typedef uint32_t hri_dmac_pendch_reg_t;
75 typedef uint32_t hri_dmac_prictrl0_reg_t;
76 typedef uint32_t hri_dmac_swtrigctrl_reg_t;
77 typedef uint32_t hri_dmac_wrbaddr_reg_t;
78 typedef uint32_t hri_dmacdescriptor_descaddr_reg_t;
79 typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t;
80 typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t;
81 typedef uint8_t hri_dmac_chctrla_reg_t;
82 typedef uint8_t hri_dmac_chid_reg_t;
83 typedef uint8_t hri_dmac_chintenset_reg_t;
84 typedef uint8_t hri_dmac_chintflag_reg_t;
85 typedef uint8_t hri_dmac_chstatus_reg_t;
86 typedef uint8_t hri_dmac_crcstatus_reg_t;
87 typedef uint8_t hri_dmac_dbgctrl_reg_t;
88 typedef uint8_t hri_dmac_qosctrl_reg_t;
89
hri_dmac_set_CHINTEN_TERR_bit(const void * const hw)90 static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw)
91 {
92 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
93 }
94
hri_dmac_get_CHINTEN_TERR_bit(const void * const hw)95 static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw)
96 {
97 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos;
98 }
99
hri_dmac_write_CHINTEN_TERR_bit(const void * const hw,bool value)100 static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, bool value)
101 {
102 if (value == 0x0) {
103 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
104 } else {
105 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR;
106 }
107 }
108
hri_dmac_clear_CHINTEN_TERR_bit(const void * const hw)109 static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw)
110 {
111 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR;
112 }
113
hri_dmac_set_CHINTEN_TCMPL_bit(const void * const hw)114 static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw)
115 {
116 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
117 }
118
hri_dmac_get_CHINTEN_TCMPL_bit(const void * const hw)119 static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw)
120 {
121 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos;
122 }
123
hri_dmac_write_CHINTEN_TCMPL_bit(const void * const hw,bool value)124 static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, bool value)
125 {
126 if (value == 0x0) {
127 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
128 } else {
129 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL;
130 }
131 }
132
hri_dmac_clear_CHINTEN_TCMPL_bit(const void * const hw)133 static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw)
134 {
135 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL;
136 }
137
hri_dmac_set_CHINTEN_SUSP_bit(const void * const hw)138 static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw)
139 {
140 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
141 }
142
hri_dmac_get_CHINTEN_SUSP_bit(const void * const hw)143 static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw)
144 {
145 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos;
146 }
147
hri_dmac_write_CHINTEN_SUSP_bit(const void * const hw,bool value)148 static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, bool value)
149 {
150 if (value == 0x0) {
151 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
152 } else {
153 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP;
154 }
155 }
156
hri_dmac_clear_CHINTEN_SUSP_bit(const void * const hw)157 static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw)
158 {
159 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP;
160 }
161
hri_dmac_set_CHINTEN_reg(const void * const hw,hri_dmac_chintenset_reg_t mask)162 static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
163 {
164 ((Dmac *)hw)->CHINTENSET.reg = mask;
165 }
166
hri_dmac_get_CHINTEN_reg(const void * const hw,hri_dmac_chintenset_reg_t mask)167 static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
168 {
169 uint8_t tmp;
170 tmp = ((Dmac *)hw)->CHINTENSET.reg;
171 tmp &= mask;
172 return tmp;
173 }
174
hri_dmac_read_CHINTEN_reg(const void * const hw)175 static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw)
176 {
177 return ((Dmac *)hw)->CHINTENSET.reg;
178 }
179
hri_dmac_write_CHINTEN_reg(const void * const hw,hri_dmac_chintenset_reg_t data)180 static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data)
181 {
182 ((Dmac *)hw)->CHINTENSET.reg = data;
183 ((Dmac *)hw)->CHINTENCLR.reg = ~data;
184 }
185
hri_dmac_clear_CHINTEN_reg(const void * const hw,hri_dmac_chintenset_reg_t mask)186 static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask)
187 {
188 ((Dmac *)hw)->CHINTENCLR.reg = mask;
189 }
190
hri_dmac_get_CHINTFLAG_TERR_bit(const void * const hw)191 static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw)
192 {
193 return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
194 }
195
hri_dmac_clear_CHINTFLAG_TERR_bit(const void * const hw)196 static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw)
197 {
198 ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
199 }
200
hri_dmac_get_CHINTFLAG_TCMPL_bit(const void * const hw)201 static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw)
202 {
203 return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
204 }
205
hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void * const hw)206 static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw)
207 {
208 ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
209 }
210
hri_dmac_get_CHINTFLAG_SUSP_bit(const void * const hw)211 static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw)
212 {
213 return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
214 }
215
hri_dmac_clear_CHINTFLAG_SUSP_bit(const void * const hw)216 static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw)
217 {
218 ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
219 }
220
hri_dmac_get_interrupt_TERR_bit(const void * const hw)221 static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw)
222 {
223 return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos;
224 }
225
hri_dmac_clear_interrupt_TERR_bit(const void * const hw)226 static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw)
227 {
228 ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR;
229 }
230
hri_dmac_get_interrupt_TCMPL_bit(const void * const hw)231 static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw)
232 {
233 return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos;
234 }
235
hri_dmac_clear_interrupt_TCMPL_bit(const void * const hw)236 static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw)
237 {
238 ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL;
239 }
240
hri_dmac_get_interrupt_SUSP_bit(const void * const hw)241 static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw)
242 {
243 return (((Dmac *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos;
244 }
245
hri_dmac_clear_interrupt_SUSP_bit(const void * const hw)246 static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw)
247 {
248 ((Dmac *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP;
249 }
250
hri_dmac_get_CHINTFLAG_reg(const void * const hw,hri_dmac_chintflag_reg_t mask)251 static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
252 {
253 uint8_t tmp;
254 tmp = ((Dmac *)hw)->CHINTFLAG.reg;
255 tmp &= mask;
256 return tmp;
257 }
258
hri_dmac_read_CHINTFLAG_reg(const void * const hw)259 static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw)
260 {
261 return ((Dmac *)hw)->CHINTFLAG.reg;
262 }
263
hri_dmac_clear_CHINTFLAG_reg(const void * const hw,hri_dmac_chintflag_reg_t mask)264 static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask)
265 {
266 ((Dmac *)hw)->CHINTFLAG.reg = mask;
267 }
268
hri_dmac_set_CTRL_SWRST_bit(const void * const hw)269 static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw)
270 {
271 DMAC_CRITICAL_SECTION_ENTER();
272 ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST;
273 DMAC_CRITICAL_SECTION_LEAVE();
274 }
275
hri_dmac_get_CTRL_SWRST_bit(const void * const hw)276 static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw)
277 {
278 uint16_t tmp;
279 tmp = ((Dmac *)hw)->CTRL.reg;
280 tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos;
281 return (bool)tmp;
282 }
283
hri_dmac_set_CTRL_DMAENABLE_bit(const void * const hw)284 static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw)
285 {
286 DMAC_CRITICAL_SECTION_ENTER();
287 ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE;
288 DMAC_CRITICAL_SECTION_LEAVE();
289 }
290
hri_dmac_get_CTRL_DMAENABLE_bit(const void * const hw)291 static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw)
292 {
293 uint16_t tmp;
294 tmp = ((Dmac *)hw)->CTRL.reg;
295 tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos;
296 return (bool)tmp;
297 }
298
hri_dmac_write_CTRL_DMAENABLE_bit(const void * const hw,bool value)299 static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value)
300 {
301 uint16_t tmp;
302 DMAC_CRITICAL_SECTION_ENTER();
303 tmp = ((Dmac *)hw)->CTRL.reg;
304 tmp &= ~DMAC_CTRL_DMAENABLE;
305 tmp |= value << DMAC_CTRL_DMAENABLE_Pos;
306 ((Dmac *)hw)->CTRL.reg = tmp;
307 DMAC_CRITICAL_SECTION_LEAVE();
308 }
309
hri_dmac_clear_CTRL_DMAENABLE_bit(const void * const hw)310 static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw)
311 {
312 DMAC_CRITICAL_SECTION_ENTER();
313 ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
314 DMAC_CRITICAL_SECTION_LEAVE();
315 }
316
hri_dmac_toggle_CTRL_DMAENABLE_bit(const void * const hw)317 static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw)
318 {
319 DMAC_CRITICAL_SECTION_ENTER();
320 ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE;
321 DMAC_CRITICAL_SECTION_LEAVE();
322 }
323
hri_dmac_set_CTRL_CRCENABLE_bit(const void * const hw)324 static inline void hri_dmac_set_CTRL_CRCENABLE_bit(const void *const hw)
325 {
326 DMAC_CRITICAL_SECTION_ENTER();
327 ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_CRCENABLE;
328 DMAC_CRITICAL_SECTION_LEAVE();
329 }
330
hri_dmac_get_CTRL_CRCENABLE_bit(const void * const hw)331 static inline bool hri_dmac_get_CTRL_CRCENABLE_bit(const void *const hw)
332 {
333 uint16_t tmp;
334 tmp = ((Dmac *)hw)->CTRL.reg;
335 tmp = (tmp & DMAC_CTRL_CRCENABLE) >> DMAC_CTRL_CRCENABLE_Pos;
336 return (bool)tmp;
337 }
338
hri_dmac_write_CTRL_CRCENABLE_bit(const void * const hw,bool value)339 static inline void hri_dmac_write_CTRL_CRCENABLE_bit(const void *const hw, bool value)
340 {
341 uint16_t tmp;
342 DMAC_CRITICAL_SECTION_ENTER();
343 tmp = ((Dmac *)hw)->CTRL.reg;
344 tmp &= ~DMAC_CTRL_CRCENABLE;
345 tmp |= value << DMAC_CTRL_CRCENABLE_Pos;
346 ((Dmac *)hw)->CTRL.reg = tmp;
347 DMAC_CRITICAL_SECTION_LEAVE();
348 }
349
hri_dmac_clear_CTRL_CRCENABLE_bit(const void * const hw)350 static inline void hri_dmac_clear_CTRL_CRCENABLE_bit(const void *const hw)
351 {
352 DMAC_CRITICAL_SECTION_ENTER();
353 ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_CRCENABLE;
354 DMAC_CRITICAL_SECTION_LEAVE();
355 }
356
hri_dmac_toggle_CTRL_CRCENABLE_bit(const void * const hw)357 static inline void hri_dmac_toggle_CTRL_CRCENABLE_bit(const void *const hw)
358 {
359 DMAC_CRITICAL_SECTION_ENTER();
360 ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_CRCENABLE;
361 DMAC_CRITICAL_SECTION_LEAVE();
362 }
363
hri_dmac_set_CTRL_LVLEN0_bit(const void * const hw)364 static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw)
365 {
366 DMAC_CRITICAL_SECTION_ENTER();
367 ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0;
368 DMAC_CRITICAL_SECTION_LEAVE();
369 }
370
hri_dmac_get_CTRL_LVLEN0_bit(const void * const hw)371 static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw)
372 {
373 uint16_t tmp;
374 tmp = ((Dmac *)hw)->CTRL.reg;
375 tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos;
376 return (bool)tmp;
377 }
378
hri_dmac_write_CTRL_LVLEN0_bit(const void * const hw,bool value)379 static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value)
380 {
381 uint16_t tmp;
382 DMAC_CRITICAL_SECTION_ENTER();
383 tmp = ((Dmac *)hw)->CTRL.reg;
384 tmp &= ~DMAC_CTRL_LVLEN0;
385 tmp |= value << DMAC_CTRL_LVLEN0_Pos;
386 ((Dmac *)hw)->CTRL.reg = tmp;
387 DMAC_CRITICAL_SECTION_LEAVE();
388 }
389
hri_dmac_clear_CTRL_LVLEN0_bit(const void * const hw)390 static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw)
391 {
392 DMAC_CRITICAL_SECTION_ENTER();
393 ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0;
394 DMAC_CRITICAL_SECTION_LEAVE();
395 }
396
hri_dmac_toggle_CTRL_LVLEN0_bit(const void * const hw)397 static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw)
398 {
399 DMAC_CRITICAL_SECTION_ENTER();
400 ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0;
401 DMAC_CRITICAL_SECTION_LEAVE();
402 }
403
hri_dmac_set_CTRL_LVLEN1_bit(const void * const hw)404 static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw)
405 {
406 DMAC_CRITICAL_SECTION_ENTER();
407 ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1;
408 DMAC_CRITICAL_SECTION_LEAVE();
409 }
410
hri_dmac_get_CTRL_LVLEN1_bit(const void * const hw)411 static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw)
412 {
413 uint16_t tmp;
414 tmp = ((Dmac *)hw)->CTRL.reg;
415 tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos;
416 return (bool)tmp;
417 }
418
hri_dmac_write_CTRL_LVLEN1_bit(const void * const hw,bool value)419 static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value)
420 {
421 uint16_t tmp;
422 DMAC_CRITICAL_SECTION_ENTER();
423 tmp = ((Dmac *)hw)->CTRL.reg;
424 tmp &= ~DMAC_CTRL_LVLEN1;
425 tmp |= value << DMAC_CTRL_LVLEN1_Pos;
426 ((Dmac *)hw)->CTRL.reg = tmp;
427 DMAC_CRITICAL_SECTION_LEAVE();
428 }
429
hri_dmac_clear_CTRL_LVLEN1_bit(const void * const hw)430 static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw)
431 {
432 DMAC_CRITICAL_SECTION_ENTER();
433 ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1;
434 DMAC_CRITICAL_SECTION_LEAVE();
435 }
436
hri_dmac_toggle_CTRL_LVLEN1_bit(const void * const hw)437 static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw)
438 {
439 DMAC_CRITICAL_SECTION_ENTER();
440 ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1;
441 DMAC_CRITICAL_SECTION_LEAVE();
442 }
443
hri_dmac_set_CTRL_LVLEN2_bit(const void * const hw)444 static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw)
445 {
446 DMAC_CRITICAL_SECTION_ENTER();
447 ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2;
448 DMAC_CRITICAL_SECTION_LEAVE();
449 }
450
hri_dmac_get_CTRL_LVLEN2_bit(const void * const hw)451 static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw)
452 {
453 uint16_t tmp;
454 tmp = ((Dmac *)hw)->CTRL.reg;
455 tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos;
456 return (bool)tmp;
457 }
458
hri_dmac_write_CTRL_LVLEN2_bit(const void * const hw,bool value)459 static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value)
460 {
461 uint16_t tmp;
462 DMAC_CRITICAL_SECTION_ENTER();
463 tmp = ((Dmac *)hw)->CTRL.reg;
464 tmp &= ~DMAC_CTRL_LVLEN2;
465 tmp |= value << DMAC_CTRL_LVLEN2_Pos;
466 ((Dmac *)hw)->CTRL.reg = tmp;
467 DMAC_CRITICAL_SECTION_LEAVE();
468 }
469
hri_dmac_clear_CTRL_LVLEN2_bit(const void * const hw)470 static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw)
471 {
472 DMAC_CRITICAL_SECTION_ENTER();
473 ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2;
474 DMAC_CRITICAL_SECTION_LEAVE();
475 }
476
hri_dmac_toggle_CTRL_LVLEN2_bit(const void * const hw)477 static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw)
478 {
479 DMAC_CRITICAL_SECTION_ENTER();
480 ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2;
481 DMAC_CRITICAL_SECTION_LEAVE();
482 }
483
hri_dmac_set_CTRL_LVLEN3_bit(const void * const hw)484 static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw)
485 {
486 DMAC_CRITICAL_SECTION_ENTER();
487 ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3;
488 DMAC_CRITICAL_SECTION_LEAVE();
489 }
490
hri_dmac_get_CTRL_LVLEN3_bit(const void * const hw)491 static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw)
492 {
493 uint16_t tmp;
494 tmp = ((Dmac *)hw)->CTRL.reg;
495 tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos;
496 return (bool)tmp;
497 }
498
hri_dmac_write_CTRL_LVLEN3_bit(const void * const hw,bool value)499 static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value)
500 {
501 uint16_t tmp;
502 DMAC_CRITICAL_SECTION_ENTER();
503 tmp = ((Dmac *)hw)->CTRL.reg;
504 tmp &= ~DMAC_CTRL_LVLEN3;
505 tmp |= value << DMAC_CTRL_LVLEN3_Pos;
506 ((Dmac *)hw)->CTRL.reg = tmp;
507 DMAC_CRITICAL_SECTION_LEAVE();
508 }
509
hri_dmac_clear_CTRL_LVLEN3_bit(const void * const hw)510 static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw)
511 {
512 DMAC_CRITICAL_SECTION_ENTER();
513 ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3;
514 DMAC_CRITICAL_SECTION_LEAVE();
515 }
516
hri_dmac_toggle_CTRL_LVLEN3_bit(const void * const hw)517 static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw)
518 {
519 DMAC_CRITICAL_SECTION_ENTER();
520 ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3;
521 DMAC_CRITICAL_SECTION_LEAVE();
522 }
523
hri_dmac_set_CTRL_reg(const void * const hw,hri_dmac_ctrl_reg_t mask)524 static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
525 {
526 DMAC_CRITICAL_SECTION_ENTER();
527 ((Dmac *)hw)->CTRL.reg |= mask;
528 DMAC_CRITICAL_SECTION_LEAVE();
529 }
530
hri_dmac_get_CTRL_reg(const void * const hw,hri_dmac_ctrl_reg_t mask)531 static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
532 {
533 uint16_t tmp;
534 tmp = ((Dmac *)hw)->CTRL.reg;
535 tmp &= mask;
536 return tmp;
537 }
538
hri_dmac_write_CTRL_reg(const void * const hw,hri_dmac_ctrl_reg_t data)539 static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data)
540 {
541 DMAC_CRITICAL_SECTION_ENTER();
542 ((Dmac *)hw)->CTRL.reg = data;
543 DMAC_CRITICAL_SECTION_LEAVE();
544 }
545
hri_dmac_clear_CTRL_reg(const void * const hw,hri_dmac_ctrl_reg_t mask)546 static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
547 {
548 DMAC_CRITICAL_SECTION_ENTER();
549 ((Dmac *)hw)->CTRL.reg &= ~mask;
550 DMAC_CRITICAL_SECTION_LEAVE();
551 }
552
hri_dmac_toggle_CTRL_reg(const void * const hw,hri_dmac_ctrl_reg_t mask)553 static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask)
554 {
555 DMAC_CRITICAL_SECTION_ENTER();
556 ((Dmac *)hw)->CTRL.reg ^= mask;
557 DMAC_CRITICAL_SECTION_LEAVE();
558 }
559
hri_dmac_read_CTRL_reg(const void * const hw)560 static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw)
561 {
562 return ((Dmac *)hw)->CTRL.reg;
563 }
564
hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)565 static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
566 {
567 DMAC_CRITICAL_SECTION_ENTER();
568 ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask);
569 DMAC_CRITICAL_SECTION_LEAVE();
570 }
571
hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)572 static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw,
573 hri_dmac_crcctrl_reg_t mask)
574 {
575 uint16_t tmp;
576 tmp = ((Dmac *)hw)->CRCCTRL.reg;
577 tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
578 return tmp;
579 }
580
hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void * const hw,hri_dmac_crcctrl_reg_t data)581 static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
582 {
583 uint16_t tmp;
584 DMAC_CRITICAL_SECTION_ENTER();
585 tmp = ((Dmac *)hw)->CRCCTRL.reg;
586 tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk;
587 tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data);
588 ((Dmac *)hw)->CRCCTRL.reg = tmp;
589 DMAC_CRITICAL_SECTION_LEAVE();
590 }
591
hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)592 static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
593 {
594 DMAC_CRITICAL_SECTION_ENTER();
595 ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask);
596 DMAC_CRITICAL_SECTION_LEAVE();
597 }
598
hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)599 static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
600 {
601 DMAC_CRITICAL_SECTION_ENTER();
602 ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask);
603 DMAC_CRITICAL_SECTION_LEAVE();
604 }
605
hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void * const hw)606 static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw)
607 {
608 uint16_t tmp;
609 tmp = ((Dmac *)hw)->CRCCTRL.reg;
610 tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos;
611 return tmp;
612 }
613
hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)614 static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
615 {
616 DMAC_CRITICAL_SECTION_ENTER();
617 ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask);
618 DMAC_CRITICAL_SECTION_LEAVE();
619 }
620
hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)621 static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
622 {
623 uint16_t tmp;
624 tmp = ((Dmac *)hw)->CRCCTRL.reg;
625 tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos;
626 return tmp;
627 }
628
hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void * const hw,hri_dmac_crcctrl_reg_t data)629 static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
630 {
631 uint16_t tmp;
632 DMAC_CRITICAL_SECTION_ENTER();
633 tmp = ((Dmac *)hw)->CRCCTRL.reg;
634 tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk;
635 tmp |= DMAC_CRCCTRL_CRCPOLY(data);
636 ((Dmac *)hw)->CRCCTRL.reg = tmp;
637 DMAC_CRITICAL_SECTION_LEAVE();
638 }
639
hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)640 static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
641 {
642 DMAC_CRITICAL_SECTION_ENTER();
643 ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask);
644 DMAC_CRITICAL_SECTION_LEAVE();
645 }
646
hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)647 static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
648 {
649 DMAC_CRITICAL_SECTION_ENTER();
650 ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask);
651 DMAC_CRITICAL_SECTION_LEAVE();
652 }
653
hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void * const hw)654 static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw)
655 {
656 uint16_t tmp;
657 tmp = ((Dmac *)hw)->CRCCTRL.reg;
658 tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos;
659 return tmp;
660 }
661
hri_dmac_set_CRCCTRL_CRCSRC_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)662 static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
663 {
664 DMAC_CRITICAL_SECTION_ENTER();
665 ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask);
666 DMAC_CRITICAL_SECTION_LEAVE();
667 }
668
hri_dmac_get_CRCCTRL_CRCSRC_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)669 static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
670 {
671 uint16_t tmp;
672 tmp = ((Dmac *)hw)->CRCCTRL.reg;
673 tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos;
674 return tmp;
675 }
676
hri_dmac_write_CRCCTRL_CRCSRC_bf(const void * const hw,hri_dmac_crcctrl_reg_t data)677 static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data)
678 {
679 uint16_t tmp;
680 DMAC_CRITICAL_SECTION_ENTER();
681 tmp = ((Dmac *)hw)->CRCCTRL.reg;
682 tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk;
683 tmp |= DMAC_CRCCTRL_CRCSRC(data);
684 ((Dmac *)hw)->CRCCTRL.reg = tmp;
685 DMAC_CRITICAL_SECTION_LEAVE();
686 }
687
hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)688 static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
689 {
690 DMAC_CRITICAL_SECTION_ENTER();
691 ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask);
692 DMAC_CRITICAL_SECTION_LEAVE();
693 }
694
hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void * const hw,hri_dmac_crcctrl_reg_t mask)695 static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask)
696 {
697 DMAC_CRITICAL_SECTION_ENTER();
698 ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask);
699 DMAC_CRITICAL_SECTION_LEAVE();
700 }
701
hri_dmac_read_CRCCTRL_CRCSRC_bf(const void * const hw)702 static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw)
703 {
704 uint16_t tmp;
705 tmp = ((Dmac *)hw)->CRCCTRL.reg;
706 tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos;
707 return tmp;
708 }
709
hri_dmac_set_CRCCTRL_reg(const void * const hw,hri_dmac_crcctrl_reg_t mask)710 static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
711 {
712 DMAC_CRITICAL_SECTION_ENTER();
713 ((Dmac *)hw)->CRCCTRL.reg |= mask;
714 DMAC_CRITICAL_SECTION_LEAVE();
715 }
716
hri_dmac_get_CRCCTRL_reg(const void * const hw,hri_dmac_crcctrl_reg_t mask)717 static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
718 {
719 uint16_t tmp;
720 tmp = ((Dmac *)hw)->CRCCTRL.reg;
721 tmp &= mask;
722 return tmp;
723 }
724
hri_dmac_write_CRCCTRL_reg(const void * const hw,hri_dmac_crcctrl_reg_t data)725 static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data)
726 {
727 DMAC_CRITICAL_SECTION_ENTER();
728 ((Dmac *)hw)->CRCCTRL.reg = data;
729 DMAC_CRITICAL_SECTION_LEAVE();
730 }
731
hri_dmac_clear_CRCCTRL_reg(const void * const hw,hri_dmac_crcctrl_reg_t mask)732 static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
733 {
734 DMAC_CRITICAL_SECTION_ENTER();
735 ((Dmac *)hw)->CRCCTRL.reg &= ~mask;
736 DMAC_CRITICAL_SECTION_LEAVE();
737 }
738
hri_dmac_toggle_CRCCTRL_reg(const void * const hw,hri_dmac_crcctrl_reg_t mask)739 static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask)
740 {
741 DMAC_CRITICAL_SECTION_ENTER();
742 ((Dmac *)hw)->CRCCTRL.reg ^= mask;
743 DMAC_CRITICAL_SECTION_LEAVE();
744 }
745
hri_dmac_read_CRCCTRL_reg(const void * const hw)746 static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw)
747 {
748 return ((Dmac *)hw)->CRCCTRL.reg;
749 }
750
hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void * const hw,hri_dmac_crcdatain_reg_t mask)751 static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
752 {
753 DMAC_CRITICAL_SECTION_ENTER();
754 ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask);
755 DMAC_CRITICAL_SECTION_LEAVE();
756 }
757
hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void * const hw,hri_dmac_crcdatain_reg_t mask)758 static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw,
759 hri_dmac_crcdatain_reg_t mask)
760 {
761 uint32_t tmp;
762 tmp = ((Dmac *)hw)->CRCDATAIN.reg;
763 tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
764 return tmp;
765 }
766
hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void * const hw,hri_dmac_crcdatain_reg_t data)767 static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data)
768 {
769 uint32_t tmp;
770 DMAC_CRITICAL_SECTION_ENTER();
771 tmp = ((Dmac *)hw)->CRCDATAIN.reg;
772 tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk;
773 tmp |= DMAC_CRCDATAIN_CRCDATAIN(data);
774 ((Dmac *)hw)->CRCDATAIN.reg = tmp;
775 DMAC_CRITICAL_SECTION_LEAVE();
776 }
777
hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void * const hw,hri_dmac_crcdatain_reg_t mask)778 static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
779 {
780 DMAC_CRITICAL_SECTION_ENTER();
781 ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask);
782 DMAC_CRITICAL_SECTION_LEAVE();
783 }
784
hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void * const hw,hri_dmac_crcdatain_reg_t mask)785 static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask)
786 {
787 DMAC_CRITICAL_SECTION_ENTER();
788 ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask);
789 DMAC_CRITICAL_SECTION_LEAVE();
790 }
791
hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void * const hw)792 static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw)
793 {
794 uint32_t tmp;
795 tmp = ((Dmac *)hw)->CRCDATAIN.reg;
796 tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos;
797 return tmp;
798 }
799
hri_dmac_set_CRCDATAIN_reg(const void * const hw,hri_dmac_crcdatain_reg_t mask)800 static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
801 {
802 DMAC_CRITICAL_SECTION_ENTER();
803 ((Dmac *)hw)->CRCDATAIN.reg |= mask;
804 DMAC_CRITICAL_SECTION_LEAVE();
805 }
806
hri_dmac_get_CRCDATAIN_reg(const void * const hw,hri_dmac_crcdatain_reg_t mask)807 static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
808 {
809 uint32_t tmp;
810 tmp = ((Dmac *)hw)->CRCDATAIN.reg;
811 tmp &= mask;
812 return tmp;
813 }
814
hri_dmac_write_CRCDATAIN_reg(const void * const hw,hri_dmac_crcdatain_reg_t data)815 static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data)
816 {
817 DMAC_CRITICAL_SECTION_ENTER();
818 ((Dmac *)hw)->CRCDATAIN.reg = data;
819 DMAC_CRITICAL_SECTION_LEAVE();
820 }
821
hri_dmac_clear_CRCDATAIN_reg(const void * const hw,hri_dmac_crcdatain_reg_t mask)822 static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
823 {
824 DMAC_CRITICAL_SECTION_ENTER();
825 ((Dmac *)hw)->CRCDATAIN.reg &= ~mask;
826 DMAC_CRITICAL_SECTION_LEAVE();
827 }
828
hri_dmac_toggle_CRCDATAIN_reg(const void * const hw,hri_dmac_crcdatain_reg_t mask)829 static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask)
830 {
831 DMAC_CRITICAL_SECTION_ENTER();
832 ((Dmac *)hw)->CRCDATAIN.reg ^= mask;
833 DMAC_CRITICAL_SECTION_LEAVE();
834 }
835
hri_dmac_read_CRCDATAIN_reg(const void * const hw)836 static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw)
837 {
838 return ((Dmac *)hw)->CRCDATAIN.reg;
839 }
840
hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void * const hw,hri_dmac_crcchksum_reg_t mask)841 static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
842 {
843 DMAC_CRITICAL_SECTION_ENTER();
844 ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
845 DMAC_CRITICAL_SECTION_LEAVE();
846 }
847
hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void * const hw,hri_dmac_crcchksum_reg_t mask)848 static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw,
849 hri_dmac_crcchksum_reg_t mask)
850 {
851 uint32_t tmp;
852 tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
853 tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
854 return tmp;
855 }
856
hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void * const hw,hri_dmac_crcchksum_reg_t data)857 static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data)
858 {
859 uint32_t tmp;
860 DMAC_CRITICAL_SECTION_ENTER();
861 tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
862 tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk;
863 tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data);
864 ((Dmac *)hw)->CRCCHKSUM.reg = tmp;
865 DMAC_CRITICAL_SECTION_LEAVE();
866 }
867
hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void * const hw,hri_dmac_crcchksum_reg_t mask)868 static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
869 {
870 DMAC_CRITICAL_SECTION_ENTER();
871 ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask);
872 DMAC_CRITICAL_SECTION_LEAVE();
873 }
874
hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void * const hw,hri_dmac_crcchksum_reg_t mask)875 static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask)
876 {
877 DMAC_CRITICAL_SECTION_ENTER();
878 ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask);
879 DMAC_CRITICAL_SECTION_LEAVE();
880 }
881
hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void * const hw)882 static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw)
883 {
884 uint32_t tmp;
885 tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
886 tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos;
887 return tmp;
888 }
889
hri_dmac_set_CRCCHKSUM_reg(const void * const hw,hri_dmac_crcchksum_reg_t mask)890 static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
891 {
892 DMAC_CRITICAL_SECTION_ENTER();
893 ((Dmac *)hw)->CRCCHKSUM.reg |= mask;
894 DMAC_CRITICAL_SECTION_LEAVE();
895 }
896
hri_dmac_get_CRCCHKSUM_reg(const void * const hw,hri_dmac_crcchksum_reg_t mask)897 static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
898 {
899 uint32_t tmp;
900 tmp = ((Dmac *)hw)->CRCCHKSUM.reg;
901 tmp &= mask;
902 return tmp;
903 }
904
hri_dmac_write_CRCCHKSUM_reg(const void * const hw,hri_dmac_crcchksum_reg_t data)905 static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data)
906 {
907 DMAC_CRITICAL_SECTION_ENTER();
908 ((Dmac *)hw)->CRCCHKSUM.reg = data;
909 DMAC_CRITICAL_SECTION_LEAVE();
910 }
911
hri_dmac_clear_CRCCHKSUM_reg(const void * const hw,hri_dmac_crcchksum_reg_t mask)912 static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
913 {
914 DMAC_CRITICAL_SECTION_ENTER();
915 ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask;
916 DMAC_CRITICAL_SECTION_LEAVE();
917 }
918
hri_dmac_toggle_CRCCHKSUM_reg(const void * const hw,hri_dmac_crcchksum_reg_t mask)919 static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask)
920 {
921 DMAC_CRITICAL_SECTION_ENTER();
922 ((Dmac *)hw)->CRCCHKSUM.reg ^= mask;
923 DMAC_CRITICAL_SECTION_LEAVE();
924 }
925
hri_dmac_read_CRCCHKSUM_reg(const void * const hw)926 static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw)
927 {
928 return ((Dmac *)hw)->CRCCHKSUM.reg;
929 }
930
hri_dmac_set_DBGCTRL_DBGRUN_bit(const void * const hw)931 static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw)
932 {
933 DMAC_CRITICAL_SECTION_ENTER();
934 ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN;
935 DMAC_CRITICAL_SECTION_LEAVE();
936 }
937
hri_dmac_get_DBGCTRL_DBGRUN_bit(const void * const hw)938 static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw)
939 {
940 uint8_t tmp;
941 tmp = ((Dmac *)hw)->DBGCTRL.reg;
942 tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos;
943 return (bool)tmp;
944 }
945
hri_dmac_write_DBGCTRL_DBGRUN_bit(const void * const hw,bool value)946 static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
947 {
948 uint8_t tmp;
949 DMAC_CRITICAL_SECTION_ENTER();
950 tmp = ((Dmac *)hw)->DBGCTRL.reg;
951 tmp &= ~DMAC_DBGCTRL_DBGRUN;
952 tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos;
953 ((Dmac *)hw)->DBGCTRL.reg = tmp;
954 DMAC_CRITICAL_SECTION_LEAVE();
955 }
956
hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void * const hw)957 static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
958 {
959 DMAC_CRITICAL_SECTION_ENTER();
960 ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN;
961 DMAC_CRITICAL_SECTION_LEAVE();
962 }
963
hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void * const hw)964 static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
965 {
966 DMAC_CRITICAL_SECTION_ENTER();
967 ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN;
968 DMAC_CRITICAL_SECTION_LEAVE();
969 }
970
hri_dmac_set_DBGCTRL_reg(const void * const hw,hri_dmac_dbgctrl_reg_t mask)971 static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
972 {
973 DMAC_CRITICAL_SECTION_ENTER();
974 ((Dmac *)hw)->DBGCTRL.reg |= mask;
975 DMAC_CRITICAL_SECTION_LEAVE();
976 }
977
hri_dmac_get_DBGCTRL_reg(const void * const hw,hri_dmac_dbgctrl_reg_t mask)978 static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
979 {
980 uint8_t tmp;
981 tmp = ((Dmac *)hw)->DBGCTRL.reg;
982 tmp &= mask;
983 return tmp;
984 }
985
hri_dmac_write_DBGCTRL_reg(const void * const hw,hri_dmac_dbgctrl_reg_t data)986 static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data)
987 {
988 DMAC_CRITICAL_SECTION_ENTER();
989 ((Dmac *)hw)->DBGCTRL.reg = data;
990 DMAC_CRITICAL_SECTION_LEAVE();
991 }
992
hri_dmac_clear_DBGCTRL_reg(const void * const hw,hri_dmac_dbgctrl_reg_t mask)993 static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
994 {
995 DMAC_CRITICAL_SECTION_ENTER();
996 ((Dmac *)hw)->DBGCTRL.reg &= ~mask;
997 DMAC_CRITICAL_SECTION_LEAVE();
998 }
999
hri_dmac_toggle_DBGCTRL_reg(const void * const hw,hri_dmac_dbgctrl_reg_t mask)1000 static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask)
1001 {
1002 DMAC_CRITICAL_SECTION_ENTER();
1003 ((Dmac *)hw)->DBGCTRL.reg ^= mask;
1004 DMAC_CRITICAL_SECTION_LEAVE();
1005 }
1006
hri_dmac_read_DBGCTRL_reg(const void * const hw)1007 static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw)
1008 {
1009 return ((Dmac *)hw)->DBGCTRL.reg;
1010 }
1011
hri_dmac_set_QOSCTRL_WRBQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1012 static inline void hri_dmac_set_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1013 {
1014 DMAC_CRITICAL_SECTION_ENTER();
1015 ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_WRBQOS(mask);
1016 DMAC_CRITICAL_SECTION_LEAVE();
1017 }
1018
hri_dmac_get_QOSCTRL_WRBQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1019 static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1020 {
1021 uint8_t tmp;
1022 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1023 tmp = (tmp & DMAC_QOSCTRL_WRBQOS(mask)) >> DMAC_QOSCTRL_WRBQOS_Pos;
1024 return tmp;
1025 }
1026
hri_dmac_write_QOSCTRL_WRBQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t data)1027 static inline void hri_dmac_write_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
1028 {
1029 uint8_t tmp;
1030 DMAC_CRITICAL_SECTION_ENTER();
1031 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1032 tmp &= ~DMAC_QOSCTRL_WRBQOS_Msk;
1033 tmp |= DMAC_QOSCTRL_WRBQOS(data);
1034 ((Dmac *)hw)->QOSCTRL.reg = tmp;
1035 DMAC_CRITICAL_SECTION_LEAVE();
1036 }
1037
hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1038 static inline void hri_dmac_clear_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1039 {
1040 DMAC_CRITICAL_SECTION_ENTER();
1041 ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_WRBQOS(mask);
1042 DMAC_CRITICAL_SECTION_LEAVE();
1043 }
1044
hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1045 static inline void hri_dmac_toggle_QOSCTRL_WRBQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1046 {
1047 DMAC_CRITICAL_SECTION_ENTER();
1048 ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_WRBQOS(mask);
1049 DMAC_CRITICAL_SECTION_LEAVE();
1050 }
1051
hri_dmac_read_QOSCTRL_WRBQOS_bf(const void * const hw)1052 static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_WRBQOS_bf(const void *const hw)
1053 {
1054 uint8_t tmp;
1055 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1056 tmp = (tmp & DMAC_QOSCTRL_WRBQOS_Msk) >> DMAC_QOSCTRL_WRBQOS_Pos;
1057 return tmp;
1058 }
1059
hri_dmac_set_QOSCTRL_FQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1060 static inline void hri_dmac_set_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1061 {
1062 DMAC_CRITICAL_SECTION_ENTER();
1063 ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_FQOS(mask);
1064 DMAC_CRITICAL_SECTION_LEAVE();
1065 }
1066
hri_dmac_get_QOSCTRL_FQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1067 static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1068 {
1069 uint8_t tmp;
1070 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1071 tmp = (tmp & DMAC_QOSCTRL_FQOS(mask)) >> DMAC_QOSCTRL_FQOS_Pos;
1072 return tmp;
1073 }
1074
hri_dmac_write_QOSCTRL_FQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t data)1075 static inline void hri_dmac_write_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
1076 {
1077 uint8_t tmp;
1078 DMAC_CRITICAL_SECTION_ENTER();
1079 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1080 tmp &= ~DMAC_QOSCTRL_FQOS_Msk;
1081 tmp |= DMAC_QOSCTRL_FQOS(data);
1082 ((Dmac *)hw)->QOSCTRL.reg = tmp;
1083 DMAC_CRITICAL_SECTION_LEAVE();
1084 }
1085
hri_dmac_clear_QOSCTRL_FQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1086 static inline void hri_dmac_clear_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1087 {
1088 DMAC_CRITICAL_SECTION_ENTER();
1089 ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_FQOS(mask);
1090 DMAC_CRITICAL_SECTION_LEAVE();
1091 }
1092
hri_dmac_toggle_QOSCTRL_FQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1093 static inline void hri_dmac_toggle_QOSCTRL_FQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1094 {
1095 DMAC_CRITICAL_SECTION_ENTER();
1096 ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_FQOS(mask);
1097 DMAC_CRITICAL_SECTION_LEAVE();
1098 }
1099
hri_dmac_read_QOSCTRL_FQOS_bf(const void * const hw)1100 static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_FQOS_bf(const void *const hw)
1101 {
1102 uint8_t tmp;
1103 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1104 tmp = (tmp & DMAC_QOSCTRL_FQOS_Msk) >> DMAC_QOSCTRL_FQOS_Pos;
1105 return tmp;
1106 }
1107
hri_dmac_set_QOSCTRL_DQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1108 static inline void hri_dmac_set_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1109 {
1110 DMAC_CRITICAL_SECTION_ENTER();
1111 ((Dmac *)hw)->QOSCTRL.reg |= DMAC_QOSCTRL_DQOS(mask);
1112 DMAC_CRITICAL_SECTION_LEAVE();
1113 }
1114
hri_dmac_get_QOSCTRL_DQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1115 static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1116 {
1117 uint8_t tmp;
1118 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1119 tmp = (tmp & DMAC_QOSCTRL_DQOS(mask)) >> DMAC_QOSCTRL_DQOS_Pos;
1120 return tmp;
1121 }
1122
hri_dmac_write_QOSCTRL_DQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t data)1123 static inline void hri_dmac_write_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t data)
1124 {
1125 uint8_t tmp;
1126 DMAC_CRITICAL_SECTION_ENTER();
1127 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1128 tmp &= ~DMAC_QOSCTRL_DQOS_Msk;
1129 tmp |= DMAC_QOSCTRL_DQOS(data);
1130 ((Dmac *)hw)->QOSCTRL.reg = tmp;
1131 DMAC_CRITICAL_SECTION_LEAVE();
1132 }
1133
hri_dmac_clear_QOSCTRL_DQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1134 static inline void hri_dmac_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1135 {
1136 DMAC_CRITICAL_SECTION_ENTER();
1137 ((Dmac *)hw)->QOSCTRL.reg &= ~DMAC_QOSCTRL_DQOS(mask);
1138 DMAC_CRITICAL_SECTION_LEAVE();
1139 }
1140
hri_dmac_toggle_QOSCTRL_DQOS_bf(const void * const hw,hri_dmac_qosctrl_reg_t mask)1141 static inline void hri_dmac_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1142 {
1143 DMAC_CRITICAL_SECTION_ENTER();
1144 ((Dmac *)hw)->QOSCTRL.reg ^= DMAC_QOSCTRL_DQOS(mask);
1145 DMAC_CRITICAL_SECTION_LEAVE();
1146 }
1147
hri_dmac_read_QOSCTRL_DQOS_bf(const void * const hw)1148 static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_DQOS_bf(const void *const hw)
1149 {
1150 uint8_t tmp;
1151 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1152 tmp = (tmp & DMAC_QOSCTRL_DQOS_Msk) >> DMAC_QOSCTRL_DQOS_Pos;
1153 return tmp;
1154 }
1155
hri_dmac_set_QOSCTRL_reg(const void * const hw,hri_dmac_qosctrl_reg_t mask)1156 static inline void hri_dmac_set_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1157 {
1158 DMAC_CRITICAL_SECTION_ENTER();
1159 ((Dmac *)hw)->QOSCTRL.reg |= mask;
1160 DMAC_CRITICAL_SECTION_LEAVE();
1161 }
1162
hri_dmac_get_QOSCTRL_reg(const void * const hw,hri_dmac_qosctrl_reg_t mask)1163 static inline hri_dmac_qosctrl_reg_t hri_dmac_get_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1164 {
1165 uint8_t tmp;
1166 tmp = ((Dmac *)hw)->QOSCTRL.reg;
1167 tmp &= mask;
1168 return tmp;
1169 }
1170
hri_dmac_write_QOSCTRL_reg(const void * const hw,hri_dmac_qosctrl_reg_t data)1171 static inline void hri_dmac_write_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t data)
1172 {
1173 DMAC_CRITICAL_SECTION_ENTER();
1174 ((Dmac *)hw)->QOSCTRL.reg = data;
1175 DMAC_CRITICAL_SECTION_LEAVE();
1176 }
1177
hri_dmac_clear_QOSCTRL_reg(const void * const hw,hri_dmac_qosctrl_reg_t mask)1178 static inline void hri_dmac_clear_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1179 {
1180 DMAC_CRITICAL_SECTION_ENTER();
1181 ((Dmac *)hw)->QOSCTRL.reg &= ~mask;
1182 DMAC_CRITICAL_SECTION_LEAVE();
1183 }
1184
hri_dmac_toggle_QOSCTRL_reg(const void * const hw,hri_dmac_qosctrl_reg_t mask)1185 static inline void hri_dmac_toggle_QOSCTRL_reg(const void *const hw, hri_dmac_qosctrl_reg_t mask)
1186 {
1187 DMAC_CRITICAL_SECTION_ENTER();
1188 ((Dmac *)hw)->QOSCTRL.reg ^= mask;
1189 DMAC_CRITICAL_SECTION_LEAVE();
1190 }
1191
hri_dmac_read_QOSCTRL_reg(const void * const hw)1192 static inline hri_dmac_qosctrl_reg_t hri_dmac_read_QOSCTRL_reg(const void *const hw)
1193 {
1194 return ((Dmac *)hw)->QOSCTRL.reg;
1195 }
1196
hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void * const hw)1197 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
1198 {
1199 DMAC_CRITICAL_SECTION_ENTER();
1200 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0;
1201 DMAC_CRITICAL_SECTION_LEAVE();
1202 }
1203
hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void * const hw)1204 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
1205 {
1206 uint32_t tmp;
1207 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1208 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos;
1209 return (bool)tmp;
1210 }
1211
hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void * const hw,bool value)1212 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value)
1213 {
1214 uint32_t tmp;
1215 DMAC_CRITICAL_SECTION_ENTER();
1216 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1217 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0;
1218 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos;
1219 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1220 DMAC_CRITICAL_SECTION_LEAVE();
1221 }
1222
hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void * const hw)1223 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
1224 {
1225 DMAC_CRITICAL_SECTION_ENTER();
1226 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0;
1227 DMAC_CRITICAL_SECTION_LEAVE();
1228 }
1229
hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void * const hw)1230 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw)
1231 {
1232 DMAC_CRITICAL_SECTION_ENTER();
1233 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0;
1234 DMAC_CRITICAL_SECTION_LEAVE();
1235 }
1236
hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void * const hw)1237 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
1238 {
1239 DMAC_CRITICAL_SECTION_ENTER();
1240 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1;
1241 DMAC_CRITICAL_SECTION_LEAVE();
1242 }
1243
hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void * const hw)1244 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
1245 {
1246 uint32_t tmp;
1247 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1248 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos;
1249 return (bool)tmp;
1250 }
1251
hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void * const hw,bool value)1252 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value)
1253 {
1254 uint32_t tmp;
1255 DMAC_CRITICAL_SECTION_ENTER();
1256 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1257 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1;
1258 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos;
1259 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1260 DMAC_CRITICAL_SECTION_LEAVE();
1261 }
1262
hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void * const hw)1263 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
1264 {
1265 DMAC_CRITICAL_SECTION_ENTER();
1266 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1;
1267 DMAC_CRITICAL_SECTION_LEAVE();
1268 }
1269
hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void * const hw)1270 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw)
1271 {
1272 DMAC_CRITICAL_SECTION_ENTER();
1273 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1;
1274 DMAC_CRITICAL_SECTION_LEAVE();
1275 }
1276
hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void * const hw)1277 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
1278 {
1279 DMAC_CRITICAL_SECTION_ENTER();
1280 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2;
1281 DMAC_CRITICAL_SECTION_LEAVE();
1282 }
1283
hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void * const hw)1284 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
1285 {
1286 uint32_t tmp;
1287 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1288 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos;
1289 return (bool)tmp;
1290 }
1291
hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void * const hw,bool value)1292 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value)
1293 {
1294 uint32_t tmp;
1295 DMAC_CRITICAL_SECTION_ENTER();
1296 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1297 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2;
1298 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos;
1299 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1300 DMAC_CRITICAL_SECTION_LEAVE();
1301 }
1302
hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void * const hw)1303 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
1304 {
1305 DMAC_CRITICAL_SECTION_ENTER();
1306 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2;
1307 DMAC_CRITICAL_SECTION_LEAVE();
1308 }
1309
hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void * const hw)1310 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw)
1311 {
1312 DMAC_CRITICAL_SECTION_ENTER();
1313 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2;
1314 DMAC_CRITICAL_SECTION_LEAVE();
1315 }
1316
hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void * const hw)1317 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
1318 {
1319 DMAC_CRITICAL_SECTION_ENTER();
1320 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3;
1321 DMAC_CRITICAL_SECTION_LEAVE();
1322 }
1323
hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void * const hw)1324 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
1325 {
1326 uint32_t tmp;
1327 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1328 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos;
1329 return (bool)tmp;
1330 }
1331
hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void * const hw,bool value)1332 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value)
1333 {
1334 uint32_t tmp;
1335 DMAC_CRITICAL_SECTION_ENTER();
1336 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1337 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3;
1338 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos;
1339 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1340 DMAC_CRITICAL_SECTION_LEAVE();
1341 }
1342
hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void * const hw)1343 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
1344 {
1345 DMAC_CRITICAL_SECTION_ENTER();
1346 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3;
1347 DMAC_CRITICAL_SECTION_LEAVE();
1348 }
1349
hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void * const hw)1350 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw)
1351 {
1352 DMAC_CRITICAL_SECTION_ENTER();
1353 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3;
1354 DMAC_CRITICAL_SECTION_LEAVE();
1355 }
1356
hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void * const hw)1357 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
1358 {
1359 DMAC_CRITICAL_SECTION_ENTER();
1360 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4;
1361 DMAC_CRITICAL_SECTION_LEAVE();
1362 }
1363
hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void * const hw)1364 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
1365 {
1366 uint32_t tmp;
1367 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1368 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos;
1369 return (bool)tmp;
1370 }
1371
hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void * const hw,bool value)1372 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value)
1373 {
1374 uint32_t tmp;
1375 DMAC_CRITICAL_SECTION_ENTER();
1376 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1377 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4;
1378 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos;
1379 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1380 DMAC_CRITICAL_SECTION_LEAVE();
1381 }
1382
hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void * const hw)1383 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
1384 {
1385 DMAC_CRITICAL_SECTION_ENTER();
1386 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4;
1387 DMAC_CRITICAL_SECTION_LEAVE();
1388 }
1389
hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void * const hw)1390 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw)
1391 {
1392 DMAC_CRITICAL_SECTION_ENTER();
1393 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4;
1394 DMAC_CRITICAL_SECTION_LEAVE();
1395 }
1396
hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void * const hw)1397 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
1398 {
1399 DMAC_CRITICAL_SECTION_ENTER();
1400 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5;
1401 DMAC_CRITICAL_SECTION_LEAVE();
1402 }
1403
hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void * const hw)1404 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
1405 {
1406 uint32_t tmp;
1407 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1408 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos;
1409 return (bool)tmp;
1410 }
1411
hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void * const hw,bool value)1412 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value)
1413 {
1414 uint32_t tmp;
1415 DMAC_CRITICAL_SECTION_ENTER();
1416 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1417 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5;
1418 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos;
1419 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1420 DMAC_CRITICAL_SECTION_LEAVE();
1421 }
1422
hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void * const hw)1423 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
1424 {
1425 DMAC_CRITICAL_SECTION_ENTER();
1426 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5;
1427 DMAC_CRITICAL_SECTION_LEAVE();
1428 }
1429
hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void * const hw)1430 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw)
1431 {
1432 DMAC_CRITICAL_SECTION_ENTER();
1433 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5;
1434 DMAC_CRITICAL_SECTION_LEAVE();
1435 }
1436
hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void * const hw)1437 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
1438 {
1439 DMAC_CRITICAL_SECTION_ENTER();
1440 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6;
1441 DMAC_CRITICAL_SECTION_LEAVE();
1442 }
1443
hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void * const hw)1444 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
1445 {
1446 uint32_t tmp;
1447 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1448 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos;
1449 return (bool)tmp;
1450 }
1451
hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void * const hw,bool value)1452 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value)
1453 {
1454 uint32_t tmp;
1455 DMAC_CRITICAL_SECTION_ENTER();
1456 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1457 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6;
1458 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos;
1459 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1460 DMAC_CRITICAL_SECTION_LEAVE();
1461 }
1462
hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void * const hw)1463 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
1464 {
1465 DMAC_CRITICAL_SECTION_ENTER();
1466 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6;
1467 DMAC_CRITICAL_SECTION_LEAVE();
1468 }
1469
hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void * const hw)1470 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw)
1471 {
1472 DMAC_CRITICAL_SECTION_ENTER();
1473 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6;
1474 DMAC_CRITICAL_SECTION_LEAVE();
1475 }
1476
hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void * const hw)1477 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
1478 {
1479 DMAC_CRITICAL_SECTION_ENTER();
1480 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7;
1481 DMAC_CRITICAL_SECTION_LEAVE();
1482 }
1483
hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void * const hw)1484 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
1485 {
1486 uint32_t tmp;
1487 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1488 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos;
1489 return (bool)tmp;
1490 }
1491
hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void * const hw,bool value)1492 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value)
1493 {
1494 uint32_t tmp;
1495 DMAC_CRITICAL_SECTION_ENTER();
1496 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1497 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7;
1498 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos;
1499 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1500 DMAC_CRITICAL_SECTION_LEAVE();
1501 }
1502
hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void * const hw)1503 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
1504 {
1505 DMAC_CRITICAL_SECTION_ENTER();
1506 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7;
1507 DMAC_CRITICAL_SECTION_LEAVE();
1508 }
1509
hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void * const hw)1510 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw)
1511 {
1512 DMAC_CRITICAL_SECTION_ENTER();
1513 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7;
1514 DMAC_CRITICAL_SECTION_LEAVE();
1515 }
1516
hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void * const hw)1517 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
1518 {
1519 DMAC_CRITICAL_SECTION_ENTER();
1520 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8;
1521 DMAC_CRITICAL_SECTION_LEAVE();
1522 }
1523
hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void * const hw)1524 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
1525 {
1526 uint32_t tmp;
1527 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1528 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos;
1529 return (bool)tmp;
1530 }
1531
hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void * const hw,bool value)1532 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value)
1533 {
1534 uint32_t tmp;
1535 DMAC_CRITICAL_SECTION_ENTER();
1536 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1537 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8;
1538 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos;
1539 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1540 DMAC_CRITICAL_SECTION_LEAVE();
1541 }
1542
hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void * const hw)1543 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
1544 {
1545 DMAC_CRITICAL_SECTION_ENTER();
1546 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8;
1547 DMAC_CRITICAL_SECTION_LEAVE();
1548 }
1549
hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void * const hw)1550 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw)
1551 {
1552 DMAC_CRITICAL_SECTION_ENTER();
1553 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8;
1554 DMAC_CRITICAL_SECTION_LEAVE();
1555 }
1556
hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void * const hw)1557 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
1558 {
1559 DMAC_CRITICAL_SECTION_ENTER();
1560 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9;
1561 DMAC_CRITICAL_SECTION_LEAVE();
1562 }
1563
hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void * const hw)1564 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
1565 {
1566 uint32_t tmp;
1567 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1568 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos;
1569 return (bool)tmp;
1570 }
1571
hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void * const hw,bool value)1572 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value)
1573 {
1574 uint32_t tmp;
1575 DMAC_CRITICAL_SECTION_ENTER();
1576 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1577 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9;
1578 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos;
1579 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1580 DMAC_CRITICAL_SECTION_LEAVE();
1581 }
1582
hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void * const hw)1583 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
1584 {
1585 DMAC_CRITICAL_SECTION_ENTER();
1586 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9;
1587 DMAC_CRITICAL_SECTION_LEAVE();
1588 }
1589
hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void * const hw)1590 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw)
1591 {
1592 DMAC_CRITICAL_SECTION_ENTER();
1593 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9;
1594 DMAC_CRITICAL_SECTION_LEAVE();
1595 }
1596
hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void * const hw)1597 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
1598 {
1599 DMAC_CRITICAL_SECTION_ENTER();
1600 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10;
1601 DMAC_CRITICAL_SECTION_LEAVE();
1602 }
1603
hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void * const hw)1604 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
1605 {
1606 uint32_t tmp;
1607 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1608 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos;
1609 return (bool)tmp;
1610 }
1611
hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void * const hw,bool value)1612 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value)
1613 {
1614 uint32_t tmp;
1615 DMAC_CRITICAL_SECTION_ENTER();
1616 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1617 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10;
1618 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos;
1619 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1620 DMAC_CRITICAL_SECTION_LEAVE();
1621 }
1622
hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void * const hw)1623 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
1624 {
1625 DMAC_CRITICAL_SECTION_ENTER();
1626 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10;
1627 DMAC_CRITICAL_SECTION_LEAVE();
1628 }
1629
hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void * const hw)1630 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw)
1631 {
1632 DMAC_CRITICAL_SECTION_ENTER();
1633 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10;
1634 DMAC_CRITICAL_SECTION_LEAVE();
1635 }
1636
hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void * const hw)1637 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
1638 {
1639 DMAC_CRITICAL_SECTION_ENTER();
1640 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11;
1641 DMAC_CRITICAL_SECTION_LEAVE();
1642 }
1643
hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void * const hw)1644 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
1645 {
1646 uint32_t tmp;
1647 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1648 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos;
1649 return (bool)tmp;
1650 }
1651
hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void * const hw,bool value)1652 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value)
1653 {
1654 uint32_t tmp;
1655 DMAC_CRITICAL_SECTION_ENTER();
1656 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1657 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11;
1658 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos;
1659 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1660 DMAC_CRITICAL_SECTION_LEAVE();
1661 }
1662
hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void * const hw)1663 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
1664 {
1665 DMAC_CRITICAL_SECTION_ENTER();
1666 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11;
1667 DMAC_CRITICAL_SECTION_LEAVE();
1668 }
1669
hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void * const hw)1670 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw)
1671 {
1672 DMAC_CRITICAL_SECTION_ENTER();
1673 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11;
1674 DMAC_CRITICAL_SECTION_LEAVE();
1675 }
1676
hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void * const hw)1677 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
1678 {
1679 DMAC_CRITICAL_SECTION_ENTER();
1680 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12;
1681 DMAC_CRITICAL_SECTION_LEAVE();
1682 }
1683
hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void * const hw)1684 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
1685 {
1686 uint32_t tmp;
1687 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1688 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos;
1689 return (bool)tmp;
1690 }
1691
hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void * const hw,bool value)1692 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value)
1693 {
1694 uint32_t tmp;
1695 DMAC_CRITICAL_SECTION_ENTER();
1696 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1697 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12;
1698 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos;
1699 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1700 DMAC_CRITICAL_SECTION_LEAVE();
1701 }
1702
hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void * const hw)1703 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
1704 {
1705 DMAC_CRITICAL_SECTION_ENTER();
1706 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12;
1707 DMAC_CRITICAL_SECTION_LEAVE();
1708 }
1709
hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void * const hw)1710 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw)
1711 {
1712 DMAC_CRITICAL_SECTION_ENTER();
1713 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12;
1714 DMAC_CRITICAL_SECTION_LEAVE();
1715 }
1716
hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void * const hw)1717 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
1718 {
1719 DMAC_CRITICAL_SECTION_ENTER();
1720 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13;
1721 DMAC_CRITICAL_SECTION_LEAVE();
1722 }
1723
hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void * const hw)1724 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
1725 {
1726 uint32_t tmp;
1727 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1728 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos;
1729 return (bool)tmp;
1730 }
1731
hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void * const hw,bool value)1732 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value)
1733 {
1734 uint32_t tmp;
1735 DMAC_CRITICAL_SECTION_ENTER();
1736 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1737 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13;
1738 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos;
1739 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1740 DMAC_CRITICAL_SECTION_LEAVE();
1741 }
1742
hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void * const hw)1743 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
1744 {
1745 DMAC_CRITICAL_SECTION_ENTER();
1746 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13;
1747 DMAC_CRITICAL_SECTION_LEAVE();
1748 }
1749
hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void * const hw)1750 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw)
1751 {
1752 DMAC_CRITICAL_SECTION_ENTER();
1753 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13;
1754 DMAC_CRITICAL_SECTION_LEAVE();
1755 }
1756
hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void * const hw)1757 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
1758 {
1759 DMAC_CRITICAL_SECTION_ENTER();
1760 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14;
1761 DMAC_CRITICAL_SECTION_LEAVE();
1762 }
1763
hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void * const hw)1764 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
1765 {
1766 uint32_t tmp;
1767 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1768 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos;
1769 return (bool)tmp;
1770 }
1771
hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void * const hw,bool value)1772 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value)
1773 {
1774 uint32_t tmp;
1775 DMAC_CRITICAL_SECTION_ENTER();
1776 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1777 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14;
1778 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos;
1779 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1780 DMAC_CRITICAL_SECTION_LEAVE();
1781 }
1782
hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void * const hw)1783 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
1784 {
1785 DMAC_CRITICAL_SECTION_ENTER();
1786 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14;
1787 DMAC_CRITICAL_SECTION_LEAVE();
1788 }
1789
hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void * const hw)1790 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw)
1791 {
1792 DMAC_CRITICAL_SECTION_ENTER();
1793 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14;
1794 DMAC_CRITICAL_SECTION_LEAVE();
1795 }
1796
hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void * const hw)1797 static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
1798 {
1799 DMAC_CRITICAL_SECTION_ENTER();
1800 ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15;
1801 DMAC_CRITICAL_SECTION_LEAVE();
1802 }
1803
hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void * const hw)1804 static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
1805 {
1806 uint32_t tmp;
1807 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1808 tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos;
1809 return (bool)tmp;
1810 }
1811
hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void * const hw,bool value)1812 static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value)
1813 {
1814 uint32_t tmp;
1815 DMAC_CRITICAL_SECTION_ENTER();
1816 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1817 tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15;
1818 tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos;
1819 ((Dmac *)hw)->SWTRIGCTRL.reg = tmp;
1820 DMAC_CRITICAL_SECTION_LEAVE();
1821 }
1822
hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void * const hw)1823 static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
1824 {
1825 DMAC_CRITICAL_SECTION_ENTER();
1826 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15;
1827 DMAC_CRITICAL_SECTION_LEAVE();
1828 }
1829
hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void * const hw)1830 static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw)
1831 {
1832 DMAC_CRITICAL_SECTION_ENTER();
1833 ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15;
1834 DMAC_CRITICAL_SECTION_LEAVE();
1835 }
1836
hri_dmac_set_SWTRIGCTRL_reg(const void * const hw,hri_dmac_swtrigctrl_reg_t mask)1837 static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
1838 {
1839 DMAC_CRITICAL_SECTION_ENTER();
1840 ((Dmac *)hw)->SWTRIGCTRL.reg |= mask;
1841 DMAC_CRITICAL_SECTION_LEAVE();
1842 }
1843
hri_dmac_get_SWTRIGCTRL_reg(const void * const hw,hri_dmac_swtrigctrl_reg_t mask)1844 static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw,
1845 hri_dmac_swtrigctrl_reg_t mask)
1846 {
1847 uint32_t tmp;
1848 tmp = ((Dmac *)hw)->SWTRIGCTRL.reg;
1849 tmp &= mask;
1850 return tmp;
1851 }
1852
hri_dmac_write_SWTRIGCTRL_reg(const void * const hw,hri_dmac_swtrigctrl_reg_t data)1853 static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data)
1854 {
1855 DMAC_CRITICAL_SECTION_ENTER();
1856 ((Dmac *)hw)->SWTRIGCTRL.reg = data;
1857 DMAC_CRITICAL_SECTION_LEAVE();
1858 }
1859
hri_dmac_clear_SWTRIGCTRL_reg(const void * const hw,hri_dmac_swtrigctrl_reg_t mask)1860 static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
1861 {
1862 DMAC_CRITICAL_SECTION_ENTER();
1863 ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask;
1864 DMAC_CRITICAL_SECTION_LEAVE();
1865 }
1866
hri_dmac_toggle_SWTRIGCTRL_reg(const void * const hw,hri_dmac_swtrigctrl_reg_t mask)1867 static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask)
1868 {
1869 DMAC_CRITICAL_SECTION_ENTER();
1870 ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask;
1871 DMAC_CRITICAL_SECTION_LEAVE();
1872 }
1873
hri_dmac_read_SWTRIGCTRL_reg(const void * const hw)1874 static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw)
1875 {
1876 return ((Dmac *)hw)->SWTRIGCTRL.reg;
1877 }
1878
hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void * const hw)1879 static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw)
1880 {
1881 DMAC_CRITICAL_SECTION_ENTER();
1882 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0;
1883 DMAC_CRITICAL_SECTION_LEAVE();
1884 }
1885
hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void * const hw)1886 static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw)
1887 {
1888 uint32_t tmp;
1889 tmp = ((Dmac *)hw)->PRICTRL0.reg;
1890 tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos;
1891 return (bool)tmp;
1892 }
1893
hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void * const hw,bool value)1894 static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value)
1895 {
1896 uint32_t tmp;
1897 DMAC_CRITICAL_SECTION_ENTER();
1898 tmp = ((Dmac *)hw)->PRICTRL0.reg;
1899 tmp &= ~DMAC_PRICTRL0_RRLVLEN0;
1900 tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos;
1901 ((Dmac *)hw)->PRICTRL0.reg = tmp;
1902 DMAC_CRITICAL_SECTION_LEAVE();
1903 }
1904
hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void * const hw)1905 static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw)
1906 {
1907 DMAC_CRITICAL_SECTION_ENTER();
1908 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0;
1909 DMAC_CRITICAL_SECTION_LEAVE();
1910 }
1911
hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void * const hw)1912 static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw)
1913 {
1914 DMAC_CRITICAL_SECTION_ENTER();
1915 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0;
1916 DMAC_CRITICAL_SECTION_LEAVE();
1917 }
1918
hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void * const hw)1919 static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw)
1920 {
1921 DMAC_CRITICAL_SECTION_ENTER();
1922 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1;
1923 DMAC_CRITICAL_SECTION_LEAVE();
1924 }
1925
hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void * const hw)1926 static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw)
1927 {
1928 uint32_t tmp;
1929 tmp = ((Dmac *)hw)->PRICTRL0.reg;
1930 tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos;
1931 return (bool)tmp;
1932 }
1933
hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void * const hw,bool value)1934 static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value)
1935 {
1936 uint32_t tmp;
1937 DMAC_CRITICAL_SECTION_ENTER();
1938 tmp = ((Dmac *)hw)->PRICTRL0.reg;
1939 tmp &= ~DMAC_PRICTRL0_RRLVLEN1;
1940 tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos;
1941 ((Dmac *)hw)->PRICTRL0.reg = tmp;
1942 DMAC_CRITICAL_SECTION_LEAVE();
1943 }
1944
hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void * const hw)1945 static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw)
1946 {
1947 DMAC_CRITICAL_SECTION_ENTER();
1948 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1;
1949 DMAC_CRITICAL_SECTION_LEAVE();
1950 }
1951
hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void * const hw)1952 static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw)
1953 {
1954 DMAC_CRITICAL_SECTION_ENTER();
1955 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1;
1956 DMAC_CRITICAL_SECTION_LEAVE();
1957 }
1958
hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void * const hw)1959 static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw)
1960 {
1961 DMAC_CRITICAL_SECTION_ENTER();
1962 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2;
1963 DMAC_CRITICAL_SECTION_LEAVE();
1964 }
1965
hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void * const hw)1966 static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw)
1967 {
1968 uint32_t tmp;
1969 tmp = ((Dmac *)hw)->PRICTRL0.reg;
1970 tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos;
1971 return (bool)tmp;
1972 }
1973
hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void * const hw,bool value)1974 static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value)
1975 {
1976 uint32_t tmp;
1977 DMAC_CRITICAL_SECTION_ENTER();
1978 tmp = ((Dmac *)hw)->PRICTRL0.reg;
1979 tmp &= ~DMAC_PRICTRL0_RRLVLEN2;
1980 tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos;
1981 ((Dmac *)hw)->PRICTRL0.reg = tmp;
1982 DMAC_CRITICAL_SECTION_LEAVE();
1983 }
1984
hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void * const hw)1985 static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw)
1986 {
1987 DMAC_CRITICAL_SECTION_ENTER();
1988 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2;
1989 DMAC_CRITICAL_SECTION_LEAVE();
1990 }
1991
hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void * const hw)1992 static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw)
1993 {
1994 DMAC_CRITICAL_SECTION_ENTER();
1995 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2;
1996 DMAC_CRITICAL_SECTION_LEAVE();
1997 }
1998
hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void * const hw)1999 static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw)
2000 {
2001 DMAC_CRITICAL_SECTION_ENTER();
2002 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3;
2003 DMAC_CRITICAL_SECTION_LEAVE();
2004 }
2005
hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void * const hw)2006 static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw)
2007 {
2008 uint32_t tmp;
2009 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2010 tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos;
2011 return (bool)tmp;
2012 }
2013
hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void * const hw,bool value)2014 static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value)
2015 {
2016 uint32_t tmp;
2017 DMAC_CRITICAL_SECTION_ENTER();
2018 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2019 tmp &= ~DMAC_PRICTRL0_RRLVLEN3;
2020 tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos;
2021 ((Dmac *)hw)->PRICTRL0.reg = tmp;
2022 DMAC_CRITICAL_SECTION_LEAVE();
2023 }
2024
hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void * const hw)2025 static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw)
2026 {
2027 DMAC_CRITICAL_SECTION_ENTER();
2028 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3;
2029 DMAC_CRITICAL_SECTION_LEAVE();
2030 }
2031
hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void * const hw)2032 static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw)
2033 {
2034 DMAC_CRITICAL_SECTION_ENTER();
2035 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3;
2036 DMAC_CRITICAL_SECTION_LEAVE();
2037 }
2038
hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2039 static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2040 {
2041 DMAC_CRITICAL_SECTION_ENTER();
2042 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask);
2043 DMAC_CRITICAL_SECTION_LEAVE();
2044 }
2045
hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2046 static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw,
2047 hri_dmac_prictrl0_reg_t mask)
2048 {
2049 uint32_t tmp;
2050 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2051 tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos;
2052 return tmp;
2053 }
2054
hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void * const hw,hri_dmac_prictrl0_reg_t data)2055 static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
2056 {
2057 uint32_t tmp;
2058 DMAC_CRITICAL_SECTION_ENTER();
2059 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2060 tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk;
2061 tmp |= DMAC_PRICTRL0_LVLPRI0(data);
2062 ((Dmac *)hw)->PRICTRL0.reg = tmp;
2063 DMAC_CRITICAL_SECTION_LEAVE();
2064 }
2065
hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2066 static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2067 {
2068 DMAC_CRITICAL_SECTION_ENTER();
2069 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask);
2070 DMAC_CRITICAL_SECTION_LEAVE();
2071 }
2072
hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2073 static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2074 {
2075 DMAC_CRITICAL_SECTION_ENTER();
2076 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask);
2077 DMAC_CRITICAL_SECTION_LEAVE();
2078 }
2079
hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void * const hw)2080 static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw)
2081 {
2082 uint32_t tmp;
2083 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2084 tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos;
2085 return tmp;
2086 }
2087
hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2088 static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2089 {
2090 DMAC_CRITICAL_SECTION_ENTER();
2091 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask);
2092 DMAC_CRITICAL_SECTION_LEAVE();
2093 }
2094
hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2095 static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw,
2096 hri_dmac_prictrl0_reg_t mask)
2097 {
2098 uint32_t tmp;
2099 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2100 tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos;
2101 return tmp;
2102 }
2103
hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void * const hw,hri_dmac_prictrl0_reg_t data)2104 static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
2105 {
2106 uint32_t tmp;
2107 DMAC_CRITICAL_SECTION_ENTER();
2108 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2109 tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk;
2110 tmp |= DMAC_PRICTRL0_LVLPRI1(data);
2111 ((Dmac *)hw)->PRICTRL0.reg = tmp;
2112 DMAC_CRITICAL_SECTION_LEAVE();
2113 }
2114
hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2115 static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2116 {
2117 DMAC_CRITICAL_SECTION_ENTER();
2118 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask);
2119 DMAC_CRITICAL_SECTION_LEAVE();
2120 }
2121
hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2122 static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2123 {
2124 DMAC_CRITICAL_SECTION_ENTER();
2125 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask);
2126 DMAC_CRITICAL_SECTION_LEAVE();
2127 }
2128
hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void * const hw)2129 static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw)
2130 {
2131 uint32_t tmp;
2132 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2133 tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos;
2134 return tmp;
2135 }
2136
hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2137 static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2138 {
2139 DMAC_CRITICAL_SECTION_ENTER();
2140 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask);
2141 DMAC_CRITICAL_SECTION_LEAVE();
2142 }
2143
hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2144 static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw,
2145 hri_dmac_prictrl0_reg_t mask)
2146 {
2147 uint32_t tmp;
2148 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2149 tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos;
2150 return tmp;
2151 }
2152
hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void * const hw,hri_dmac_prictrl0_reg_t data)2153 static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
2154 {
2155 uint32_t tmp;
2156 DMAC_CRITICAL_SECTION_ENTER();
2157 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2158 tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk;
2159 tmp |= DMAC_PRICTRL0_LVLPRI2(data);
2160 ((Dmac *)hw)->PRICTRL0.reg = tmp;
2161 DMAC_CRITICAL_SECTION_LEAVE();
2162 }
2163
hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2164 static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2165 {
2166 DMAC_CRITICAL_SECTION_ENTER();
2167 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask);
2168 DMAC_CRITICAL_SECTION_LEAVE();
2169 }
2170
hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2171 static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2172 {
2173 DMAC_CRITICAL_SECTION_ENTER();
2174 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask);
2175 DMAC_CRITICAL_SECTION_LEAVE();
2176 }
2177
hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void * const hw)2178 static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw)
2179 {
2180 uint32_t tmp;
2181 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2182 tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos;
2183 return tmp;
2184 }
2185
hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2186 static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2187 {
2188 DMAC_CRITICAL_SECTION_ENTER();
2189 ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask);
2190 DMAC_CRITICAL_SECTION_LEAVE();
2191 }
2192
hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2193 static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw,
2194 hri_dmac_prictrl0_reg_t mask)
2195 {
2196 uint32_t tmp;
2197 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2198 tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos;
2199 return tmp;
2200 }
2201
hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void * const hw,hri_dmac_prictrl0_reg_t data)2202 static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data)
2203 {
2204 uint32_t tmp;
2205 DMAC_CRITICAL_SECTION_ENTER();
2206 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2207 tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk;
2208 tmp |= DMAC_PRICTRL0_LVLPRI3(data);
2209 ((Dmac *)hw)->PRICTRL0.reg = tmp;
2210 DMAC_CRITICAL_SECTION_LEAVE();
2211 }
2212
hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2213 static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2214 {
2215 DMAC_CRITICAL_SECTION_ENTER();
2216 ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask);
2217 DMAC_CRITICAL_SECTION_LEAVE();
2218 }
2219
hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void * const hw,hri_dmac_prictrl0_reg_t mask)2220 static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2221 {
2222 DMAC_CRITICAL_SECTION_ENTER();
2223 ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask);
2224 DMAC_CRITICAL_SECTION_LEAVE();
2225 }
2226
hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void * const hw)2227 static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw)
2228 {
2229 uint32_t tmp;
2230 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2231 tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos;
2232 return tmp;
2233 }
2234
hri_dmac_set_PRICTRL0_reg(const void * const hw,hri_dmac_prictrl0_reg_t mask)2235 static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2236 {
2237 DMAC_CRITICAL_SECTION_ENTER();
2238 ((Dmac *)hw)->PRICTRL0.reg |= mask;
2239 DMAC_CRITICAL_SECTION_LEAVE();
2240 }
2241
hri_dmac_get_PRICTRL0_reg(const void * const hw,hri_dmac_prictrl0_reg_t mask)2242 static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2243 {
2244 uint32_t tmp;
2245 tmp = ((Dmac *)hw)->PRICTRL0.reg;
2246 tmp &= mask;
2247 return tmp;
2248 }
2249
hri_dmac_write_PRICTRL0_reg(const void * const hw,hri_dmac_prictrl0_reg_t data)2250 static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data)
2251 {
2252 DMAC_CRITICAL_SECTION_ENTER();
2253 ((Dmac *)hw)->PRICTRL0.reg = data;
2254 DMAC_CRITICAL_SECTION_LEAVE();
2255 }
2256
hri_dmac_clear_PRICTRL0_reg(const void * const hw,hri_dmac_prictrl0_reg_t mask)2257 static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2258 {
2259 DMAC_CRITICAL_SECTION_ENTER();
2260 ((Dmac *)hw)->PRICTRL0.reg &= ~mask;
2261 DMAC_CRITICAL_SECTION_LEAVE();
2262 }
2263
hri_dmac_toggle_PRICTRL0_reg(const void * const hw,hri_dmac_prictrl0_reg_t mask)2264 static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask)
2265 {
2266 DMAC_CRITICAL_SECTION_ENTER();
2267 ((Dmac *)hw)->PRICTRL0.reg ^= mask;
2268 DMAC_CRITICAL_SECTION_LEAVE();
2269 }
2270
hri_dmac_read_PRICTRL0_reg(const void * const hw)2271 static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw)
2272 {
2273 return ((Dmac *)hw)->PRICTRL0.reg;
2274 }
2275
hri_dmac_set_INTPEND_TERR_bit(const void * const hw)2276 static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw)
2277 {
2278 DMAC_CRITICAL_SECTION_ENTER();
2279 ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR;
2280 DMAC_CRITICAL_SECTION_LEAVE();
2281 }
2282
hri_dmac_get_INTPEND_TERR_bit(const void * const hw)2283 static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw)
2284 {
2285 uint16_t tmp;
2286 tmp = ((Dmac *)hw)->INTPEND.reg;
2287 tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos;
2288 return (bool)tmp;
2289 }
2290
hri_dmac_write_INTPEND_TERR_bit(const void * const hw,bool value)2291 static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value)
2292 {
2293 uint16_t tmp;
2294 DMAC_CRITICAL_SECTION_ENTER();
2295 tmp = ((Dmac *)hw)->INTPEND.reg;
2296 tmp &= ~DMAC_INTPEND_TERR;
2297 tmp |= value << DMAC_INTPEND_TERR_Pos;
2298 ((Dmac *)hw)->INTPEND.reg = tmp;
2299 DMAC_CRITICAL_SECTION_LEAVE();
2300 }
2301
hri_dmac_clear_INTPEND_TERR_bit(const void * const hw)2302 static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw)
2303 {
2304 DMAC_CRITICAL_SECTION_ENTER();
2305 ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR;
2306 DMAC_CRITICAL_SECTION_LEAVE();
2307 }
2308
hri_dmac_toggle_INTPEND_TERR_bit(const void * const hw)2309 static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw)
2310 {
2311 DMAC_CRITICAL_SECTION_ENTER();
2312 ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR;
2313 DMAC_CRITICAL_SECTION_LEAVE();
2314 }
2315
hri_dmac_set_INTPEND_TCMPL_bit(const void * const hw)2316 static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw)
2317 {
2318 DMAC_CRITICAL_SECTION_ENTER();
2319 ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL;
2320 DMAC_CRITICAL_SECTION_LEAVE();
2321 }
2322
hri_dmac_get_INTPEND_TCMPL_bit(const void * const hw)2323 static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw)
2324 {
2325 uint16_t tmp;
2326 tmp = ((Dmac *)hw)->INTPEND.reg;
2327 tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos;
2328 return (bool)tmp;
2329 }
2330
hri_dmac_write_INTPEND_TCMPL_bit(const void * const hw,bool value)2331 static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value)
2332 {
2333 uint16_t tmp;
2334 DMAC_CRITICAL_SECTION_ENTER();
2335 tmp = ((Dmac *)hw)->INTPEND.reg;
2336 tmp &= ~DMAC_INTPEND_TCMPL;
2337 tmp |= value << DMAC_INTPEND_TCMPL_Pos;
2338 ((Dmac *)hw)->INTPEND.reg = tmp;
2339 DMAC_CRITICAL_SECTION_LEAVE();
2340 }
2341
hri_dmac_clear_INTPEND_TCMPL_bit(const void * const hw)2342 static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw)
2343 {
2344 DMAC_CRITICAL_SECTION_ENTER();
2345 ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL;
2346 DMAC_CRITICAL_SECTION_LEAVE();
2347 }
2348
hri_dmac_toggle_INTPEND_TCMPL_bit(const void * const hw)2349 static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw)
2350 {
2351 DMAC_CRITICAL_SECTION_ENTER();
2352 ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL;
2353 DMAC_CRITICAL_SECTION_LEAVE();
2354 }
2355
hri_dmac_set_INTPEND_SUSP_bit(const void * const hw)2356 static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw)
2357 {
2358 DMAC_CRITICAL_SECTION_ENTER();
2359 ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP;
2360 DMAC_CRITICAL_SECTION_LEAVE();
2361 }
2362
hri_dmac_get_INTPEND_SUSP_bit(const void * const hw)2363 static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw)
2364 {
2365 uint16_t tmp;
2366 tmp = ((Dmac *)hw)->INTPEND.reg;
2367 tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos;
2368 return (bool)tmp;
2369 }
2370
hri_dmac_write_INTPEND_SUSP_bit(const void * const hw,bool value)2371 static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value)
2372 {
2373 uint16_t tmp;
2374 DMAC_CRITICAL_SECTION_ENTER();
2375 tmp = ((Dmac *)hw)->INTPEND.reg;
2376 tmp &= ~DMAC_INTPEND_SUSP;
2377 tmp |= value << DMAC_INTPEND_SUSP_Pos;
2378 ((Dmac *)hw)->INTPEND.reg = tmp;
2379 DMAC_CRITICAL_SECTION_LEAVE();
2380 }
2381
hri_dmac_clear_INTPEND_SUSP_bit(const void * const hw)2382 static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw)
2383 {
2384 DMAC_CRITICAL_SECTION_ENTER();
2385 ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP;
2386 DMAC_CRITICAL_SECTION_LEAVE();
2387 }
2388
hri_dmac_toggle_INTPEND_SUSP_bit(const void * const hw)2389 static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw)
2390 {
2391 DMAC_CRITICAL_SECTION_ENTER();
2392 ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP;
2393 DMAC_CRITICAL_SECTION_LEAVE();
2394 }
2395
hri_dmac_set_INTPEND_FERR_bit(const void * const hw)2396 static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw)
2397 {
2398 DMAC_CRITICAL_SECTION_ENTER();
2399 ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR;
2400 DMAC_CRITICAL_SECTION_LEAVE();
2401 }
2402
hri_dmac_get_INTPEND_FERR_bit(const void * const hw)2403 static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw)
2404 {
2405 uint16_t tmp;
2406 tmp = ((Dmac *)hw)->INTPEND.reg;
2407 tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos;
2408 return (bool)tmp;
2409 }
2410
hri_dmac_write_INTPEND_FERR_bit(const void * const hw,bool value)2411 static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value)
2412 {
2413 uint16_t tmp;
2414 DMAC_CRITICAL_SECTION_ENTER();
2415 tmp = ((Dmac *)hw)->INTPEND.reg;
2416 tmp &= ~DMAC_INTPEND_FERR;
2417 tmp |= value << DMAC_INTPEND_FERR_Pos;
2418 ((Dmac *)hw)->INTPEND.reg = tmp;
2419 DMAC_CRITICAL_SECTION_LEAVE();
2420 }
2421
hri_dmac_clear_INTPEND_FERR_bit(const void * const hw)2422 static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw)
2423 {
2424 DMAC_CRITICAL_SECTION_ENTER();
2425 ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR;
2426 DMAC_CRITICAL_SECTION_LEAVE();
2427 }
2428
hri_dmac_toggle_INTPEND_FERR_bit(const void * const hw)2429 static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw)
2430 {
2431 DMAC_CRITICAL_SECTION_ENTER();
2432 ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR;
2433 DMAC_CRITICAL_SECTION_LEAVE();
2434 }
2435
hri_dmac_set_INTPEND_BUSY_bit(const void * const hw)2436 static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw)
2437 {
2438 DMAC_CRITICAL_SECTION_ENTER();
2439 ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY;
2440 DMAC_CRITICAL_SECTION_LEAVE();
2441 }
2442
hri_dmac_get_INTPEND_BUSY_bit(const void * const hw)2443 static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw)
2444 {
2445 uint16_t tmp;
2446 tmp = ((Dmac *)hw)->INTPEND.reg;
2447 tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos;
2448 return (bool)tmp;
2449 }
2450
hri_dmac_write_INTPEND_BUSY_bit(const void * const hw,bool value)2451 static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value)
2452 {
2453 uint16_t tmp;
2454 DMAC_CRITICAL_SECTION_ENTER();
2455 tmp = ((Dmac *)hw)->INTPEND.reg;
2456 tmp &= ~DMAC_INTPEND_BUSY;
2457 tmp |= value << DMAC_INTPEND_BUSY_Pos;
2458 ((Dmac *)hw)->INTPEND.reg = tmp;
2459 DMAC_CRITICAL_SECTION_LEAVE();
2460 }
2461
hri_dmac_clear_INTPEND_BUSY_bit(const void * const hw)2462 static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw)
2463 {
2464 DMAC_CRITICAL_SECTION_ENTER();
2465 ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY;
2466 DMAC_CRITICAL_SECTION_LEAVE();
2467 }
2468
hri_dmac_toggle_INTPEND_BUSY_bit(const void * const hw)2469 static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw)
2470 {
2471 DMAC_CRITICAL_SECTION_ENTER();
2472 ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY;
2473 DMAC_CRITICAL_SECTION_LEAVE();
2474 }
2475
hri_dmac_set_INTPEND_PEND_bit(const void * const hw)2476 static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw)
2477 {
2478 DMAC_CRITICAL_SECTION_ENTER();
2479 ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND;
2480 DMAC_CRITICAL_SECTION_LEAVE();
2481 }
2482
hri_dmac_get_INTPEND_PEND_bit(const void * const hw)2483 static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw)
2484 {
2485 uint16_t tmp;
2486 tmp = ((Dmac *)hw)->INTPEND.reg;
2487 tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos;
2488 return (bool)tmp;
2489 }
2490
hri_dmac_write_INTPEND_PEND_bit(const void * const hw,bool value)2491 static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value)
2492 {
2493 uint16_t tmp;
2494 DMAC_CRITICAL_SECTION_ENTER();
2495 tmp = ((Dmac *)hw)->INTPEND.reg;
2496 tmp &= ~DMAC_INTPEND_PEND;
2497 tmp |= value << DMAC_INTPEND_PEND_Pos;
2498 ((Dmac *)hw)->INTPEND.reg = tmp;
2499 DMAC_CRITICAL_SECTION_LEAVE();
2500 }
2501
hri_dmac_clear_INTPEND_PEND_bit(const void * const hw)2502 static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw)
2503 {
2504 DMAC_CRITICAL_SECTION_ENTER();
2505 ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND;
2506 DMAC_CRITICAL_SECTION_LEAVE();
2507 }
2508
hri_dmac_toggle_INTPEND_PEND_bit(const void * const hw)2509 static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw)
2510 {
2511 DMAC_CRITICAL_SECTION_ENTER();
2512 ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND;
2513 DMAC_CRITICAL_SECTION_LEAVE();
2514 }
2515
hri_dmac_set_INTPEND_ID_bf(const void * const hw,hri_dmac_intpend_reg_t mask)2516 static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
2517 {
2518 DMAC_CRITICAL_SECTION_ENTER();
2519 ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask);
2520 DMAC_CRITICAL_SECTION_LEAVE();
2521 }
2522
hri_dmac_get_INTPEND_ID_bf(const void * const hw,hri_dmac_intpend_reg_t mask)2523 static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
2524 {
2525 uint16_t tmp;
2526 tmp = ((Dmac *)hw)->INTPEND.reg;
2527 tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos;
2528 return tmp;
2529 }
2530
hri_dmac_write_INTPEND_ID_bf(const void * const hw,hri_dmac_intpend_reg_t data)2531 static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data)
2532 {
2533 uint16_t tmp;
2534 DMAC_CRITICAL_SECTION_ENTER();
2535 tmp = ((Dmac *)hw)->INTPEND.reg;
2536 tmp &= ~DMAC_INTPEND_ID_Msk;
2537 tmp |= DMAC_INTPEND_ID(data);
2538 ((Dmac *)hw)->INTPEND.reg = tmp;
2539 DMAC_CRITICAL_SECTION_LEAVE();
2540 }
2541
hri_dmac_clear_INTPEND_ID_bf(const void * const hw,hri_dmac_intpend_reg_t mask)2542 static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
2543 {
2544 DMAC_CRITICAL_SECTION_ENTER();
2545 ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask);
2546 DMAC_CRITICAL_SECTION_LEAVE();
2547 }
2548
hri_dmac_toggle_INTPEND_ID_bf(const void * const hw,hri_dmac_intpend_reg_t mask)2549 static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask)
2550 {
2551 DMAC_CRITICAL_SECTION_ENTER();
2552 ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask);
2553 DMAC_CRITICAL_SECTION_LEAVE();
2554 }
2555
hri_dmac_read_INTPEND_ID_bf(const void * const hw)2556 static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw)
2557 {
2558 uint16_t tmp;
2559 tmp = ((Dmac *)hw)->INTPEND.reg;
2560 tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos;
2561 return tmp;
2562 }
2563
hri_dmac_set_INTPEND_reg(const void * const hw,hri_dmac_intpend_reg_t mask)2564 static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
2565 {
2566 DMAC_CRITICAL_SECTION_ENTER();
2567 ((Dmac *)hw)->INTPEND.reg |= mask;
2568 DMAC_CRITICAL_SECTION_LEAVE();
2569 }
2570
hri_dmac_get_INTPEND_reg(const void * const hw,hri_dmac_intpend_reg_t mask)2571 static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
2572 {
2573 uint16_t tmp;
2574 tmp = ((Dmac *)hw)->INTPEND.reg;
2575 tmp &= mask;
2576 return tmp;
2577 }
2578
hri_dmac_write_INTPEND_reg(const void * const hw,hri_dmac_intpend_reg_t data)2579 static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data)
2580 {
2581 DMAC_CRITICAL_SECTION_ENTER();
2582 ((Dmac *)hw)->INTPEND.reg = data;
2583 DMAC_CRITICAL_SECTION_LEAVE();
2584 }
2585
hri_dmac_clear_INTPEND_reg(const void * const hw,hri_dmac_intpend_reg_t mask)2586 static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
2587 {
2588 DMAC_CRITICAL_SECTION_ENTER();
2589 ((Dmac *)hw)->INTPEND.reg &= ~mask;
2590 DMAC_CRITICAL_SECTION_LEAVE();
2591 }
2592
hri_dmac_toggle_INTPEND_reg(const void * const hw,hri_dmac_intpend_reg_t mask)2593 static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask)
2594 {
2595 DMAC_CRITICAL_SECTION_ENTER();
2596 ((Dmac *)hw)->INTPEND.reg ^= mask;
2597 DMAC_CRITICAL_SECTION_LEAVE();
2598 }
2599
hri_dmac_read_INTPEND_reg(const void * const hw)2600 static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw)
2601 {
2602 return ((Dmac *)hw)->INTPEND.reg;
2603 }
2604
hri_dmac_set_BASEADDR_BASEADDR_bf(const void * const hw,hri_dmac_baseaddr_reg_t mask)2605 static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
2606 {
2607 DMAC_CRITICAL_SECTION_ENTER();
2608 ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask);
2609 DMAC_CRITICAL_SECTION_LEAVE();
2610 }
2611
hri_dmac_get_BASEADDR_BASEADDR_bf(const void * const hw,hri_dmac_baseaddr_reg_t mask)2612 static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw,
2613 hri_dmac_baseaddr_reg_t mask)
2614 {
2615 uint32_t tmp;
2616 tmp = ((Dmac *)hw)->BASEADDR.reg;
2617 tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos;
2618 return tmp;
2619 }
2620
hri_dmac_write_BASEADDR_BASEADDR_bf(const void * const hw,hri_dmac_baseaddr_reg_t data)2621 static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data)
2622 {
2623 uint32_t tmp;
2624 DMAC_CRITICAL_SECTION_ENTER();
2625 tmp = ((Dmac *)hw)->BASEADDR.reg;
2626 tmp &= ~DMAC_BASEADDR_BASEADDR_Msk;
2627 tmp |= DMAC_BASEADDR_BASEADDR(data);
2628 ((Dmac *)hw)->BASEADDR.reg = tmp;
2629 DMAC_CRITICAL_SECTION_LEAVE();
2630 }
2631
hri_dmac_clear_BASEADDR_BASEADDR_bf(const void * const hw,hri_dmac_baseaddr_reg_t mask)2632 static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
2633 {
2634 DMAC_CRITICAL_SECTION_ENTER();
2635 ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask);
2636 DMAC_CRITICAL_SECTION_LEAVE();
2637 }
2638
hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void * const hw,hri_dmac_baseaddr_reg_t mask)2639 static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask)
2640 {
2641 DMAC_CRITICAL_SECTION_ENTER();
2642 ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask);
2643 DMAC_CRITICAL_SECTION_LEAVE();
2644 }
2645
hri_dmac_read_BASEADDR_BASEADDR_bf(const void * const hw)2646 static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw)
2647 {
2648 uint32_t tmp;
2649 tmp = ((Dmac *)hw)->BASEADDR.reg;
2650 tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos;
2651 return tmp;
2652 }
2653
hri_dmac_set_BASEADDR_reg(const void * const hw,hri_dmac_baseaddr_reg_t mask)2654 static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
2655 {
2656 DMAC_CRITICAL_SECTION_ENTER();
2657 ((Dmac *)hw)->BASEADDR.reg |= mask;
2658 DMAC_CRITICAL_SECTION_LEAVE();
2659 }
2660
hri_dmac_get_BASEADDR_reg(const void * const hw,hri_dmac_baseaddr_reg_t mask)2661 static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
2662 {
2663 uint32_t tmp;
2664 tmp = ((Dmac *)hw)->BASEADDR.reg;
2665 tmp &= mask;
2666 return tmp;
2667 }
2668
hri_dmac_write_BASEADDR_reg(const void * const hw,hri_dmac_baseaddr_reg_t data)2669 static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data)
2670 {
2671 DMAC_CRITICAL_SECTION_ENTER();
2672 ((Dmac *)hw)->BASEADDR.reg = data;
2673 DMAC_CRITICAL_SECTION_LEAVE();
2674 }
2675
hri_dmac_clear_BASEADDR_reg(const void * const hw,hri_dmac_baseaddr_reg_t mask)2676 static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
2677 {
2678 DMAC_CRITICAL_SECTION_ENTER();
2679 ((Dmac *)hw)->BASEADDR.reg &= ~mask;
2680 DMAC_CRITICAL_SECTION_LEAVE();
2681 }
2682
hri_dmac_toggle_BASEADDR_reg(const void * const hw,hri_dmac_baseaddr_reg_t mask)2683 static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask)
2684 {
2685 DMAC_CRITICAL_SECTION_ENTER();
2686 ((Dmac *)hw)->BASEADDR.reg ^= mask;
2687 DMAC_CRITICAL_SECTION_LEAVE();
2688 }
2689
hri_dmac_read_BASEADDR_reg(const void * const hw)2690 static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw)
2691 {
2692 return ((Dmac *)hw)->BASEADDR.reg;
2693 }
2694
hri_dmac_set_WRBADDR_WRBADDR_bf(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2695 static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2696 {
2697 DMAC_CRITICAL_SECTION_ENTER();
2698 ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask);
2699 DMAC_CRITICAL_SECTION_LEAVE();
2700 }
2701
hri_dmac_get_WRBADDR_WRBADDR_bf(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2702 static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2703 {
2704 uint32_t tmp;
2705 tmp = ((Dmac *)hw)->WRBADDR.reg;
2706 tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos;
2707 return tmp;
2708 }
2709
hri_dmac_write_WRBADDR_WRBADDR_bf(const void * const hw,hri_dmac_wrbaddr_reg_t data)2710 static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data)
2711 {
2712 uint32_t tmp;
2713 DMAC_CRITICAL_SECTION_ENTER();
2714 tmp = ((Dmac *)hw)->WRBADDR.reg;
2715 tmp &= ~DMAC_WRBADDR_WRBADDR_Msk;
2716 tmp |= DMAC_WRBADDR_WRBADDR(data);
2717 ((Dmac *)hw)->WRBADDR.reg = tmp;
2718 DMAC_CRITICAL_SECTION_LEAVE();
2719 }
2720
hri_dmac_clear_WRBADDR_WRBADDR_bf(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2721 static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2722 {
2723 DMAC_CRITICAL_SECTION_ENTER();
2724 ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask);
2725 DMAC_CRITICAL_SECTION_LEAVE();
2726 }
2727
hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2728 static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2729 {
2730 DMAC_CRITICAL_SECTION_ENTER();
2731 ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask);
2732 DMAC_CRITICAL_SECTION_LEAVE();
2733 }
2734
hri_dmac_read_WRBADDR_WRBADDR_bf(const void * const hw)2735 static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw)
2736 {
2737 uint32_t tmp;
2738 tmp = ((Dmac *)hw)->WRBADDR.reg;
2739 tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos;
2740 return tmp;
2741 }
2742
hri_dmac_set_WRBADDR_reg(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2743 static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2744 {
2745 DMAC_CRITICAL_SECTION_ENTER();
2746 ((Dmac *)hw)->WRBADDR.reg |= mask;
2747 DMAC_CRITICAL_SECTION_LEAVE();
2748 }
2749
hri_dmac_get_WRBADDR_reg(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2750 static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2751 {
2752 uint32_t tmp;
2753 tmp = ((Dmac *)hw)->WRBADDR.reg;
2754 tmp &= mask;
2755 return tmp;
2756 }
2757
hri_dmac_write_WRBADDR_reg(const void * const hw,hri_dmac_wrbaddr_reg_t data)2758 static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data)
2759 {
2760 DMAC_CRITICAL_SECTION_ENTER();
2761 ((Dmac *)hw)->WRBADDR.reg = data;
2762 DMAC_CRITICAL_SECTION_LEAVE();
2763 }
2764
hri_dmac_clear_WRBADDR_reg(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2765 static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2766 {
2767 DMAC_CRITICAL_SECTION_ENTER();
2768 ((Dmac *)hw)->WRBADDR.reg &= ~mask;
2769 DMAC_CRITICAL_SECTION_LEAVE();
2770 }
2771
hri_dmac_toggle_WRBADDR_reg(const void * const hw,hri_dmac_wrbaddr_reg_t mask)2772 static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask)
2773 {
2774 DMAC_CRITICAL_SECTION_ENTER();
2775 ((Dmac *)hw)->WRBADDR.reg ^= mask;
2776 DMAC_CRITICAL_SECTION_LEAVE();
2777 }
2778
hri_dmac_read_WRBADDR_reg(const void * const hw)2779 static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw)
2780 {
2781 return ((Dmac *)hw)->WRBADDR.reg;
2782 }
2783
hri_dmac_set_CHID_ID_bf(const void * const hw,hri_dmac_chid_reg_t mask)2784 static inline void hri_dmac_set_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
2785 {
2786 DMAC_CRITICAL_SECTION_ENTER();
2787 ((Dmac *)hw)->CHID.reg |= DMAC_CHID_ID(mask);
2788 DMAC_CRITICAL_SECTION_LEAVE();
2789 }
2790
hri_dmac_get_CHID_ID_bf(const void * const hw,hri_dmac_chid_reg_t mask)2791 static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
2792 {
2793 uint8_t tmp;
2794 tmp = ((Dmac *)hw)->CHID.reg;
2795 tmp = (tmp & DMAC_CHID_ID(mask)) >> DMAC_CHID_ID_Pos;
2796 return tmp;
2797 }
2798
hri_dmac_write_CHID_ID_bf(const void * const hw,hri_dmac_chid_reg_t data)2799 static inline void hri_dmac_write_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t data)
2800 {
2801 uint8_t tmp;
2802 DMAC_CRITICAL_SECTION_ENTER();
2803 tmp = ((Dmac *)hw)->CHID.reg;
2804 tmp &= ~DMAC_CHID_ID_Msk;
2805 tmp |= DMAC_CHID_ID(data);
2806 ((Dmac *)hw)->CHID.reg = tmp;
2807 DMAC_CRITICAL_SECTION_LEAVE();
2808 }
2809
hri_dmac_clear_CHID_ID_bf(const void * const hw,hri_dmac_chid_reg_t mask)2810 static inline void hri_dmac_clear_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
2811 {
2812 DMAC_CRITICAL_SECTION_ENTER();
2813 ((Dmac *)hw)->CHID.reg &= ~DMAC_CHID_ID(mask);
2814 DMAC_CRITICAL_SECTION_LEAVE();
2815 }
2816
hri_dmac_toggle_CHID_ID_bf(const void * const hw,hri_dmac_chid_reg_t mask)2817 static inline void hri_dmac_toggle_CHID_ID_bf(const void *const hw, hri_dmac_chid_reg_t mask)
2818 {
2819 DMAC_CRITICAL_SECTION_ENTER();
2820 ((Dmac *)hw)->CHID.reg ^= DMAC_CHID_ID(mask);
2821 DMAC_CRITICAL_SECTION_LEAVE();
2822 }
2823
hri_dmac_read_CHID_ID_bf(const void * const hw)2824 static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_ID_bf(const void *const hw)
2825 {
2826 uint8_t tmp;
2827 tmp = ((Dmac *)hw)->CHID.reg;
2828 tmp = (tmp & DMAC_CHID_ID_Msk) >> DMAC_CHID_ID_Pos;
2829 return tmp;
2830 }
2831
hri_dmac_set_CHID_reg(const void * const hw,hri_dmac_chid_reg_t mask)2832 static inline void hri_dmac_set_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
2833 {
2834 DMAC_CRITICAL_SECTION_ENTER();
2835 ((Dmac *)hw)->CHID.reg |= mask;
2836 DMAC_CRITICAL_SECTION_LEAVE();
2837 }
2838
hri_dmac_get_CHID_reg(const void * const hw,hri_dmac_chid_reg_t mask)2839 static inline hri_dmac_chid_reg_t hri_dmac_get_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
2840 {
2841 uint8_t tmp;
2842 tmp = ((Dmac *)hw)->CHID.reg;
2843 tmp &= mask;
2844 return tmp;
2845 }
2846
hri_dmac_write_CHID_reg(const void * const hw,hri_dmac_chid_reg_t data)2847 static inline void hri_dmac_write_CHID_reg(const void *const hw, hri_dmac_chid_reg_t data)
2848 {
2849 DMAC_CRITICAL_SECTION_ENTER();
2850 ((Dmac *)hw)->CHID.reg = data;
2851 DMAC_CRITICAL_SECTION_LEAVE();
2852 }
2853
hri_dmac_clear_CHID_reg(const void * const hw,hri_dmac_chid_reg_t mask)2854 static inline void hri_dmac_clear_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
2855 {
2856 DMAC_CRITICAL_SECTION_ENTER();
2857 ((Dmac *)hw)->CHID.reg &= ~mask;
2858 DMAC_CRITICAL_SECTION_LEAVE();
2859 }
2860
hri_dmac_toggle_CHID_reg(const void * const hw,hri_dmac_chid_reg_t mask)2861 static inline void hri_dmac_toggle_CHID_reg(const void *const hw, hri_dmac_chid_reg_t mask)
2862 {
2863 DMAC_CRITICAL_SECTION_ENTER();
2864 ((Dmac *)hw)->CHID.reg ^= mask;
2865 DMAC_CRITICAL_SECTION_LEAVE();
2866 }
2867
hri_dmac_read_CHID_reg(const void * const hw)2868 static inline hri_dmac_chid_reg_t hri_dmac_read_CHID_reg(const void *const hw)
2869 {
2870 return ((Dmac *)hw)->CHID.reg;
2871 }
2872
hri_dmac_set_CHCTRLA_SWRST_bit(const void * const hw)2873 static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw)
2874 {
2875 DMAC_CRITICAL_SECTION_ENTER();
2876 ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST;
2877 DMAC_CRITICAL_SECTION_LEAVE();
2878 }
2879
hri_dmac_get_CHCTRLA_SWRST_bit(const void * const hw)2880 static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw)
2881 {
2882 uint8_t tmp;
2883 tmp = ((Dmac *)hw)->CHCTRLA.reg;
2884 tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos;
2885 return (bool)tmp;
2886 }
2887
hri_dmac_set_CHCTRLA_ENABLE_bit(const void * const hw)2888 static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw)
2889 {
2890 DMAC_CRITICAL_SECTION_ENTER();
2891 ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
2892 DMAC_CRITICAL_SECTION_LEAVE();
2893 }
2894
hri_dmac_get_CHCTRLA_ENABLE_bit(const void * const hw)2895 static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw)
2896 {
2897 uint8_t tmp;
2898 tmp = ((Dmac *)hw)->CHCTRLA.reg;
2899 tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos;
2900 return (bool)tmp;
2901 }
2902
hri_dmac_write_CHCTRLA_ENABLE_bit(const void * const hw,bool value)2903 static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value)
2904 {
2905 uint8_t tmp;
2906 DMAC_CRITICAL_SECTION_ENTER();
2907 tmp = ((Dmac *)hw)->CHCTRLA.reg;
2908 tmp &= ~DMAC_CHCTRLA_ENABLE;
2909 tmp |= value << DMAC_CHCTRLA_ENABLE_Pos;
2910 ((Dmac *)hw)->CHCTRLA.reg = tmp;
2911 DMAC_CRITICAL_SECTION_LEAVE();
2912 }
2913
hri_dmac_clear_CHCTRLA_ENABLE_bit(const void * const hw)2914 static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw)
2915 {
2916 DMAC_CRITICAL_SECTION_ENTER();
2917 ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
2918 DMAC_CRITICAL_SECTION_LEAVE();
2919 }
2920
hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void * const hw)2921 static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw)
2922 {
2923 DMAC_CRITICAL_SECTION_ENTER();
2924 ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE;
2925 DMAC_CRITICAL_SECTION_LEAVE();
2926 }
2927
hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void * const hw)2928 static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw)
2929 {
2930 DMAC_CRITICAL_SECTION_ENTER();
2931 ((Dmac *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
2932 DMAC_CRITICAL_SECTION_LEAVE();
2933 }
2934
hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void * const hw)2935 static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw)
2936 {
2937 uint8_t tmp;
2938 tmp = ((Dmac *)hw)->CHCTRLA.reg;
2939 tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos;
2940 return (bool)tmp;
2941 }
2942
hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void * const hw,bool value)2943 static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value)
2944 {
2945 uint8_t tmp;
2946 DMAC_CRITICAL_SECTION_ENTER();
2947 tmp = ((Dmac *)hw)->CHCTRLA.reg;
2948 tmp &= ~DMAC_CHCTRLA_RUNSTDBY;
2949 tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos;
2950 ((Dmac *)hw)->CHCTRLA.reg = tmp;
2951 DMAC_CRITICAL_SECTION_LEAVE();
2952 }
2953
hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void * const hw)2954 static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw)
2955 {
2956 DMAC_CRITICAL_SECTION_ENTER();
2957 ((Dmac *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY;
2958 DMAC_CRITICAL_SECTION_LEAVE();
2959 }
2960
hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void * const hw)2961 static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw)
2962 {
2963 DMAC_CRITICAL_SECTION_ENTER();
2964 ((Dmac *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY;
2965 DMAC_CRITICAL_SECTION_LEAVE();
2966 }
2967
hri_dmac_set_CHCTRLA_reg(const void * const hw,hri_dmac_chctrla_reg_t mask)2968 static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
2969 {
2970 DMAC_CRITICAL_SECTION_ENTER();
2971 ((Dmac *)hw)->CHCTRLA.reg |= mask;
2972 DMAC_CRITICAL_SECTION_LEAVE();
2973 }
2974
hri_dmac_get_CHCTRLA_reg(const void * const hw,hri_dmac_chctrla_reg_t mask)2975 static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
2976 {
2977 uint8_t tmp;
2978 tmp = ((Dmac *)hw)->CHCTRLA.reg;
2979 tmp &= mask;
2980 return tmp;
2981 }
2982
hri_dmac_write_CHCTRLA_reg(const void * const hw,hri_dmac_chctrla_reg_t data)2983 static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data)
2984 {
2985 DMAC_CRITICAL_SECTION_ENTER();
2986 ((Dmac *)hw)->CHCTRLA.reg = data;
2987 DMAC_CRITICAL_SECTION_LEAVE();
2988 }
2989
hri_dmac_clear_CHCTRLA_reg(const void * const hw,hri_dmac_chctrla_reg_t mask)2990 static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
2991 {
2992 DMAC_CRITICAL_SECTION_ENTER();
2993 ((Dmac *)hw)->CHCTRLA.reg &= ~mask;
2994 DMAC_CRITICAL_SECTION_LEAVE();
2995 }
2996
hri_dmac_toggle_CHCTRLA_reg(const void * const hw,hri_dmac_chctrla_reg_t mask)2997 static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask)
2998 {
2999 DMAC_CRITICAL_SECTION_ENTER();
3000 ((Dmac *)hw)->CHCTRLA.reg ^= mask;
3001 DMAC_CRITICAL_SECTION_LEAVE();
3002 }
3003
hri_dmac_read_CHCTRLA_reg(const void * const hw)3004 static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw)
3005 {
3006 return ((Dmac *)hw)->CHCTRLA.reg;
3007 }
3008
hri_dmac_set_CHCTRLB_EVIE_bit(const void * const hw)3009 static inline void hri_dmac_set_CHCTRLB_EVIE_bit(const void *const hw)
3010 {
3011 DMAC_CRITICAL_SECTION_ENTER();
3012 ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVIE;
3013 DMAC_CRITICAL_SECTION_LEAVE();
3014 }
3015
hri_dmac_get_CHCTRLB_EVIE_bit(const void * const hw)3016 static inline bool hri_dmac_get_CHCTRLB_EVIE_bit(const void *const hw)
3017 {
3018 uint32_t tmp;
3019 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3020 tmp = (tmp & DMAC_CHCTRLB_EVIE) >> DMAC_CHCTRLB_EVIE_Pos;
3021 return (bool)tmp;
3022 }
3023
hri_dmac_write_CHCTRLB_EVIE_bit(const void * const hw,bool value)3024 static inline void hri_dmac_write_CHCTRLB_EVIE_bit(const void *const hw, bool value)
3025 {
3026 uint32_t tmp;
3027 DMAC_CRITICAL_SECTION_ENTER();
3028 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3029 tmp &= ~DMAC_CHCTRLB_EVIE;
3030 tmp |= value << DMAC_CHCTRLB_EVIE_Pos;
3031 ((Dmac *)hw)->CHCTRLB.reg = tmp;
3032 DMAC_CRITICAL_SECTION_LEAVE();
3033 }
3034
hri_dmac_clear_CHCTRLB_EVIE_bit(const void * const hw)3035 static inline void hri_dmac_clear_CHCTRLB_EVIE_bit(const void *const hw)
3036 {
3037 DMAC_CRITICAL_SECTION_ENTER();
3038 ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVIE;
3039 DMAC_CRITICAL_SECTION_LEAVE();
3040 }
3041
hri_dmac_toggle_CHCTRLB_EVIE_bit(const void * const hw)3042 static inline void hri_dmac_toggle_CHCTRLB_EVIE_bit(const void *const hw)
3043 {
3044 DMAC_CRITICAL_SECTION_ENTER();
3045 ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVIE;
3046 DMAC_CRITICAL_SECTION_LEAVE();
3047 }
3048
hri_dmac_set_CHCTRLB_EVOE_bit(const void * const hw)3049 static inline void hri_dmac_set_CHCTRLB_EVOE_bit(const void *const hw)
3050 {
3051 DMAC_CRITICAL_SECTION_ENTER();
3052 ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVOE;
3053 DMAC_CRITICAL_SECTION_LEAVE();
3054 }
3055
hri_dmac_get_CHCTRLB_EVOE_bit(const void * const hw)3056 static inline bool hri_dmac_get_CHCTRLB_EVOE_bit(const void *const hw)
3057 {
3058 uint32_t tmp;
3059 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3060 tmp = (tmp & DMAC_CHCTRLB_EVOE) >> DMAC_CHCTRLB_EVOE_Pos;
3061 return (bool)tmp;
3062 }
3063
hri_dmac_write_CHCTRLB_EVOE_bit(const void * const hw,bool value)3064 static inline void hri_dmac_write_CHCTRLB_EVOE_bit(const void *const hw, bool value)
3065 {
3066 uint32_t tmp;
3067 DMAC_CRITICAL_SECTION_ENTER();
3068 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3069 tmp &= ~DMAC_CHCTRLB_EVOE;
3070 tmp |= value << DMAC_CHCTRLB_EVOE_Pos;
3071 ((Dmac *)hw)->CHCTRLB.reg = tmp;
3072 DMAC_CRITICAL_SECTION_LEAVE();
3073 }
3074
hri_dmac_clear_CHCTRLB_EVOE_bit(const void * const hw)3075 static inline void hri_dmac_clear_CHCTRLB_EVOE_bit(const void *const hw)
3076 {
3077 DMAC_CRITICAL_SECTION_ENTER();
3078 ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVOE;
3079 DMAC_CRITICAL_SECTION_LEAVE();
3080 }
3081
hri_dmac_toggle_CHCTRLB_EVOE_bit(const void * const hw)3082 static inline void hri_dmac_toggle_CHCTRLB_EVOE_bit(const void *const hw)
3083 {
3084 DMAC_CRITICAL_SECTION_ENTER();
3085 ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVOE;
3086 DMAC_CRITICAL_SECTION_LEAVE();
3087 }
3088
hri_dmac_set_CHCTRLB_EVACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3089 static inline void hri_dmac_set_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3090 {
3091 DMAC_CRITICAL_SECTION_ENTER();
3092 ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_EVACT(mask);
3093 DMAC_CRITICAL_SECTION_LEAVE();
3094 }
3095
hri_dmac_get_CHCTRLB_EVACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3096 static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3097 {
3098 uint32_t tmp;
3099 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3100 tmp = (tmp & DMAC_CHCTRLB_EVACT(mask)) >> DMAC_CHCTRLB_EVACT_Pos;
3101 return tmp;
3102 }
3103
hri_dmac_write_CHCTRLB_EVACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t data)3104 static inline void hri_dmac_write_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
3105 {
3106 uint32_t tmp;
3107 DMAC_CRITICAL_SECTION_ENTER();
3108 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3109 tmp &= ~DMAC_CHCTRLB_EVACT_Msk;
3110 tmp |= DMAC_CHCTRLB_EVACT(data);
3111 ((Dmac *)hw)->CHCTRLB.reg = tmp;
3112 DMAC_CRITICAL_SECTION_LEAVE();
3113 }
3114
hri_dmac_clear_CHCTRLB_EVACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3115 static inline void hri_dmac_clear_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3116 {
3117 DMAC_CRITICAL_SECTION_ENTER();
3118 ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_EVACT(mask);
3119 DMAC_CRITICAL_SECTION_LEAVE();
3120 }
3121
hri_dmac_toggle_CHCTRLB_EVACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3122 static inline void hri_dmac_toggle_CHCTRLB_EVACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3123 {
3124 DMAC_CRITICAL_SECTION_ENTER();
3125 ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_EVACT(mask);
3126 DMAC_CRITICAL_SECTION_LEAVE();
3127 }
3128
hri_dmac_read_CHCTRLB_EVACT_bf(const void * const hw)3129 static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_EVACT_bf(const void *const hw)
3130 {
3131 uint32_t tmp;
3132 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3133 tmp = (tmp & DMAC_CHCTRLB_EVACT_Msk) >> DMAC_CHCTRLB_EVACT_Pos;
3134 return tmp;
3135 }
3136
hri_dmac_set_CHCTRLB_LVL_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3137 static inline void hri_dmac_set_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3138 {
3139 DMAC_CRITICAL_SECTION_ENTER();
3140 ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_LVL(mask);
3141 DMAC_CRITICAL_SECTION_LEAVE();
3142 }
3143
hri_dmac_get_CHCTRLB_LVL_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3144 static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3145 {
3146 uint32_t tmp;
3147 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3148 tmp = (tmp & DMAC_CHCTRLB_LVL(mask)) >> DMAC_CHCTRLB_LVL_Pos;
3149 return tmp;
3150 }
3151
hri_dmac_write_CHCTRLB_LVL_bf(const void * const hw,hri_dmac_chctrlb_reg_t data)3152 static inline void hri_dmac_write_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
3153 {
3154 uint32_t tmp;
3155 DMAC_CRITICAL_SECTION_ENTER();
3156 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3157 tmp &= ~DMAC_CHCTRLB_LVL_Msk;
3158 tmp |= DMAC_CHCTRLB_LVL(data);
3159 ((Dmac *)hw)->CHCTRLB.reg = tmp;
3160 DMAC_CRITICAL_SECTION_LEAVE();
3161 }
3162
hri_dmac_clear_CHCTRLB_LVL_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3163 static inline void hri_dmac_clear_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3164 {
3165 DMAC_CRITICAL_SECTION_ENTER();
3166 ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_LVL(mask);
3167 DMAC_CRITICAL_SECTION_LEAVE();
3168 }
3169
hri_dmac_toggle_CHCTRLB_LVL_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3170 static inline void hri_dmac_toggle_CHCTRLB_LVL_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3171 {
3172 DMAC_CRITICAL_SECTION_ENTER();
3173 ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_LVL(mask);
3174 DMAC_CRITICAL_SECTION_LEAVE();
3175 }
3176
hri_dmac_read_CHCTRLB_LVL_bf(const void * const hw)3177 static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_LVL_bf(const void *const hw)
3178 {
3179 uint32_t tmp;
3180 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3181 tmp = (tmp & DMAC_CHCTRLB_LVL_Msk) >> DMAC_CHCTRLB_LVL_Pos;
3182 return tmp;
3183 }
3184
hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3185 static inline void hri_dmac_set_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3186 {
3187 DMAC_CRITICAL_SECTION_ENTER();
3188 ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGSRC(mask);
3189 DMAC_CRITICAL_SECTION_LEAVE();
3190 }
3191
hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3192 static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3193 {
3194 uint32_t tmp;
3195 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3196 tmp = (tmp & DMAC_CHCTRLB_TRIGSRC(mask)) >> DMAC_CHCTRLB_TRIGSRC_Pos;
3197 return tmp;
3198 }
3199
hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void * const hw,hri_dmac_chctrlb_reg_t data)3200 static inline void hri_dmac_write_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
3201 {
3202 uint32_t tmp;
3203 DMAC_CRITICAL_SECTION_ENTER();
3204 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3205 tmp &= ~DMAC_CHCTRLB_TRIGSRC_Msk;
3206 tmp |= DMAC_CHCTRLB_TRIGSRC(data);
3207 ((Dmac *)hw)->CHCTRLB.reg = tmp;
3208 DMAC_CRITICAL_SECTION_LEAVE();
3209 }
3210
hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3211 static inline void hri_dmac_clear_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3212 {
3213 DMAC_CRITICAL_SECTION_ENTER();
3214 ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGSRC(mask);
3215 DMAC_CRITICAL_SECTION_LEAVE();
3216 }
3217
hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3218 static inline void hri_dmac_toggle_CHCTRLB_TRIGSRC_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3219 {
3220 DMAC_CRITICAL_SECTION_ENTER();
3221 ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGSRC(mask);
3222 DMAC_CRITICAL_SECTION_LEAVE();
3223 }
3224
hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void * const hw)3225 static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGSRC_bf(const void *const hw)
3226 {
3227 uint32_t tmp;
3228 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3229 tmp = (tmp & DMAC_CHCTRLB_TRIGSRC_Msk) >> DMAC_CHCTRLB_TRIGSRC_Pos;
3230 return tmp;
3231 }
3232
hri_dmac_set_CHCTRLB_TRIGACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3233 static inline void hri_dmac_set_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3234 {
3235 DMAC_CRITICAL_SECTION_ENTER();
3236 ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_TRIGACT(mask);
3237 DMAC_CRITICAL_SECTION_LEAVE();
3238 }
3239
hri_dmac_get_CHCTRLB_TRIGACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3240 static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3241 {
3242 uint32_t tmp;
3243 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3244 tmp = (tmp & DMAC_CHCTRLB_TRIGACT(mask)) >> DMAC_CHCTRLB_TRIGACT_Pos;
3245 return tmp;
3246 }
3247
hri_dmac_write_CHCTRLB_TRIGACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t data)3248 static inline void hri_dmac_write_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
3249 {
3250 uint32_t tmp;
3251 DMAC_CRITICAL_SECTION_ENTER();
3252 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3253 tmp &= ~DMAC_CHCTRLB_TRIGACT_Msk;
3254 tmp |= DMAC_CHCTRLB_TRIGACT(data);
3255 ((Dmac *)hw)->CHCTRLB.reg = tmp;
3256 DMAC_CRITICAL_SECTION_LEAVE();
3257 }
3258
hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3259 static inline void hri_dmac_clear_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3260 {
3261 DMAC_CRITICAL_SECTION_ENTER();
3262 ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_TRIGACT(mask);
3263 DMAC_CRITICAL_SECTION_LEAVE();
3264 }
3265
hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3266 static inline void hri_dmac_toggle_CHCTRLB_TRIGACT_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3267 {
3268 DMAC_CRITICAL_SECTION_ENTER();
3269 ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_TRIGACT(mask);
3270 DMAC_CRITICAL_SECTION_LEAVE();
3271 }
3272
hri_dmac_read_CHCTRLB_TRIGACT_bf(const void * const hw)3273 static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_TRIGACT_bf(const void *const hw)
3274 {
3275 uint32_t tmp;
3276 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3277 tmp = (tmp & DMAC_CHCTRLB_TRIGACT_Msk) >> DMAC_CHCTRLB_TRIGACT_Pos;
3278 return tmp;
3279 }
3280
hri_dmac_set_CHCTRLB_CMD_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3281 static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3282 {
3283 DMAC_CRITICAL_SECTION_ENTER();
3284 ((Dmac *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask);
3285 DMAC_CRITICAL_SECTION_LEAVE();
3286 }
3287
hri_dmac_get_CHCTRLB_CMD_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3288 static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3289 {
3290 uint32_t tmp;
3291 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3292 tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos;
3293 return tmp;
3294 }
3295
hri_dmac_write_CHCTRLB_CMD_bf(const void * const hw,hri_dmac_chctrlb_reg_t data)3296 static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data)
3297 {
3298 uint32_t tmp;
3299 DMAC_CRITICAL_SECTION_ENTER();
3300 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3301 tmp &= ~DMAC_CHCTRLB_CMD_Msk;
3302 tmp |= DMAC_CHCTRLB_CMD(data);
3303 ((Dmac *)hw)->CHCTRLB.reg = tmp;
3304 DMAC_CRITICAL_SECTION_LEAVE();
3305 }
3306
hri_dmac_clear_CHCTRLB_CMD_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3307 static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3308 {
3309 DMAC_CRITICAL_SECTION_ENTER();
3310 ((Dmac *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask);
3311 DMAC_CRITICAL_SECTION_LEAVE();
3312 }
3313
hri_dmac_toggle_CHCTRLB_CMD_bf(const void * const hw,hri_dmac_chctrlb_reg_t mask)3314 static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3315 {
3316 DMAC_CRITICAL_SECTION_ENTER();
3317 ((Dmac *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask);
3318 DMAC_CRITICAL_SECTION_LEAVE();
3319 }
3320
hri_dmac_read_CHCTRLB_CMD_bf(const void * const hw)3321 static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw)
3322 {
3323 uint32_t tmp;
3324 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3325 tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos;
3326 return tmp;
3327 }
3328
hri_dmac_set_CHCTRLB_reg(const void * const hw,hri_dmac_chctrlb_reg_t mask)3329 static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3330 {
3331 DMAC_CRITICAL_SECTION_ENTER();
3332 ((Dmac *)hw)->CHCTRLB.reg |= mask;
3333 DMAC_CRITICAL_SECTION_LEAVE();
3334 }
3335
hri_dmac_get_CHCTRLB_reg(const void * const hw,hri_dmac_chctrlb_reg_t mask)3336 static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3337 {
3338 uint32_t tmp;
3339 tmp = ((Dmac *)hw)->CHCTRLB.reg;
3340 tmp &= mask;
3341 return tmp;
3342 }
3343
hri_dmac_write_CHCTRLB_reg(const void * const hw,hri_dmac_chctrlb_reg_t data)3344 static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data)
3345 {
3346 DMAC_CRITICAL_SECTION_ENTER();
3347 ((Dmac *)hw)->CHCTRLB.reg = data;
3348 DMAC_CRITICAL_SECTION_LEAVE();
3349 }
3350
hri_dmac_clear_CHCTRLB_reg(const void * const hw,hri_dmac_chctrlb_reg_t mask)3351 static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3352 {
3353 DMAC_CRITICAL_SECTION_ENTER();
3354 ((Dmac *)hw)->CHCTRLB.reg &= ~mask;
3355 DMAC_CRITICAL_SECTION_LEAVE();
3356 }
3357
hri_dmac_toggle_CHCTRLB_reg(const void * const hw,hri_dmac_chctrlb_reg_t mask)3358 static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask)
3359 {
3360 DMAC_CRITICAL_SECTION_ENTER();
3361 ((Dmac *)hw)->CHCTRLB.reg ^= mask;
3362 DMAC_CRITICAL_SECTION_LEAVE();
3363 }
3364
hri_dmac_read_CHCTRLB_reg(const void * const hw)3365 static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw)
3366 {
3367 return ((Dmac *)hw)->CHCTRLB.reg;
3368 }
3369
hri_dmac_get_INTSTATUS_CHINT0_bit(const void * const hw)3370 static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw)
3371 {
3372 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos;
3373 }
3374
hri_dmac_get_INTSTATUS_CHINT1_bit(const void * const hw)3375 static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw)
3376 {
3377 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos;
3378 }
3379
hri_dmac_get_INTSTATUS_CHINT2_bit(const void * const hw)3380 static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw)
3381 {
3382 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos;
3383 }
3384
hri_dmac_get_INTSTATUS_CHINT3_bit(const void * const hw)3385 static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw)
3386 {
3387 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos;
3388 }
3389
hri_dmac_get_INTSTATUS_CHINT4_bit(const void * const hw)3390 static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw)
3391 {
3392 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos;
3393 }
3394
hri_dmac_get_INTSTATUS_CHINT5_bit(const void * const hw)3395 static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw)
3396 {
3397 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos;
3398 }
3399
hri_dmac_get_INTSTATUS_CHINT6_bit(const void * const hw)3400 static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw)
3401 {
3402 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos;
3403 }
3404
hri_dmac_get_INTSTATUS_CHINT7_bit(const void * const hw)3405 static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw)
3406 {
3407 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos;
3408 }
3409
hri_dmac_get_INTSTATUS_CHINT8_bit(const void * const hw)3410 static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw)
3411 {
3412 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos;
3413 }
3414
hri_dmac_get_INTSTATUS_CHINT9_bit(const void * const hw)3415 static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw)
3416 {
3417 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos;
3418 }
3419
hri_dmac_get_INTSTATUS_CHINT10_bit(const void * const hw)3420 static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw)
3421 {
3422 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos;
3423 }
3424
hri_dmac_get_INTSTATUS_CHINT11_bit(const void * const hw)3425 static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw)
3426 {
3427 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos;
3428 }
3429
hri_dmac_get_INTSTATUS_CHINT12_bit(const void * const hw)3430 static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw)
3431 {
3432 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos;
3433 }
3434
hri_dmac_get_INTSTATUS_CHINT13_bit(const void * const hw)3435 static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw)
3436 {
3437 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos;
3438 }
3439
hri_dmac_get_INTSTATUS_CHINT14_bit(const void * const hw)3440 static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw)
3441 {
3442 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos;
3443 }
3444
hri_dmac_get_INTSTATUS_CHINT15_bit(const void * const hw)3445 static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw)
3446 {
3447 return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos;
3448 }
3449
hri_dmac_get_INTSTATUS_reg(const void * const hw,hri_dmac_intstatus_reg_t mask)3450 static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask)
3451 {
3452 uint32_t tmp;
3453 tmp = ((Dmac *)hw)->INTSTATUS.reg;
3454 tmp &= mask;
3455 return tmp;
3456 }
3457
hri_dmac_read_INTSTATUS_reg(const void * const hw)3458 static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw)
3459 {
3460 return ((Dmac *)hw)->INTSTATUS.reg;
3461 }
3462
hri_dmac_get_BUSYCH_BUSYCH0_bit(const void * const hw)3463 static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw)
3464 {
3465 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos;
3466 }
3467
hri_dmac_get_BUSYCH_BUSYCH1_bit(const void * const hw)3468 static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw)
3469 {
3470 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos;
3471 }
3472
hri_dmac_get_BUSYCH_BUSYCH2_bit(const void * const hw)3473 static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw)
3474 {
3475 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos;
3476 }
3477
hri_dmac_get_BUSYCH_BUSYCH3_bit(const void * const hw)3478 static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw)
3479 {
3480 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos;
3481 }
3482
hri_dmac_get_BUSYCH_BUSYCH4_bit(const void * const hw)3483 static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw)
3484 {
3485 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos;
3486 }
3487
hri_dmac_get_BUSYCH_BUSYCH5_bit(const void * const hw)3488 static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw)
3489 {
3490 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos;
3491 }
3492
hri_dmac_get_BUSYCH_BUSYCH6_bit(const void * const hw)3493 static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw)
3494 {
3495 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos;
3496 }
3497
hri_dmac_get_BUSYCH_BUSYCH7_bit(const void * const hw)3498 static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw)
3499 {
3500 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos;
3501 }
3502
hri_dmac_get_BUSYCH_BUSYCH8_bit(const void * const hw)3503 static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw)
3504 {
3505 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos;
3506 }
3507
hri_dmac_get_BUSYCH_BUSYCH9_bit(const void * const hw)3508 static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw)
3509 {
3510 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos;
3511 }
3512
hri_dmac_get_BUSYCH_BUSYCH10_bit(const void * const hw)3513 static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw)
3514 {
3515 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos;
3516 }
3517
hri_dmac_get_BUSYCH_BUSYCH11_bit(const void * const hw)3518 static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw)
3519 {
3520 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos;
3521 }
3522
hri_dmac_get_BUSYCH_BUSYCH12_bit(const void * const hw)3523 static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw)
3524 {
3525 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos;
3526 }
3527
hri_dmac_get_BUSYCH_BUSYCH13_bit(const void * const hw)3528 static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw)
3529 {
3530 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos;
3531 }
3532
hri_dmac_get_BUSYCH_BUSYCH14_bit(const void * const hw)3533 static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw)
3534 {
3535 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos;
3536 }
3537
hri_dmac_get_BUSYCH_BUSYCH15_bit(const void * const hw)3538 static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw)
3539 {
3540 return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos;
3541 }
3542
hri_dmac_get_BUSYCH_reg(const void * const hw,hri_dmac_busych_reg_t mask)3543 static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask)
3544 {
3545 uint32_t tmp;
3546 tmp = ((Dmac *)hw)->BUSYCH.reg;
3547 tmp &= mask;
3548 return tmp;
3549 }
3550
hri_dmac_read_BUSYCH_reg(const void * const hw)3551 static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw)
3552 {
3553 return ((Dmac *)hw)->BUSYCH.reg;
3554 }
3555
hri_dmac_get_PENDCH_PENDCH0_bit(const void * const hw)3556 static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw)
3557 {
3558 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos;
3559 }
3560
hri_dmac_get_PENDCH_PENDCH1_bit(const void * const hw)3561 static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw)
3562 {
3563 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos;
3564 }
3565
hri_dmac_get_PENDCH_PENDCH2_bit(const void * const hw)3566 static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw)
3567 {
3568 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos;
3569 }
3570
hri_dmac_get_PENDCH_PENDCH3_bit(const void * const hw)3571 static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw)
3572 {
3573 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos;
3574 }
3575
hri_dmac_get_PENDCH_PENDCH4_bit(const void * const hw)3576 static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw)
3577 {
3578 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos;
3579 }
3580
hri_dmac_get_PENDCH_PENDCH5_bit(const void * const hw)3581 static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw)
3582 {
3583 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos;
3584 }
3585
hri_dmac_get_PENDCH_PENDCH6_bit(const void * const hw)3586 static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw)
3587 {
3588 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos;
3589 }
3590
hri_dmac_get_PENDCH_PENDCH7_bit(const void * const hw)3591 static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw)
3592 {
3593 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos;
3594 }
3595
hri_dmac_get_PENDCH_PENDCH8_bit(const void * const hw)3596 static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw)
3597 {
3598 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos;
3599 }
3600
hri_dmac_get_PENDCH_PENDCH9_bit(const void * const hw)3601 static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw)
3602 {
3603 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos;
3604 }
3605
hri_dmac_get_PENDCH_PENDCH10_bit(const void * const hw)3606 static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw)
3607 {
3608 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos;
3609 }
3610
hri_dmac_get_PENDCH_PENDCH11_bit(const void * const hw)3611 static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw)
3612 {
3613 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos;
3614 }
3615
hri_dmac_get_PENDCH_PENDCH12_bit(const void * const hw)3616 static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw)
3617 {
3618 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos;
3619 }
3620
hri_dmac_get_PENDCH_PENDCH13_bit(const void * const hw)3621 static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw)
3622 {
3623 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos;
3624 }
3625
hri_dmac_get_PENDCH_PENDCH14_bit(const void * const hw)3626 static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw)
3627 {
3628 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos;
3629 }
3630
hri_dmac_get_PENDCH_PENDCH15_bit(const void * const hw)3631 static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw)
3632 {
3633 return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos;
3634 }
3635
hri_dmac_get_PENDCH_reg(const void * const hw,hri_dmac_pendch_reg_t mask)3636 static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask)
3637 {
3638 uint32_t tmp;
3639 tmp = ((Dmac *)hw)->PENDCH.reg;
3640 tmp &= mask;
3641 return tmp;
3642 }
3643
hri_dmac_read_PENDCH_reg(const void * const hw)3644 static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw)
3645 {
3646 return ((Dmac *)hw)->PENDCH.reg;
3647 }
3648
hri_dmac_get_ACTIVE_LVLEX0_bit(const void * const hw)3649 static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw)
3650 {
3651 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos;
3652 }
3653
hri_dmac_get_ACTIVE_LVLEX1_bit(const void * const hw)3654 static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw)
3655 {
3656 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos;
3657 }
3658
hri_dmac_get_ACTIVE_LVLEX2_bit(const void * const hw)3659 static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw)
3660 {
3661 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos;
3662 }
3663
hri_dmac_get_ACTIVE_LVLEX3_bit(const void * const hw)3664 static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw)
3665 {
3666 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos;
3667 }
3668
hri_dmac_get_ACTIVE_ABUSY_bit(const void * const hw)3669 static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw)
3670 {
3671 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos;
3672 }
3673
hri_dmac_get_ACTIVE_ID_bf(const void * const hw,hri_dmac_active_reg_t mask)3674 static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask)
3675 {
3676 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos;
3677 }
3678
hri_dmac_read_ACTIVE_ID_bf(const void * const hw)3679 static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw)
3680 {
3681 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos;
3682 }
3683
hri_dmac_get_ACTIVE_BTCNT_bf(const void * const hw,hri_dmac_active_reg_t mask)3684 static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask)
3685 {
3686 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos;
3687 }
3688
hri_dmac_read_ACTIVE_BTCNT_bf(const void * const hw)3689 static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw)
3690 {
3691 return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos;
3692 }
3693
hri_dmac_get_ACTIVE_reg(const void * const hw,hri_dmac_active_reg_t mask)3694 static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask)
3695 {
3696 uint32_t tmp;
3697 tmp = ((Dmac *)hw)->ACTIVE.reg;
3698 tmp &= mask;
3699 return tmp;
3700 }
3701
hri_dmac_read_ACTIVE_reg(const void * const hw)3702 static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw)
3703 {
3704 return ((Dmac *)hw)->ACTIVE.reg;
3705 }
3706
hri_dmac_get_CHSTATUS_PEND_bit(const void * const hw)3707 static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw)
3708 {
3709 return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos;
3710 }
3711
hri_dmac_get_CHSTATUS_BUSY_bit(const void * const hw)3712 static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw)
3713 {
3714 return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos;
3715 }
3716
hri_dmac_get_CHSTATUS_FERR_bit(const void * const hw)3717 static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw)
3718 {
3719 return (((Dmac *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos;
3720 }
3721
hri_dmac_get_CHSTATUS_reg(const void * const hw,hri_dmac_chstatus_reg_t mask)3722 static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask)
3723 {
3724 uint8_t tmp;
3725 tmp = ((Dmac *)hw)->CHSTATUS.reg;
3726 tmp &= mask;
3727 return tmp;
3728 }
3729
hri_dmac_read_CHSTATUS_reg(const void * const hw)3730 static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw)
3731 {
3732 return ((Dmac *)hw)->CHSTATUS.reg;
3733 }
3734
hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void * const hw)3735 static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw)
3736 {
3737 return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos;
3738 }
3739
hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void * const hw)3740 static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw)
3741 {
3742 DMAC_CRITICAL_SECTION_ENTER();
3743 ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY;
3744 DMAC_CRITICAL_SECTION_LEAVE();
3745 }
3746
hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void * const hw)3747 static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw)
3748 {
3749 return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos;
3750 }
3751
hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void * const hw)3752 static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw)
3753 {
3754 DMAC_CRITICAL_SECTION_ENTER();
3755 ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO;
3756 DMAC_CRITICAL_SECTION_LEAVE();
3757 }
3758
hri_dmac_get_CRCSTATUS_reg(const void * const hw,hri_dmac_crcstatus_reg_t mask)3759 static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
3760 {
3761 uint8_t tmp;
3762 tmp = ((Dmac *)hw)->CRCSTATUS.reg;
3763 tmp &= mask;
3764 return tmp;
3765 }
3766
hri_dmac_clear_CRCSTATUS_reg(const void * const hw,hri_dmac_crcstatus_reg_t mask)3767 static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask)
3768 {
3769 DMAC_CRITICAL_SECTION_ENTER();
3770 ((Dmac *)hw)->CRCSTATUS.reg = mask;
3771 DMAC_CRITICAL_SECTION_LEAVE();
3772 }
3773
hri_dmac_read_CRCSTATUS_reg(const void * const hw)3774 static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw)
3775 {
3776 return ((Dmac *)hw)->CRCSTATUS.reg;
3777 }
3778
hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void * const hw)3779 static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw)
3780 {
3781 DMAC_CRITICAL_SECTION_ENTER();
3782 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID;
3783 DMAC_CRITICAL_SECTION_LEAVE();
3784 }
3785
hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void * const hw)3786 static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw)
3787 {
3788 uint16_t tmp;
3789 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3790 tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos;
3791 return (bool)tmp;
3792 }
3793
hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void * const hw,bool value)3794 static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value)
3795 {
3796 uint16_t tmp;
3797 DMAC_CRITICAL_SECTION_ENTER();
3798 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3799 tmp &= ~DMAC_BTCTRL_VALID;
3800 tmp |= value << DMAC_BTCTRL_VALID_Pos;
3801 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
3802 DMAC_CRITICAL_SECTION_LEAVE();
3803 }
3804
hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void * const hw)3805 static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw)
3806 {
3807 DMAC_CRITICAL_SECTION_ENTER();
3808 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID;
3809 DMAC_CRITICAL_SECTION_LEAVE();
3810 }
3811
hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void * const hw)3812 static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw)
3813 {
3814 DMAC_CRITICAL_SECTION_ENTER();
3815 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID;
3816 DMAC_CRITICAL_SECTION_LEAVE();
3817 }
3818
hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void * const hw)3819 static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw)
3820 {
3821 DMAC_CRITICAL_SECTION_ENTER();
3822 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC;
3823 DMAC_CRITICAL_SECTION_LEAVE();
3824 }
3825
hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void * const hw)3826 static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw)
3827 {
3828 uint16_t tmp;
3829 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3830 tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos;
3831 return (bool)tmp;
3832 }
3833
hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void * const hw,bool value)3834 static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value)
3835 {
3836 uint16_t tmp;
3837 DMAC_CRITICAL_SECTION_ENTER();
3838 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3839 tmp &= ~DMAC_BTCTRL_SRCINC;
3840 tmp |= value << DMAC_BTCTRL_SRCINC_Pos;
3841 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
3842 DMAC_CRITICAL_SECTION_LEAVE();
3843 }
3844
hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void * const hw)3845 static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw)
3846 {
3847 DMAC_CRITICAL_SECTION_ENTER();
3848 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC;
3849 DMAC_CRITICAL_SECTION_LEAVE();
3850 }
3851
hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void * const hw)3852 static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw)
3853 {
3854 DMAC_CRITICAL_SECTION_ENTER();
3855 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC;
3856 DMAC_CRITICAL_SECTION_LEAVE();
3857 }
3858
hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void * const hw)3859 static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw)
3860 {
3861 DMAC_CRITICAL_SECTION_ENTER();
3862 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC;
3863 DMAC_CRITICAL_SECTION_LEAVE();
3864 }
3865
hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void * const hw)3866 static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw)
3867 {
3868 uint16_t tmp;
3869 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3870 tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos;
3871 return (bool)tmp;
3872 }
3873
hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void * const hw,bool value)3874 static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value)
3875 {
3876 uint16_t tmp;
3877 DMAC_CRITICAL_SECTION_ENTER();
3878 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3879 tmp &= ~DMAC_BTCTRL_DSTINC;
3880 tmp |= value << DMAC_BTCTRL_DSTINC_Pos;
3881 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
3882 DMAC_CRITICAL_SECTION_LEAVE();
3883 }
3884
hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void * const hw)3885 static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw)
3886 {
3887 DMAC_CRITICAL_SECTION_ENTER();
3888 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC;
3889 DMAC_CRITICAL_SECTION_LEAVE();
3890 }
3891
hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void * const hw)3892 static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw)
3893 {
3894 DMAC_CRITICAL_SECTION_ENTER();
3895 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC;
3896 DMAC_CRITICAL_SECTION_LEAVE();
3897 }
3898
hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void * const hw)3899 static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw)
3900 {
3901 DMAC_CRITICAL_SECTION_ENTER();
3902 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL;
3903 DMAC_CRITICAL_SECTION_LEAVE();
3904 }
3905
hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void * const hw)3906 static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw)
3907 {
3908 uint16_t tmp;
3909 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3910 tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos;
3911 return (bool)tmp;
3912 }
3913
hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void * const hw,bool value)3914 static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value)
3915 {
3916 uint16_t tmp;
3917 DMAC_CRITICAL_SECTION_ENTER();
3918 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3919 tmp &= ~DMAC_BTCTRL_STEPSEL;
3920 tmp |= value << DMAC_BTCTRL_STEPSEL_Pos;
3921 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
3922 DMAC_CRITICAL_SECTION_LEAVE();
3923 }
3924
hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void * const hw)3925 static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw)
3926 {
3927 DMAC_CRITICAL_SECTION_ENTER();
3928 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL;
3929 DMAC_CRITICAL_SECTION_LEAVE();
3930 }
3931
hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void * const hw)3932 static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw)
3933 {
3934 DMAC_CRITICAL_SECTION_ENTER();
3935 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL;
3936 DMAC_CRITICAL_SECTION_LEAVE();
3937 }
3938
hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)3939 static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
3940 {
3941 DMAC_CRITICAL_SECTION_ENTER();
3942 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask);
3943 DMAC_CRITICAL_SECTION_LEAVE();
3944 }
3945
3946 static inline hri_dmacdescriptor_btctrl_reg_t
hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)3947 hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
3948 {
3949 uint16_t tmp;
3950 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3951 tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos;
3952 return tmp;
3953 }
3954
hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t data)3955 static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
3956 {
3957 uint16_t tmp;
3958 DMAC_CRITICAL_SECTION_ENTER();
3959 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3960 tmp &= ~DMAC_BTCTRL_EVOSEL_Msk;
3961 tmp |= DMAC_BTCTRL_EVOSEL(data);
3962 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
3963 DMAC_CRITICAL_SECTION_LEAVE();
3964 }
3965
hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)3966 static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
3967 {
3968 DMAC_CRITICAL_SECTION_ENTER();
3969 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask);
3970 DMAC_CRITICAL_SECTION_LEAVE();
3971 }
3972
hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)3973 static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw,
3974 hri_dmacdescriptor_btctrl_reg_t mask)
3975 {
3976 DMAC_CRITICAL_SECTION_ENTER();
3977 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask);
3978 DMAC_CRITICAL_SECTION_LEAVE();
3979 }
3980
hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void * const hw)3981 static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw)
3982 {
3983 uint16_t tmp;
3984 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
3985 tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos;
3986 return tmp;
3987 }
3988
hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)3989 static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
3990 {
3991 DMAC_CRITICAL_SECTION_ENTER();
3992 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask);
3993 DMAC_CRITICAL_SECTION_LEAVE();
3994 }
3995
3996 static inline hri_dmacdescriptor_btctrl_reg_t
hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)3997 hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
3998 {
3999 uint16_t tmp;
4000 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4001 tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos;
4002 return tmp;
4003 }
4004
hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t data)4005 static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw,
4006 hri_dmacdescriptor_btctrl_reg_t data)
4007 {
4008 uint16_t tmp;
4009 DMAC_CRITICAL_SECTION_ENTER();
4010 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4011 tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk;
4012 tmp |= DMAC_BTCTRL_BLOCKACT(data);
4013 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
4014 DMAC_CRITICAL_SECTION_LEAVE();
4015 }
4016
hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4017 static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw,
4018 hri_dmacdescriptor_btctrl_reg_t mask)
4019 {
4020 DMAC_CRITICAL_SECTION_ENTER();
4021 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask);
4022 DMAC_CRITICAL_SECTION_LEAVE();
4023 }
4024
hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4025 static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw,
4026 hri_dmacdescriptor_btctrl_reg_t mask)
4027 {
4028 DMAC_CRITICAL_SECTION_ENTER();
4029 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask);
4030 DMAC_CRITICAL_SECTION_LEAVE();
4031 }
4032
hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void * const hw)4033 static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw)
4034 {
4035 uint16_t tmp;
4036 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4037 tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos;
4038 return tmp;
4039 }
4040
hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4041 static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
4042 {
4043 DMAC_CRITICAL_SECTION_ENTER();
4044 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask);
4045 DMAC_CRITICAL_SECTION_LEAVE();
4046 }
4047
4048 static inline hri_dmacdescriptor_btctrl_reg_t
hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4049 hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
4050 {
4051 uint16_t tmp;
4052 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4053 tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos;
4054 return tmp;
4055 }
4056
hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t data)4057 static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw,
4058 hri_dmacdescriptor_btctrl_reg_t data)
4059 {
4060 uint16_t tmp;
4061 DMAC_CRITICAL_SECTION_ENTER();
4062 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4063 tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk;
4064 tmp |= DMAC_BTCTRL_BEATSIZE(data);
4065 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
4066 DMAC_CRITICAL_SECTION_LEAVE();
4067 }
4068
hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4069 static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw,
4070 hri_dmacdescriptor_btctrl_reg_t mask)
4071 {
4072 DMAC_CRITICAL_SECTION_ENTER();
4073 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask);
4074 DMAC_CRITICAL_SECTION_LEAVE();
4075 }
4076
hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4077 static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw,
4078 hri_dmacdescriptor_btctrl_reg_t mask)
4079 {
4080 DMAC_CRITICAL_SECTION_ENTER();
4081 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask);
4082 DMAC_CRITICAL_SECTION_LEAVE();
4083 }
4084
hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void * const hw)4085 static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw)
4086 {
4087 uint16_t tmp;
4088 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4089 tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos;
4090 return tmp;
4091 }
4092
hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4093 static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
4094 {
4095 DMAC_CRITICAL_SECTION_ENTER();
4096 ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask);
4097 DMAC_CRITICAL_SECTION_LEAVE();
4098 }
4099
4100 static inline hri_dmacdescriptor_btctrl_reg_t
hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4101 hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
4102 {
4103 uint16_t tmp;
4104 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4105 tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos;
4106 return tmp;
4107 }
4108
hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t data)4109 static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw,
4110 hri_dmacdescriptor_btctrl_reg_t data)
4111 {
4112 uint16_t tmp;
4113 DMAC_CRITICAL_SECTION_ENTER();
4114 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4115 tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk;
4116 tmp |= DMAC_BTCTRL_STEPSIZE(data);
4117 ((DmacDescriptor *)hw)->BTCTRL.reg = tmp;
4118 DMAC_CRITICAL_SECTION_LEAVE();
4119 }
4120
hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4121 static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw,
4122 hri_dmacdescriptor_btctrl_reg_t mask)
4123 {
4124 DMAC_CRITICAL_SECTION_ENTER();
4125 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask);
4126 DMAC_CRITICAL_SECTION_LEAVE();
4127 }
4128
hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4129 static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw,
4130 hri_dmacdescriptor_btctrl_reg_t mask)
4131 {
4132 DMAC_CRITICAL_SECTION_ENTER();
4133 ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask);
4134 DMAC_CRITICAL_SECTION_LEAVE();
4135 }
4136
hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void * const hw)4137 static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw)
4138 {
4139 uint16_t tmp;
4140 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4141 tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos;
4142 return tmp;
4143 }
4144
hri_dmacdescriptor_set_BTCTRL_reg(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4145 static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
4146 {
4147 DMAC_CRITICAL_SECTION_ENTER();
4148 ((DmacDescriptor *)hw)->BTCTRL.reg |= mask;
4149 DMAC_CRITICAL_SECTION_LEAVE();
4150 }
4151
hri_dmacdescriptor_get_BTCTRL_reg(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4152 static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw,
4153 hri_dmacdescriptor_btctrl_reg_t mask)
4154 {
4155 uint16_t tmp;
4156 tmp = ((DmacDescriptor *)hw)->BTCTRL.reg;
4157 tmp &= mask;
4158 return tmp;
4159 }
4160
hri_dmacdescriptor_write_BTCTRL_reg(const void * const hw,hri_dmacdescriptor_btctrl_reg_t data)4161 static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data)
4162 {
4163 DMAC_CRITICAL_SECTION_ENTER();
4164 ((DmacDescriptor *)hw)->BTCTRL.reg = data;
4165 DMAC_CRITICAL_SECTION_LEAVE();
4166 }
4167
hri_dmacdescriptor_clear_BTCTRL_reg(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4168 static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
4169 {
4170 DMAC_CRITICAL_SECTION_ENTER();
4171 ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask;
4172 DMAC_CRITICAL_SECTION_LEAVE();
4173 }
4174
hri_dmacdescriptor_toggle_BTCTRL_reg(const void * const hw,hri_dmacdescriptor_btctrl_reg_t mask)4175 static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask)
4176 {
4177 DMAC_CRITICAL_SECTION_ENTER();
4178 ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask;
4179 DMAC_CRITICAL_SECTION_LEAVE();
4180 }
4181
hri_dmacdescriptor_read_BTCTRL_reg(const void * const hw)4182 static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw)
4183 {
4184 return ((DmacDescriptor *)hw)->BTCTRL.reg;
4185 }
4186
hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4187 static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
4188 {
4189 DMAC_CRITICAL_SECTION_ENTER();
4190 ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask);
4191 DMAC_CRITICAL_SECTION_LEAVE();
4192 }
4193
hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4194 static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw,
4195 hri_dmacdescriptor_btcnt_reg_t mask)
4196 {
4197 uint16_t tmp;
4198 tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
4199 tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos;
4200 return tmp;
4201 }
4202
hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void * const hw,hri_dmacdescriptor_btcnt_reg_t data)4203 static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
4204 {
4205 uint16_t tmp;
4206 DMAC_CRITICAL_SECTION_ENTER();
4207 tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
4208 tmp &= ~DMAC_BTCNT_BTCNT_Msk;
4209 tmp |= DMAC_BTCNT_BTCNT(data);
4210 ((DmacDescriptor *)hw)->BTCNT.reg = tmp;
4211 DMAC_CRITICAL_SECTION_LEAVE();
4212 }
4213
hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4214 static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
4215 {
4216 DMAC_CRITICAL_SECTION_ENTER();
4217 ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask);
4218 DMAC_CRITICAL_SECTION_LEAVE();
4219 }
4220
hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4221 static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
4222 {
4223 DMAC_CRITICAL_SECTION_ENTER();
4224 ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask);
4225 DMAC_CRITICAL_SECTION_LEAVE();
4226 }
4227
hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void * const hw)4228 static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw)
4229 {
4230 uint16_t tmp;
4231 tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
4232 tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos;
4233 return tmp;
4234 }
4235
hri_dmacdescriptor_set_BTCNT_reg(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4236 static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
4237 {
4238 DMAC_CRITICAL_SECTION_ENTER();
4239 ((DmacDescriptor *)hw)->BTCNT.reg |= mask;
4240 DMAC_CRITICAL_SECTION_LEAVE();
4241 }
4242
hri_dmacdescriptor_get_BTCNT_reg(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4243 static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw,
4244 hri_dmacdescriptor_btcnt_reg_t mask)
4245 {
4246 uint16_t tmp;
4247 tmp = ((DmacDescriptor *)hw)->BTCNT.reg;
4248 tmp &= mask;
4249 return tmp;
4250 }
4251
hri_dmacdescriptor_write_BTCNT_reg(const void * const hw,hri_dmacdescriptor_btcnt_reg_t data)4252 static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data)
4253 {
4254 DMAC_CRITICAL_SECTION_ENTER();
4255 ((DmacDescriptor *)hw)->BTCNT.reg = data;
4256 DMAC_CRITICAL_SECTION_LEAVE();
4257 }
4258
hri_dmacdescriptor_clear_BTCNT_reg(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4259 static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
4260 {
4261 DMAC_CRITICAL_SECTION_ENTER();
4262 ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask;
4263 DMAC_CRITICAL_SECTION_LEAVE();
4264 }
4265
hri_dmacdescriptor_toggle_BTCNT_reg(const void * const hw,hri_dmacdescriptor_btcnt_reg_t mask)4266 static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask)
4267 {
4268 DMAC_CRITICAL_SECTION_ENTER();
4269 ((DmacDescriptor *)hw)->BTCNT.reg ^= mask;
4270 DMAC_CRITICAL_SECTION_LEAVE();
4271 }
4272
hri_dmacdescriptor_read_BTCNT_reg(const void * const hw)4273 static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw)
4274 {
4275 return ((DmacDescriptor *)hw)->BTCNT.reg;
4276 }
4277
hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4278 static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw,
4279 hri_dmacdescriptor_srcaddr_reg_t mask)
4280 {
4281 DMAC_CRITICAL_SECTION_ENTER();
4282 ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask);
4283 DMAC_CRITICAL_SECTION_LEAVE();
4284 }
4285
4286 static inline hri_dmacdescriptor_srcaddr_reg_t
hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4287 hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
4288 {
4289 uint32_t tmp;
4290 tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
4291 tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos;
4292 return tmp;
4293 }
4294
hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t data)4295 static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw,
4296 hri_dmacdescriptor_srcaddr_reg_t data)
4297 {
4298 uint32_t tmp;
4299 DMAC_CRITICAL_SECTION_ENTER();
4300 tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
4301 tmp &= ~DMAC_SRCADDR_SRCADDR_Msk;
4302 tmp |= DMAC_SRCADDR_SRCADDR(data);
4303 ((DmacDescriptor *)hw)->SRCADDR.reg = tmp;
4304 DMAC_CRITICAL_SECTION_LEAVE();
4305 }
4306
hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4307 static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw,
4308 hri_dmacdescriptor_srcaddr_reg_t mask)
4309 {
4310 DMAC_CRITICAL_SECTION_ENTER();
4311 ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask);
4312 DMAC_CRITICAL_SECTION_LEAVE();
4313 }
4314
hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4315 static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw,
4316 hri_dmacdescriptor_srcaddr_reg_t mask)
4317 {
4318 DMAC_CRITICAL_SECTION_ENTER();
4319 ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask);
4320 DMAC_CRITICAL_SECTION_LEAVE();
4321 }
4322
hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void * const hw)4323 static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw)
4324 {
4325 uint32_t tmp;
4326 tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
4327 tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos;
4328 return tmp;
4329 }
4330
hri_dmacdescriptor_set_SRCADDR_reg(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4331 static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
4332 {
4333 DMAC_CRITICAL_SECTION_ENTER();
4334 ((DmacDescriptor *)hw)->SRCADDR.reg |= mask;
4335 DMAC_CRITICAL_SECTION_LEAVE();
4336 }
4337
hri_dmacdescriptor_get_SRCADDR_reg(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4338 static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw,
4339 hri_dmacdescriptor_srcaddr_reg_t mask)
4340 {
4341 uint32_t tmp;
4342 tmp = ((DmacDescriptor *)hw)->SRCADDR.reg;
4343 tmp &= mask;
4344 return tmp;
4345 }
4346
hri_dmacdescriptor_write_SRCADDR_reg(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t data)4347 static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data)
4348 {
4349 DMAC_CRITICAL_SECTION_ENTER();
4350 ((DmacDescriptor *)hw)->SRCADDR.reg = data;
4351 DMAC_CRITICAL_SECTION_LEAVE();
4352 }
4353
hri_dmacdescriptor_clear_SRCADDR_reg(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4354 static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
4355 {
4356 DMAC_CRITICAL_SECTION_ENTER();
4357 ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask;
4358 DMAC_CRITICAL_SECTION_LEAVE();
4359 }
4360
hri_dmacdescriptor_toggle_SRCADDR_reg(const void * const hw,hri_dmacdescriptor_srcaddr_reg_t mask)4361 static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask)
4362 {
4363 DMAC_CRITICAL_SECTION_ENTER();
4364 ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask;
4365 DMAC_CRITICAL_SECTION_LEAVE();
4366 }
4367
hri_dmacdescriptor_read_SRCADDR_reg(const void * const hw)4368 static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw)
4369 {
4370 return ((DmacDescriptor *)hw)->SRCADDR.reg;
4371 }
4372
hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4373 static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw,
4374 hri_dmacdescriptor_dstaddr_reg_t mask)
4375 {
4376 DMAC_CRITICAL_SECTION_ENTER();
4377 ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask);
4378 DMAC_CRITICAL_SECTION_LEAVE();
4379 }
4380
4381 static inline hri_dmacdescriptor_dstaddr_reg_t
hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4382 hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
4383 {
4384 uint32_t tmp;
4385 tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
4386 tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos;
4387 return tmp;
4388 }
4389
hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t data)4390 static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw,
4391 hri_dmacdescriptor_dstaddr_reg_t data)
4392 {
4393 uint32_t tmp;
4394 DMAC_CRITICAL_SECTION_ENTER();
4395 tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
4396 tmp &= ~DMAC_DSTADDR_DSTADDR_Msk;
4397 tmp |= DMAC_DSTADDR_DSTADDR(data);
4398 ((DmacDescriptor *)hw)->DSTADDR.reg = tmp;
4399 DMAC_CRITICAL_SECTION_LEAVE();
4400 }
4401
hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4402 static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw,
4403 hri_dmacdescriptor_dstaddr_reg_t mask)
4404 {
4405 DMAC_CRITICAL_SECTION_ENTER();
4406 ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask);
4407 DMAC_CRITICAL_SECTION_LEAVE();
4408 }
4409
hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4410 static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw,
4411 hri_dmacdescriptor_dstaddr_reg_t mask)
4412 {
4413 DMAC_CRITICAL_SECTION_ENTER();
4414 ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask);
4415 DMAC_CRITICAL_SECTION_LEAVE();
4416 }
4417
hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void * const hw)4418 static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw)
4419 {
4420 uint32_t tmp;
4421 tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
4422 tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos;
4423 return tmp;
4424 }
4425
hri_dmacdescriptor_set_DSTADDR_reg(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4426 static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
4427 {
4428 DMAC_CRITICAL_SECTION_ENTER();
4429 ((DmacDescriptor *)hw)->DSTADDR.reg |= mask;
4430 DMAC_CRITICAL_SECTION_LEAVE();
4431 }
4432
hri_dmacdescriptor_get_DSTADDR_reg(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4433 static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw,
4434 hri_dmacdescriptor_dstaddr_reg_t mask)
4435 {
4436 uint32_t tmp;
4437 tmp = ((DmacDescriptor *)hw)->DSTADDR.reg;
4438 tmp &= mask;
4439 return tmp;
4440 }
4441
hri_dmacdescriptor_write_DSTADDR_reg(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t data)4442 static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data)
4443 {
4444 DMAC_CRITICAL_SECTION_ENTER();
4445 ((DmacDescriptor *)hw)->DSTADDR.reg = data;
4446 DMAC_CRITICAL_SECTION_LEAVE();
4447 }
4448
hri_dmacdescriptor_clear_DSTADDR_reg(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4449 static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
4450 {
4451 DMAC_CRITICAL_SECTION_ENTER();
4452 ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask;
4453 DMAC_CRITICAL_SECTION_LEAVE();
4454 }
4455
hri_dmacdescriptor_toggle_DSTADDR_reg(const void * const hw,hri_dmacdescriptor_dstaddr_reg_t mask)4456 static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask)
4457 {
4458 DMAC_CRITICAL_SECTION_ENTER();
4459 ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask;
4460 DMAC_CRITICAL_SECTION_LEAVE();
4461 }
4462
hri_dmacdescriptor_read_DSTADDR_reg(const void * const hw)4463 static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw)
4464 {
4465 return ((DmacDescriptor *)hw)->DSTADDR.reg;
4466 }
4467
hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4468 static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw,
4469 hri_dmacdescriptor_descaddr_reg_t mask)
4470 {
4471 DMAC_CRITICAL_SECTION_ENTER();
4472 ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask);
4473 DMAC_CRITICAL_SECTION_LEAVE();
4474 }
4475
4476 static inline hri_dmacdescriptor_descaddr_reg_t
hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4477 hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
4478 {
4479 uint32_t tmp;
4480 tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
4481 tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos;
4482 return tmp;
4483 }
4484
hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void * const hw,hri_dmacdescriptor_descaddr_reg_t data)4485 static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw,
4486 hri_dmacdescriptor_descaddr_reg_t data)
4487 {
4488 uint32_t tmp;
4489 DMAC_CRITICAL_SECTION_ENTER();
4490 tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
4491 tmp &= ~DMAC_DESCADDR_DESCADDR_Msk;
4492 tmp |= DMAC_DESCADDR_DESCADDR(data);
4493 ((DmacDescriptor *)hw)->DESCADDR.reg = tmp;
4494 DMAC_CRITICAL_SECTION_LEAVE();
4495 }
4496
hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4497 static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw,
4498 hri_dmacdescriptor_descaddr_reg_t mask)
4499 {
4500 DMAC_CRITICAL_SECTION_ENTER();
4501 ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask);
4502 DMAC_CRITICAL_SECTION_LEAVE();
4503 }
4504
hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4505 static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw,
4506 hri_dmacdescriptor_descaddr_reg_t mask)
4507 {
4508 DMAC_CRITICAL_SECTION_ENTER();
4509 ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask);
4510 DMAC_CRITICAL_SECTION_LEAVE();
4511 }
4512
hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void * const hw)4513 static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw)
4514 {
4515 uint32_t tmp;
4516 tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
4517 tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos;
4518 return tmp;
4519 }
4520
hri_dmacdescriptor_set_DESCADDR_reg(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4521 static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
4522 {
4523 DMAC_CRITICAL_SECTION_ENTER();
4524 ((DmacDescriptor *)hw)->DESCADDR.reg |= mask;
4525 DMAC_CRITICAL_SECTION_LEAVE();
4526 }
4527
4528 static inline hri_dmacdescriptor_descaddr_reg_t
hri_dmacdescriptor_get_DESCADDR_reg(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4529 hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
4530 {
4531 uint32_t tmp;
4532 tmp = ((DmacDescriptor *)hw)->DESCADDR.reg;
4533 tmp &= mask;
4534 return tmp;
4535 }
4536
hri_dmacdescriptor_write_DESCADDR_reg(const void * const hw,hri_dmacdescriptor_descaddr_reg_t data)4537 static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data)
4538 {
4539 DMAC_CRITICAL_SECTION_ENTER();
4540 ((DmacDescriptor *)hw)->DESCADDR.reg = data;
4541 DMAC_CRITICAL_SECTION_LEAVE();
4542 }
4543
hri_dmacdescriptor_clear_DESCADDR_reg(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4544 static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
4545 {
4546 DMAC_CRITICAL_SECTION_ENTER();
4547 ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask;
4548 DMAC_CRITICAL_SECTION_LEAVE();
4549 }
4550
hri_dmacdescriptor_toggle_DESCADDR_reg(const void * const hw,hri_dmacdescriptor_descaddr_reg_t mask)4551 static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask)
4552 {
4553 DMAC_CRITICAL_SECTION_ENTER();
4554 ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask;
4555 DMAC_CRITICAL_SECTION_LEAVE();
4556 }
4557
hri_dmacdescriptor_read_DESCADDR_reg(const void * const hw)4558 static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw)
4559 {
4560 return ((DmacDescriptor *)hw)->DESCADDR.reg;
4561 }
4562
4563 #ifdef __cplusplus
4564 }
4565 #endif
4566
4567 #endif /* _HRI_DMAC_L21_H_INCLUDED */
4568 #endif /* _SAML21_DMAC_COMPONENT_ */
4569
