1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /*******************************************************************************************************************//** 8 * @ingroup RENESAS_GRAPHICS_INTERFACES 9 * @defgroup MIPI_DSI_API MIPI DSI Interface 10 * @brief Interface for MIPI DSI communications. 11 * 12 * @section MIPI_DSI_API_SUMMARY Summary 13 * The MIPI DSI interface provides functionality involved with driving display panels over MIPI. 14 * 15 * @{ 16 **********************************************************************************************************************/ 17 18 #ifndef R_MIPI_DSI_API_H 19 #define R_MIPI_DSI_API_H 20 21 /*********************************************************************************************************************** 22 * Includes 23 **********************************************************************************************************************/ 24 25 /* Includes board and MCU related header files. */ 26 #include "bsp_api.h" 27 #include "r_mipi_dsi_cfg.h" 28 29 #include "r_mipi_phy.h" 30 31 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 32 FSP_HEADER 33 34 /********************************************************************************************************************** 35 * Macro definitions 36 **********************************************************************************************************************/ 37 38 /********************************************************************************************************************** 39 * Typedef definitions 40 **********************************************************************************************************************/ 41 42 /** MIPI DSI packet Data Type (commands) - See MIPI specification for additional information */ 43 typedef enum e_mipi_dsi_cmd_id 44 { 45 MIPI_DSI_CMD_ID_V_SYNC_START = 0x01, ///< (Short) Sync Event, V Sync Start 46 MIPI_DSI_CMD_ID_V_SYNC_END = 0x11, ///< (Short) Sync Event, V Sync End 47 MIPI_DSI_CMD_ID_H_SYNC_START = 0x21, ///< (Short) Sync Event, H Sync Start 48 MIPI_DSI_CMD_ID_H_SYNC_END = 0x31, ///< (Short) Sync Event, H Sync End 49 50 MIPI_DSI_CMD_ID_COMPRESSION_MODE = 0x07, ///< (Short) Compression Mode Command 51 MIPI_DSI_CMD_ID_END_OF_TRANSMISSION = 0x08, ///< (Short) End of Transmission packet (EoTp) 52 53 MIPI_DSI_CMD_ID_COLOR_MODE_OFF = 0x02, ///< (Short) Color Mode (CM) Off Command 54 MIPI_DSI_CMD_ID_COLOR_MODE_ON = 0x12, ///< (Short) Color Mode (CM) On Command 55 MIPI_DSI_CMD_ID_SHUTDOWN_PERIPHERAL = 0x22, ///< (Short) Shut Down Peripheral Command 56 MIPI_DSI_CMD_ID_TURN_ON_PERIPHERAL = 0x32, ///< (Short) Turn On Peripheral Command 57 58 MIPI_DSI_CMD_ID_GENERIC_SHORT_WRITE_0_PARAM = 0x03, ///< (Short) Generic Short WRITE, no parameters 59 MIPI_DSI_CMD_ID_GENERIC_SHORT_WRITE_1_PARAM = 0x13, ///< (Short) Generic Short WRITE, 1 parameter 60 MIPI_DSI_CMD_ID_GENERIC_SHORT_WRITE_2_PARAM = 0x23, ///< (Short) Generic Short WRITE, 2 parameters 61 62 MIPI_DSI_CMD_ID_GENERIC_READ_REQUEST_0_PARAM = 0x04, ///< (Short) Generic READ, no parameters 63 MIPI_DSI_CMD_ID_GENERIC_READ_REQUEST_1_PARAM = 0x14, ///< (Short) Generic READ, 1 parameter 64 MIPI_DSI_CMD_ID_GENERIC_READ_REQUEST_2_PARAM = 0x24, ///< (Short) Generic READ, 2 parameters 65 66 MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_0_PARAM = 0x05, ///< (Short) DCS Short WRITE, no parameters 67 MIPI_DSI_CMD_ID_DCS_SHORT_WRITE_1_PARAM = 0x15, ///< (Short) DCS Short WRITE, 1 parameter 68 69 MIPI_DSI_CMD_ID_DCS_READ = 0x06, ///< (Short) DCS READ, no parameters 70 MIPI_DSI_CMD_ID_EXECUTE_QUEUE = 0x16, ///< (Short) Execute Queue 71 72 MIPI_DSI_CMD_ID_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, ///< (Short) Set Maximum Return Packet Size 73 74 MIPI_DSI_CMD_ID_NULL_PACKET = 0x09, ///< (Long) Null Packet, no data 75 MIPI_DSI_CMD_ID_BLANKING_PACKET = 0x19, ///< (Long) Blanking Packet, no data 76 MIPI_DSI_CMD_ID_GENERIC_LONG_WRITE = 0x29, ///< (Long) Generic Long Write 77 MIPI_DSI_CMD_ID_DCS_LONG_WRITE = 0x39, ///< (Long) DCS Long Write/write_LUT Command Packet 78 79 MIPI_DSI_CMD_ID_PICTURE_PARAMETER_SET = 0x0A, ///< (Long) Picture Parameter Set 80 MIPI_DSI_CMD_ID_COMPRESSED_PIXEL_STREAM = 0x0B, ///< (Long) Compressed Pixel Stream 81 82 MIPI_DSI_CMD_ID_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0C, ///< (Long) Loosely Packed Pixel Stream, 20-bit YCbCr, 4:2:2 Format 83 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR24 = 0x1C, ///< (Long) Packed Pixel Stream, 24-bit YCbCr, 4:2:2 Format 84 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR16 = 0x2C, ///< (Long) Packed Pixel Stream, 16-bit YCbCr, 4:2:2 Format 85 86 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_30 = 0x0D, ///< (Long) Packed Pixel Stream, 30-bit RGB, 10-10-10 Format 87 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_36 = 0x1D, ///< (Long) Packed Pixel Stream, 36-bit RGB, 12-12-12 Format 88 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_YCBCR12 = 0x3D, ///< (Long) Packed Pixel Stream, 12-bit YCbCr, 4:2:0 Format 89 90 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_16 = 0x0E, ///< (Long) Packed Pixel Stream, 16-bit RGB, 5-6-5 Format 91 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_18 = 0x1E, ///< (Long) Packed Pixel Stream, 18-bit RGB, 6-6-6 Format 92 MIPI_DSI_CMD_ID_LOOSELY_PACKED_PIXEL_STREAM_18 = 0x2E, ///< (Long) Loosely Packed Pixel Stream, 18-bit RGB, 6-6-6 Format 93 MIPI_DSI_CMD_ID_PACKED_PIXEL_STREAM_24 = 0x3E, ///< (Long) Packed Pixel Stream, 24-bit RGB, 8-8-8 Format 94 } mipi_dsi_cmd_id_t; 95 96 /** MIPI DCS ID types - See MIPI DCS specification for additional information */ 97 typedef enum e_mipi_dsi_dcs_id 98 { 99 MIPI_DSI_DCS_ID_ENTER_IDLE_MODE = 0x39, ///< Enter idle mode 100 MIPI_DSI_DCS_ID_ENTER_INVERT_MODE = 0x21, ///< Displayed image colors inverted 101 MIPI_DSI_DCS_ID_ENTER_NORMAL_MODE = 0x13, ///< Whole display area used for image 102 MIPI_DSI_DCS_ID_ENTER_PARTIAL_MODE = 0x12, ///< Part of display area used for image 103 MIPI_DSI_DCS_ID_ENTER_SLEEP_MODE = 0x10, ///< Power off the display panel 104 MIPI_DSI_DCS_ID_EXIT_IDLE_MODE = 0x38, ///< Full color depth used 105 MIPI_DSI_DCS_ID_EXIT_INVERT_MODE = 0x20, ///< Displayed image colors not inverted 106 MIPI_DSI_DCS_ID_EXIT_SLEEP_MODE = 0x11, ///< Power on the display panel 107 MIPI_DSI_DCS_ID_GET_3D_CONTROL = 0x3F, ///< Get display module 3D mode 108 MIPI_DSI_DCS_ID_GET_ADDRESS_MODE = 0x0B, ///< Get data order for transfers from host to the display device 109 MIPI_DSI_DCS_ID_GET_BLUE_CHANNEL = 0x08, ///< Get blue component of pixel at 0,0 110 MIPI_DSI_DCS_ID_GET_CABC_MIN_BRIGHTNESS = 0x5F, ///< Get current minimum brightness level of the active CABC mode 111 MIPI_DSI_DCS_ID_GET_COMPRESSION_MODE = 0x03, ///< Get current compression mode 112 MIPI_DSI_DCS_ID_GET_CONTROL_DISPLAY = 0x54, ///< Get control display mode 113 MIPI_DSI_DCS_ID_GET_DIAGNOSTIC_RESULT = 0x0F, ///< Get peripheral self-diagnostic result 114 MIPI_DSI_DCS_ID_GET_DISPLAY_BRIGHTNESS = 0x52, ///< Get current display brightness level 115 MIPI_DSI_DCS_ID_GET_DISPLAY_MODE = 0x0D, ///< Get current display mode from the peripheral 116 MIPI_DSI_DCS_ID_GET_DSI_MODE = 0x70, ///< Get DSI operation mode 117 MIPI_DSI_DCS_ID_GET_ERROR_COUNT_ON_DSI = 0x05, ///< Get number of corrupted packets on DSI 118 MIPI_DSI_DCS_ID_GET_GREEN_CHANNEL = 0x07, ///< Get green component of pixel at 0,0 119 MIPI_DSI_DCS_ID_GET_IMAGE_CHECKSUM_CT = 0x15, ///< Returns checksum of frame of color-transformed pixel data 120 MIPI_DSI_DCS_ID_GET_IMAGE_CHECKSUM_RGB = 0x14, ///< Returns checksum of frame of RGB pixel data 121 MIPI_DSI_DCS_ID_GET_PIXEL_FORMAT = 0x0C, ///< Get current pixel format 122 MIPI_DSI_DCS_ID_GET_POWER_MODE = 0x0A, ///< Get current power mode 123 MIPI_DSI_DCS_ID_GET_POWER_SAVE = 0x56, ///< Get current power-save mode 124 MIPI_DSI_DCS_ID_GET_RED_CHANNEL = 0x06, ///< Get red component of pixel at 0,0 125 MIPI_DSI_DCS_ID_GET_SCANLINE = 0x45, ///< Get current scanline 126 MIPI_DSI_DCS_ID_GET_SIGNAL_MODE = 0x0E, ///< Get display module signaling mode 127 MIPI_DSI_DCS_ID_NOP = 0x00, ///< No operation 128 MIPI_DSI_DCS_ID_READ_ACMD = 0x62, ///< Perform read access to the ACMD registers 129 MIPI_DSI_DCS_ID_READ_DDB_CONTINUE = 0xA8, ///< Continue reading the DDB from the last read location 130 MIPI_DSI_DCS_ID_READ_DDB_START = 0xA1, ///< Read the DDB from the provided location 131 MIPI_DSI_DCS_ID_READ_DSE_MAILBOX = 0x57, ///< Read access to the registers of the DSE read or write control mailbox 132 MIPI_DSI_DCS_ID_READ_MEMORY_CONTINUE = 0x3E, ///< Read image data from peripheral, continuing after last read 133 MIPI_DSI_DCS_ID_READ_MEMORY_START = 0x2E, ///< Read image data from the peripheral to the host 134 MIPI_DSI_DCS_ID_READ_PPS_CONTINUE = 0xA9, ///< Continue reading the specified length of PPS data 135 MIPI_DSI_DCS_ID_READ_PPS_START = 0xA2, ///< Read PPS data 136 MIPI_DSI_DCS_ID_SET_3D_CONTROL = 0x3D, ///< 3D is used on the display panel 137 MIPI_DSI_DCS_ID_SET_ADDRESS_MODE = 0x36, ///< Set data order for transfers from host to peripheral 138 MIPI_DSI_DCS_ID_SET_ARP_OFF = 0x60, ///< Disable ARP 139 MIPI_DSI_DCS_ID_SET_ARP_ON = 0x61, ///< Enable ARP and set T2 timer 140 MIPI_DSI_DCS_ID_SET_CABC_MIN_BRIGHTNESS = 0x5E, ///< Set minimum brightness level for CABC mode 141 MIPI_DSI_DCS_ID_SET_COLUMN_ADDRESS = 0x2A, ///< Set column extent 142 MIPI_DSI_DCS_ID_SET_DISPLAY_BRIGHTNESS = 0x51, ///< Set display brightness level 143 MIPI_DSI_DCS_ID_SET_DISPLAY_OFF = 0x28, ///< Blank the display device 144 MIPI_DSI_DCS_ID_SET_DISPLAY_ON = 0x29, ///< Show image on display device 145 MIPI_DSI_DCS_ID_SET_DSI_MODE = 0x71, ///< Set DSI operation mode 146 MIPI_DSI_DCS_ID_SET_GAMMA_CURVE = 0x26, ///< Select gamma curve used by display 147 MIPI_DSI_DCS_ID_SET_PAGE_ADDRESS = 0x2B, ///< Set page extent 148 MIPI_DSI_DCS_ID_SET_PARTIAL_COLUMNS = 0x31, ///< Define the number of columns in the partial display area 149 MIPI_DSI_DCS_ID_SET_PARTIAL_ROWS = 0x30, ///< Define the number of rows in the partial display area 150 MIPI_DSI_DCS_ID_SET_PIXEL_FORMAT = 0x3A, ///< Define how many bits per pixel are used 151 MIPI_DSI_DCS_ID_SET_SCROLL_AREA = 0x33, ///< Define vertical scrolling and fixed area 152 MIPI_DSI_DCS_ID_SET_SCROLL_START = 0x37, ///< Define vertical scrolling starting point 153 MIPI_DSI_DCS_ID_SET_TEAR_OFF = 0x34, ///< Sync information not sent from the display module to the host 154 MIPI_DSI_DCS_ID_SET_TEAR_ON = 0x35, ///< Sync information is sent from the display module to the host 155 MIPI_DSI_DCS_ID_SET_TEAR_SCANLINE = 0x44, ///< Sync information is sent from display to the host when display refresh reaches profivided scan line 156 MIPI_DSI_DCS_ID_SET_VSYNC_TIMING = 0x40, ///< Set VSYNC timing to the specified length of PPS data 157 MIPI_DSI_DCS_ID_SOFT_RESET = 0x01, ///< Software reset 158 MIPI_DSI_DCS_ID_WRITE_ACMD = 0x63, ///< Write access to ACMD registers 159 MIPI_DSI_DCS_ID_WRITE_CONTROL_DISPLAY = 0x53, ///< Write control mode of display brightness 160 MIPI_DSI_DCS_ID_WRITE_DSE_MAILBOX = 0x58, ///< Write registers of DSE read or write control mailbox 161 MIPI_DSI_DCS_ID_WRITE_LUT = 0x2D, ///< Fill peripheral look-up table with provided data 162 MIPI_DSI_DCS_ID_WRITE_MEMORY_CONTINUE = 0x3C, ///< Continue image information transfer from last address 163 MIPI_DSI_DCS_ID_WRITE_MEMORY_START = 0x2C, ///< Transfer image information from host to peripheral 164 MIPI_DSI_DCS_ID_WRITE_POWER_SAVE = 0x55, ///< Writes power save mode 165 } mipi_dsi_dcs_id_t; 166 167 /** MIPI DSI Video Data type */ 168 typedef enum e_mipi_dsi_video_data 169 { 170 MIPI_DSI_VIDEO_DATA_16RGB_PIXEL_STREAM = 0x0E, ///< 16-bit RGB Packed Pixel Stream 171 MIPI_DSI_VIDEO_DATA_18RGB_PIXEL_STREAM = 0x1E, ///< 18-bit RGB Packed Pixel Stream 172 MIPI_DSI_VIDEO_DATA_24RGB_PIXEL_STREAM = 0x3E, ///< 24-bit RGB Packed Pixel Stream 173 } mipi_dsi_video_data_t; 174 175 /** MIPI DSI Acknowledge and Error type */ 176 typedef enum e_mipi_dsi_ack_err 177 { 178 MIPI_DSI_ACK_ERR_NONE = 0x0000, ///< No Errors 179 MIPI_DSI_ACK_ERR_SOT_ERROR = 0x0001, ///< SoT Error 180 MIPI_DSI_ACK_ERR_SOT_SYNC_ERROR = 0x0002, ///< SoT Sync Error 181 MIPI_DSI_ACK_ERR_EOT_SYNC_ERROR = 0x0004, ///< EoT Sync Error 182 MIPI_DSI_ACK_ERR_ESCAPE_ENTRY_ERROR = 0x0008, ///< Escape Mode Entry Error 183 MIPI_DSI_ACK_ERR_LOW_POWER_SYNC_ERROR = 0x0010, ///< Low-Power Transmit Sync Error 184 MIPI_DSI_ACK_ERR_PERIPHERAL_TIMEOUT_ERROR = 0x0020, ///< Peripheral Timeout Error 185 MIPI_DSI_ACK_ERR_FALSE_CONTROL_ERROR = 0x0040, ///< False Control Error 186 MIPI_DSI_ACK_ERR_CONTENTION_DETECTED = 0x0080, ///< Contention Detected Error 187 MIPI_DSI_ACK_ERR_ECC_SINGLE = 0x0100, ///< ECC Error, single-bit 188 MIPI_DSI_ACK_ERR_ECC_MULTI = 0x0200, ///< ECC Error, multi-bit 189 MIPI_DSI_ACK_ERR_CKSM_ERROR = 0x0400, ///< Checksum Error (Long packet only) 190 MIPI_DSI_ACK_ERR_DSI_DATA_ERROR = 0x0800, ///< DSI Data Type Not Recognized 191 MIPI_DSI_ACK_ERR_DSI_VC_ID_ERROR = 0x1000, ///< DSI VC ID Invalid 192 MIPI_DSI_ACK_ERR_INVALID_TX_LEN = 0x2000, ///< Invalid Transmission Length 193 MIPI_DSI_ACK_ERR_DSI_PROTOCOL_VIOLATION = 0x8000, ///< DSI Protocol Violation 194 } mipi_dsi_ack_err_t; 195 196 /* MIPI DSI Virtual Channel ID Type*/ 197 typedef enum e_mipi_dsi_vc 198 { 199 MIPI_DSI_VC_NONE = 0x0, ///< No channels selected 200 MIPI_DSI_VC_0 = 0x1, ///< Virtual channel 0 201 MIPI_DSI_VC_1 = 0x2, ///< Virtual channel 1 202 MIPI_DSI_VC_2 = 0x4, ///< Virtual channel 2 203 MIPI_DSI_VC_3 = 0x8, ///< Virtual channel 3 204 } mipi_dsi_vc_t; 205 206 /** MIPI DSI Message Flags */ 207 typedef enum e_mipi_dsi_cmd_flag 208 { 209 MIPI_DSI_CMD_FLAG_NONE = 0x00, ///< No flags 210 MIPI_DSI_CMD_FLAG_BTA = 0x01, ///< Assert bus turnaround at end of transfer 211 MIPI_DSI_CMD_FLAG_BTA_READ = 0x02, ///< Assert bus turnaround followed by read request (No WRITE request before BTA) 212 MIPI_DSI_CMD_FLAG_BTA_NO_WRITE = 0x03, ///< Immediately assert bus turnaround (No WRITE request before BTA) 213 MIPI_DSI_CMD_FLAG_AUX_OPERATION = 0x20, ///< Execute auxiliary operation command 214 MIPI_DSI_CMD_FLAG_ACT_CODE_RESET_TRIGGER = 0x20, ///< Send action code reset trigger message. 215 MIPI_DSI_CMD_FLAG_ACT_CODE_INITIAL_SKEW_CAL = 0x24, ///< Send action code initial skew calibration message. 216 MIPI_DSI_CMD_FLAG_ACT_CODE_PERIODIC_SKEW_CAL = 0x25, ///< Send action code periodic skew message. 217 MIPI_DSI_CMD_FLAG_ACT_CODE_NO_OPERATION = 0x28, ///< Send action code NOOP message. 218 MIPI_DSI_CMD_FLAG_LOW_POWER = 0x40, ///< Transmit in low-power mode 219 } mipi_dsi_cmd_flag_t; 220 221 /** MIPI DSI event codes */ 222 typedef enum e_mipi_dsi_event 223 { 224 MIPI_DSI_EVENT_SEQUENCE_0, ///< Sequence 0 event (Low-Power) 225 MIPI_DSI_EVENT_SEQUENCE_1, ///< Sequence 1 event (High-Speed) 226 MIPI_DSI_EVENT_VIDEO, ///< Video event 227 MIPI_DSI_EVENT_RECEIVE, ///< Receive event 228 MIPI_DSI_EVENT_FATAL, ///< Fatal event 229 MIPI_DSI_EVENT_PHY, ///< Physical layer event 230 231 /* Software triggered events - To allow application specific processing */ 232 MIPI_DSI_EVENT_POST_OPEN, ///< Interface has been opened. Perform post-open application processing 233 MIPI_DSI_EVENT_PRE_START, ///< Video is about to start. Perform pre-video application processing 234 } mipi_dsi_event_t; 235 236 /** MIPI DSI Sequence status */ 237 typedef enum e_mipi_dsi_sequence_status 238 { 239 MIPI_DSI_SEQUENCE_STATUS_NONE = 0X00000000, ///< Sequence status not set 240 MIPI_DSI_SEQUENCE_STATUS_RUNNING = 0x00000004, ///< Sequence operation in progress 241 MIPI_DSI_SEQUENCE_STATUS_ACTIONS_FINISHED = 0x00000010, ///< All descriptor actions finished 242 MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED = 0x00000100, ///< All descriptors finished 243 MIPI_DSI_SEQUENCE_STATUS_DESCRIPTOR_ABORT = 0x00010000, ///< Descriptor abort interrupt 244 MIPI_DSI_SEQUENCE_STATUS_SIZE_ERROR = 0x00080000, ///< Packet size error 245 MIPI_DSI_SEQUENCE_STATUS_TX_INTERNAL_BUS_ERROR = 0x01000000, ///< Tx internal bus error 246 MIPI_DSI_SEQUENCE_STATUS_RX_FATAL_ERROR = 0x04800000, ///< Receive fatal error 247 MIPI_DSI_SEQUENCE_STATUS_RX_FAIL = 0x08000000, ///< Receive fail 248 MIPI_DSI_SEQUENCE_STATUS_RX_PACKET_DATA_FAIL = 0x10000000, ///< Receive packet data fail 249 MIPI_DSI_SEQUENCE_STATUS_RX_CORRECTABLE_ERROR = 0x20000000, ///< Receive correctable error 250 MIPI_DSI_SEQUENCE_STATUS_RX_ACK_AND_ERROR = 0x40000000, ///< Receive acknowledge and error report 251 } mipi_dsi_sequence_status_t; 252 253 /** MIPI DSI video status errors */ 254 typedef enum e_mipi_dsi_video_status 255 { 256 MIPI_DSI_VIDEO_STATUS_NONE = 0x00000000, ///< Video status not set 257 MIPI_DSI_VIDEO_STATUS_START = 0x00000001, ///< Video started event 258 MIPI_DSI_VIDEO_STATUS_STOP = 0x00000002, ///< Video stopped event 259 MIPI_DSI_VIDEO_STATUS_RUNNING = 0x00000004, ///< Video running status 260 MIPI_DSI_VIDEO_STATUS_READY = 0x00000008, ///< Video ready event 261 MIPI_DSI_VIDEO_STATUS_TIMING_ERROR = 0x00100000, ///< Video timing error event 262 MIPI_DSI_VIDEO_STATUS_UNDERFLOW = 0x00400000, ///< Video buffer underflow event 263 MIPI_DSI_VIDEO_STATUS_OVERFLOW = 0x00800000, ///< Video buffer overflow event 264 } mipi_dsi_video_status_t; 265 266 /** MIPI DSI receive status errors */ 267 typedef enum e_mipi_dsi_receive_status 268 { 269 MIPI_DSI_RECEIVE_STATUS_NONE = 0x00000000, ///< Receive status not set 270 MIPI_DSI_RECEIVE_STATUS_BTA_REQUEST_END = 0x00000001, ///< Receive BTA request end 271 MIPI_DSI_RECEIVE_STATUS_LP_RX_HOST_TIMEOUT = 0x00000002, ///< Receive low power receive timeout 272 MIPI_DSI_RECEIVE_STATUS_BTA_ACK_TIMEOUT = 0x00000004, ///< Receive BTA ack timeout 273 MIPI_DSI_RECEIVE_STATUS_RESPONSE_PACKET = 0x00000100, ///< Receive response 274 MIPI_DSI_RECEIVE_STATUS_EOTP = 0x00000400, ///< Receive end of transmission packet 275 MIPI_DSI_RECEIVE_STATUS_TEARING_TRIGGER = 0x00002000, ///< Receive tearing trigger 276 MIPI_DSI_RECEIVE_STATUS_ACK_TRIGGER = 0x00004000, ///< Receive ack trigger 277 MIPI_DSI_RECEIVE_STATUS_TEARING_DETECT = 0x00008000, ///< Receive tearing detect 278 MIPI_DSI_RECEIVE_STATUS_MALFORM_ERROR = 0x00010000, ///< Receive malform error 279 MIPI_DSI_RECEIVE_STATUS_ECC_MULTI = 0x00020000, ///< Receive ecc multi-bit error 280 MIPI_DSI_RECEIVE_STATUS_UNEXPECTED_PACKET = 0x00040000, ///< Receive unexpected packet 281 MIPI_DSI_RECEIVE_STATUS_WORD_COUNT = 0x00100000, ///< Receive word count 282 MIPI_DSI_RECEIVE_STATUS_CRC = 0x00200000, ///< Receive crc error 283 MIPI_DSI_RECEIVE_STATUS_INTERNAL_BUS = 0x00400000, ///< Receive internal bus error 284 MIPI_DSI_RECEIVE_STATUS_BUFFER_OVERFLOW = 0x00800000, ///< Receive buffer overflow 285 MIPI_DSI_RECEIVE_STATUS_TIMEOUT = 0x01000000, ///< Receive timeout 286 MIPI_DSI_RECEIVE_STATUS_NO_RESPONSE = 0x02000000, ///< Receive no response 287 MIPI_DSI_RECEIVE_STATUS_PACKET_SIZE = 0x04000000, ///< Receive packet size error 288 MIPI_DSI_RECEIVE_STATUS_ECC_SINGLE = 0x10000000, ///< Receive ecc single bit error 289 MIPI_DSI_RECEIVE_STATUS_ACK_AND_ERROR = 0x40000000, ///< Receive ack and error 290 } mipi_dsi_receive_status_t; 291 292 /** MIPI DSI fatal status errors */ 293 typedef enum e_mipi_dsi_fatal_status 294 { 295 MIPI_DSI_FATAL_STATUS_NONE = 0x00000000, ///< Fatal status not set 296 MIPI_DSI_FATAL_STATUS_HS_TX_TIMEOUT = 0x00000001, ///< Fatal high speed transmit timeout 297 MIPI_DSI_FATAL_STATUS_LP_RX_TIMEOUT = 0x00000002, ///< Fatal low power receive timeout 298 MIPI_DSI_FATAL_STATUS_BTA_ACK_TIMEOUT = 0x00000004, ///< Fatal BTA ack timeout 299 MIPI_DSI_FATAL_STATUS_ESCAPE_ENTRY_ERROR = 0x00010000, ///< Fatal escape mode entry error 300 MIPI_DSI_FATAL_STATUS_LPDT_SYNC_ERROR = 0x00020000, ///< Fatal low power data transmission synchronization error 301 MIPI_DSI_FATAL_STATUS_CTRL_ERROR = 0x00040000, ///< Fatal control error 302 MIPI_DSI_FATAL_STATUS_LP0_CONTENTION_DETECT = 0x00080000, ///< Fatal lane 0 low power contention detect 303 MIPI_DSI_FATAL_STATUS_LP1_CONTENTION_DETECT = 0x00100000, ///< Fatal lane 1 low power contention detect 304 MIPI_DSI_FATAL_STATUS_LP0_CONTENTION = 0x80000000, ///< Fatal lane 0 low power contention status 305 MIPI_DSI_FATAL_STATUS_LP1_CONTENTION = 0x10000000, ///< Fatal lane 1 low power contention status 306 } mipi_dsi_fatal_status_t; 307 308 /** MIPI DSI physical lane status */ 309 typedef enum e_mipi_dsi_phy_status 310 { 311 MIPI_DSI_PHY_STATUS_NONE = 0x00000000, ///< Physical lane status not set 312 MIPI_DSI_PHY_STATUS_ULP_NOT_ACTIVE = 0x00000001, ///< Physical lane ULP not active 313 MIPI_DSI_PHY_STATUS_CLOCK_LANE_STOP = 0x00000002, ///< Clock lane in stopped state 314 MIPI_DSI_PHY_STATUS_DATA_LANE0_LP_RX = 0x00000004, ///< Data lane low power receive mode 315 MIPI_DSI_PHY_STATUS_DATA_LANE0_ULP_RX = 0x00000008, ///< Data lane ultra low power receive mode 316 MIPI_DSI_PHY_STATUS_DATA_LANE0_NOT_ULP = 0x00000010, ///< Data lane 0 not in ULP mode 317 MIPI_DSI_PHY_STATUS_DATA_LANE1_NOT_ULP = 0x00000020, ///< Data lane 1 not in ULP mode 318 MIPI_DSI_PHY_STATUS_DATA_LANE0_STOP = 0x00000100, ///< Data lane 0 stop state 319 MIPI_DSI_PHY_STATUS_DATA_LANE1_STOP = 0x00000200, ///< Data lane 1 stop state 320 MIPI_DSI_PHY_STATUS_DATA_LANE0_RX_TO_TX = 0x00001000, ///< Data lane Rx to Tx transition event 321 MIPI_DSI_PHY_STATUS_DATA_LANE0_TX_TO_RX = 0x00002000, ///< Data lane Tx to Rx transition event 322 MIPI_DSI_PHY_STATUS_DATA_LANE0_RX_STATE = 0x00008000, ///< Data lane Rx active state 323 MIPI_DSI_PHY_STATUS_CLOCK_ULPS_ENTER = 0x01000000, ///< Clock lane ULPS enter event 324 MIPI_DSI_PHY_STATUS_CLOCK_ULPS_EXIT = 0x02000000, ///< Clock lane ULPS exit event 325 MIPI_DSI_PHY_STATUS_CLOCK_LP_TO_HS = 0x04000000, ///< Clock lane LP to HS transition event 326 MIPI_DSI_PHY_STATUS_CLOCK_HS_TO_LP = 0x08000000, ///< Clock lane HS to LP transition event 327 MIPI_DSI_PHY_STATUS_DATA_LANE_ULPS_ENTER = 0x10000000, ///< Data lane ULPS enter event 328 MIPI_DSI_PHY_STATUS_DATA_LANE_ULPS_EXIT = 0x20000000, ///< Data lane ULPS exit event 329 } mipi_dsi_phy_status_t; 330 331 /** MIPI DSI link status bits */ 332 typedef enum e_mipi_dsi_link_status 333 { 334 MIPI_DSI_LINK_STATUS_IDLE = 0x0000, ///< Link idle or uninitialized 335 MIPI_DSI_LINK_STATUS_CH0_RUNNING = 0x0001, ///< Channel 0 running 336 MIPI_DSI_LINK_STATUS_CH1_RUNNING = 0x0010, ///< Channel 1 running 337 MIPI_DSI_LINK_STATUS_VIDEO_RUNNING = 0x0100, ///< Video output running 338 MIPI_DSI_LINK_STATUS_HP_MODE_BUSY = 0x1000, ///< HP operation busy 339 MIPI_DSI_LINK_STATUS_LP_MODE_BUSY = 0x2000, ///< LP operation busy 340 } mipi_dsi_link_status_t; 341 342 /** MIPI DSI Lane Type */ 343 typedef enum e_mipi_dsi_lane 344 { 345 MIPI_DSI_LANE_CLOCK = 0x01, ///< Clock Lanes 346 MIPI_DSI_LANE_DATA_ALL = 0x02, ///< All Data Lanes 347 } mipi_dsi_lane_t; 348 349 /** MIPI DSI Command */ 350 typedef struct st_mipi_dsi_cmd 351 { 352 uint8_t channel; ///< Virtual Channel ID 353 mipi_dsi_cmd_id_t cmd_id; ///< Message ID 354 mipi_dsi_cmd_flag_t flags; ///< Flags controlling this message transition 355 uint16_t tx_len; ///< Transmit buffer size 356 const uint8_t * p_tx_buffer; ///< Transmit buffer pointer 357 const uint8_t * p_rx_buffer; ///< Receive buffer pointer 358 } mipi_dsi_cmd_t; 359 360 /** MIPI DSI Acknowledge and Error status type */ 361 typedef union st_mipi_dsi_ack_err_status_t 362 { 363 __PACKED_STRUCT 364 { 365 mipi_dsi_ack_err_t error_report : 16; ///< Error report bits 366 mipi_dsi_vc_t virtual_channel : 4; ///< Virtual Channel ID 367 uint32_t : 12; // Padding 368 }; 369 uint32_t bits; 370 } mipi_dsi_ack_err_status_t; 371 372 /** MIPI DSI status type */ 373 typedef struct st_mipi_dsi_status_t 374 { 375 mipi_dsi_link_status_t link_status; ///< Link status 376 mipi_dsi_ack_err_status_t ack_err_latest; ///< Latest Acknowledge and Error Report Packet Latest Info 377 mipi_dsi_ack_err_status_t ack_err_accumulated; ///< Accumulated Acknowledge and Error Report Packet Latest Info 378 } mipi_dsi_status_t; 379 380 /** MIPI DSI Result */ 381 typedef __PACKED_STRUCT st_mipi_dsi_result 382 { 383 uint8_t data[2]; ///< Data of received packet header 384 mipi_dsi_cmd_id_t cmd_id : 6; ///< Data type 385 uint8_t virtual_channel_id : 2; ///< Virtual channel ID 386 uint8_t long_packet : 1; ///< Sort packet (0) or Long packet (1) 387 uint8_t rx_success : 1; ///< Response packet or ack trigger received 388 uint8_t timeout : 1; ///< Fatal timeout error 389 uint8_t rx_fail : 1; ///< Expected receive not done 390 uint8_t rx_data_fail : 1; ///< Receive packet data fail 391 uint8_t rx_correctable_error : 1; ///< Correctable error detected 392 uint8_t rx_ack_err : 1; ///< Rx acknowledge and error report packet received 393 uint8_t info_overwrite : 1; ///< This information was overwritten 394 } mipi_dsi_receive_result_t; 395 396 /** MIPI DSI callback parameter definition */ 397 typedef struct st_mipi_dsi_callback_args 398 { 399 mipi_dsi_event_t event; ///< Event code 400 union 401 { 402 mipi_dsi_sequence_status_t tx_status; ///< Sequence status 403 mipi_dsi_receive_status_t rx_status; ///< Receive status 404 mipi_dsi_fatal_status_t fatal_status; ///< Fatal status 405 mipi_dsi_video_status_t video_status; ///< Video status 406 mipi_dsi_phy_status_t phy_status; ///< Phy Status 407 }; 408 mipi_dsi_receive_result_t * p_result; ///< Receive result pointer 409 void const * p_context; ///< Context provided to user during callback 410 } mipi_dsi_callback_args_t; 411 412 /** MIPI DSI transition timing */ 413 typedef struct st_mipi_dsi_timing 414 { 415 uint32_t clock_stop_time; ///< Clock stop time 416 uint32_t clock_beforehand_time; ///< Clock beforehand time 417 uint32_t clock_keep_time; ///< Clock Keep time 418 uint32_t go_lp_and_back; ///< Go LP and Back time 419 } mipi_dsi_timing_t; 420 421 /** MIPI DSI main configuration structure */ 422 typedef struct st_mipi_dsi_cfg 423 { 424 mipi_phy_instance_t const * p_mipi_phy_instance; ///< Pointer to mipi physical layer instance 425 426 mipi_dsi_timing_t const * p_timing; ///< Pointer to MIPI DSI timing configuration 427 428 bool hsa_no_lp; ///< Suppress the transition to LP during HSA period and keep HS 429 bool hbp_no_lp; ///< Suppress the transition to LP during HBP period and keep HS 430 bool hfp_no_lp; ///< Suppress the transition to LP during HFP period and keep HS 431 uint8_t num_lanes; ///< Number of MIPI lanes to use. 432 uint8_t ulps_wakeup_period; ///< ULPS wakeup period 433 uint8_t continuous_clock; ///< Always run HS clock on/off 434 uint32_t hs_tx_timeout; ///< HS-Tx Timeout value 435 uint32_t lp_rx_timeout; ///< LP-Rx host processor timeout 436 uint32_t turnaround_timeout; ///< Turnaround Acknowledge Timeout 437 uint32_t bta_timeout; ///< Peripheral Response Timeout 438 uint32_t lprw_timeout; ///< LP Read and Write Timeouts 439 uint32_t hsrw_timeout; ///< HS Read and Write Timeouts 440 uint32_t max_return_packet_size; ///< Maximum return packet size 441 bool ecc_enable; ///< ECC Check enable 442 mipi_dsi_vc_t crc_check_mask; ///< Virtual channel CRC check enable 443 bool scramble_enable; ///< Scramble on/off 444 bool tearing_detect; ///< External tearing effect detection mode (0:rising, 1:falling edge) 445 bool eotp_enable; ///< End of Transmit Packet (EoTP) on/off 446 bool sync_pulse; ///< Enable for Non-Burst Mode with Sync Pulse sequence 447 mipi_dsi_video_data_t data_type; ///< Video mode data type: 16-bit RGB, 18-bit RGB, 24-bit RGB 448 uint8_t virtual_channel_id; ///< Video mode virtual channel to use (from 0x0 to 0x3) 449 uint32_t vertical_sync_lines; ///< Number of vertical sync active lines 450 bool vertical_sync_polarity; ///< V-Sync Polarity 451 uint32_t vertical_active_lines; ///< Number of vertical active lines 452 uint32_t vertical_back_porch; ///< Vertical back porch 453 uint32_t vertical_front_porch; ///< Vertical front porch 454 uint32_t horizontal_sync_lines; ///< Number of horizontal sync active lines 455 bool horizontal_sync_polarity; ///< H-Sync Polarity 456 uint32_t horizontal_active_lines; ///< Number of horizontal active lines 457 uint32_t horizontal_back_porch; ///< Horizontal back porch 458 uint32_t horizontal_front_porch; ///< Horizontal front porch 459 uint32_t video_mode_delay; 460 461 /** Callback configuration */ 462 void (* p_callback)(mipi_dsi_callback_args_t * p_args); ///< Pointer to callback function 463 void const * p_context; ///< User defined context passed into callback function 464 465 /** Pointer to display peripheral specific configuration */ 466 void const * p_extend; ///< MIPI hardware dependent configuration 467 } mipi_dsi_cfg_t; 468 469 /** MIPI DSI control block. Allocate an instance specific control block to pass into the MIPI DSI API calls. */ 470 typedef void mipi_dsi_ctrl_t; 471 472 /** Shared Interface definition for MIPI DSI peripheral */ 473 typedef struct st_mipi_dsi_api 474 { 475 /** Open MIPI DSI device. 476 * 477 * @param[in,out] p_ctrl Pointer to MIPI DSI interface control block. Must be declared by user. Value set here. 478 * @param[in] p_cfg Pointer to MIPI DSI configuration structure. All elements of this structure must be set by user. 479 */ 480 fsp_err_t (* open)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_cfg_t const * const p_cfg); 481 482 /** Close MIPI DSI device. 483 * 484 * @param[in] p_ctrl Pointer to MIPI DSI interface control block. 485 */ 486 fsp_err_t (* close)(mipi_dsi_ctrl_t * const p_ctrl); 487 488 /** Start pixel data output. 489 * 490 * @param[in] p_ctrl Pointer to MIPI DSI interface control block. 491 */ 492 fsp_err_t (* start)(mipi_dsi_ctrl_t * const p_ctrl); 493 494 /** Stop pixel data output. 495 * 496 * @param[in] p_ctrl Pointer to MIPI DSI interface control block. 497 */ 498 fsp_err_t (* stop)(mipi_dsi_ctrl_t * const p_ctrl); 499 500 /** Enter Ultra-low Power State (ULPS). 501 * 502 * @param[in] p_ctrl Pointer to MIPI DSI interface control block. 503 * @param[in] lane Physical lane(s) to transition into ULPS 504 */ 505 fsp_err_t (* ulpsEnter)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_lane_t lane); 506 507 /** Exit Ultra-low Power State (ULPS). 508 * 509 * @param[in] p_ctrl Pointer to MIPI DSI interface control block. 510 * @param[in] lane Physical lane(s) to transition from ULPS 511 */ 512 fsp_err_t (* ulpsExit)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_lane_t lane); 513 514 /** Send a command to the display. 515 * 516 * @param[in] p_ctrl Pointer to MIPI DSI interface control block. 517 * @param[in] p_cmd Pointer to a command structure 518 */ 519 fsp_err_t (* command)(mipi_dsi_ctrl_t * const p_api_ctrl, mipi_dsi_cmd_t * p_cmd); 520 521 /** Get status of MIPI link. 522 * 523 * @param[in] p_ctrl Pointer to MIPI DSI interface control block. 524 * @param[in] p_status Pointer to MIPI DSI interface status structure. 525 */ 526 fsp_err_t (* statusGet)(mipi_dsi_ctrl_t * const p_ctrl, mipi_dsi_status_t * p_status); 527 } mipi_dsi_api_t; 528 529 /** This structure encompasses everything that is needed to use an instance of this interface. */ 530 typedef struct st_mipi_dsi_instance 531 { 532 mipi_dsi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance 533 mipi_dsi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance 534 mipi_dsi_api_t const * p_api; ///< Pointer to the API structure for this instance 535 } mipi_dsi_instance_t; 536 537 /* @} (end defgroup MIPI_DSI_API) */ 538 539 /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 540 FSP_FOOTER 541 #endif 542
