1 /**
2 ******************************************************************************
3 * @file h3lis331dl_reg.c
4 * @author Sensors Software Solution Team
5 * @brief H3LIS331DL driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "h3lis331dl_reg.h"
21
22 /**
23 * @defgroup H3LIS331DL
24 * @brief This file provides a set of functions needed to drive the
25 * h3lis331dl enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup H3LIS331DL_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
h3lis331dl_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak h3lis331dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
h3lis331dl_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak h3lis331dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup H3LIS331DL_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
h3lis331dl_from_fs100_to_mg(int16_t lsb)97 float_t h3lis331dl_from_fs100_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb * 3.0625f);
100 }
101
h3lis331dl_from_fs200_to_mg(int16_t lsb)102 float_t h3lis331dl_from_fs200_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb * 6.125f);
105 }
106
h3lis331dl_from_fs400_to_mg(int16_t lsb)107 float_t h3lis331dl_from_fs400_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb * 12.1875f);
110 }
111
112 /**
113 * @}
114 *
115 */
116
117 /**
118 * @defgroup H3LIS331DL_Data_Generation
119 * @brief This section group all the functions concerning
120 * data generation
121 * @{
122 *
123 */
124
125 /**
126 * @brief X axis enable/disable.[set]
127 *
128 * @param ctx read / write interface definitions(ptr)
129 * @param val change the values of xen in reg CTRL_REG1
130 * @retval interface status (MANDATORY: return 0 -> no Error)
131 *
132 */
h3lis331dl_axis_x_data_set(const stmdev_ctx_t * ctx,uint8_t val)133 int32_t h3lis331dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val)
134 {
135 h3lis331dl_ctrl_reg1_t ctrl_reg1;
136 int32_t ret;
137
138 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
139 (uint8_t *)&ctrl_reg1, 1);
140
141 if (ret == 0)
142 {
143 ctrl_reg1.xen = val;
144 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
145 (uint8_t *)&ctrl_reg1, 1);
146 }
147
148 return ret;
149 }
150
151 /**
152 * @brief X axis enable/disable.[get]
153 *
154 * @param ctx read / write interface definitions(ptr)
155 * @param val change the values of xen in reg CTRL_REG1
156 * @retval interface status (MANDATORY: return 0 -> no Error)
157 *
158 */
h3lis331dl_axis_x_data_get(const stmdev_ctx_t * ctx,uint8_t * val)159 int32_t h3lis331dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
160 {
161 h3lis331dl_ctrl_reg1_t ctrl_reg1;
162 int32_t ret;
163
164 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
165 (uint8_t *)&ctrl_reg1, 1);
166 *val = ctrl_reg1.xen;
167
168 return ret;
169 }
170
171 /**
172 * @brief Y axis enable/disable.[set]
173 *
174 * @param ctx read / write interface definitions(ptr)
175 * @param val change the values of yen in reg CTRL_REG1
176 * @retval interface status (MANDATORY: return 0 -> no Error)
177 *
178 */
h3lis331dl_axis_y_data_set(const stmdev_ctx_t * ctx,uint8_t val)179 int32_t h3lis331dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val)
180 {
181 h3lis331dl_ctrl_reg1_t ctrl_reg1;
182 int32_t ret;
183
184 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
185 (uint8_t *)&ctrl_reg1, 1);
186
187 if (ret == 0)
188 {
189 ctrl_reg1.yen = val;
190 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
191 (uint8_t *)&ctrl_reg1, 1);
192 }
193
194 return ret;
195 }
196
197 /**
198 * @brief Y axis enable/disable.[get]
199 *
200 * @param ctx read / write interface definitions(ptr)
201 * @param val change the values of yen in reg CTRL_REG1
202 * @retval interface status (MANDATORY: return 0 -> no Error)
203 *
204 */
h3lis331dl_axis_y_data_get(const stmdev_ctx_t * ctx,uint8_t * val)205 int32_t h3lis331dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
206 {
207 h3lis331dl_ctrl_reg1_t ctrl_reg1;
208 int32_t ret;
209
210 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
211 (uint8_t *)&ctrl_reg1, 1);
212 *val = ctrl_reg1.yen;
213
214 return ret;
215 }
216
217 /**
218 * @brief Z axis enable/disable.[set]
219 *
220 * @param ctx read / write interface definitions(ptr)
221 * @param val change the values of zen in reg CTRL_REG1
222 * @retval interface status (MANDATORY: return 0 -> no Error)
223 *
224 */
h3lis331dl_axis_z_data_set(const stmdev_ctx_t * ctx,uint8_t val)225 int32_t h3lis331dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val)
226 {
227 h3lis331dl_ctrl_reg1_t ctrl_reg1;
228 int32_t ret;
229
230 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
231 (uint8_t *)&ctrl_reg1, 1);
232
233 if (ret == 0)
234 {
235 ctrl_reg1.zen = val;
236 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
237 (uint8_t *)&ctrl_reg1, 1);
238 }
239
240 return ret;
241 }
242
243 /**
244 * @brief Z axis enable/disable.[get]
245 *
246 * @param ctx read / write interface definitions(ptr)
247 * @param val change the values of zen in reg CTRL_REG1
248 * @retval interface status (MANDATORY: return 0 -> no Error)
249 *
250 */
h3lis331dl_axis_z_data_get(const stmdev_ctx_t * ctx,uint8_t * val)251 int32_t h3lis331dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
252 {
253 h3lis331dl_ctrl_reg1_t ctrl_reg1;
254 int32_t ret;
255
256 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
257 (uint8_t *)&ctrl_reg1, 1);
258 *val = ctrl_reg1.zen;
259
260 return ret;
261 }
262
263 /**
264 * @brief Accelerometer data rate selection.[set]
265 *
266 * @param ctx read / write interface definitions(ptr)
267 * @param val change the values of dr in reg CTRL_REG1
268 * @retval interface status (MANDATORY: return 0 -> no Error)
269 *
270 */
h3lis331dl_data_rate_set(const stmdev_ctx_t * ctx,h3lis331dl_dr_t val)271 int32_t h3lis331dl_data_rate_set(const stmdev_ctx_t *ctx,
272 h3lis331dl_dr_t val)
273 {
274 h3lis331dl_ctrl_reg1_t ctrl_reg1;
275 int32_t ret;
276
277 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
278 (uint8_t *)&ctrl_reg1, 1);
279
280 if (ret == 0)
281 {
282 ctrl_reg1.pm = (uint8_t)val & 0x07U;
283 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
284 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG1,
285 (uint8_t *)&ctrl_reg1, 1);
286 }
287
288 return ret;
289 }
290
291 /**
292 * @brief Accelerometer data rate selection.[get]
293 *
294 * @param ctx read / write interface definitions(ptr)
295 * @param val Get the values of dr in reg CTRL_REG1
296 * @retval interface status (MANDATORY: return 0 -> no Error)
297 *
298 */
h3lis331dl_data_rate_get(const stmdev_ctx_t * ctx,h3lis331dl_dr_t * val)299 int32_t h3lis331dl_data_rate_get(const stmdev_ctx_t *ctx,
300 h3lis331dl_dr_t *val)
301 {
302 h3lis331dl_ctrl_reg1_t ctrl_reg1;
303 int32_t ret;
304
305 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG1,
306 (uint8_t *)&ctrl_reg1, 1);
307
308 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
309 {
310 case H3LIS331DL_ODR_OFF:
311 *val = H3LIS331DL_ODR_OFF;
312 break;
313
314 case H3LIS331DL_ODR_Hz5:
315 *val = H3LIS331DL_ODR_Hz5;
316 break;
317
318 case H3LIS331DL_ODR_1Hz:
319 *val = H3LIS331DL_ODR_1Hz;
320 break;
321
322 case H3LIS331DL_ODR_2Hz:
323 *val = H3LIS331DL_ODR_2Hz;
324 break;
325
326 case H3LIS331DL_ODR_5Hz:
327 *val = H3LIS331DL_ODR_5Hz;
328 break;
329
330 case H3LIS331DL_ODR_10Hz:
331 *val = H3LIS331DL_ODR_10Hz;
332 break;
333
334 case H3LIS331DL_ODR_50Hz:
335 *val = H3LIS331DL_ODR_50Hz;
336 break;
337
338 case H3LIS331DL_ODR_100Hz:
339 *val = H3LIS331DL_ODR_100Hz;
340 break;
341
342 case H3LIS331DL_ODR_400Hz:
343 *val = H3LIS331DL_ODR_400Hz;
344 break;
345
346 case H3LIS331DL_ODR_1kHz:
347 *val = H3LIS331DL_ODR_1kHz;
348 break;
349
350 default:
351 *val = H3LIS331DL_ODR_OFF;
352 break;
353 }
354
355 return ret;
356 }
357
358 /**
359 * @brief High pass filter mode selection.[set]
360 *
361 * @param ctx read / write interface definitions(ptr)
362 * @param val change the values of hpm in reg CTRL_REG2
363 * @retval interface status (MANDATORY: return 0 -> no Error)
364 *
365 */
h3lis331dl_reference_mode_set(const stmdev_ctx_t * ctx,h3lis331dl_hpm_t val)366 int32_t h3lis331dl_reference_mode_set(const stmdev_ctx_t *ctx,
367 h3lis331dl_hpm_t val)
368 {
369 h3lis331dl_ctrl_reg2_t ctrl_reg2;
370 int32_t ret;
371
372 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
373 (uint8_t *)&ctrl_reg2, 1);
374
375 if (ret == 0)
376 {
377 ctrl_reg2.hpm = (uint8_t)val;
378 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
379 (uint8_t *)&ctrl_reg2, 1);
380 }
381
382 return ret;
383 }
384
385 /**
386 * @brief High pass filter mode selection.[get]
387 *
388 * @param ctx read / write interface definitions(ptr)
389 * @param val Get the values of hpm in reg CTRL_REG2
390 * @retval interface status (MANDATORY: return 0 -> no Error)
391 *
392 */
h3lis331dl_reference_mode_get(const stmdev_ctx_t * ctx,h3lis331dl_hpm_t * val)393 int32_t h3lis331dl_reference_mode_get(const stmdev_ctx_t *ctx,
394 h3lis331dl_hpm_t *val)
395 {
396 h3lis331dl_ctrl_reg2_t ctrl_reg2;
397 int32_t ret;
398
399 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
400 (uint8_t *)&ctrl_reg2, 1);
401
402 switch (ctrl_reg2.hpm)
403 {
404 case H3LIS331DL_NORMAL_MODE:
405 *val = H3LIS331DL_NORMAL_MODE;
406 break;
407
408 case H3LIS331DL_REF_MODE_ENABLE:
409 *val = H3LIS331DL_REF_MODE_ENABLE;
410 break;
411
412 default:
413 *val = H3LIS331DL_NORMAL_MODE;
414 break;
415 }
416
417 return ret;
418 }
419
420 /**
421 * @brief Accelerometer full-scale selection.[set]
422 *
423 * @param ctx read / write interface definitions(ptr)
424 * @param val change the values of fs in reg CTRL_REG4
425 * @retval interface status (MANDATORY: return 0 -> no Error)
426 *
427 */
h3lis331dl_full_scale_set(const stmdev_ctx_t * ctx,h3lis331dl_fs_t val)428 int32_t h3lis331dl_full_scale_set(const stmdev_ctx_t *ctx,
429 h3lis331dl_fs_t val)
430 {
431 h3lis331dl_ctrl_reg4_t ctrl_reg4;
432 int32_t ret;
433
434 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
435 (uint8_t *)&ctrl_reg4, 1);
436
437 if (ret == 0)
438 {
439 ctrl_reg4.fs = (uint8_t)val;
440 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
441 (uint8_t *)&ctrl_reg4, 1);
442 }
443
444 return ret;
445 }
446
447 /**
448 * @brief Accelerometer full-scale selection.[get]
449 *
450 * @param ctx read / write interface definitions(ptr)
451 * @param val Get the values of fs in reg CTRL_REG4
452 * @retval interface status (MANDATORY: return 0 -> no Error)
453 *
454 */
h3lis331dl_full_scale_get(const stmdev_ctx_t * ctx,h3lis331dl_fs_t * val)455 int32_t h3lis331dl_full_scale_get(const stmdev_ctx_t *ctx,
456 h3lis331dl_fs_t *val)
457 {
458 h3lis331dl_ctrl_reg4_t ctrl_reg4;
459 int32_t ret;
460
461 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
462 (uint8_t *)&ctrl_reg4, 1);
463
464 switch (ctrl_reg4.fs)
465 {
466 case H3LIS331DL_100g:
467 *val = H3LIS331DL_100g;
468 break;
469
470 case H3LIS331DL_200g:
471 *val = H3LIS331DL_200g;
472 break;
473
474 case H3LIS331DL_400g:
475 *val = H3LIS331DL_400g;
476 break;
477
478 default:
479 *val = H3LIS331DL_100g;
480 break;
481 }
482
483 return ret;
484 }
485
486 /**
487 * @brief Block data update.[set]
488 *
489 * @param ctx read / write interface definitions(ptr)
490 * @param val change the values of bdu in reg CTRL_REG4
491 * @retval interface status (MANDATORY: return 0 -> no Error)
492 *
493 */
h3lis331dl_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)494 int32_t h3lis331dl_block_data_update_set(const stmdev_ctx_t *ctx,
495 uint8_t val)
496 {
497 h3lis331dl_ctrl_reg4_t ctrl_reg4;
498 int32_t ret;
499
500 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
501 (uint8_t *)&ctrl_reg4, 1);
502
503 if (ret == 0)
504 {
505 ctrl_reg4.bdu = val;
506 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
507 (uint8_t *)&ctrl_reg4, 1);
508 }
509
510 return ret;
511 }
512
513 /**
514 * @brief Block data update.[get]
515 *
516 * @param ctx read / write interface definitions(ptr)
517 * @param val change the values of bdu in reg CTRL_REG4
518 * @retval interface status (MANDATORY: return 0 -> no Error)
519 *
520 */
h3lis331dl_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)521 int32_t h3lis331dl_block_data_update_get(const stmdev_ctx_t *ctx,
522 uint8_t *val)
523 {
524 h3lis331dl_ctrl_reg4_t ctrl_reg4;
525 int32_t ret;
526
527 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
528 (uint8_t *)&ctrl_reg4, 1);
529 *val = ctrl_reg4.bdu;
530
531 return ret;
532 }
533
534 /**
535 * @brief The STATUS_REG register is read by the interface.[get]
536 *
537 * @param ctx read / write interface definitions(ptr)
538 * @param val registers STATUS_REG
539 * @retval interface status (MANDATORY: return 0 -> no Error)
540 *
541 */
h3lis331dl_status_reg_get(const stmdev_ctx_t * ctx,h3lis331dl_status_reg_t * val)542 int32_t h3lis331dl_status_reg_get(const stmdev_ctx_t *ctx,
543 h3lis331dl_status_reg_t *val)
544 {
545 int32_t ret;
546
547 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_STATUS_REG,
548 (uint8_t *) val, 1);
549
550 return ret;
551 }
552
553 /**
554 * @brief Accelerometer new data available.[get]
555 *
556 * @param ctx read / write interface definitions(ptr)
557 * @param val change the values of zyxda in reg STATUS_REG
558 * @retval interface status (MANDATORY: return 0 -> no Error)
559 *
560 */
h3lis331dl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)561 int32_t h3lis331dl_flag_data_ready_get(const stmdev_ctx_t *ctx,
562 uint8_t *val)
563 {
564 h3lis331dl_status_reg_t status_reg;
565 int32_t ret;
566
567 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_STATUS_REG,
568 (uint8_t *)&status_reg, 1);
569 *val = status_reg.zyxda;
570
571 return ret;
572 }
573
574 /**
575 * @}
576 *
577 */
578
579 /**
580 * @defgroup H3LIS331DL_Data_Output
581 * @brief This section groups all the data output functions.
582 * @{
583 *
584 */
585
586 /**
587 * @brief Linear acceleration output register. The value is expressed
588 * as a 16-bit word in two’s complement.[get]
589 *
590 * @param ctx read / write interface definitions(ptr)
591 * @param buff buffer that stores data read
592 * @retval interface status (MANDATORY: return 0 -> no Error)
593 *
594 */
h3lis331dl_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)595 int32_t h3lis331dl_acceleration_raw_get(const stmdev_ctx_t *ctx,
596 int16_t *val)
597 {
598 uint8_t buff[6];
599 int32_t ret;
600
601 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_OUT_X_L, buff, 6);
602 val[0] = (int16_t)buff[1];
603 val[0] = (val[0] * 256) + (int16_t)buff[0];
604 val[1] = (int16_t)buff[3];
605 val[1] = (val[1] * 256) + (int16_t)buff[2];
606 val[2] = (int16_t)buff[5];
607 val[2] = (val[2] * 256) + (int16_t)buff[4];
608
609 return ret;
610 }
611
612 /**
613 * @}
614 *
615 */
616
617 /**
618 * @defgroup H3LIS331DL_Common
619 * @brief This section groups common useful functions.
620 * @{
621 *
622 */
623
624 /**
625 * @brief Device Who am I.[get]
626 *
627 * @param ctx read / write interface definitions(ptr)
628 * @param buff buffer that stores data read
629 * @retval interface status (MANDATORY: return 0 -> no Error)
630 *
631 */
h3lis331dl_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)632 int32_t h3lis331dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
633 {
634 int32_t ret;
635
636 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_WHO_AM_I, buff, 1);
637
638 return ret;
639 }
640
641 /**
642 * @brief Reboot memory content. Reload the calibration parameters.[set]
643 *
644 * @param ctx read / write interface definitions(ptr)
645 * @param val change the values of boot in reg CTRL_REG2
646 * @retval interface status (MANDATORY: return 0 -> no Error)
647 *
648 */
h3lis331dl_boot_set(const stmdev_ctx_t * ctx,uint8_t val)649 int32_t h3lis331dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
650 {
651 h3lis331dl_ctrl_reg2_t ctrl_reg2;
652 int32_t ret;
653
654 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
655 (uint8_t *)&ctrl_reg2, 1);
656
657 if (ret == 0)
658 {
659 ctrl_reg2.boot = val;
660 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
661 (uint8_t *)&ctrl_reg2, 1);
662 }
663
664 return ret;
665 }
666
667 /**
668 * @brief Reboot memory content. Reload the calibration parameters.[get]
669 *
670 * @param ctx read / write interface definitions(ptr)
671 * @param val change the values of boot in reg CTRL_REG2
672 * @retval interface status (MANDATORY: return 0 -> no Error)
673 *
674 */
h3lis331dl_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)675 int32_t h3lis331dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
676 {
677 h3lis331dl_ctrl_reg2_t ctrl_reg2;
678 int32_t ret;
679
680 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
681 (uint8_t *)&ctrl_reg2, 1);
682 *val = ctrl_reg2.boot;
683
684 return ret;
685 }
686
687 /**
688 * @brief Big/Little Endian Data selection.[set]
689 *
690 * @param ctx read / write interface definitions(ptr)
691 * @param val change the values of ble in reg CTRL_REG4
692 * @retval interface status (MANDATORY: return 0 -> no Error)
693 *
694 */
h3lis331dl_data_format_set(const stmdev_ctx_t * ctx,h3lis331dl_ble_t val)695 int32_t h3lis331dl_data_format_set(const stmdev_ctx_t *ctx,
696 h3lis331dl_ble_t val)
697 {
698 h3lis331dl_ctrl_reg4_t ctrl_reg4;
699 int32_t ret;
700
701 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
702 (uint8_t *)&ctrl_reg4, 1);
703
704 if (ret == 0)
705 {
706 ctrl_reg4.ble = (uint8_t)val;
707 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
708 (uint8_t *)&ctrl_reg4, 1);
709 }
710
711 return ret;
712 }
713
714 /**
715 * @brief Big/Little Endian Data selection.[get]
716 *
717 * @param ctx read / write interface definitions(ptr)
718 * @param val Get the values of ble in reg CTRL_REG4
719 * @retval interface status (MANDATORY: return 0 -> no Error)
720 *
721 */
h3lis331dl_data_format_get(const stmdev_ctx_t * ctx,h3lis331dl_ble_t * val)722 int32_t h3lis331dl_data_format_get(const stmdev_ctx_t *ctx,
723 h3lis331dl_ble_t *val)
724 {
725 h3lis331dl_ctrl_reg4_t ctrl_reg4;
726 int32_t ret;
727
728 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
729 (uint8_t *)&ctrl_reg4, 1);
730
731 switch (ctrl_reg4.ble)
732 {
733 case H3LIS331DL_LSB_AT_LOW_ADD:
734 *val = H3LIS331DL_LSB_AT_LOW_ADD;
735 break;
736
737 case H3LIS331DL_MSB_AT_LOW_ADD:
738 *val = H3LIS331DL_MSB_AT_LOW_ADD;
739 break;
740
741 default:
742 *val = H3LIS331DL_LSB_AT_LOW_ADD;
743 break;
744 }
745
746 return ret;
747 }
748
749 /**
750 * @}
751 *
752 */
753
754 /**
755 * @defgroup H3LIS331DL_Filters
756 * @brief This section group all the functions concerning the
757 * filters configuration.
758 * @{
759 *
760 */
761
762 /**
763 * @brief High pass filter cut-off frequency configuration.[set]
764 *
765 * @param ctx read / write interface definitions(ptr)
766 * @param val change the values of hpcf in reg CTRL_REG2
767 * @retval interface status (MANDATORY: return 0 -> no Error)
768 *
769 */
h3lis331dl_hp_bandwidth_set(const stmdev_ctx_t * ctx,h3lis331dl_hpcf_t val)770 int32_t h3lis331dl_hp_bandwidth_set(const stmdev_ctx_t *ctx,
771 h3lis331dl_hpcf_t val)
772 {
773 h3lis331dl_ctrl_reg2_t ctrl_reg2;
774 int32_t ret;
775
776 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
777 (uint8_t *)&ctrl_reg2, 1);
778
779 if (ret == 0)
780 {
781 ctrl_reg2.hpcf = (uint8_t)val;
782 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
783 (uint8_t *)&ctrl_reg2, 1);
784 }
785
786 return ret;
787 }
788
789 /**
790 * @brief High pass filter cut-off frequency configuration.[get]
791 *
792 * @param ctx read / write interface definitions(ptr)
793 * @param val Get the values of hpcf in reg CTRL_REG2
794 * @retval interface status (MANDATORY: return 0 -> no Error)
795 *
796 */
h3lis331dl_hp_bandwidth_get(const stmdev_ctx_t * ctx,h3lis331dl_hpcf_t * val)797 int32_t h3lis331dl_hp_bandwidth_get(const stmdev_ctx_t *ctx,
798 h3lis331dl_hpcf_t *val)
799 {
800 h3lis331dl_ctrl_reg2_t ctrl_reg2;
801 int32_t ret;
802
803 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
804 (uint8_t *)&ctrl_reg2, 1);
805
806 switch (ctrl_reg2.hpcf)
807 {
808 case H3LIS331DL_CUT_OFF_8Hz:
809 *val = H3LIS331DL_CUT_OFF_8Hz;
810 break;
811
812 case H3LIS331DL_CUT_OFF_16Hz:
813 *val = H3LIS331DL_CUT_OFF_16Hz;
814 break;
815
816 case H3LIS331DL_CUT_OFF_32Hz:
817 *val = H3LIS331DL_CUT_OFF_32Hz;
818 break;
819
820 case H3LIS331DL_CUT_OFF_64Hz:
821 *val = H3LIS331DL_CUT_OFF_64Hz;
822 break;
823
824 default:
825 *val = H3LIS331DL_CUT_OFF_8Hz;
826 break;
827 }
828
829 return ret;
830 }
831
832 /**
833 * @brief Select High Pass filter path.[set]
834 *
835 * @param ctx read / write interface definitions(ptr)
836 * @param val change the values of hpen in reg CTRL_REG2
837 * @retval interface status (MANDATORY: return 0 -> no Error)
838 *
839 */
h3lis331dl_hp_path_set(const stmdev_ctx_t * ctx,h3lis331dl_hpen_t val)840 int32_t h3lis331dl_hp_path_set(const stmdev_ctx_t *ctx,
841 h3lis331dl_hpen_t val)
842 {
843 h3lis331dl_ctrl_reg2_t ctrl_reg2;
844 int32_t ret;
845
846 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
847 (uint8_t *)&ctrl_reg2, 1);
848
849 if (ret == 0)
850 {
851 ctrl_reg2.hpen = (uint8_t)val & 0x03U;
852 ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
853 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG2,
854 (uint8_t *)&ctrl_reg2, 1);
855 }
856
857 return ret;
858 }
859
860 /**
861 * @brief Select High Pass filter path.[get]
862 *
863 * @param ctx read / write interface definitions(ptr)
864 * @param val Get the values of hpen in reg CTRL_REG2
865 * @retval interface status (MANDATORY: return 0 -> no Error)
866 *
867 */
h3lis331dl_hp_path_get(const stmdev_ctx_t * ctx,h3lis331dl_hpen_t * val)868 int32_t h3lis331dl_hp_path_get(const stmdev_ctx_t *ctx,
869 h3lis331dl_hpen_t *val)
870 {
871 h3lis331dl_ctrl_reg2_t ctrl_reg2;
872 int32_t ret;
873
874 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG2,
875 (uint8_t *)&ctrl_reg2, 1);
876
877 switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
878 {
879 case H3LIS331DL_HP_DISABLE:
880 *val = H3LIS331DL_HP_DISABLE;
881 break;
882
883 case H3LIS331DL_HP_ON_OUT:
884 *val = H3LIS331DL_HP_ON_OUT;
885 break;
886
887 case H3LIS331DL_HP_ON_INT1:
888 *val = H3LIS331DL_HP_ON_INT1;
889 break;
890
891 case H3LIS331DL_HP_ON_INT2:
892 *val = H3LIS331DL_HP_ON_INT2;
893 break;
894
895 case H3LIS331DL_HP_ON_INT1_INT2:
896 *val = H3LIS331DL_HP_ON_INT1_INT2;
897 break;
898
899 case H3LIS331DL_HP_ON_INT1_INT2_OUT:
900 *val = H3LIS331DL_HP_ON_INT1_INT2_OUT;
901 break;
902
903 case H3LIS331DL_HP_ON_INT2_OUT:
904 *val = H3LIS331DL_HP_ON_INT2_OUT;
905 break;
906
907 case H3LIS331DL_HP_ON_INT1_OUT:
908 *val = H3LIS331DL_HP_ON_INT1_OUT;
909 break;
910
911 default:
912 *val = H3LIS331DL_HP_DISABLE;
913 break;
914 }
915
916 return ret;
917 }
918
919 /**
920 * @brief Reading at this address zeroes instantaneously
921 * the content of the internal high pass-filter.
922 * If the high pass filter is enabled all three axes
923 * are instantaneously set to 0g. This allows to
924 * overcome the settling time of the high pass
925 * filter.[get]
926 *
927 * @param ctx read / write interface definitions(ptr)
928 * @retval interface status (MANDATORY: return 0 -> no Error)
929 *
930 */
h3lis331dl_hp_reset_get(const stmdev_ctx_t * ctx)931 int32_t h3lis331dl_hp_reset_get(const stmdev_ctx_t *ctx)
932 {
933 uint8_t dummy;
934 int32_t ret;
935
936 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_HP_FILTER_RESET,
937 (uint8_t *)&dummy, 1);
938
939 return ret;
940 }
941
942 /**
943 * @brief Reference value for high-pass filter.[set]
944 *
945 * @param ctx read / write interface definitions(ptr)
946 * @param val change the values of ref in reg REFERENCE
947 * @retval interface status (MANDATORY: return 0 -> no Error)
948 *
949 */
h3lis331dl_hp_reference_value_set(const stmdev_ctx_t * ctx,uint8_t val)950 int32_t h3lis331dl_hp_reference_value_set(const stmdev_ctx_t *ctx,
951 uint8_t val)
952 {
953 int32_t ret;
954
955 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_REFERENCE, (uint8_t *)&val, 1);
956
957 return ret;
958 }
959
960 /**
961 * @brief Reference value for high-pass filter.[get]
962 *
963 * @param ctx read / write interface definitions(ptr)
964 * @param val change the values of ref in reg REFERENCE
965 * @retval interface status (MANDATORY: return 0 -> no Error)
966 *
967 */
h3lis331dl_hp_reference_value_get(const stmdev_ctx_t * ctx,uint8_t * val)968 int32_t h3lis331dl_hp_reference_value_get(const stmdev_ctx_t *ctx,
969 uint8_t *val)
970 {
971 int32_t ret;
972
973 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_REFERENCE, val, 1);
974
975 return ret;
976 }
977
978 /**
979 * @}
980 *
981 */
982
983 /**
984 * @defgroup H3LIS331DL_Serial_Interface
985 * @brief This section groups all the functions concerning serial
986 * interface management.
987 * @{
988 *
989 */
990
991 /**
992 * @brief SPI 3- or 4-wire interface.[set]
993 *
994 * @param ctx read / write interface definitions(ptr)
995 * @param val change the values of sim in reg CTRL_REG4
996 * @retval interface status (MANDATORY: return 0 -> no Error)
997 *
998 */
h3lis331dl_spi_mode_set(const stmdev_ctx_t * ctx,h3lis331dl_sim_t val)999 int32_t h3lis331dl_spi_mode_set(const stmdev_ctx_t *ctx,
1000 h3lis331dl_sim_t val)
1001 {
1002 h3lis331dl_ctrl_reg4_t ctrl_reg4;
1003 int32_t ret;
1004
1005 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
1006 (uint8_t *)&ctrl_reg4, 1);
1007
1008 if (ret == 0)
1009 {
1010 ctrl_reg4.sim = (uint8_t)val;
1011 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG4,
1012 (uint8_t *)&ctrl_reg4, 1);
1013 }
1014
1015 return ret;
1016 }
1017
1018 /**
1019 * @brief SPI 3- or 4-wire interface.[get]
1020 *
1021 * @param ctx read / write interface definitions(ptr)
1022 * @param val Get the values of sim in reg CTRL_REG4
1023 * @retval interface status (MANDATORY: return 0 -> no Error)
1024 *
1025 */
h3lis331dl_spi_mode_get(const stmdev_ctx_t * ctx,h3lis331dl_sim_t * val)1026 int32_t h3lis331dl_spi_mode_get(const stmdev_ctx_t *ctx,
1027 h3lis331dl_sim_t *val)
1028 {
1029 h3lis331dl_ctrl_reg4_t ctrl_reg4;
1030 int32_t ret;
1031
1032 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG4,
1033 (uint8_t *)&ctrl_reg4, 1);
1034
1035 switch (ctrl_reg4.sim)
1036 {
1037 case H3LIS331DL_SPI_4_WIRE:
1038 *val = H3LIS331DL_SPI_4_WIRE;
1039 break;
1040
1041 case H3LIS331DL_SPI_3_WIRE:
1042 *val = H3LIS331DL_SPI_3_WIRE;
1043 break;
1044
1045 default:
1046 *val = H3LIS331DL_SPI_4_WIRE;
1047 break;
1048 }
1049
1050 return ret;
1051 }
1052
1053 /**
1054 * @}
1055 *
1056 */
1057
1058 /**
1059 * @defgroup H3LIS331DL_Interrupt_Pins
1060 * @brief This section groups all the functions that manage
1061 * interrupt pins.
1062 * @{
1063 *
1064 */
1065
1066 /**
1067 * @brief Data signal on INT 1 pad control bits.[set]
1068 *
1069 * @param ctx read / write interface definitions(ptr)
1070 * @param val change the values of i1_cfg in reg CTRL_REG3
1071 * @retval interface status (MANDATORY: return 0 -> no Error)
1072 *
1073 */
h3lis331dl_pin_int1_route_set(const stmdev_ctx_t * ctx,h3lis331dl_i1_cfg_t val)1074 int32_t h3lis331dl_pin_int1_route_set(const stmdev_ctx_t *ctx,
1075 h3lis331dl_i1_cfg_t val)
1076 {
1077 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1078 int32_t ret;
1079
1080 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1081 (uint8_t *)&ctrl_reg3, 1);
1082
1083 if (ret == 0)
1084 {
1085 ctrl_reg3.i1_cfg = (uint8_t)val;
1086 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
1087 (uint8_t *)&ctrl_reg3, 1);
1088 }
1089
1090 return ret;
1091 }
1092
1093 /**
1094 * @brief Data signal on INT 1 pad control bits.[get]
1095 *
1096 * @param ctx read / write interface definitions(ptr)
1097 * @param val Get the values of i1_cfg in reg CTRL_REG3
1098 * @retval interface status (MANDATORY: return 0 -> no Error)
1099 *
1100 */
h3lis331dl_pin_int1_route_get(const stmdev_ctx_t * ctx,h3lis331dl_i1_cfg_t * val)1101 int32_t h3lis331dl_pin_int1_route_get(const stmdev_ctx_t *ctx,
1102 h3lis331dl_i1_cfg_t *val)
1103 {
1104 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1105 int32_t ret;
1106
1107 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1108 (uint8_t *)&ctrl_reg3, 1);
1109
1110 switch (ctrl_reg3.i1_cfg)
1111 {
1112 case H3LIS331DL_PAD1_INT1_SRC:
1113 *val = H3LIS331DL_PAD1_INT1_SRC;
1114 break;
1115
1116 case H3LIS331DL_PAD1_INT1_OR_INT2_SRC:
1117 *val = H3LIS331DL_PAD1_INT1_OR_INT2_SRC;
1118 break;
1119
1120 case H3LIS331DL_PAD1_DRDY:
1121 *val = H3LIS331DL_PAD1_DRDY;
1122 break;
1123
1124 case H3LIS331DL_PAD1_BOOT:
1125 *val = H3LIS331DL_PAD1_BOOT;
1126 break;
1127
1128 default:
1129 *val = H3LIS331DL_PAD1_INT1_SRC;
1130 break;
1131 }
1132
1133 return ret;
1134 }
1135
1136 /**
1137 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1138 * register cleared by reading INT1_SRC register.[set]
1139 *
1140 * @param ctx read / write interface definitions(ptr)
1141 * @param val change the values of lir1 in reg CTRL_REG3
1142 * @retval interface status (MANDATORY: return 0 -> no Error)
1143 *
1144 */
h3lis331dl_int1_notification_set(const stmdev_ctx_t * ctx,h3lis331dl_lir1_t val)1145 int32_t h3lis331dl_int1_notification_set(const stmdev_ctx_t *ctx,
1146 h3lis331dl_lir1_t val)
1147 {
1148 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1149 int32_t ret;
1150
1151 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1152 (uint8_t *)&ctrl_reg3, 1);
1153
1154 if (ret == 0)
1155 {
1156 ctrl_reg3.lir1 = (uint8_t)val;
1157 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
1158 (uint8_t *)&ctrl_reg3, 1);
1159 }
1160
1161 return ret;
1162 }
1163
1164 /**
1165 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
1166 * register cleared by reading INT1_SRC register.[get]
1167 *
1168 * @param ctx read / write interface definitions(ptr)
1169 * @param val Get the values of lir1 in reg CTRL_REG3
1170 * @retval interface status (MANDATORY: return 0 -> no Error)
1171 *
1172 */
h3lis331dl_int1_notification_get(const stmdev_ctx_t * ctx,h3lis331dl_lir1_t * val)1173 int32_t h3lis331dl_int1_notification_get(const stmdev_ctx_t *ctx,
1174 h3lis331dl_lir1_t *val)
1175 {
1176 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1177 int32_t ret;
1178
1179 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1180 (uint8_t *)&ctrl_reg3, 1);
1181
1182 switch (ctrl_reg3.lir1)
1183 {
1184 case H3LIS331DL_INT1_PULSED:
1185 *val = H3LIS331DL_INT1_PULSED;
1186 break;
1187
1188 case H3LIS331DL_INT1_LATCHED:
1189 *val = H3LIS331DL_INT1_LATCHED;
1190 break;
1191
1192 default:
1193 *val = H3LIS331DL_INT1_PULSED;
1194 break;
1195 }
1196
1197 return ret;
1198 }
1199
1200 /**
1201 * @brief Data signal on INT 2 pad control bits.[set]
1202 *
1203 * @param ctx read / write interface definitions(ptr)
1204 * @param val change the values of i2_cfg in reg CTRL_REG3
1205 * @retval interface status (MANDATORY: return 0 -> no Error)
1206 *
1207 */
h3lis331dl_pin_int2_route_set(const stmdev_ctx_t * ctx,h3lis331dl_i2_cfg_t val)1208 int32_t h3lis331dl_pin_int2_route_set(const stmdev_ctx_t *ctx,
1209 h3lis331dl_i2_cfg_t val)
1210 {
1211 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1212 int32_t ret;
1213
1214 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1215 (uint8_t *)&ctrl_reg3, 1);
1216
1217 if (ret == 0)
1218 {
1219 ctrl_reg3.i2_cfg = (uint8_t)val;
1220 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
1221 (uint8_t *)&ctrl_reg3, 1);
1222 }
1223
1224 return ret;
1225 }
1226
1227 /**
1228 * @brief Data signal on INT 2 pad control bits.[get]
1229 *
1230 * @param ctx read / write interface definitions(ptr)
1231 * @param val Get the values of i2_cfg in reg CTRL_REG3
1232 * @retval interface status (MANDATORY: return 0 -> no Error)
1233 *
1234 */
h3lis331dl_pin_int2_route_get(const stmdev_ctx_t * ctx,h3lis331dl_i2_cfg_t * val)1235 int32_t h3lis331dl_pin_int2_route_get(const stmdev_ctx_t *ctx,
1236 h3lis331dl_i2_cfg_t *val)
1237 {
1238 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1239 int32_t ret;
1240
1241 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1242 (uint8_t *)&ctrl_reg3, 1);
1243
1244 switch (ctrl_reg3.i2_cfg)
1245 {
1246 case H3LIS331DL_PAD2_INT2_SRC:
1247 *val = H3LIS331DL_PAD2_INT2_SRC;
1248 break;
1249
1250 case H3LIS331DL_PAD2_INT1_OR_INT2_SRC:
1251 *val = H3LIS331DL_PAD2_INT1_OR_INT2_SRC;
1252 break;
1253
1254 case H3LIS331DL_PAD2_DRDY:
1255 *val = H3LIS331DL_PAD2_DRDY;
1256 break;
1257
1258 case H3LIS331DL_PAD2_BOOT:
1259 *val = H3LIS331DL_PAD2_BOOT;
1260 break;
1261
1262 default:
1263 *val = H3LIS331DL_PAD2_INT2_SRC;
1264 break;
1265 }
1266
1267 return ret;
1268 }
1269
1270 /**
1271 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1272 * register cleared by reading INT2_SRC itself.[set]
1273 *
1274 * @param ctx read / write interface definitions(ptr)
1275 * @param val change the values of lir2 in reg CTRL_REG3
1276 * @retval interface status (MANDATORY: return 0 -> no Error)
1277 *
1278 */
h3lis331dl_int2_notification_set(const stmdev_ctx_t * ctx,h3lis331dl_lir2_t val)1279 int32_t h3lis331dl_int2_notification_set(const stmdev_ctx_t *ctx,
1280 h3lis331dl_lir2_t val)
1281 {
1282 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1283 int32_t ret;
1284
1285 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1286 (uint8_t *)&ctrl_reg3, 1);
1287
1288 if (ret == 0)
1289 {
1290 ctrl_reg3.lir2 = (uint8_t)val;
1291 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
1292 (uint8_t *)&ctrl_reg3, 1);
1293 }
1294
1295 return ret;
1296 }
1297
1298 /**
1299 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1300 * register cleared by reading INT2_SRC itself.[get]
1301 *
1302 * @param ctx read / write interface definitions(ptr)
1303 * @param val Get the values of lir2 in reg CTRL_REG3
1304 * @retval interface status (MANDATORY: return 0 -> no Error)
1305 *
1306 */
h3lis331dl_int2_notification_get(const stmdev_ctx_t * ctx,h3lis331dl_lir2_t * val)1307 int32_t h3lis331dl_int2_notification_get(const stmdev_ctx_t *ctx,
1308 h3lis331dl_lir2_t *val)
1309 {
1310 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1311 int32_t ret;
1312
1313 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1314 (uint8_t *)&ctrl_reg3, 1);
1315
1316 switch (ctrl_reg3.lir2)
1317 {
1318 case H3LIS331DL_INT2_PULSED:
1319 *val = H3LIS331DL_INT2_PULSED;
1320 break;
1321
1322 case H3LIS331DL_INT2_LATCHED:
1323 *val = H3LIS331DL_INT2_LATCHED;
1324 break;
1325
1326 default:
1327 *val = H3LIS331DL_INT2_PULSED;
1328 break;
1329 }
1330
1331 return ret;
1332 }
1333
1334 /**
1335 * @brief Push-pull/open drain selection on interrupt pads.[set]
1336 *
1337 * @param ctx read / write interface definitions(ptr)
1338 * @param val change the values of pp_od in reg CTRL_REG3
1339 * @retval interface status (MANDATORY: return 0 -> no Error)
1340 *
1341 */
h3lis331dl_pin_mode_set(const stmdev_ctx_t * ctx,h3lis331dl_pp_od_t val)1342 int32_t h3lis331dl_pin_mode_set(const stmdev_ctx_t *ctx,
1343 h3lis331dl_pp_od_t val)
1344 {
1345 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1346 int32_t ret;
1347
1348 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1349 (uint8_t *)&ctrl_reg3, 1);
1350
1351 if (ret == 0)
1352 {
1353 ctrl_reg3.pp_od = (uint8_t)val;
1354 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
1355 (uint8_t *)&ctrl_reg3, 1);
1356 }
1357
1358 return ret;
1359 }
1360
1361 /**
1362 * @brief Push-pull/open drain selection on interrupt pads.[get]
1363 *
1364 * @param ctx read / write interface definitions(ptr)
1365 * @param val Get the values of pp_od in reg CTRL_REG3
1366 * @retval interface status (MANDATORY: return 0 -> no Error)
1367 *
1368 */
h3lis331dl_pin_mode_get(const stmdev_ctx_t * ctx,h3lis331dl_pp_od_t * val)1369 int32_t h3lis331dl_pin_mode_get(const stmdev_ctx_t *ctx,
1370 h3lis331dl_pp_od_t *val)
1371 {
1372 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1373 int32_t ret;
1374
1375 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1376 (uint8_t *)&ctrl_reg3, 1);
1377
1378 switch (ctrl_reg3.pp_od)
1379 {
1380 case H3LIS331DL_PUSH_PULL:
1381 *val = H3LIS331DL_PUSH_PULL;
1382 break;
1383
1384 case H3LIS331DL_OPEN_DRAIN:
1385 *val = H3LIS331DL_OPEN_DRAIN;
1386 break;
1387
1388 default:
1389 *val = H3LIS331DL_PUSH_PULL;
1390 break;
1391 }
1392
1393 return ret;
1394 }
1395
1396 /**
1397 * @brief Interrupt active-high/low.[set]
1398 *
1399 * @param ctx read / write interface definitions(ptr)
1400 * @param val change the values of ihl in reg CTRL_REG3
1401 * @retval interface status (MANDATORY: return 0 -> no Error)
1402 *
1403 */
h3lis331dl_pin_polarity_set(const stmdev_ctx_t * ctx,h3lis331dl_ihl_t val)1404 int32_t h3lis331dl_pin_polarity_set(const stmdev_ctx_t *ctx,
1405 h3lis331dl_ihl_t val)
1406 {
1407 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1408 int32_t ret;
1409
1410 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1411 (uint8_t *)&ctrl_reg3, 1);
1412
1413 if (ret == 0)
1414 {
1415 ctrl_reg3.ihl = (uint8_t)val;
1416 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG3,
1417 (uint8_t *)&ctrl_reg3, 1);
1418 }
1419
1420 return ret;
1421 }
1422
1423 /**
1424 * @brief Interrupt active-high/low.[get]
1425 *
1426 * @param ctx read / write interface definitions(ptr)
1427 * @param val Get the values of ihl in reg CTRL_REG3
1428 * @retval interface status (MANDATORY: return 0 -> no Error)
1429 *
1430 */
h3lis331dl_pin_polarity_get(const stmdev_ctx_t * ctx,h3lis331dl_ihl_t * val)1431 int32_t h3lis331dl_pin_polarity_get(const stmdev_ctx_t *ctx,
1432 h3lis331dl_ihl_t *val)
1433 {
1434 h3lis331dl_ctrl_reg3_t ctrl_reg3;
1435 int32_t ret;
1436
1437 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG3,
1438 (uint8_t *)&ctrl_reg3, 1);
1439
1440 switch (ctrl_reg3.ihl)
1441 {
1442 case H3LIS331DL_ACTIVE_HIGH:
1443 *val = H3LIS331DL_ACTIVE_HIGH;
1444 break;
1445
1446 case H3LIS331DL_ACTIVE_LOW:
1447 *val = H3LIS331DL_ACTIVE_LOW;
1448 break;
1449
1450 default:
1451 *val = H3LIS331DL_ACTIVE_HIGH;
1452 break;
1453 }
1454
1455 return ret;
1456 }
1457
1458 /**
1459 * @}
1460 *
1461 */
1462
1463 /**
1464 * @defgroup H3LIS331DL_interrupt_on_threshold
1465 * @brief This section groups all the functions that manage
1466 * the interrupt on threshold event generation.
1467 * @{
1468 *
1469 */
1470
1471 /**
1472 * @brief Configure the interrupt 1 threshold sign.[set]
1473 *
1474 * @param ctx read / write interface definitions(ptr)
1475 * @param val enable sign and axis for interrupt on threshold
1476 * @retval interface status (MANDATORY: return 0 -> no Error)
1477 *
1478 */
h3lis331dl_int1_on_threshold_conf_set(const stmdev_ctx_t * ctx,h3lis331dl_int1_on_th_conf_t val)1479 int32_t h3lis331dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1480 h3lis331dl_int1_on_th_conf_t val)
1481 {
1482 h3lis331dl_int1_cfg_t int1_cfg;
1483 int32_t ret;
1484
1485 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
1486 (uint8_t *)&int1_cfg, 1);
1487
1488 if (ret == 0)
1489 {
1490 int1_cfg.xlie = val.int1_xlie;
1491 int1_cfg.xhie = val.int1_xhie;
1492 int1_cfg.ylie = val.int1_ylie;
1493 int1_cfg.yhie = val.int1_yhie;
1494 int1_cfg.zlie = val.int1_zlie;
1495 int1_cfg.zhie = val.int1_zhie;
1496 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_CFG,
1497 (uint8_t *)&int1_cfg, 1);
1498 }
1499
1500 return ret;
1501 }
1502
1503 /**
1504 * @brief Configure the interrupt 1 threshold sign.[get]
1505 *
1506 * @param ctx read / write interface definitions(ptr)
1507 * @param val enable sign and axis for interrupt on threshold
1508 * @retval interface status (MANDATORY: return 0 -> no Error)
1509 *
1510 */
h3lis331dl_int1_on_threshold_conf_get(const stmdev_ctx_t * ctx,h3lis331dl_int1_on_th_conf_t * val)1511 int32_t h3lis331dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1512 h3lis331dl_int1_on_th_conf_t *val)
1513 {
1514 h3lis331dl_int1_cfg_t int1_cfg;
1515 int32_t ret;
1516
1517 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
1518 (uint8_t *)&int1_cfg, 1);
1519 val->int1_xlie = int1_cfg.xlie;
1520 val->int1_xhie = int1_cfg.xhie;
1521 val->int1_ylie = int1_cfg.ylie;
1522 val->int1_yhie = int1_cfg.yhie;
1523 val->int1_zlie = int1_cfg.zlie;
1524 val->int1_zhie = int1_cfg.zhie;
1525
1526 return ret;
1527 }
1528
1529 /**
1530 * @brief AND/OR combination of Interrupt 1 events.[set]
1531 *
1532 * @param ctx read / write interface definitions(ptr)
1533 * @param val change the values of aoi in reg INT1_CFG
1534 * @retval interface status (MANDATORY: return 0 -> no Error)
1535 *
1536 */
h3lis331dl_int1_on_threshold_mode_set(const stmdev_ctx_t * ctx,h3lis331dl_int1_aoi_t val)1537 int32_t h3lis331dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1538 h3lis331dl_int1_aoi_t val)
1539 {
1540 h3lis331dl_int1_cfg_t int1_cfg;
1541 int32_t ret;
1542
1543 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
1544 (uint8_t *)&int1_cfg, 1);
1545
1546 if (ret == 0)
1547 {
1548 int1_cfg.aoi = (uint8_t) val;
1549 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_CFG,
1550 (uint8_t *)&int1_cfg, 1);
1551 }
1552
1553 return ret;
1554 }
1555
1556 /**
1557 * @brief AND/OR combination of Interrupt 1 events.[get]
1558 *
1559 * @param ctx read / write interface definitions(ptr)
1560 * @param val Get the values of aoi in reg INT1_CFG
1561 * @retval interface status (MANDATORY: return 0 -> no Error)
1562 *
1563 */
h3lis331dl_int1_on_threshold_mode_get(const stmdev_ctx_t * ctx,h3lis331dl_int1_aoi_t * val)1564 int32_t h3lis331dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1565 h3lis331dl_int1_aoi_t *val)
1566 {
1567 h3lis331dl_int1_cfg_t int1_cfg;
1568 int32_t ret;
1569
1570 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_CFG,
1571 (uint8_t *)&int1_cfg, 1);
1572
1573 switch (int1_cfg.aoi)
1574 {
1575 case H3LIS331DL_INT1_ON_THRESHOLD_OR:
1576 *val = H3LIS331DL_INT1_ON_THRESHOLD_OR;
1577 break;
1578
1579 case H3LIS331DL_INT1_ON_THRESHOLD_AND:
1580 *val = H3LIS331DL_INT1_ON_THRESHOLD_AND;
1581 break;
1582
1583 default:
1584 *val = H3LIS331DL_INT1_ON_THRESHOLD_OR;
1585 break;
1586 }
1587
1588 return ret;
1589 }
1590
1591 /**
1592 * @brief Interrupt generator 1 on threshold source register.[get]
1593 *
1594 * @param ctx read / write interface definitions(ptr)
1595 * @param val registers INT1_SRC
1596 * @retval interface status (MANDATORY: return 0 -> no Error)
1597 *
1598 */
h3lis331dl_int1_src_get(const stmdev_ctx_t * ctx,h3lis331dl_int1_src_t * val)1599 int32_t h3lis331dl_int1_src_get(const stmdev_ctx_t *ctx,
1600 h3lis331dl_int1_src_t *val)
1601 {
1602 int32_t ret;
1603
1604 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_SRC, (uint8_t *) val, 1);
1605
1606 return ret;
1607 }
1608
1609 /**
1610 * @brief Interrupt 1 threshold.[set]
1611 *
1612 * @param ctx read / write interface definitions(ptr)
1613 * @param val change the values of ths in reg INT1_THS
1614 * @retval interface status (MANDATORY: return 0 -> no Error)
1615 *
1616 */
h3lis331dl_int1_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1617 int32_t h3lis331dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1618 {
1619 h3lis331dl_int1_ths_t int1_ths;
1620 int32_t ret;
1621
1622 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_THS,
1623 (uint8_t *)&int1_ths, 1);
1624
1625 if (ret == 0)
1626 {
1627 int1_ths.ths = val;
1628 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_THS,
1629 (uint8_t *)&int1_ths, 1);
1630 }
1631
1632 return ret;
1633 }
1634
1635 /**
1636 * @brief Interrupt 1 threshold.[get]
1637 *
1638 * @param ctx read / write interface definitions(ptr)
1639 * @param val change the values of ths in reg INT1_THS
1640 * @retval interface status (MANDATORY: return 0 -> no Error)
1641 *
1642 */
h3lis331dl_int1_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1643 int32_t h3lis331dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1644 {
1645 h3lis331dl_int1_ths_t int1_ths;
1646 int32_t ret;
1647
1648 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_THS,
1649 (uint8_t *)&int1_ths, 1);
1650 *val = int1_ths.ths;
1651
1652 return ret;
1653 }
1654
1655 /**
1656 * @brief Duration value for interrupt 1 generator.[set]
1657 *
1658 * @param ctx read / write interface definitions(ptr)
1659 * @param val change the values of d in reg INT1_DURATION
1660 * @retval interface status (MANDATORY: return 0 -> no Error)
1661 *
1662 */
h3lis331dl_int1_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1663 int32_t h3lis331dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1664 {
1665 h3lis331dl_int1_duration_t int1_duration;
1666 int32_t ret;
1667
1668 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_DURATION,
1669 (uint8_t *)&int1_duration, 1);
1670
1671 if (ret == 0)
1672 {
1673 int1_duration.d = val;
1674 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT1_DURATION,
1675 (uint8_t *)&int1_duration, 1);
1676 }
1677
1678 return ret;
1679 }
1680
1681 /**
1682 * @brief Duration value for interrupt 1 generator.[get]
1683 *
1684 * @param ctx read / write interface definitions(ptr)
1685 * @param val change the values of d in reg INT1_DURATION
1686 * @retval interface status (MANDATORY: return 0 -> no Error)
1687 *
1688 */
h3lis331dl_int1_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1689 int32_t h3lis331dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1690 {
1691 h3lis331dl_int1_duration_t int1_duration;
1692 int32_t ret;
1693
1694 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT1_DURATION,
1695 (uint8_t *)&int1_duration, 1);
1696 *val = int1_duration.d;
1697
1698 return ret;
1699 }
1700
1701 /**
1702 * @brief Configure the interrupt 2 threshold sign.[set]
1703 *
1704 * @param ctx read / write interface definitions(ptr)
1705 * @param val enable sign and axis for interrupt on threshold
1706 * @retval interface status (MANDATORY: return 0 -> no Error)
1707 *
1708 */
h3lis331dl_int2_on_threshold_conf_set(const stmdev_ctx_t * ctx,h3lis331dl_int2_on_th_conf_t val)1709 int32_t h3lis331dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1710 h3lis331dl_int2_on_th_conf_t val)
1711 {
1712 h3lis331dl_int2_cfg_t int2_cfg;
1713 int32_t ret;
1714
1715 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
1716 (uint8_t *)&int2_cfg, 1);
1717
1718 if (ret == 0)
1719 {
1720 int2_cfg.xlie = val.int2_xlie;
1721 int2_cfg.xhie = val.int2_xhie;
1722 int2_cfg.ylie = val.int2_ylie;
1723 int2_cfg.yhie = val.int2_yhie;
1724 int2_cfg.zlie = val.int2_zlie;
1725 int2_cfg.zhie = val.int2_zhie;
1726 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_CFG,
1727 (uint8_t *)&int2_cfg, 1);
1728 }
1729
1730 return ret;
1731 }
1732
1733 /**
1734 * @brief Configure the interrupt 2 threshold sign.[get]
1735 *
1736 * @param ctx read / write interface definitions(ptr)
1737 * @param val enable sign and axis for interrupt on threshold
1738 * @retval interface status (MANDATORY: return 0 -> no Error)
1739 *
1740 */
h3lis331dl_int2_on_threshold_conf_get(const stmdev_ctx_t * ctx,h3lis331dl_int2_on_th_conf_t * val)1741 int32_t h3lis331dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1742 h3lis331dl_int2_on_th_conf_t *val)
1743 {
1744 h3lis331dl_int2_cfg_t int2_cfg;
1745 int32_t ret;
1746
1747 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
1748 (uint8_t *)&int2_cfg, 1);
1749 val->int2_xlie = int2_cfg.xlie;
1750 val->int2_xhie = int2_cfg.xhie;
1751 val->int2_ylie = int2_cfg.ylie;
1752 val->int2_yhie = int2_cfg.yhie;
1753 val->int2_zlie = int2_cfg.zlie;
1754 val->int2_zhie = int2_cfg.zhie;
1755
1756 return ret;
1757 }
1758
1759 /**
1760 * @brief AND/OR combination of Interrupt 2 events.[set]
1761 *
1762 * @param ctx read / write interface definitions(ptr)
1763 * @param val change the values of aoi in reg INT2_CFG
1764 * @retval interface status (MANDATORY: return 0 -> no Error)
1765 *
1766 */
h3lis331dl_int2_on_threshold_mode_set(const stmdev_ctx_t * ctx,h3lis331dl_int2_aoi_t val)1767 int32_t h3lis331dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1768 h3lis331dl_int2_aoi_t val)
1769 {
1770 h3lis331dl_int2_cfg_t int2_cfg;
1771 int32_t ret;
1772
1773 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
1774 (uint8_t *)&int2_cfg, 1);
1775
1776 if (ret == 0)
1777 {
1778 int2_cfg.aoi = (uint8_t) val;
1779 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_CFG,
1780 (uint8_t *)&int2_cfg, 1);
1781 }
1782
1783 return ret;
1784 }
1785
1786 /**
1787 * @brief AND/OR combination of Interrupt 2 events.[get]
1788 *
1789 * @param ctx read / write interface definitions(ptr)
1790 * @param val Get the values of aoi in reg INT2_CFG
1791 * @retval interface status (MANDATORY: return 0 -> no Error)
1792 *
1793 */
h3lis331dl_int2_on_threshold_mode_get(const stmdev_ctx_t * ctx,h3lis331dl_int2_aoi_t * val)1794 int32_t h3lis331dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1795 h3lis331dl_int2_aoi_t *val)
1796 {
1797 h3lis331dl_int2_cfg_t int2_cfg;
1798 int32_t ret;
1799
1800 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_CFG,
1801 (uint8_t *)&int2_cfg, 1);
1802
1803 switch (int2_cfg.aoi)
1804 {
1805 case H3LIS331DL_INT2_ON_THRESHOLD_OR:
1806 *val = H3LIS331DL_INT2_ON_THRESHOLD_OR;
1807 break;
1808
1809 case H3LIS331DL_INT2_ON_THRESHOLD_AND:
1810 *val = H3LIS331DL_INT2_ON_THRESHOLD_AND;
1811 break;
1812
1813 default:
1814 *val = H3LIS331DL_INT2_ON_THRESHOLD_OR;
1815 break;
1816 }
1817
1818 return ret;
1819 }
1820
1821 /**
1822 * @brief Interrupt generator 2 on threshold source register.[get]
1823 *
1824 * @param ctx read / write interface definitions(ptr)
1825 * @param val registers INT2_SRC
1826 * @retval interface status (MANDATORY: return 0 -> no Error)
1827 *
1828 */
h3lis331dl_int2_src_get(const stmdev_ctx_t * ctx,h3lis331dl_int2_src_t * val)1829 int32_t h3lis331dl_int2_src_get(const stmdev_ctx_t *ctx,
1830 h3lis331dl_int2_src_t *val)
1831 {
1832 int32_t ret;
1833
1834 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_SRC, (uint8_t *) val, 1);
1835
1836 return ret;
1837 }
1838
1839 /**
1840 * @brief Interrupt 2 threshold.[set]
1841 *
1842 * @param ctx read / write interface definitions(ptr)
1843 * @param val change the values of ths in reg INT2_THS
1844 * @retval interface status (MANDATORY: return 0 -> no Error)
1845 *
1846 */
h3lis331dl_int2_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1847 int32_t h3lis331dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1848 {
1849 h3lis331dl_int2_ths_t int2_ths;
1850 int32_t ret;
1851
1852 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_THS,
1853 (uint8_t *)&int2_ths, 1);
1854
1855 if (ret == 0)
1856 {
1857 int2_ths.ths = val;
1858 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_THS,
1859 (uint8_t *)&int2_ths, 1);
1860 }
1861
1862 return ret;
1863 }
1864
1865 /**
1866 * @brief Interrupt 2 threshold.[get]
1867 *
1868 * @param ctx read / write interface definitions(ptr)
1869 * @param val change the values of ths in reg INT2_THS
1870 * @retval interface status (MANDATORY: return 0 -> no Error)
1871 *
1872 */
h3lis331dl_int2_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1873 int32_t h3lis331dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1874 {
1875 h3lis331dl_int2_ths_t int2_ths;
1876 int32_t ret;
1877
1878 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_THS,
1879 (uint8_t *)&int2_ths, 1);
1880 *val = int2_ths.ths;
1881
1882 return ret;
1883 }
1884
1885 /**
1886 * @brief Duration value for interrupt 2 generator.[set]
1887 *
1888 * @param ctx read / write interface definitions(ptr)
1889 * @param val change the values of d in reg INT2_DURATION
1890 * @retval interface status (MANDATORY: return 0 -> no Error)
1891 *
1892 */
h3lis331dl_int2_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1893 int32_t h3lis331dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1894 {
1895 h3lis331dl_int2_duration_t int2_duration;
1896 int32_t ret;
1897
1898 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_DURATION,
1899 (uint8_t *)&int2_duration, 1);
1900
1901 if (ret == 0)
1902 {
1903 int2_duration.d = val;
1904 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_INT2_DURATION,
1905 (uint8_t *)&int2_duration, 1);
1906 }
1907
1908 return ret;
1909 }
1910
1911 /**
1912 * @brief Duration value for interrupt 2 generator.[get]
1913 *
1914 * @param ctx read / write interface definitions(ptr)
1915 * @param val change the values of d in reg INT2_DURATION
1916 * @retval interface status (MANDATORY: return 0 -> no Error)
1917 *
1918 */
h3lis331dl_int2_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1919 int32_t h3lis331dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1920 {
1921 h3lis331dl_int2_duration_t int2_duration;
1922 int32_t ret;
1923
1924 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_INT2_DURATION,
1925 (uint8_t *)&int2_duration, 1);
1926 *val = int2_duration.d;
1927
1928 return ret;
1929 }
1930
1931 /**
1932 * @}
1933 *
1934 */
1935
1936 /**
1937 * @defgroup H3LIS331DL_Wake_Up_Event
1938 * @brief This section groups all the functions that manage the
1939 * Wake Up event generation.
1940 * @{
1941 *
1942 */
1943
1944 /**
1945 * @brief Turn-on mode selection for sleep to wake function.[set]
1946 *
1947 * @param ctx read / write interface definitions(ptr)
1948 * @param val change the values of turnon in reg CTRL_REG5
1949 * @retval interface status (MANDATORY: return 0 -> no Error)
1950 *
1951 */
h3lis331dl_wkup_to_sleep_set(const stmdev_ctx_t * ctx,uint8_t val)1952 int32_t h3lis331dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val)
1953 {
1954 h3lis331dl_ctrl_reg5_t ctrl_reg5;
1955 int32_t ret;
1956
1957 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG5,
1958 (uint8_t *)&ctrl_reg5, 1);
1959
1960 if (ret == 0)
1961 {
1962 ctrl_reg5.turnon = val;
1963 ret = h3lis331dl_write_reg(ctx, H3LIS331DL_CTRL_REG5,
1964 (uint8_t *)&ctrl_reg5, 1);
1965 }
1966
1967 return ret;
1968 }
1969
1970 /**
1971 * @brief Turn-on mode selection for sleep to wake function.[get]
1972 *
1973 * @param ctx read / write interface definitions(ptr)
1974 * @param val change the values of turnon in reg CTRL_REG5
1975 * @retval interface status (MANDATORY: return 0 -> no Error)
1976 *
1977 */
h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t * ctx,uint8_t * val)1978 int32_t h3lis331dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val)
1979 {
1980 h3lis331dl_ctrl_reg5_t ctrl_reg5;
1981 int32_t ret;
1982
1983 ret = h3lis331dl_read_reg(ctx, H3LIS331DL_CTRL_REG5,
1984 (uint8_t *)&ctrl_reg5, 1);
1985 *val = ctrl_reg5.turnon;
1986
1987 return ret;
1988 }
1989
1990 /**
1991 * @}
1992 *
1993 */
1994
1995 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1996
