1 /** 2 ****************************************************************************** 3 * @file h3lis100dl_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * h3lis100dl_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef H3LIS100DL_REGS_H 23 #define H3LIS100DL_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup H3LIS100DL 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 167 /** @defgroup H3LIS100DL_Infos 168 * @{ 169 * 170 */ 171 172 /** I2C Device Address 8 bit format if SA0=0 -> 0x31 if SA0=1 -> 0x33 **/ 173 #define H3LIS100DL_I2C_ADD_L 0x31U 174 #define H3LIS100DL_I2C_ADD_H 0x33U 175 176 /** Device Identification (Who am I) **/ 177 #define H3LIS100DL_ID 0x32U 178 179 /** 180 * @} 181 * 182 */ 183 184 #define H3LIS100DL_WHO_AM_I 0x0FU 185 #define H3LIS100DL_CTRL_REG1 0x20U 186 typedef struct 187 { 188 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 189 uint8_t xen : 1; 190 uint8_t yen : 1; 191 uint8_t zen : 1; 192 uint8_t dr : 2; 193 uint8_t pm : 3; 194 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 195 uint8_t pm : 3; 196 uint8_t dr : 2; 197 uint8_t zen : 1; 198 uint8_t yen : 1; 199 uint8_t xen : 1; 200 #endif /* DRV_BYTE_ORDER */ 201 } h3lis100dl_ctrl_reg1_t; 202 203 #define H3LIS100DL_CTRL_REG2 0x21U 204 typedef struct 205 { 206 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 207 uint8_t hpcf : 2; 208 uint8_t hpen : 2; 209 uint8_t fds : 1; 210 uint8_t hpm : 2; 211 uint8_t boot : 1; 212 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 213 uint8_t boot : 1; 214 uint8_t hpm : 2; 215 uint8_t fds : 1; 216 uint8_t hpen : 2; 217 uint8_t hpcf : 2; 218 #endif /* DRV_BYTE_ORDER */ 219 } h3lis100dl_ctrl_reg2_t; 220 221 #define H3LIS100DL_CTRL_REG3 0x22U 222 typedef struct 223 { 224 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 225 uint8_t i1_cfg : 2; 226 uint8_t lir1 : 1; 227 uint8_t i2_cfg : 2; 228 uint8_t lir2 : 1; 229 uint8_t pp_od : 1; 230 uint8_t ihl : 1; 231 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 232 uint8_t ihl : 1; 233 uint8_t pp_od : 1; 234 uint8_t lir2 : 1; 235 uint8_t i2_cfg : 2; 236 uint8_t lir1 : 1; 237 uint8_t i1_cfg : 2; 238 #endif /* DRV_BYTE_ORDER */ 239 } h3lis100dl_ctrl_reg3_t; 240 241 #define H3LIS100DL_CTRL_REG4 0x23U 242 typedef struct 243 { 244 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 245 uint8_t sim : 1; 246 uint8_t not_used_01 : 6; 247 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 248 uint8_t not_used_01 : 6; 249 uint8_t sim : 1; 250 #endif /* DRV_BYTE_ORDER */ 251 } h3lis100dl_ctrl_reg4_t; 252 253 #define H3LIS100DL_CTRL_REG5 0x24U 254 typedef struct 255 { 256 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 257 uint8_t turnon : 2; 258 uint8_t not_used_01 : 6; 259 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 260 uint8_t not_used_01 : 6; 261 uint8_t turnon : 2; 262 #endif /* DRV_BYTE_ORDER */ 263 } h3lis100dl_ctrl_reg5_t; 264 265 #define H3LIS100DL_HP_FILTER_RESET 0x25U 266 #define H3LIS100DL_REFERENCE 0x26U 267 #define H3LIS100DL_STATUS_REG 0x27U 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t xda : 1; 272 uint8_t yda : 1; 273 uint8_t zda : 1; 274 uint8_t zyxda : 1; 275 uint8_t _xor : 1; 276 uint8_t yor : 1; 277 uint8_t zor : 1; 278 uint8_t zyxor : 1; 279 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 280 uint8_t zyxor : 1; 281 uint8_t zor : 1; 282 uint8_t yor : 1; 283 uint8_t _xor : 1; 284 uint8_t zyxda : 1; 285 uint8_t zda : 1; 286 uint8_t yda : 1; 287 uint8_t xda : 1; 288 #endif /* DRV_BYTE_ORDER */ 289 } h3lis100dl_status_reg_t; 290 291 #define H3LIS100DL_OUT_X 0x29U 292 #define H3LIS100DL_OUT_Y 0x2BU 293 #define H3LIS100DL_OUT_Z 0x2DU 294 #define H3LIS100DL_INT1_CFG 0x30U 295 typedef struct 296 { 297 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 298 uint8_t xlie : 1; 299 uint8_t xhie : 1; 300 uint8_t ylie : 1; 301 uint8_t yhie : 1; 302 uint8_t zlie : 1; 303 uint8_t zhie : 1; 304 uint8_t not_used_01 : 1; 305 uint8_t aoi : 1; 306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 307 uint8_t aoi : 1; 308 uint8_t not_used_01 : 1; 309 uint8_t zhie : 1; 310 uint8_t zlie : 1; 311 uint8_t yhie : 1; 312 uint8_t ylie : 1; 313 uint8_t xhie : 1; 314 uint8_t xlie : 1; 315 #endif /* DRV_BYTE_ORDER */ 316 } h3lis100dl_int1_cfg_t; 317 318 #define H3LIS100DL_INT1_SRC 0x31U 319 typedef struct 320 { 321 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 322 uint8_t xl : 1; 323 uint8_t xh : 1; 324 uint8_t yl : 1; 325 uint8_t yh : 1; 326 uint8_t zl : 1; 327 uint8_t zh : 1; 328 uint8_t ia : 1; 329 uint8_t not_used_01 : 1; 330 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 331 uint8_t not_used_01 : 1; 332 uint8_t ia : 1; 333 uint8_t zh : 1; 334 uint8_t zl : 1; 335 uint8_t yh : 1; 336 uint8_t yl : 1; 337 uint8_t xh : 1; 338 uint8_t xl : 1; 339 #endif /* DRV_BYTE_ORDER */ 340 } h3lis100dl_int1_src_t; 341 342 #define H3LIS100DL_INT1_THS 0x32U 343 typedef struct 344 { 345 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 346 uint8_t ths : 7; 347 uint8_t not_used_01 : 1; 348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 349 uint8_t not_used_01 : 1; 350 uint8_t ths : 7; 351 #endif /* DRV_BYTE_ORDER */ 352 } h3lis100dl_int1_ths_t; 353 354 #define H3LIS100DL_INT1_DURATION 0x33U 355 typedef struct 356 { 357 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 358 uint8_t d : 7; 359 uint8_t not_used_01 : 1; 360 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 361 uint8_t not_used_01 : 1; 362 uint8_t d : 7; 363 #endif /* DRV_BYTE_ORDER */ 364 } h3lis100dl_int1_duration_t; 365 366 #define H3LIS100DL_INT2_CFG 0x34U 367 typedef struct 368 { 369 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 370 uint8_t xlie : 1; 371 uint8_t xhie : 1; 372 uint8_t ylie : 1; 373 uint8_t yhie : 1; 374 uint8_t zlie : 1; 375 uint8_t zhie : 1; 376 uint8_t not_used_01 : 1; 377 uint8_t aoi : 1; 378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 379 uint8_t aoi : 1; 380 uint8_t not_used_01 : 1; 381 uint8_t zhie : 1; 382 uint8_t zlie : 1; 383 uint8_t yhie : 1; 384 uint8_t ylie : 1; 385 uint8_t xhie : 1; 386 uint8_t xlie : 1; 387 #endif /* DRV_BYTE_ORDER */ 388 } h3lis100dl_int2_cfg_t; 389 390 #define H3LIS100DL_INT2_SRC 0x35U 391 typedef struct 392 { 393 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 394 uint8_t xl : 1; 395 uint8_t xh : 1; 396 uint8_t yl : 1; 397 uint8_t yh : 1; 398 uint8_t zl : 1; 399 uint8_t zh : 1; 400 uint8_t ia : 1; 401 uint8_t not_used_01 : 1; 402 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 403 uint8_t not_used_01 : 1; 404 uint8_t ia : 1; 405 uint8_t zh : 1; 406 uint8_t zl : 1; 407 uint8_t yh : 1; 408 uint8_t yl : 1; 409 uint8_t xh : 1; 410 uint8_t xl : 1; 411 #endif /* DRV_BYTE_ORDER */ 412 } h3lis100dl_int2_src_t; 413 414 #define H3LIS100DL_INT2_THS 0x36U 415 typedef struct 416 { 417 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 418 uint8_t ths : 7; 419 uint8_t not_used_01 : 1; 420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 421 uint8_t not_used_01 : 1; 422 uint8_t ths : 7; 423 #endif /* DRV_BYTE_ORDER */ 424 } h3lis100dl_int2_ths_t; 425 426 #define H3LIS100DL_INT2_DURATION 0x37U 427 typedef struct 428 { 429 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 430 uint8_t d : 7; 431 uint8_t not_used_01 : 1; 432 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 433 uint8_t not_used_01 : 1; 434 uint8_t d : 7; 435 #endif /* DRV_BYTE_ORDER */ 436 } h3lis100dl_int2_duration_t; 437 438 /** 439 * @defgroup H3LIS100DL_Register_Union 440 * @brief This union group all the registers having a bit-field 441 * description. 442 * This union is useful but it's not needed by the driver. 443 * 444 * REMOVING this union you are compliant with: 445 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 446 * 447 * @{ 448 * 449 */ 450 typedef union 451 { 452 h3lis100dl_ctrl_reg1_t ctrl_reg1; 453 h3lis100dl_ctrl_reg2_t ctrl_reg2; 454 h3lis100dl_ctrl_reg3_t ctrl_reg3; 455 h3lis100dl_ctrl_reg4_t ctrl_reg4; 456 h3lis100dl_ctrl_reg5_t ctrl_reg5; 457 h3lis100dl_status_reg_t status_reg; 458 h3lis100dl_int1_cfg_t int1_cfg; 459 h3lis100dl_int1_src_t int1_src; 460 h3lis100dl_int1_ths_t int1_ths; 461 h3lis100dl_int1_duration_t int1_duration; 462 h3lis100dl_int2_cfg_t int2_cfg; 463 h3lis100dl_int2_src_t int2_src; 464 h3lis100dl_int2_ths_t int2_ths; 465 h3lis100dl_int2_duration_t int2_duration; 466 bitwise_t bitwise; 467 uint8_t byte; 468 } h3lis100dl_reg_t; 469 470 /** 471 * @} 472 * 473 */ 474 475 #ifndef __weak 476 #define __weak __attribute__((weak)) 477 #endif /* __weak */ 478 479 /* 480 * These are the basic platform dependent I/O routines to read 481 * and write device registers connected on a standard bus. 482 * The driver keeps offering a default implementation based on function 483 * pointers to read/write routines for backward compatibility. 484 * The __weak directive allows the final application to overwrite 485 * them with a custom implementation. 486 */ 487 488 int32_t h3lis100dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 489 uint8_t *data, 490 uint16_t len); 491 int32_t h3lis100dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 492 uint8_t *data, 493 uint16_t len); 494 495 float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb); 496 497 int32_t h3lis100dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val); 498 int32_t h3lis100dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 499 500 int32_t h3lis100dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val); 501 int32_t h3lis100dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 502 503 int32_t h3lis100dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val); 504 int32_t h3lis100dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val); 505 506 typedef enum 507 { 508 H3LIS100DL_ODR_OFF = 0x00, 509 H3LIS100DL_ODR_Hz5 = 0x02, 510 H3LIS100DL_ODR_1Hz = 0x03, 511 H3LIS100DL_ODR_2Hz = 0x04, 512 H3LIS100DL_ODR_5Hz = 0x05, 513 H3LIS100DL_ODR_10Hz = 0x06, 514 H3LIS100DL_ODR_50Hz = 0x01, 515 H3LIS100DL_ODR_100Hz = 0x11, 516 H3LIS100DL_ODR_400Hz = 0x21, 517 } h3lis100dl_dr_t; 518 int32_t h3lis100dl_data_rate_set(const stmdev_ctx_t *ctx, 519 h3lis100dl_dr_t val); 520 int32_t h3lis100dl_data_rate_get(const stmdev_ctx_t *ctx, 521 h3lis100dl_dr_t *val); 522 523 typedef enum 524 { 525 H3LIS100DL_NORMAL_MODE = 0, 526 H3LIS100DL_REF_MODE_ENABLE = 1, 527 } h3lis100dl_hpm_t; 528 int32_t h3lis100dl_reference_mode_set(const stmdev_ctx_t *ctx, 529 h3lis100dl_hpm_t val); 530 int32_t h3lis100dl_reference_mode_get(const stmdev_ctx_t *ctx, 531 h3lis100dl_hpm_t *val); 532 533 int32_t h3lis100dl_status_reg_get(const stmdev_ctx_t *ctx, 534 h3lis100dl_status_reg_t *val); 535 536 int32_t h3lis100dl_flag_data_ready_get(const stmdev_ctx_t *ctx, 537 uint8_t *val); 538 539 int32_t h3lis100dl_acceleration_raw_get(const stmdev_ctx_t *ctx, 540 int8_t *val); 541 542 int32_t h3lis100dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 543 544 int32_t h3lis100dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 545 int32_t h3lis100dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 546 547 typedef enum 548 { 549 H3LIS100DL_CUT_OFF_8Hz = 0, 550 H3LIS100DL_CUT_OFF_16Hz = 1, 551 H3LIS100DL_CUT_OFF_32Hz = 2, 552 H3LIS100DL_CUT_OFF_64Hz = 3, 553 } h3lis100dl_hpcf_t; 554 int32_t h3lis100dl_hp_bandwidth_set(const stmdev_ctx_t *ctx, 555 h3lis100dl_hpcf_t val); 556 int32_t h3lis100dl_hp_bandwidth_get(const stmdev_ctx_t *ctx, 557 h3lis100dl_hpcf_t *val); 558 559 typedef enum 560 { 561 H3LIS100DL_HP_DISABLE = 0, 562 H3LIS100DL_HP_ON_OUT = 4, 563 H3LIS100DL_HP_ON_INT1 = 1, 564 H3LIS100DL_HP_ON_INT2 = 2, 565 H3LIS100DL_HP_ON_INT1_INT2 = 3, 566 H3LIS100DL_HP_ON_INT1_INT2_OUT = 7, 567 H3LIS100DL_HP_ON_INT2_OUT = 6, 568 H3LIS100DL_HP_ON_INT1_OUT = 5, 569 } h3lis100dl_hpen_t; 570 int32_t h3lis100dl_hp_path_set(const stmdev_ctx_t *ctx, 571 h3lis100dl_hpen_t val); 572 int32_t h3lis100dl_hp_path_get(const stmdev_ctx_t *ctx, 573 h3lis100dl_hpen_t *val); 574 575 int32_t h3lis100dl_hp_reset_get(const stmdev_ctx_t *ctx); 576 577 int32_t h3lis100dl_hp_reference_value_set(const stmdev_ctx_t *ctx, 578 uint8_t val); 579 int32_t h3lis100dl_hp_reference_value_get(const stmdev_ctx_t *ctx, 580 uint8_t *val); 581 582 typedef enum 583 { 584 H3LIS100DL_SPI_4_WIRE = 0, 585 H3LIS100DL_SPI_3_WIRE = 1, 586 } h3lis100dl_sim_t; 587 int32_t h3lis100dl_spi_mode_set(const stmdev_ctx_t *ctx, 588 h3lis100dl_sim_t val); 589 int32_t h3lis100dl_spi_mode_get(const stmdev_ctx_t *ctx, 590 h3lis100dl_sim_t *val); 591 592 typedef enum 593 { 594 H3LIS100DL_PAD1_INT1_SRC = 0, 595 H3LIS100DL_PAD1_INT1_OR_INT2_SRC = 1, 596 H3LIS100DL_PAD1_DRDY = 2, 597 H3LIS100DL_PAD1_BOOT = 3, 598 } h3lis100dl_i1_cfg_t; 599 int32_t h3lis100dl_pin_int1_route_set(const stmdev_ctx_t *ctx, 600 h3lis100dl_i1_cfg_t val); 601 int32_t h3lis100dl_pin_int1_route_get(const stmdev_ctx_t *ctx, 602 h3lis100dl_i1_cfg_t *val); 603 604 typedef enum 605 { 606 H3LIS100DL_INT1_PULSED = 0, 607 H3LIS100DL_INT1_LATCHED = 1, 608 } h3lis100dl_lir1_t; 609 int32_t h3lis100dl_int1_notification_set(const stmdev_ctx_t *ctx, 610 h3lis100dl_lir1_t val); 611 int32_t h3lis100dl_int1_notification_get(const stmdev_ctx_t *ctx, 612 h3lis100dl_lir1_t *val); 613 614 typedef enum 615 { 616 H3LIS100DL_PAD2_INT2_SRC = 0, 617 H3LIS100DL_PAD2_INT1_OR_INT2_SRC = 1, 618 H3LIS100DL_PAD2_DRDY = 2, 619 H3LIS100DL_PAD2_BOOT = 3, 620 } h3lis100dl_i2_cfg_t; 621 int32_t h3lis100dl_pin_int2_route_set(const stmdev_ctx_t *ctx, 622 h3lis100dl_i2_cfg_t val); 623 int32_t h3lis100dl_pin_int2_route_get(const stmdev_ctx_t *ctx, 624 h3lis100dl_i2_cfg_t *val); 625 626 typedef enum 627 { 628 H3LIS100DL_INT2_PULSED = 0, 629 H3LIS100DL_INT2_LATCHED = 1, 630 } h3lis100dl_lir2_t; 631 int32_t h3lis100dl_int2_notification_set(const stmdev_ctx_t *ctx, 632 h3lis100dl_lir2_t val); 633 int32_t h3lis100dl_int2_notification_get(const stmdev_ctx_t *ctx, 634 h3lis100dl_lir2_t *val); 635 636 typedef enum 637 { 638 H3LIS100DL_PUSH_PULL = 0, 639 H3LIS100DL_OPEN_DRAIN = 1, 640 } h3lis100dl_pp_od_t; 641 int32_t h3lis100dl_pin_mode_set(const stmdev_ctx_t *ctx, 642 h3lis100dl_pp_od_t val); 643 int32_t h3lis100dl_pin_mode_get(const stmdev_ctx_t *ctx, 644 h3lis100dl_pp_od_t *val); 645 646 typedef enum 647 { 648 H3LIS100DL_ACTIVE_HIGH = 0, 649 H3LIS100DL_ACTIVE_LOW = 1, 650 } h3lis100dl_ihl_t; 651 int32_t h3lis100dl_pin_polarity_set(const stmdev_ctx_t *ctx, 652 h3lis100dl_ihl_t val); 653 int32_t h3lis100dl_pin_polarity_get(const stmdev_ctx_t *ctx, 654 h3lis100dl_ihl_t *val); 655 656 typedef struct 657 { 658 uint8_t int1_xlie : 1; 659 uint8_t int1_xhie : 1; 660 uint8_t int1_ylie : 1; 661 uint8_t int1_yhie : 1; 662 uint8_t int1_zlie : 1; 663 uint8_t int1_zhie : 1; 664 } int1_on_th_conf_t; 665 int32_t h3lis100dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx, 666 int1_on_th_conf_t val); 667 int32_t h3lis100dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx, 668 int1_on_th_conf_t *val); 669 670 typedef enum 671 { 672 H3LIS100DL_INT1_ON_THRESHOLD_OR = 0, 673 H3LIS100DL_INT1_ON_THRESHOLD_AND = 1, 674 } h3lis100dl_int1_aoi_t; 675 int32_t h3lis100dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx, 676 h3lis100dl_int1_aoi_t val); 677 int32_t h3lis100dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx, 678 h3lis100dl_int1_aoi_t *val); 679 680 int32_t h3lis100dl_int1_src_get(const stmdev_ctx_t *ctx, 681 h3lis100dl_int1_src_t *val); 682 683 int32_t h3lis100dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 684 int32_t h3lis100dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 685 686 int32_t h3lis100dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 687 int32_t h3lis100dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 688 689 typedef struct 690 { 691 uint8_t int2_xlie : 1; 692 uint8_t int2_xhie : 1; 693 uint8_t int2_ylie : 1; 694 uint8_t int2_yhie : 1; 695 uint8_t int2_zlie : 1; 696 uint8_t int2_zhie : 1; 697 } int2_on_th_conf_t; 698 int32_t h3lis100dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx, 699 int2_on_th_conf_t val); 700 int32_t h3lis100dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx, 701 int2_on_th_conf_t *val); 702 703 typedef enum 704 { 705 H3LIS100DL_INT2_ON_THRESHOLD_OR = 0, 706 H3LIS100DL_INT2_ON_THRESHOLD_AND = 1, 707 } h3lis100dl_int2_aoi_t; 708 int32_t h3lis100dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx, 709 h3lis100dl_int2_aoi_t val); 710 int32_t h3lis100dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx, 711 h3lis100dl_int2_aoi_t *val); 712 713 int32_t h3lis100dl_int2_src_get(const stmdev_ctx_t *ctx, 714 h3lis100dl_int2_src_t *val); 715 716 int32_t h3lis100dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 717 int32_t h3lis100dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 718 719 int32_t h3lis100dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 720 int32_t h3lis100dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 721 722 int32_t h3lis100dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val); 723 int32_t h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val); 724 725 /** 726 *@} 727 * 728 */ 729 730 #ifdef __cplusplus 731 } 732 #endif 733 734 #endif /* H3LIS100DL_REGS_H */ 735 736 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 737
