1 /**
2 ******************************************************************************
3 * @file h3lis100dl_reg.c
4 * @author Sensors Software Solution Team
5 * @brief H3LIS100DL driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "h3lis100dl_reg.h"
21
22 /**
23 * @defgroup H3LIS100DL
24 * @brief This file provides a set of functions needed to drive the
25 * h3lis100dl enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup H3LIS100DL_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
h3lis100dl_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak h3lis100dl_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL) return -1;
56
57 ret = ctx->read_reg(ctx->handle, reg, data, len);
58
59 return ret;
60 }
61
62 /**
63 * @brief Write generic device register
64 *
65 * @param ctx read / write interface definitions(ptr)
66 * @param reg register to write
67 * @param data pointer to data to write in register reg(ptr)
68 * @param len number of consecutive register to write
69 * @retval interface status (MANDATORY: return 0 -> no Error)
70 *
71 */
h3lis100dl_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)72 int32_t __weak h3lis100dl_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
73 uint8_t *data,
74 uint16_t len)
75 {
76 int32_t ret;
77
78 if (ctx == NULL) return -1;
79
80 ret = ctx->write_reg(ctx->handle, reg, data, len);
81
82 return ret;
83 }
84
85 /**
86 * @}
87 *
88 */
89
90 /**
91 * @defgroup H3LIS100DL_Sensitivity
92 * @brief These functions convert raw-data into engineering units.
93 * @{
94 *
95 */
96
h3lis100dl_from_fs100g_to_mg(int8_t lsb)97 float_t h3lis100dl_from_fs100g_to_mg(int8_t lsb)
98 {
99 return (float_t)lsb * 780.0f;
100 }
101
102 /**
103 * @}
104 *
105 */
106
107 /**
108 * @defgroup H3LIS100DL_Data_Generation
109 * @brief This section group all the functions concerning
110 * data generation
111 * @{
112 *
113 */
114
115 /**
116 * @brief X axis enable/disable.[set]
117 *
118 * @param ctx read / write interface definitions(ptr)
119 * @param val change the values of xen in reg CTRL_REG1
120 * @retval interface status (MANDATORY: return 0 -> no Error)
121 *
122 */
h3lis100dl_axis_x_data_set(const stmdev_ctx_t * ctx,uint8_t val)123 int32_t h3lis100dl_axis_x_data_set(const stmdev_ctx_t *ctx, uint8_t val)
124 {
125 h3lis100dl_ctrl_reg1_t ctrl_reg1;
126 int32_t ret;
127
128 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
129 (uint8_t *)&ctrl_reg1, 1);
130
131 if (ret == 0)
132 {
133 ctrl_reg1.xen = val;
134 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
135 (uint8_t *)&ctrl_reg1, 1);
136 }
137
138 return ret;
139 }
140
141 /**
142 * @brief X axis enable/disable.[get]
143 *
144 * @param ctx read / write interface definitions(ptr)
145 * @param val change the values of xen in reg CTRL_REG1
146 * @retval interface status (MANDATORY: return 0 -> no Error)
147 *
148 */
h3lis100dl_axis_x_data_get(const stmdev_ctx_t * ctx,uint8_t * val)149 int32_t h3lis100dl_axis_x_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
150 {
151 h3lis100dl_ctrl_reg1_t ctrl_reg1;
152 int32_t ret;
153
154 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
155 (uint8_t *)&ctrl_reg1, 1);
156 *val = ctrl_reg1.xen;
157
158 return ret;
159 }
160
161 /**
162 * @brief Y axis enable/disable.[set]
163 *
164 * @param ctx read / write interface definitions(ptr)
165 * @param val change the values of yen in reg CTRL_REG1
166 * @retval interface status (MANDATORY: return 0 -> no Error)
167 *
168 */
h3lis100dl_axis_y_data_set(const stmdev_ctx_t * ctx,uint8_t val)169 int32_t h3lis100dl_axis_y_data_set(const stmdev_ctx_t *ctx, uint8_t val)
170 {
171 h3lis100dl_ctrl_reg1_t ctrl_reg1;
172 int32_t ret;
173
174 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
175 (uint8_t *)&ctrl_reg1, 1);
176
177 if (ret == 0)
178 {
179 ctrl_reg1.yen = val;
180 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
181 (uint8_t *)&ctrl_reg1, 1);
182 }
183
184 return ret;
185 }
186
187 /**
188 * @brief Y axis enable/disable.[get]
189 *
190 * @param ctx read / write interface definitions(ptr)
191 * @param val change the values of yen in reg CTRL_REG1
192 * @retval interface status (MANDATORY: return 0 -> no Error)
193 *
194 */
h3lis100dl_axis_y_data_get(const stmdev_ctx_t * ctx,uint8_t * val)195 int32_t h3lis100dl_axis_y_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
196 {
197 h3lis100dl_ctrl_reg1_t ctrl_reg1;
198 int32_t ret;
199
200 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
201 (uint8_t *)&ctrl_reg1, 1);
202 *val = ctrl_reg1.yen;
203
204 return ret;
205 }
206
207 /**
208 * @brief Z axis enable/disable.[set]
209 *
210 * @param ctx read / write interface definitions(ptr)
211 * @param val change the values of zen in reg CTRL_REG1
212 * @retval interface status (MANDATORY: return 0 -> no Error)
213 *
214 */
h3lis100dl_axis_z_data_set(const stmdev_ctx_t * ctx,uint8_t val)215 int32_t h3lis100dl_axis_z_data_set(const stmdev_ctx_t *ctx, uint8_t val)
216 {
217 h3lis100dl_ctrl_reg1_t ctrl_reg1;
218 int32_t ret;
219
220 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
221 (uint8_t *)&ctrl_reg1, 1);
222
223 if (ret == 0)
224 {
225 ctrl_reg1.zen = val;
226 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
227 (uint8_t *)&ctrl_reg1, 1);
228 }
229
230 return ret;
231 }
232
233 /**
234 * @brief Z axis enable/disable.[get]
235 *
236 * @param ctx read / write interface definitions(ptr)
237 * @param val change the values of zen in reg CTRL_REG1
238 * @retval interface status (MANDATORY: return 0 -> no Error)
239 *
240 */
h3lis100dl_axis_z_data_get(const stmdev_ctx_t * ctx,uint8_t * val)241 int32_t h3lis100dl_axis_z_data_get(const stmdev_ctx_t *ctx, uint8_t *val)
242 {
243 h3lis100dl_ctrl_reg1_t ctrl_reg1;
244 int32_t ret;
245
246 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
247 (uint8_t *)&ctrl_reg1, 1);
248 *val = ctrl_reg1.zen;
249
250 return ret;
251 }
252
253 /**
254 * @brief Accelerometer data rate selection.[set]
255 *
256 * @param ctx read / write interface definitions(ptr)
257 * @param val change the values of dr in reg CTRL_REG1
258 * @retval interface status (MANDATORY: return 0 -> no Error)
259 *
260 */
h3lis100dl_data_rate_set(const stmdev_ctx_t * ctx,h3lis100dl_dr_t val)261 int32_t h3lis100dl_data_rate_set(const stmdev_ctx_t *ctx,
262 h3lis100dl_dr_t val)
263 {
264 h3lis100dl_ctrl_reg1_t ctrl_reg1;
265 int32_t ret;
266
267 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
268 (uint8_t *)&ctrl_reg1, 1);
269
270 if (ret == 0)
271 {
272 ctrl_reg1.pm = (uint8_t)val & 0x07U;
273 ctrl_reg1.dr = ((uint8_t)val & 0x30U) >> 4;
274 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG1,
275 (uint8_t *)&ctrl_reg1, 1);
276 }
277
278 return ret;
279 }
280
281 /**
282 * @brief Accelerometer data rate selection.[get]
283 *
284 * @param ctx read / write interface definitions(ptr)
285 * @param val Get the values of dr in reg CTRL_REG1
286 * @retval interface status (MANDATORY: return 0 -> no Error)
287 *
288 */
h3lis100dl_data_rate_get(const stmdev_ctx_t * ctx,h3lis100dl_dr_t * val)289 int32_t h3lis100dl_data_rate_get(const stmdev_ctx_t *ctx,
290 h3lis100dl_dr_t *val)
291 {
292 h3lis100dl_ctrl_reg1_t ctrl_reg1;
293 int32_t ret;
294
295 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG1,
296 (uint8_t *)&ctrl_reg1, 1);
297
298 switch ((ctrl_reg1.dr << 4) + ctrl_reg1.pm)
299 {
300 case H3LIS100DL_ODR_OFF:
301 *val = H3LIS100DL_ODR_OFF;
302 break;
303
304 case H3LIS100DL_ODR_Hz5:
305 *val = H3LIS100DL_ODR_Hz5;
306 break;
307
308 case H3LIS100DL_ODR_1Hz:
309 *val = H3LIS100DL_ODR_1Hz;
310 break;
311
312 case H3LIS100DL_ODR_2Hz:
313 *val = H3LIS100DL_ODR_2Hz;
314 break;
315
316 case H3LIS100DL_ODR_5Hz:
317 *val = H3LIS100DL_ODR_5Hz;
318 break;
319
320 case H3LIS100DL_ODR_10Hz:
321 *val = H3LIS100DL_ODR_10Hz;
322 break;
323
324 case H3LIS100DL_ODR_50Hz:
325 *val = H3LIS100DL_ODR_50Hz;
326 break;
327
328 case H3LIS100DL_ODR_100Hz:
329 *val = H3LIS100DL_ODR_100Hz;
330 break;
331
332 case H3LIS100DL_ODR_400Hz:
333 *val = H3LIS100DL_ODR_400Hz;
334 break;
335
336 default:
337 *val = H3LIS100DL_ODR_OFF;
338 break;
339 }
340
341 return ret;
342 }
343
344 /**
345 * @brief High pass filter mode selection.[set]
346 *
347 * @param ctx read / write interface definitions(ptr)
348 * @param val change the values of hpm in reg CTRL_REG2
349 * @retval interface status (MANDATORY: return 0 -> no Error)
350 *
351 */
h3lis100dl_reference_mode_set(const stmdev_ctx_t * ctx,h3lis100dl_hpm_t val)352 int32_t h3lis100dl_reference_mode_set(const stmdev_ctx_t *ctx,
353 h3lis100dl_hpm_t val)
354 {
355 h3lis100dl_ctrl_reg2_t ctrl_reg2;
356 int32_t ret;
357
358 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
359 (uint8_t *)&ctrl_reg2, 1);
360
361 if (ret == 0)
362 {
363 ctrl_reg2.hpm = (uint8_t)val;
364 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
365 (uint8_t *)&ctrl_reg2, 1);
366 }
367
368 return ret;
369 }
370
371 /**
372 * @brief High pass filter mode selection.[get]
373 *
374 * @param ctx read / write interface definitions(ptr)
375 * @param val Get the values of hpm in reg CTRL_REG2
376 * @retval interface status (MANDATORY: return 0 -> no Error)
377 *
378 */
h3lis100dl_reference_mode_get(const stmdev_ctx_t * ctx,h3lis100dl_hpm_t * val)379 int32_t h3lis100dl_reference_mode_get(const stmdev_ctx_t *ctx,
380 h3lis100dl_hpm_t *val)
381 {
382 h3lis100dl_ctrl_reg2_t ctrl_reg2;
383 int32_t ret;
384
385 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
386 (uint8_t *)&ctrl_reg2, 1);
387
388 switch (ctrl_reg2.hpm)
389 {
390 case H3LIS100DL_NORMAL_MODE:
391 *val = H3LIS100DL_NORMAL_MODE;
392 break;
393
394 case H3LIS100DL_REF_MODE_ENABLE:
395 *val = H3LIS100DL_REF_MODE_ENABLE;
396 break;
397
398 default:
399 *val = H3LIS100DL_NORMAL_MODE;
400 break;
401 }
402
403 return ret;
404 }
405
406 /**
407 * @brief The STATUS_REG register is read by the interface.[get]
408 *
409 * @param ctx read / write interface definitions(ptr)
410 * @param val registers STATUS_REG
411 * @retval interface status (MANDATORY: return 0 -> no Error)
412 *
413 */
h3lis100dl_status_reg_get(const stmdev_ctx_t * ctx,h3lis100dl_status_reg_t * val)414 int32_t h3lis100dl_status_reg_get(const stmdev_ctx_t *ctx,
415 h3lis100dl_status_reg_t *val)
416 {
417 int32_t ret;
418
419 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_STATUS_REG, (uint8_t *) val, 1);
420
421 return ret;
422 }
423
424 /**
425 * @brief Accelerometer new data available.[get]
426 *
427 * @param ctx read / write interface definitions(ptr)
428 * @param val change the values of zyxda in reg STATUS_REG
429 * @retval interface status (MANDATORY: return 0 -> no Error)
430 *
431 */
h3lis100dl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)432 int32_t h3lis100dl_flag_data_ready_get(const stmdev_ctx_t *ctx,
433 uint8_t *val)
434 {
435 h3lis100dl_status_reg_t status_reg;
436 int32_t ret;
437
438 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_STATUS_REG,
439 (uint8_t *)&status_reg, 1);
440 *val = status_reg.zyxda;
441
442 return ret;
443 }
444
445 /**
446 * @}
447 *
448 */
449
450 /**
451 * @defgroup H3LIS100DL_Data_Output
452 * @brief This section groups all the data output functions.
453 * @{
454 *
455 */
456
457 /**
458 * @brief Linear acceleration output register. The value is expressed
459 * as a 8-bit word in two's complement.[get]
460 *
461 * @param ctx read / write interface definitions(ptr)
462 * @param buff buffer that stores data read
463 * @retval interface status (MANDATORY: return 0 -> no Error)
464 *
465 */
h3lis100dl_acceleration_raw_get(const stmdev_ctx_t * ctx,int8_t * val)466 int32_t h3lis100dl_acceleration_raw_get(const stmdev_ctx_t *ctx,
467 int8_t *val)
468 {
469 int32_t ret;
470
471 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_X, (uint8_t *)&val[0], 1);
472 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Y, (uint8_t *)&val[1], 1);
473 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_OUT_Z, (uint8_t *)&val[2], 1);
474
475 return ret;
476 }
477
478 /**
479 * @}
480 *
481 */
482
483 /**
484 * @defgroup H3LIS100DL_Common
485 * @brief This section groups common useful functions.
486 * @{
487 *
488 */
489
490 /**
491 * @brief Device Who am I.[get]
492 *
493 * @param ctx read / write interface definitions(ptr)
494 * @param buff buffer that stores data read
495 * @retval interface status (MANDATORY: return 0 -> no Error)
496 *
497 */
h3lis100dl_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)498 int32_t h3lis100dl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
499 {
500 int32_t ret;
501
502 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_WHO_AM_I, buff, 1);
503
504 return ret;
505 }
506
507 /**
508 * @brief Reboot memory content. Reload the calibration parameters.[set]
509 *
510 * @param ctx read / write interface definitions(ptr)
511 * @param val change the values of boot in reg CTRL_REG2
512 * @retval interface status (MANDATORY: return 0 -> no Error)
513 *
514 */
h3lis100dl_boot_set(const stmdev_ctx_t * ctx,uint8_t val)515 int32_t h3lis100dl_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
516 {
517 h3lis100dl_ctrl_reg2_t ctrl_reg2;
518 int32_t ret;
519
520 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
521 (uint8_t *)&ctrl_reg2, 1);
522
523 if (ret == 0)
524 {
525 ctrl_reg2.boot = val;
526 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
527 (uint8_t *)&ctrl_reg2, 1);
528 }
529
530 return ret;
531 }
532
533 /**
534 * @brief Reboot memory content. Reload the calibration parameters.[get]
535 *
536 * @param ctx read / write interface definitions(ptr)
537 * @param val change the values of boot in reg CTRL_REG2
538 * @retval interface status (MANDATORY: return 0 -> no Error)
539 *
540 */
h3lis100dl_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)541 int32_t h3lis100dl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
542 {
543 h3lis100dl_ctrl_reg2_t ctrl_reg2;
544 int32_t ret;
545
546 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
547 (uint8_t *)&ctrl_reg2, 1);
548 *val = ctrl_reg2.boot;
549
550 return ret;
551 }
552
553 /**
554 * @}
555 *
556 */
557
558 /**
559 * @defgroup H3LIS100DL_Filters
560 * @brief This section group all the functions concerning the
561 * filters configuration.
562 * @{
563 *
564 */
565
566 /**
567 * @brief High pass filter cut-off frequency configuration.[set]
568 *
569 * @param ctx read / write interface definitions(ptr)
570 * @param val change the values of hpcf in reg CTRL_REG2
571 * @retval interface status (MANDATORY: return 0 -> no Error)
572 *
573 */
h3lis100dl_hp_bandwidth_set(const stmdev_ctx_t * ctx,h3lis100dl_hpcf_t val)574 int32_t h3lis100dl_hp_bandwidth_set(const stmdev_ctx_t *ctx,
575 h3lis100dl_hpcf_t val)
576 {
577 h3lis100dl_ctrl_reg2_t ctrl_reg2;
578 int32_t ret;
579
580 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
581 (uint8_t *)&ctrl_reg2, 1);
582
583 if (ret == 0)
584 {
585 ctrl_reg2.hpcf = (uint8_t)val;
586 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
587 (uint8_t *)&ctrl_reg2, 1);
588 }
589
590 return ret;
591 }
592
593 /**
594 * @brief High pass filter cut-off frequency configuration.[get]
595 *
596 * @param ctx read / write interface definitions(ptr)
597 * @param val Get the values of hpcf in reg CTRL_REG2
598 * @retval interface status (MANDATORY: return 0 -> no Error)
599 *
600 */
h3lis100dl_hp_bandwidth_get(const stmdev_ctx_t * ctx,h3lis100dl_hpcf_t * val)601 int32_t h3lis100dl_hp_bandwidth_get(const stmdev_ctx_t *ctx,
602 h3lis100dl_hpcf_t *val)
603 {
604 h3lis100dl_ctrl_reg2_t ctrl_reg2;
605 int32_t ret;
606
607 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
608 (uint8_t *)&ctrl_reg2, 1);
609
610 switch (ctrl_reg2.hpcf)
611 {
612 case H3LIS100DL_CUT_OFF_8Hz:
613 *val = H3LIS100DL_CUT_OFF_8Hz;
614 break;
615
616 case H3LIS100DL_CUT_OFF_16Hz:
617 *val = H3LIS100DL_CUT_OFF_16Hz;
618 break;
619
620 case H3LIS100DL_CUT_OFF_32Hz:
621 *val = H3LIS100DL_CUT_OFF_32Hz;
622 break;
623
624 case H3LIS100DL_CUT_OFF_64Hz:
625 *val = H3LIS100DL_CUT_OFF_64Hz;
626 break;
627
628 default:
629 *val = H3LIS100DL_CUT_OFF_8Hz;
630 break;
631 }
632
633 return ret;
634 }
635
636 /**
637 * @brief Select High Pass filter path.[set]
638 *
639 * @param ctx read / write interface definitions(ptr)
640 * @param val change the values of hpen in reg CTRL_REG2
641 * @retval interface status (MANDATORY: return 0 -> no Error)
642 *
643 */
h3lis100dl_hp_path_set(const stmdev_ctx_t * ctx,h3lis100dl_hpen_t val)644 int32_t h3lis100dl_hp_path_set(const stmdev_ctx_t *ctx,
645 h3lis100dl_hpen_t val)
646 {
647 h3lis100dl_ctrl_reg2_t ctrl_reg2;
648 int32_t ret;
649
650 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
651 (uint8_t *)&ctrl_reg2, 1);
652
653 if (ret == 0)
654 {
655 ctrl_reg2.hpen = (uint8_t)val & 0x03U;
656 ctrl_reg2.fds = ((uint8_t)val & 0x04U) >> 2;
657 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG2,
658 (uint8_t *)&ctrl_reg2, 1);
659 }
660
661 return ret;
662 }
663
664 /**
665 * @brief Select High Pass filter path.[get]
666 *
667 * @param ctx read / write interface definitions(ptr)
668 * @param val Get the values of hpen in reg CTRL_REG2
669 * @retval interface status (MANDATORY: return 0 -> no Error)
670 *
671 */
h3lis100dl_hp_path_get(const stmdev_ctx_t * ctx,h3lis100dl_hpen_t * val)672 int32_t h3lis100dl_hp_path_get(const stmdev_ctx_t *ctx,
673 h3lis100dl_hpen_t *val)
674 {
675 h3lis100dl_ctrl_reg2_t ctrl_reg2;
676 int32_t ret;
677
678 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG2,
679 (uint8_t *)&ctrl_reg2, 1);
680
681 switch ((ctrl_reg2.fds << 2) + ctrl_reg2.hpen)
682 {
683 case H3LIS100DL_HP_DISABLE:
684 *val = H3LIS100DL_HP_DISABLE;
685 break;
686
687 case H3LIS100DL_HP_ON_OUT:
688 *val = H3LIS100DL_HP_ON_OUT;
689 break;
690
691 case H3LIS100DL_HP_ON_INT1:
692 *val = H3LIS100DL_HP_ON_INT1;
693 break;
694
695 case H3LIS100DL_HP_ON_INT2:
696 *val = H3LIS100DL_HP_ON_INT2;
697 break;
698
699 case H3LIS100DL_HP_ON_INT1_INT2:
700 *val = H3LIS100DL_HP_ON_INT1_INT2;
701 break;
702
703 case H3LIS100DL_HP_ON_INT1_INT2_OUT:
704 *val = H3LIS100DL_HP_ON_INT1_INT2_OUT;
705 break;
706
707 case H3LIS100DL_HP_ON_INT2_OUT:
708 *val = H3LIS100DL_HP_ON_INT2_OUT;
709 break;
710
711 case H3LIS100DL_HP_ON_INT1_OUT:
712 *val = H3LIS100DL_HP_ON_INT1_OUT;
713 break;
714
715 default:
716 *val = H3LIS100DL_HP_DISABLE;
717 break;
718 }
719
720 return ret;
721 }
722
723 /**
724 * @brief Reading at this address zeroes instantaneously
725 * the content of the internal high pass-filter.
726 * If the high pass filter is enabled all three axes
727 * are instantaneously set to 0g. This allows to
728 * overcome the settling time of the high pass
729 * filter.[get]
730 *
731 * @param ctx read / write interface definitions(ptr)
732 * @retval interface status (MANDATORY: return 0 -> no Error)
733 *
734 */
h3lis100dl_hp_reset_get(const stmdev_ctx_t * ctx)735 int32_t h3lis100dl_hp_reset_get(const stmdev_ctx_t *ctx)
736 {
737 uint8_t dummy;
738 int32_t ret;
739
740 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_HP_FILTER_RESET,
741 (uint8_t *)&dummy, 1);
742
743 return ret;
744 }
745
746 /**
747 * @brief Reference value for high-pass filter.[set]
748 *
749 * @param ctx read / write interface definitions(ptr)
750 * @param val change the values of ref in reg REFERENCE
751 * @retval interface status (MANDATORY: return 0 -> no Error)
752 *
753 */
h3lis100dl_hp_reference_value_set(const stmdev_ctx_t * ctx,uint8_t val)754 int32_t h3lis100dl_hp_reference_value_set(const stmdev_ctx_t *ctx,
755 uint8_t val)
756 {
757 int32_t ret;
758
759 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_REFERENCE, (uint8_t *)&val, 1);
760
761 return ret;
762 }
763
764 /**
765 * @brief Reference value for high-pass filter.[get]
766 *
767 * @param ctx read / write interface definitions(ptr)
768 * @param val change the values of ref in reg REFERENCE
769 * @retval interface status (MANDATORY: return 0 -> no Error)
770 *
771 */
h3lis100dl_hp_reference_value_get(const stmdev_ctx_t * ctx,uint8_t * val)772 int32_t h3lis100dl_hp_reference_value_get(const stmdev_ctx_t *ctx,
773 uint8_t *val)
774 {
775 int32_t ret;
776
777 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_REFERENCE, val, 1);
778
779 return ret;
780 }
781
782 /**
783 * @}
784 *
785 */
786
787 /**
788 * @defgroup H3LIS100DL_Serial_Interface
789 * @brief This section groups all the functions concerning serial
790 * interface management.
791 * @{
792 *
793 */
794
795 /**
796 * @brief SPI 3- or 4-wire interface.[set]
797 *
798 * @param ctx read / write interface definitions(ptr)
799 * @param val change the values of sim in reg CTRL_REG4
800 * @retval interface status (MANDATORY: return 0 -> no Error)
801 *
802 */
h3lis100dl_spi_mode_set(const stmdev_ctx_t * ctx,h3lis100dl_sim_t val)803 int32_t h3lis100dl_spi_mode_set(const stmdev_ctx_t *ctx,
804 h3lis100dl_sim_t val)
805 {
806 h3lis100dl_ctrl_reg4_t ctrl_reg4;
807 int32_t ret;
808
809 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG4,
810 (uint8_t *)&ctrl_reg4, 1);
811
812 if (ret == 0)
813 {
814 ctrl_reg4.sim = (uint8_t)val;
815 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG4,
816 (uint8_t *)&ctrl_reg4, 1);
817 }
818
819 return ret;
820 }
821
822 /**
823 * @brief SPI 3- or 4-wire interface.[get]
824 *
825 * @param ctx read / write interface definitions(ptr)
826 * @param val Get the values of sim in reg CTRL_REG4
827 * @retval interface status (MANDATORY: return 0 -> no Error)
828 *
829 */
h3lis100dl_spi_mode_get(const stmdev_ctx_t * ctx,h3lis100dl_sim_t * val)830 int32_t h3lis100dl_spi_mode_get(const stmdev_ctx_t *ctx,
831 h3lis100dl_sim_t *val)
832 {
833 h3lis100dl_ctrl_reg4_t ctrl_reg4;
834 int32_t ret;
835
836 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG4,
837 (uint8_t *)&ctrl_reg4, 1);
838
839 switch (ctrl_reg4.sim)
840 {
841 case H3LIS100DL_SPI_4_WIRE:
842 *val = H3LIS100DL_SPI_4_WIRE;
843 break;
844
845 case H3LIS100DL_SPI_3_WIRE:
846 *val = H3LIS100DL_SPI_3_WIRE;
847 break;
848
849 default:
850 *val = H3LIS100DL_SPI_4_WIRE;
851 break;
852 }
853
854 return ret;
855 }
856
857 /**
858 * @}
859 *
860 */
861
862 /**
863 * @defgroup H3LIS100DL_Interrupt_Pins
864 * @brief This section groups all the functions that manage
865 * interrupt pins.
866 * @{
867 *
868 */
869
870 /**
871 * @brief Data signal on INT 1 pad control bits.[set]
872 *
873 * @param ctx read / write interface definitions(ptr)
874 * @param val change the values of i1_cfg in reg CTRL_REG3
875 * @retval interface status (MANDATORY: return 0 -> no Error)
876 *
877 */
h3lis100dl_pin_int1_route_set(const stmdev_ctx_t * ctx,h3lis100dl_i1_cfg_t val)878 int32_t h3lis100dl_pin_int1_route_set(const stmdev_ctx_t *ctx,
879 h3lis100dl_i1_cfg_t val)
880 {
881 h3lis100dl_ctrl_reg3_t ctrl_reg3;
882 int32_t ret;
883
884 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
885 (uint8_t *)&ctrl_reg3, 1);
886
887 if (ret == 0)
888 {
889 ctrl_reg3.i1_cfg = (uint8_t)val;
890 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
891 (uint8_t *)&ctrl_reg3, 1);
892 }
893
894 return ret;
895 }
896
897 /**
898 * @brief Data signal on INT 1 pad control bits.[get]
899 *
900 * @param ctx read / write interface definitions(ptr)
901 * @param val Get the values of i1_cfg in reg CTRL_REG3
902 * @retval interface status (MANDATORY: return 0 -> no Error)
903 *
904 */
h3lis100dl_pin_int1_route_get(const stmdev_ctx_t * ctx,h3lis100dl_i1_cfg_t * val)905 int32_t h3lis100dl_pin_int1_route_get(const stmdev_ctx_t *ctx,
906 h3lis100dl_i1_cfg_t *val)
907 {
908 h3lis100dl_ctrl_reg3_t ctrl_reg3;
909 int32_t ret;
910
911 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
912 (uint8_t *)&ctrl_reg3, 1);
913
914 switch (ctrl_reg3.i1_cfg)
915 {
916 case H3LIS100DL_PAD1_INT1_SRC:
917 *val = H3LIS100DL_PAD1_INT1_SRC;
918 break;
919
920 case H3LIS100DL_PAD1_INT1_OR_INT2_SRC:
921 *val = H3LIS100DL_PAD1_INT1_OR_INT2_SRC;
922 break;
923
924 case H3LIS100DL_PAD1_DRDY:
925 *val = H3LIS100DL_PAD1_DRDY;
926 break;
927
928 case H3LIS100DL_PAD1_BOOT:
929 *val = H3LIS100DL_PAD1_BOOT;
930 break;
931
932 default:
933 *val = H3LIS100DL_PAD1_INT1_SRC;
934 break;
935 }
936
937 return ret;
938 }
939
940 /**
941 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
942 * register cleared by reading INT1_SRC register.[set]
943 *
944 * @param ctx read / write interface definitions(ptr)
945 * @param val change the values of lir1 in reg CTRL_REG3
946 * @retval interface status (MANDATORY: return 0 -> no Error)
947 *
948 */
h3lis100dl_int1_notification_set(const stmdev_ctx_t * ctx,h3lis100dl_lir1_t val)949 int32_t h3lis100dl_int1_notification_set(const stmdev_ctx_t *ctx,
950 h3lis100dl_lir1_t val)
951 {
952 h3lis100dl_ctrl_reg3_t ctrl_reg3;
953 int32_t ret;
954
955 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
956 (uint8_t *)&ctrl_reg3, 1);
957
958 if (ret == 0)
959 {
960 ctrl_reg3.lir1 = (uint8_t)val;
961 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
962 (uint8_t *)&ctrl_reg3, 1);
963 }
964
965 return ret;
966 }
967
968 /**
969 * @brief Latch interrupt request on INT1_SRC register, with INT1_SRC
970 * register cleared by reading INT1_SRC register.[get]
971 *
972 * @param ctx read / write interface definitions(ptr)
973 * @param val Get the values of lir1 in reg CTRL_REG3
974 * @retval interface status (MANDATORY: return 0 -> no Error)
975 *
976 */
h3lis100dl_int1_notification_get(const stmdev_ctx_t * ctx,h3lis100dl_lir1_t * val)977 int32_t h3lis100dl_int1_notification_get(const stmdev_ctx_t *ctx,
978 h3lis100dl_lir1_t *val)
979 {
980 h3lis100dl_ctrl_reg3_t ctrl_reg3;
981 int32_t ret;
982
983 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
984 (uint8_t *)&ctrl_reg3, 1);
985
986 switch (ctrl_reg3.lir1)
987 {
988 case H3LIS100DL_INT1_PULSED:
989 *val = H3LIS100DL_INT1_PULSED;
990 break;
991
992 case H3LIS100DL_INT1_LATCHED:
993 *val = H3LIS100DL_INT1_LATCHED;
994 break;
995
996 default:
997 *val = H3LIS100DL_INT1_PULSED;
998 break;
999 }
1000
1001 return ret;
1002 }
1003
1004 /**
1005 * @brief Data signal on INT 2 pad control bits.[set]
1006 *
1007 * @param ctx read / write interface definitions(ptr)
1008 * @param val change the values of i2_cfg in reg CTRL_REG3
1009 * @retval interface status (MANDATORY: return 0 -> no Error)
1010 *
1011 */
h3lis100dl_pin_int2_route_set(const stmdev_ctx_t * ctx,h3lis100dl_i2_cfg_t val)1012 int32_t h3lis100dl_pin_int2_route_set(const stmdev_ctx_t *ctx,
1013 h3lis100dl_i2_cfg_t val)
1014 {
1015 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1016 int32_t ret;
1017
1018 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1019 (uint8_t *)&ctrl_reg3, 1);
1020
1021 if (ret == 0)
1022 {
1023 ctrl_reg3.i2_cfg = (uint8_t)val;
1024 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
1025 (uint8_t *)&ctrl_reg3, 1);
1026 }
1027
1028 return ret;
1029 }
1030
1031 /**
1032 * @brief Data signal on INT 2 pad control bits.[get]
1033 *
1034 * @param ctx read / write interface definitions(ptr)
1035 * @param val Get the values of i2_cfg in reg CTRL_REG3
1036 * @retval interface status (MANDATORY: return 0 -> no Error)
1037 *
1038 */
h3lis100dl_pin_int2_route_get(const stmdev_ctx_t * ctx,h3lis100dl_i2_cfg_t * val)1039 int32_t h3lis100dl_pin_int2_route_get(const stmdev_ctx_t *ctx,
1040 h3lis100dl_i2_cfg_t *val)
1041 {
1042 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1043 int32_t ret;
1044
1045 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1046 (uint8_t *)&ctrl_reg3, 1);
1047
1048 switch (ctrl_reg3.i2_cfg)
1049 {
1050 case H3LIS100DL_PAD2_INT2_SRC:
1051 *val = H3LIS100DL_PAD2_INT2_SRC;
1052 break;
1053
1054 case H3LIS100DL_PAD2_INT1_OR_INT2_SRC:
1055 *val = H3LIS100DL_PAD2_INT1_OR_INT2_SRC;
1056 break;
1057
1058 case H3LIS100DL_PAD2_DRDY:
1059 *val = H3LIS100DL_PAD2_DRDY;
1060 break;
1061
1062 case H3LIS100DL_PAD2_BOOT:
1063 *val = H3LIS100DL_PAD2_BOOT;
1064 break;
1065
1066 default:
1067 *val = H3LIS100DL_PAD2_INT2_SRC;
1068 break;
1069 }
1070
1071 return ret;
1072 }
1073
1074 /**
1075 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1076 * register cleared by reading INT2_SRC itself.[set]
1077 *
1078 * @param ctx read / write interface definitions(ptr)
1079 * @param val change the values of lir2 in reg CTRL_REG3
1080 * @retval interface status (MANDATORY: return 0 -> no Error)
1081 *
1082 */
h3lis100dl_int2_notification_set(const stmdev_ctx_t * ctx,h3lis100dl_lir2_t val)1083 int32_t h3lis100dl_int2_notification_set(const stmdev_ctx_t *ctx,
1084 h3lis100dl_lir2_t val)
1085 {
1086 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1087 int32_t ret;
1088
1089 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1090 (uint8_t *)&ctrl_reg3, 1);
1091
1092 if (ret == 0)
1093 {
1094 ctrl_reg3.lir2 = (uint8_t)val;
1095 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
1096 (uint8_t *)&ctrl_reg3, 1);
1097 }
1098
1099 return ret;
1100 }
1101
1102 /**
1103 * @brief Latch interrupt request on INT2_SRC register, with INT2_SRC
1104 * register cleared by reading INT2_SRC itself.[get]
1105 *
1106 * @param ctx read / write interface definitions(ptr)
1107 * @param val Get the values of lir2 in reg CTRL_REG3
1108 * @retval interface status (MANDATORY: return 0 -> no Error)
1109 *
1110 */
h3lis100dl_int2_notification_get(const stmdev_ctx_t * ctx,h3lis100dl_lir2_t * val)1111 int32_t h3lis100dl_int2_notification_get(const stmdev_ctx_t *ctx,
1112 h3lis100dl_lir2_t *val)
1113 {
1114 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1115 int32_t ret;
1116
1117 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1118 (uint8_t *)&ctrl_reg3, 1);
1119
1120 switch (ctrl_reg3.lir2)
1121 {
1122 case H3LIS100DL_INT2_PULSED:
1123 *val = H3LIS100DL_INT2_PULSED;
1124 break;
1125
1126 case H3LIS100DL_INT2_LATCHED:
1127 *val = H3LIS100DL_INT2_LATCHED;
1128 break;
1129
1130 default:
1131 *val = H3LIS100DL_INT2_PULSED;
1132 break;
1133 }
1134
1135 return ret;
1136 }
1137
1138 /**
1139 * @brief Push-pull/open drain selection on interrupt pads.[set]
1140 *
1141 * @param ctx read / write interface definitions(ptr)
1142 * @param val change the values of pp_od in reg CTRL_REG3
1143 * @retval interface status (MANDATORY: return 0 -> no Error)
1144 *
1145 */
h3lis100dl_pin_mode_set(const stmdev_ctx_t * ctx,h3lis100dl_pp_od_t val)1146 int32_t h3lis100dl_pin_mode_set(const stmdev_ctx_t *ctx,
1147 h3lis100dl_pp_od_t val)
1148 {
1149 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1150 int32_t ret;
1151
1152 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1153 (uint8_t *)&ctrl_reg3, 1);
1154
1155 if (ret == 0)
1156 {
1157 ctrl_reg3.pp_od = (uint8_t)val;
1158 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
1159 (uint8_t *)&ctrl_reg3, 1);
1160 }
1161
1162 return ret;
1163 }
1164
1165 /**
1166 * @brief Push-pull/open drain selection on interrupt pads.[get]
1167 *
1168 * @param ctx read / write interface definitions(ptr)
1169 * @param val Get the values of pp_od in reg CTRL_REG3
1170 * @retval interface status (MANDATORY: return 0 -> no Error)
1171 *
1172 */
h3lis100dl_pin_mode_get(const stmdev_ctx_t * ctx,h3lis100dl_pp_od_t * val)1173 int32_t h3lis100dl_pin_mode_get(const stmdev_ctx_t *ctx,
1174 h3lis100dl_pp_od_t *val)
1175 {
1176 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1177 int32_t ret;
1178
1179 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1180 (uint8_t *)&ctrl_reg3, 1);
1181
1182 switch (ctrl_reg3.pp_od)
1183 {
1184 case H3LIS100DL_PUSH_PULL:
1185 *val = H3LIS100DL_PUSH_PULL;
1186 break;
1187
1188 case H3LIS100DL_OPEN_DRAIN:
1189 *val = H3LIS100DL_OPEN_DRAIN;
1190 break;
1191
1192 default:
1193 *val = H3LIS100DL_PUSH_PULL;
1194 break;
1195 }
1196
1197 return ret;
1198 }
1199
1200 /**
1201 * @brief Interrupt active-high/low.[set]
1202 *
1203 * @param ctx read / write interface definitions(ptr)
1204 * @param val change the values of ihl in reg CTRL_REG3
1205 * @retval interface status (MANDATORY: return 0 -> no Error)
1206 *
1207 */
h3lis100dl_pin_polarity_set(const stmdev_ctx_t * ctx,h3lis100dl_ihl_t val)1208 int32_t h3lis100dl_pin_polarity_set(const stmdev_ctx_t *ctx,
1209 h3lis100dl_ihl_t val)
1210 {
1211 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1212 int32_t ret;
1213
1214 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1215 (uint8_t *)&ctrl_reg3, 1);
1216
1217 if (ret == 0)
1218 {
1219 ctrl_reg3.ihl = (uint8_t)val;
1220 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG3,
1221 (uint8_t *)&ctrl_reg3, 1);
1222 }
1223
1224 return ret;
1225 }
1226
1227 /**
1228 * @brief Interrupt active-high/low.[get]
1229 *
1230 * @param ctx read / write interface definitions(ptr)
1231 * @param val Get the values of ihl in reg CTRL_REG3
1232 * @retval interface status (MANDATORY: return 0 -> no Error)
1233 *
1234 */
h3lis100dl_pin_polarity_get(const stmdev_ctx_t * ctx,h3lis100dl_ihl_t * val)1235 int32_t h3lis100dl_pin_polarity_get(const stmdev_ctx_t *ctx,
1236 h3lis100dl_ihl_t *val)
1237 {
1238 h3lis100dl_ctrl_reg3_t ctrl_reg3;
1239 int32_t ret;
1240
1241 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG3,
1242 (uint8_t *)&ctrl_reg3, 1);
1243
1244 switch (ctrl_reg3.ihl)
1245 {
1246 case H3LIS100DL_ACTIVE_HIGH:
1247 *val = H3LIS100DL_ACTIVE_HIGH;
1248 break;
1249
1250 case H3LIS100DL_ACTIVE_LOW:
1251 *val = H3LIS100DL_ACTIVE_LOW;
1252 break;
1253
1254 default:
1255 *val = H3LIS100DL_ACTIVE_HIGH;
1256 break;
1257 }
1258
1259 return ret;
1260 }
1261
1262 /**
1263 * @}
1264 *
1265 */
1266
1267 /**
1268 * @defgroup H3LIS100DL_interrupt_on_threshold
1269 * @brief This section groups all the functions that manage
1270 * the interrupt on threshold event generation.
1271 * @{
1272 *
1273 */
1274
1275 /**
1276 * @brief Configure the interrupt 1 threshold sign.[set]
1277 *
1278 * @param ctx read / write interface definitions(ptr)
1279 * @param val enable sign and axis for interrupt on threshold
1280 * @retval interface status (MANDATORY: return 0 -> no Error)
1281 *
1282 */
h3lis100dl_int1_on_threshold_conf_set(const stmdev_ctx_t * ctx,int1_on_th_conf_t val)1283 int32_t h3lis100dl_int1_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1284 int1_on_th_conf_t val)
1285 {
1286 h3lis100dl_int1_cfg_t int1_cfg;
1287 int32_t ret;
1288
1289 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
1290 (uint8_t *)&int1_cfg, 1);
1291
1292 if (ret == 0)
1293 {
1294 int1_cfg.xlie = val.int1_xlie;
1295 int1_cfg.xhie = val.int1_xhie;
1296 int1_cfg.ylie = val.int1_ylie;
1297 int1_cfg.yhie = val.int1_yhie;
1298 int1_cfg.zlie = val.int1_zlie;
1299 int1_cfg.zhie = val.int1_zhie;
1300 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_CFG,
1301 (uint8_t *)&int1_cfg, 1);
1302 }
1303
1304 return ret;
1305 }
1306
1307 /**
1308 * @brief Configure the interrupt 1 threshold sign.[get]
1309 *
1310 * @param ctx read / write interface definitions(ptr)
1311 * @param val enable sign and axis for interrupt on threshold
1312 * @retval interface status (MANDATORY: return 0 -> no Error)
1313 *
1314 */
h3lis100dl_int1_on_threshold_conf_get(const stmdev_ctx_t * ctx,int1_on_th_conf_t * val)1315 int32_t h3lis100dl_int1_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1316 int1_on_th_conf_t *val)
1317 {
1318 h3lis100dl_int1_cfg_t int1_cfg;
1319 int32_t ret;
1320
1321 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
1322 (uint8_t *)&int1_cfg, 1);
1323 val->int1_xlie = int1_cfg.xlie;
1324 val->int1_xhie = int1_cfg.xhie;
1325 val->int1_ylie = int1_cfg.ylie;
1326 val->int1_yhie = int1_cfg.yhie;
1327 val->int1_zlie = int1_cfg.zlie;
1328 val->int1_zhie = int1_cfg.zhie;
1329
1330 return ret;
1331 }
1332
1333 /**
1334 * @brief AND/OR combination of Interrupt 1 events.[set]
1335 *
1336 * @param ctx read / write interface definitions(ptr)
1337 * @param val change the values of aoi in reg INT1_CFG
1338 * @retval interface status (MANDATORY: return 0 -> no Error)
1339 *
1340 */
h3lis100dl_int1_on_threshold_mode_set(const stmdev_ctx_t * ctx,h3lis100dl_int1_aoi_t val)1341 int32_t h3lis100dl_int1_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1342 h3lis100dl_int1_aoi_t val)
1343 {
1344 h3lis100dl_int1_cfg_t int1_cfg;
1345 int32_t ret;
1346
1347 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
1348 (uint8_t *)&int1_cfg, 1);
1349
1350 if (ret == 0)
1351 {
1352 int1_cfg.aoi = (uint8_t) val;
1353 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_CFG,
1354 (uint8_t *)&int1_cfg, 1);
1355 }
1356
1357 return ret;
1358 }
1359
1360 /**
1361 * @brief AND/OR combination of Interrupt 1 events.[get]
1362 *
1363 * @param ctx read / write interface definitions(ptr)
1364 * @param val Get the values of aoi in reg INT1_CFG
1365 * @retval interface status (MANDATORY: return 0 -> no Error)
1366 *
1367 */
h3lis100dl_int1_on_threshold_mode_get(const stmdev_ctx_t * ctx,h3lis100dl_int1_aoi_t * val)1368 int32_t h3lis100dl_int1_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1369 h3lis100dl_int1_aoi_t *val)
1370 {
1371 h3lis100dl_int1_cfg_t int1_cfg;
1372 int32_t ret;
1373
1374 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_CFG,
1375 (uint8_t *)&int1_cfg, 1);
1376
1377 switch (int1_cfg.aoi)
1378 {
1379 case H3LIS100DL_INT1_ON_THRESHOLD_OR:
1380 *val = H3LIS100DL_INT1_ON_THRESHOLD_OR;
1381 break;
1382
1383 case H3LIS100DL_INT1_ON_THRESHOLD_AND:
1384 *val = H3LIS100DL_INT1_ON_THRESHOLD_AND;
1385 break;
1386
1387 default:
1388 *val = H3LIS100DL_INT1_ON_THRESHOLD_OR;
1389 break;
1390 }
1391
1392 return ret;
1393 }
1394
1395 /**
1396 * @brief Interrupt generator 1 on threshold source register.[get]
1397 *
1398 * @param ctx read / write interface definitions(ptr)
1399 * @param val registers INT1_SRC
1400 * @retval interface status (MANDATORY: return 0 -> no Error)
1401 *
1402 */
h3lis100dl_int1_src_get(const stmdev_ctx_t * ctx,h3lis100dl_int1_src_t * val)1403 int32_t h3lis100dl_int1_src_get(const stmdev_ctx_t *ctx,
1404 h3lis100dl_int1_src_t *val)
1405 {
1406 int32_t ret;
1407
1408 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_SRC, (uint8_t *) val, 1);
1409
1410 return ret;
1411 }
1412
1413 /**
1414 * @brief Interrupt 1 threshold.[set]
1415 *
1416 * @param ctx read / write interface definitions(ptr)
1417 * @param val change the values of ths in reg INT1_THS
1418 * @retval interface status (MANDATORY: return 0 -> no Error)
1419 *
1420 */
h3lis100dl_int1_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1421 int32_t h3lis100dl_int1_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1422 {
1423 h3lis100dl_int1_ths_t int1_ths;
1424 int32_t ret;
1425
1426 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_THS,
1427 (uint8_t *)&int1_ths, 1);
1428
1429 if (ret == 0)
1430 {
1431 int1_ths.ths = val;
1432 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_THS,
1433 (uint8_t *)&int1_ths, 1);
1434 }
1435
1436 return ret;
1437 }
1438
1439 /**
1440 * @brief Interrupt 1 threshold.[get]
1441 *
1442 * @param ctx read / write interface definitions(ptr)
1443 * @param val change the values of ths in reg INT1_THS
1444 * @retval interface status (MANDATORY: return 0 -> no Error)
1445 *
1446 */
h3lis100dl_int1_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1447 int32_t h3lis100dl_int1_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1448 {
1449 h3lis100dl_int1_ths_t int1_ths;
1450 int32_t ret;
1451
1452 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_THS,
1453 (uint8_t *)&int1_ths, 1);
1454 *val = int1_ths.ths;
1455
1456 return ret;
1457 }
1458
1459 /**
1460 * @brief Duration value for interrupt 1 generator.[set]
1461 *
1462 * @param ctx read / write interface definitions(ptr)
1463 * @param val change the values of d in reg INT1_DURATION
1464 * @retval interface status (MANDATORY: return 0 -> no Error)
1465 *
1466 */
h3lis100dl_int1_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1467 int32_t h3lis100dl_int1_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1468 {
1469 h3lis100dl_int1_duration_t int1_duration;
1470 int32_t ret;
1471
1472 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_DURATION,
1473 (uint8_t *)&int1_duration, 1);
1474
1475 if (ret == 0)
1476 {
1477 int1_duration.d = val;
1478 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT1_DURATION,
1479 (uint8_t *)&int1_duration, 1);
1480 }
1481
1482 return ret;
1483 }
1484
1485 /**
1486 * @brief Duration value for interrupt 1 generator.[get]
1487 *
1488 * @param ctx read / write interface definitions(ptr)
1489 * @param val change the values of d in reg INT1_DURATION
1490 * @retval interface status (MANDATORY: return 0 -> no Error)
1491 *
1492 */
h3lis100dl_int1_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1493 int32_t h3lis100dl_int1_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1494 {
1495 h3lis100dl_int1_duration_t int1_duration;
1496 int32_t ret;
1497
1498 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT1_DURATION,
1499 (uint8_t *)&int1_duration, 1);
1500 *val = int1_duration.d;
1501
1502 return ret;
1503 }
1504
1505 /**
1506 * @brief Configure the interrupt 2 threshold sign.[set]
1507 *
1508 * @param ctx read / write interface definitions(ptr)
1509 * @param val enable sign and axis for interrupt on threshold
1510 * @retval interface status (MANDATORY: return 0 -> no Error)
1511 *
1512 */
h3lis100dl_int2_on_threshold_conf_set(const stmdev_ctx_t * ctx,int2_on_th_conf_t val)1513 int32_t h3lis100dl_int2_on_threshold_conf_set(const stmdev_ctx_t *ctx,
1514 int2_on_th_conf_t val)
1515 {
1516 h3lis100dl_int2_cfg_t int2_cfg;
1517 int32_t ret;
1518
1519 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
1520 (uint8_t *)&int2_cfg, 1);
1521
1522 if (ret == 0)
1523 {
1524 int2_cfg.xlie = val.int2_xlie;
1525 int2_cfg.xhie = val.int2_xhie;
1526 int2_cfg.ylie = val.int2_ylie;
1527 int2_cfg.yhie = val.int2_yhie;
1528 int2_cfg.zlie = val.int2_zlie;
1529 int2_cfg.zhie = val.int2_zhie;
1530 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_CFG,
1531 (uint8_t *)&int2_cfg, 1);
1532 }
1533
1534 return ret;
1535 }
1536
1537 /**
1538 * @brief Configure the interrupt 2 threshold sign.[get]
1539 *
1540 * @param ctx read / write interface definitions(ptr)
1541 * @param val enable sign and axis for interrupt on threshold
1542 * @retval interface status (MANDATORY: return 0 -> no Error)
1543 *
1544 */
h3lis100dl_int2_on_threshold_conf_get(const stmdev_ctx_t * ctx,int2_on_th_conf_t * val)1545 int32_t h3lis100dl_int2_on_threshold_conf_get(const stmdev_ctx_t *ctx,
1546 int2_on_th_conf_t *val)
1547 {
1548 h3lis100dl_int2_cfg_t int2_cfg;
1549 int32_t ret;
1550
1551 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
1552 (uint8_t *)&int2_cfg, 1);
1553 val->int2_xlie = int2_cfg.xlie;
1554 val->int2_xhie = int2_cfg.xhie;
1555 val->int2_ylie = int2_cfg.ylie;
1556 val->int2_yhie = int2_cfg.yhie;
1557 val->int2_zlie = int2_cfg.zlie;
1558 val->int2_zhie = int2_cfg.zhie;
1559
1560 return ret;
1561 }
1562
1563 /**
1564 * @brief AND/OR combination of Interrupt 2 events.[set]
1565 *
1566 * @param ctx read / write interface definitions(ptr)
1567 * @param val change the values of aoi in reg INT2_CFG
1568 * @retval interface status (MANDATORY: return 0 -> no Error)
1569 *
1570 */
h3lis100dl_int2_on_threshold_mode_set(const stmdev_ctx_t * ctx,h3lis100dl_int2_aoi_t val)1571 int32_t h3lis100dl_int2_on_threshold_mode_set(const stmdev_ctx_t *ctx,
1572 h3lis100dl_int2_aoi_t val)
1573 {
1574 h3lis100dl_int2_cfg_t int2_cfg;
1575 int32_t ret;
1576
1577 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
1578 (uint8_t *)&int2_cfg, 1);
1579
1580 if (ret == 0)
1581 {
1582 int2_cfg.aoi = (uint8_t) val;
1583 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_CFG,
1584 (uint8_t *)&int2_cfg, 1);
1585 }
1586
1587 return ret;
1588 }
1589
1590 /**
1591 * @brief AND/OR combination of Interrupt 2 events.[get]
1592 *
1593 * @param ctx read / write interface definitions(ptr)
1594 * @param val Get the values of aoi in reg INT2_CFG
1595 * @retval interface status (MANDATORY: return 0 -> no Error)
1596 *
1597 */
h3lis100dl_int2_on_threshold_mode_get(const stmdev_ctx_t * ctx,h3lis100dl_int2_aoi_t * val)1598 int32_t h3lis100dl_int2_on_threshold_mode_get(const stmdev_ctx_t *ctx,
1599 h3lis100dl_int2_aoi_t *val)
1600 {
1601 h3lis100dl_int2_cfg_t int2_cfg;
1602 int32_t ret;
1603
1604 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_CFG,
1605 (uint8_t *)&int2_cfg, 1);
1606
1607 switch (int2_cfg.aoi)
1608 {
1609 case H3LIS100DL_INT2_ON_THRESHOLD_OR:
1610 *val = H3LIS100DL_INT2_ON_THRESHOLD_OR;
1611 break;
1612
1613 case H3LIS100DL_INT2_ON_THRESHOLD_AND:
1614 *val = H3LIS100DL_INT2_ON_THRESHOLD_AND;
1615 break;
1616
1617 default:
1618 *val = H3LIS100DL_INT2_ON_THRESHOLD_OR;
1619 break;
1620 }
1621
1622 return ret;
1623 }
1624
1625 /**
1626 * @brief Interrupt generator 1 on threshold source register.[get]
1627 *
1628 * @param ctx read / write interface definitions(ptr)
1629 * @param val registers INT2_SRC
1630 * @retval interface status (MANDATORY: return 0 -> no Error)
1631 *
1632 */
h3lis100dl_int2_src_get(const stmdev_ctx_t * ctx,h3lis100dl_int2_src_t * val)1633 int32_t h3lis100dl_int2_src_get(const stmdev_ctx_t *ctx,
1634 h3lis100dl_int2_src_t *val)
1635 {
1636 int32_t ret;
1637
1638 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_SRC, (uint8_t *) val, 1);
1639
1640 return ret;
1641 }
1642
1643 /**
1644 * @brief Interrupt 2 threshold.[set]
1645 *
1646 * @param ctx read / write interface definitions(ptr)
1647 * @param val change the values of ths in reg INT2_THS
1648 * @retval interface status (MANDATORY: return 0 -> no Error)
1649 *
1650 */
h3lis100dl_int2_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)1651 int32_t h3lis100dl_int2_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
1652 {
1653 h3lis100dl_int2_ths_t int2_ths;
1654 int32_t ret;
1655
1656 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_THS,
1657 (uint8_t *)&int2_ths, 1);
1658
1659 if (ret == 0)
1660 {
1661 int2_ths.ths = val;
1662 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_THS,
1663 (uint8_t *)&int2_ths, 1);
1664 }
1665
1666 return ret;
1667 }
1668
1669 /**
1670 * @brief Interrupt 2 threshold.[get]
1671 *
1672 * @param ctx read / write interface definitions(ptr)
1673 * @param val change the values of ths in reg INT2_THS
1674 * @retval interface status (MANDATORY: return 0 -> no Error)
1675 *
1676 */
h3lis100dl_int2_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)1677 int32_t h3lis100dl_int2_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
1678 {
1679 h3lis100dl_int2_ths_t int2_ths;
1680 int32_t ret;
1681
1682 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_THS,
1683 (uint8_t *)&int2_ths, 1);
1684 *val = int2_ths.ths;
1685
1686 return ret;
1687 }
1688
1689 /**
1690 * @brief Duration value for interrupt 2 generator.[set]
1691 *
1692 * @param ctx read / write interface definitions(ptr)
1693 * @param val change the values of d in reg INT2_DURATION
1694 * @retval interface status (MANDATORY: return 0 -> no Error)
1695 *
1696 */
h3lis100dl_int2_dur_set(const stmdev_ctx_t * ctx,uint8_t val)1697 int32_t h3lis100dl_int2_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
1698 {
1699 h3lis100dl_int2_duration_t int2_duration;
1700 int32_t ret;
1701
1702 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_DURATION,
1703 (uint8_t *)&int2_duration, 1);
1704
1705 if (ret == 0)
1706 {
1707 int2_duration.d = val;
1708 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_INT2_DURATION,
1709 (uint8_t *)&int2_duration, 1);
1710 }
1711
1712 return ret;
1713 }
1714
1715 /**
1716 * @brief Duration value for interrupt 2 generator.[get]
1717 *
1718 * @param ctx read / write interface definitions(ptr)
1719 * @param val change the values of d in reg INT2_DURATION
1720 * @retval interface status (MANDATORY: return 0 -> no Error)
1721 *
1722 */
h3lis100dl_int2_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)1723 int32_t h3lis100dl_int2_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
1724 {
1725 h3lis100dl_int2_duration_t int2_duration;
1726 int32_t ret;
1727
1728 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_INT2_DURATION,
1729 (uint8_t *)&int2_duration, 1);
1730 *val = int2_duration.d;
1731
1732 return ret;
1733 }
1734
1735 /**
1736 * @}
1737 *
1738 */
1739
1740 /**
1741 * @defgroup H3LIS100DL_Wake_Up_Event
1742 * @brief This section groups all the functions that manage the
1743 * Wake Up event generation.
1744 * @{
1745 *
1746 */
1747
1748 /**
1749 * @brief Turn-on mode selection for sleep to wake function.[set]
1750 *
1751 * @param ctx read / write interface definitions(ptr)
1752 * @param val change the values of turnon in reg CTRL_REG5
1753 * @retval interface status (MANDATORY: return 0 -> no Error)
1754 *
1755 */
h3lis100dl_wkup_to_sleep_set(const stmdev_ctx_t * ctx,uint8_t val)1756 int32_t h3lis100dl_wkup_to_sleep_set(const stmdev_ctx_t *ctx, uint8_t val)
1757 {
1758 h3lis100dl_ctrl_reg5_t ctrl_reg5;
1759 int32_t ret;
1760
1761 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG5,
1762 (uint8_t *)&ctrl_reg5, 1);
1763
1764 if (ret == 0)
1765 {
1766 ctrl_reg5.turnon = val;
1767 ret = h3lis100dl_write_reg(ctx, H3LIS100DL_CTRL_REG5,
1768 (uint8_t *)&ctrl_reg5, 1);
1769 }
1770
1771 return ret;
1772 }
1773
1774 /**
1775 * @brief Turn-on mode selection for sleep to wake function.[get]
1776 *
1777 * @param ctx read / write interface definitions(ptr)
1778 * @param val change the values of turnon in reg CTRL_REG5
1779 * @retval interface status (MANDATORY: return 0 -> no Error)
1780 *
1781 */
h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t * ctx,uint8_t * val)1782 int32_t h3lis100dl_wkup_to_sleep_get(const stmdev_ctx_t *ctx, uint8_t *val)
1783 {
1784 h3lis100dl_ctrl_reg5_t ctrl_reg5;
1785 int32_t ret;
1786
1787 ret = h3lis100dl_read_reg(ctx, H3LIS100DL_CTRL_REG5,
1788 (uint8_t *)&ctrl_reg5, 1);
1789 *val = ctrl_reg5.turnon;
1790
1791 return ret;
1792 }
1793
1794 /**
1795 * @}
1796 *
1797 */
1798
1799 /**
1800 * @}
1801 *
1802 */
1803
1804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1805
