1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * This file has been automatically generated and modified 9 * Tool Version: 1.0.0 10 * Generation Date: 2023-08-01 11 */ 12 13 #ifndef _SEDI_GPIO_REGS_H_ 14 #define _SEDI_GPIO_REGS_H_ 15 16 #include <sedi_reg_defs.h> 17 18 19 /* ********* GPIO GCCR *********** 20 * 21 * Register of SEDI GPIO 22 * GCCR: GPIO Pin DirectionLock 23 * AddressOffset : 0x0 24 * AccessType : RW 25 * WritableBitMask: 0x1 26 * ResetValue : (uint32_t)0x0 27 */ 28 SEDI_REG_DEFINE(GPIO, GCCR, 0x0, RW, (uint32_t)0x1, (uint32_t)0x0); 29 30 /* 31 * Bit Field of Register GCCR 32 * GPDR_LOCK: 33 * BitOffset : 0 34 * BitWidth : 1 35 * AccessType: RW 36 * ResetValue: (uint32_t)0x0 37 */ 38 SEDI_RBF_DEFINE(GPIO, GCCR, GPDR_LOCK, 0, 1, RW, (uint32_t)0x0); 39 SEDI_RBFV_DEFINE(GPIO, GCCR, GPDR_LOCK, 0, 0); 40 SEDI_RBFV_DEFINE(GPIO, GCCR, GPDR_LOCK, 1, 1); 41 42 /* 43 * Bit Field of Register GCCR 44 * RESERVED0: 45 * BitOffset : 1 46 * BitWidth : 31 47 * AccessType: RO 48 * ResetValue: (uint32_t)0x0 49 */ 50 SEDI_RBF_DEFINE(GPIO, GCCR, RESERVED0, 1, 31, RO, (uint32_t)0x0); 51 52 /* ********* GPIO GPLR0 *********** 53 * 54 * Register of SEDI GPIO 55 * GPLR0: GPIO Pin Level 56 * AddressOffset : 0x4 57 * AccessType : RO 58 * WritableBitMask: 0xffffffff 59 * ResetValue : (uint32_t)0x0 60 */ 61 SEDI_REG_DEFINE(GPIO, GPLR0, 0x4, RO, (uint32_t)0xffffffff, (uint32_t)0x0); 62 63 /* 64 * Bit Field of Register GPLR0 65 * GPLR0: 66 * BitOffset : 0 67 * BitWidth : 32 68 * AccessType: RO_V 69 * ResetValue: (uint32_t)0x0 70 */ 71 SEDI_RBF_DEFINE(GPIO, GPLR0, GPLR0, 0, 32, RO_V, (uint32_t)0x0); 72 73 /* ********* GPIO GPDR0 *********** 74 * 75 * Register of SEDI GPIO 76 * GPDR0: GPIO Pin Direction 77 * AddressOffset : 0x1c 78 * AccessType : RW 79 * WritableBitMask: 0xffffffff 80 * ResetValue : (uint32_t)0x0 81 */ 82 SEDI_REG_DEFINE(GPIO, GPDR0, 0x1c, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 83 84 /* 85 * Bit Field of Register GPDR0 86 * GPDR0: 87 * BitOffset : 0 88 * BitWidth : 32 89 * AccessType: RW_L 90 * ResetValue: (uint32_t)0x0 91 */ 92 SEDI_RBF_DEFINE(GPIO, GPDR0, GPDR0, 0, 32, RW_L, (uint32_t)0x0); 93 94 /* ********* GPIO GPSR0 *********** 95 * 96 * Register of SEDI GPIO 97 * GPSR0: GPIO Pin Output Set 98 * AddressOffset : 0x34 99 * AccessType : RO 100 * WritableBitMask: 0xffffffff 101 * ResetValue : (uint32_t)0x0 102 */ 103 SEDI_REG_DEFINE(GPIO, GPSR0, 0x34, RO, (uint32_t)0xffffffff, (uint32_t)0x0); 104 105 /* 106 * Bit Field of Register GPSR0 107 * GPSR0: 108 * BitOffset : 0 109 * BitWidth : 32 110 * AccessType: WO 111 * ResetValue: (uint32_t)0x0 112 */ 113 SEDI_RBF_DEFINE(GPIO, GPSR0, GPSR0, 0, 32, WO, (uint32_t)0x0); 114 115 /* ********* GPIO GPCR0 *********** 116 * 117 * Register of SEDI GPIO 118 * GPCR0: GPIO Pin Output Clear 119 * AddressOffset : 0x4c 120 * AccessType : RO 121 * WritableBitMask: 0xffffffff 122 * ResetValue : (uint32_t)0x0 123 */ 124 SEDI_REG_DEFINE(GPIO, GPCR0, 0x4c, RO, (uint32_t)0xffffffff, (uint32_t)0x0); 125 126 /* 127 * Bit Field of Register GPCR0 128 * GPCR0: 129 * BitOffset : 0 130 * BitWidth : 32 131 * AccessType: WO 132 * ResetValue: (uint32_t)0x0 133 */ 134 SEDI_RBF_DEFINE(GPIO, GPCR0, GPCR0, 0, 32, WO, (uint32_t)0x0); 135 136 /* ********* GPIO GRER0 *********** 137 * 138 * Register of SEDI GPIO 139 * GRER0: GPIO Rising Edge Detect Enable 140 * AddressOffset : 0x64 141 * AccessType : RW 142 * WritableBitMask: 0xffffffff 143 * ResetValue : (uint32_t)0x0 144 */ 145 SEDI_REG_DEFINE(GPIO, GRER0, 0x64, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 146 147 /* 148 * Bit Field of Register GRER0 149 * GRER0: 150 * BitOffset : 0 151 * BitWidth : 32 152 * AccessType: RW 153 * ResetValue: (uint32_t)0x0 154 */ 155 SEDI_RBF_DEFINE(GPIO, GRER0, GRER0, 0, 32, RW, (uint32_t)0x0); 156 157 /* ********* GPIO GFER0 *********** 158 * 159 * Register of SEDI GPIO 160 * GFER0: GPIO Falling Edge Detect Enable 161 * AddressOffset : 0x7c 162 * AccessType : RW 163 * WritableBitMask: 0xffffffff 164 * ResetValue : (uint32_t)0x0 165 */ 166 SEDI_REG_DEFINE(GPIO, GFER0, 0x7c, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 167 168 /* 169 * Bit Field of Register GFER0 170 * GFER0: 171 * BitOffset : 0 172 * BitWidth : 32 173 * AccessType: RW 174 * ResetValue: (uint32_t)0x0 175 */ 176 SEDI_RBF_DEFINE(GPIO, GFER0, GFER0, 0, 32, RW, (uint32_t)0x0); 177 178 /* ********* GPIO GFBR0 *********** 179 * 180 * Register of SEDI GPIO 181 * GFBR0: GPIO Glitch Filter Bypass 182 * AddressOffset : 0x94 183 * AccessType : RW 184 * WritableBitMask: 0xffffffff 185 * ResetValue : (uint32_t)-1 186 */ 187 SEDI_REG_DEFINE(GPIO, GFBR0, 0x94, RW, (uint32_t)0xffffffff, (uint32_t)-1); 188 189 /* 190 * Bit Field of Register GFBR0 191 * GFBR0: 192 * BitOffset : 0 193 * BitWidth : 32 194 * AccessType: RW 195 * ResetValue: (uint32_t)-1 196 */ 197 SEDI_RBF_DEFINE(GPIO, GFBR0, GFBR0, 0, 32, RW, (uint32_t)-1); 198 199 /* ********* GPIO GIMR0 *********** 200 * 201 * Register of SEDI GPIO 202 * GIMR0: GPIO Interrupt Mask 203 * AddressOffset : 0xac 204 * AccessType : RW 205 * WritableBitMask: 0xffffffff 206 * ResetValue : (uint32_t)0x0 207 */ 208 SEDI_REG_DEFINE(GPIO, GIMR0, 0xac, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 209 210 /* 211 * Bit Field of Register GIMR0 212 * GIMR0: 213 * BitOffset : 0 214 * BitWidth : 32 215 * AccessType: RW 216 * ResetValue: (uint32_t)0x0 217 */ 218 SEDI_RBF_DEFINE(GPIO, GIMR0, GIMR0, 0, 32, RW, (uint32_t)0x0); 219 220 /* ********* GPIO GISR0 *********** 221 * 222 * Register of SEDI GPIO 223 * GISR0: GPIO Interrupt Source 224 * AddressOffset : 0xc4 225 * AccessType : RW 226 * WritableBitMask: 0xffffffff 227 * ResetValue : (uint32_t)0x0 228 */ 229 SEDI_REG_DEFINE(GPIO, GISR0, 0xc4, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 230 231 /* 232 * Bit Field of Register GISR0 233 * GISR0: 234 * BitOffset : 0 235 * BitWidth : 32 236 * AccessType: RW_1C_V 237 * ResetValue: (uint32_t)0x0 238 */ 239 SEDI_RBF_DEFINE(GPIO, GISR0, GISR0, 0, 32, RW_1C_V, (uint32_t)0x0); 240 241 /* ********* GPIO GWMR0 *********** 242 * 243 * Register of SEDI GPIO 244 * GWMR0: GPIO Wake Mask 245 * AddressOffset : 0x100 246 * AccessType : RW 247 * WritableBitMask: 0xffffffff 248 * ResetValue : (uint32_t)0x0 249 */ 250 SEDI_REG_DEFINE(GPIO, GWMR0, 0x100, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 251 252 /* 253 * Bit Field of Register GWMR0 254 * GWMR0: 255 * BitOffset : 0 256 * BitWidth : 32 257 * AccessType: RW 258 * ResetValue: (uint32_t)0x0 259 */ 260 SEDI_RBF_DEFINE(GPIO, GWMR0, GWMR0, 0, 32, RW, (uint32_t)0x0); 261 262 /* ********* GPIO GWSR0 *********** 263 * 264 * Register of SEDI GPIO 265 * GWSR0: GPIO Wake Source 266 * AddressOffset : 0x118 267 * AccessType : RW 268 * WritableBitMask: 0xffffffff 269 * ResetValue : (uint32_t)0x0 270 */ 271 SEDI_REG_DEFINE(GPIO, GWSR0, 0x118, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 272 273 /* 274 * Bit Field of Register GWSR0 275 * GWSR0: 276 * BitOffset : 0 277 * BitWidth : 32 278 * AccessType: RW_1C_V 279 * ResetValue: (uint32_t)0x0 280 */ 281 SEDI_RBF_DEFINE(GPIO, GWSR0, GWSR0, 0, 32, RW_1C_V, (uint32_t)0x0); 282 283 /* ********* GPIO GSEC *********** 284 * 285 * Register of SEDI GPIO 286 * GSEC: GPIO Secure Input 287 * AddressOffset : 0x130 288 * AccessType : RW 289 * WritableBitMask: 0xffffffff 290 * ResetValue : (uint32_t)0x0 291 */ 292 SEDI_REG_DEFINE(GPIO, GSEC, 0x130, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 293 294 /* 295 * Bit Field of Register GSEC 296 * GSEC: 297 * BitOffset : 0 298 * BitWidth : 32 299 * AccessType: RW 300 * ResetValue: (uint32_t)0x0 301 */ 302 SEDI_RBF_DEFINE(GPIO, GSEC, GSEC, 0, 32, RW, (uint32_t)0x0); 303 304 /* ********* GPIO SPARE *********** 305 * 306 * Register of SEDI GPIO 307 * SPARE: Spare Register 308 * AddressOffset : 0x200 309 * AccessType : RW 310 * WritableBitMask: 0xffffffff 311 * ResetValue : (uint32_t)0x0 312 */ 313 SEDI_REG_DEFINE(GPIO, SPARE, 0x200, RW, (uint32_t)0xffffffff, (uint32_t)0x0); 314 315 /* 316 * Bit Field of Register SPARE 317 * SPARE: 318 * BitOffset : 0 319 * BitWidth : 32 320 * AccessType: RW 321 * ResetValue: (uint32_t)0x0 322 */ 323 SEDI_RBF_DEFINE(GPIO, SPARE, SPARE, 0, 32, RW, (uint32_t)0x0); 324 325 /* 326 * Registers' Address Map Structure 327 */ 328 329 typedef struct { 330 /* GPIO Pin DirectionLock */ 331 __IO_RW uint32_t gccr; 332 333 /* GPIO Pin Level */ 334 __IO_RW uint32_t gplr[6]; 335 336 /* GPIO Pin Direction */ 337 __IO_RW uint32_t gpdr[6]; 338 339 /* GPIO Pin Output Set */ 340 __IO_RW uint32_t gpsr[6]; 341 342 /* GPIO Pin Output Clear */ 343 __IO_RW uint32_t gpcr[6]; 344 345 /* GPIO Rising Edge Detect Enable */ 346 __IO_RW uint32_t grer[6]; 347 348 /* GPIO Falling Edge Detect Enable */ 349 __IO_RW uint32_t gfer[6]; 350 351 /* GPIO Glitch Filter Bypass */ 352 __IO_RW uint32_t gfbr[6]; 353 354 /* GPIO Interrupt Mask */ 355 __IO_RW uint32_t gimr[6]; 356 357 /* GPIO Interrupt Source */ 358 __IO_RW uint32_t gisr[6]; 359 360 /* Reserved */ 361 __IO_RW uint32_t reserved0[9]; 362 363 /* GPIO Wake Mask */ 364 __IO_RW uint32_t gwmr[6]; 365 366 /* GPIO Wake Source */ 367 __IO_RW uint32_t gwsr[6]; 368 369 /* GPIO Secure Input */ 370 __IO_RW uint32_t gsec; 371 372 /* Reserved */ 373 __IO_RW uint32_t reserved1[51]; 374 375 /* Spare Register */ 376 __IO_RW uint32_t spare; 377 378 } sedi_gpio_regs_t; 379 380 381 #endif /* _SEDI_GPIO_REGS_H_ */ 382
