1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stddef.h>
8 #include <string.h>
9 #include <sys/lock.h>
10 #include <sys/param.h>
11
12 #include "esp_attr.h"
13 #include "esp_sleep.h"
14 #include "esp_log.h"
15 #include "esp_memory_utils.h"
16 #include "soc/soc_caps.h"
17
18 #include "sdkconfig.h"
19
20 #include "driver/gpio.h"
21 #include "hal/gpio_hal.h"
22 #include "hal/rtc_io_hal.h"
23
24 #if SOC_LP_AON_SUPPORTED
25 #include "hal/lp_aon_hal.h"
26 #else
27 #if !CONFIG_IDF_TARGET_ESP32H2
28 #include "hal/rtc_hal.h"
29 #endif
30 #endif
31
32 #include "esp_private/gpio.h"
33 #include "esp_private/sleep_gpio.h"
34 #include "esp_private/spi_flash_os.h"
35 #include "esp_private/startup_internal.h"
36 #include "bootloader_flash.h"
37
38 static const char *TAG = "sleep";
39
40 #if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
gpio_sleep_mode_config_apply(void)41 void gpio_sleep_mode_config_apply(void)
42 {
43 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
44 if (GPIO_IS_VALID_GPIO(gpio_num)) {
45 gpio_sleep_pupd_config_apply(gpio_num);
46 }
47 }
48 }
49
gpio_sleep_mode_config_unapply(void)50 IRAM_ATTR void gpio_sleep_mode_config_unapply(void)
51 {
52 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
53 if (GPIO_IS_VALID_GPIO(gpio_num)) {
54 gpio_sleep_pupd_config_unapply(gpio_num);
55 }
56 }
57 }
58 #endif
59
esp_sleep_config_gpio_isolate(void)60 void esp_sleep_config_gpio_isolate(void)
61 {
62 ESP_EARLY_LOGI(TAG, "Configure to isolate all GPIO pins in sleep state");
63 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
64 if (GPIO_IS_VALID_GPIO(gpio_num)) {
65 gpio_sleep_set_direction(gpio_num, GPIO_MODE_DISABLE);
66 gpio_sleep_set_pull_mode(gpio_num, GPIO_FLOATING);
67 }
68 }
69
70 #if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
71 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CS1), GPIO_PULLUP_ONLY);
72 #endif // CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
73
74 #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
75 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CS0), GPIO_PULLUP_ONLY);
76 #endif // CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
77
78 #if CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU
79 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CLK), GPIO_PULLUP_ONLY);
80 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_Q), GPIO_PULLUP_ONLY);
81 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D), GPIO_PULLUP_ONLY);
82 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_HD), GPIO_PULLUP_ONLY);
83 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_WP), GPIO_PULLUP_ONLY);
84 #if SOC_SPI_MEM_SUPPORT_OPI_MODE
85 bool octal_mspi_required = bootloader_flash_is_octal_mode_enabled();
86 #if CONFIG_SPIRAM_MODE_OCT
87 octal_mspi_required |= true;
88 #endif // CONFIG_SPIRAM_MODE_OCT
89 if (octal_mspi_required) {
90 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_DQS), GPIO_PULLUP_ONLY);
91 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D4), GPIO_PULLUP_ONLY);
92 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D5), GPIO_PULLUP_ONLY);
93 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D6), GPIO_PULLUP_ONLY);
94 gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D7), GPIO_PULLUP_ONLY);
95 }
96 #endif // SOC_SPI_MEM_SUPPORT_OPI_MODE
97 #endif // CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU
98 }
99
esp_sleep_enable_gpio_switch(bool enable)100 void esp_sleep_enable_gpio_switch(bool enable)
101 {
102 ESP_EARLY_LOGI(TAG, "%s automatic switching of GPIO sleep configuration", enable ? "Enable" : "Disable");
103 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
104 if (GPIO_IS_VALID_GPIO(gpio_num)) {
105 if (enable) {
106 gpio_sleep_sel_en(gpio_num);
107 } else {
108 gpio_sleep_sel_dis(gpio_num);
109 }
110 }
111 }
112 }
113
114 #if !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
esp_sleep_isolate_digital_gpio(void)115 IRAM_ATTR void esp_sleep_isolate_digital_gpio(void)
116 {
117 gpio_hal_context_t gpio_hal = {
118 .dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
119 };
120
121 /* no need to do isolate if digital IOs are not being held in deep sleep */
122 if (!gpio_hal_deep_sleep_hold_is_en(&gpio_hal)) {
123 return;
124 }
125
126 /**
127 * there is a situation where we cannot isolate digital IO before deep sleep:
128 * - task stack is located in external ram(mspi ram), since we will isolate mspi io
129 *
130 * assert here instead of returning directly, because if digital IO is not isolated,
131 * the bottom current of deep sleep will be higher than light sleep, and there is no
132 * reason to use deep sleep at this time.
133 */
134 assert(esp_ptr_internal(&gpio_hal) && "If hold digital IO, the stack of the task calling esp_deep_sleep_start must be in internal ram!");
135
136 /* isolate digital IO that is not held(keep the configuration of digital IOs held by users) */
137 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
138 if (GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) && !gpio_hal_is_digital_io_hold(&gpio_hal, gpio_num)) {
139 /* disable I/O */
140 gpio_hal_input_disable(&gpio_hal, gpio_num);
141 gpio_hal_output_disable(&gpio_hal, gpio_num);
142
143 /* disable pull up/down */
144 gpio_hal_pullup_dis(&gpio_hal, gpio_num);
145 gpio_hal_pulldown_dis(&gpio_hal, gpio_num);
146
147 /* make pad work as gpio(otherwise, deep sleep bottom current will rise) */
148 gpio_hal_func_sel(&gpio_hal, gpio_num, PIN_FUNC_GPIO);
149 }
150 }
151 }
152 #endif // !SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP
153
esp_deep_sleep_wakeup_io_reset(void)154 void esp_deep_sleep_wakeup_io_reset(void)
155 {
156 #if SOC_PM_SUPPORT_EXT1_WAKEUP
157 uint32_t rtc_io_mask = rtc_hal_ext1_get_wakeup_pins();
158 // Disable ext1 wakeup before releasing hold, such that wakeup status can reflect the correct wakeup pin
159 rtc_hal_ext1_clear_wakeup_pins();
160 for (int gpio_num = 0; gpio_num < SOC_GPIO_PIN_COUNT && rtc_io_mask != 0; ++gpio_num) {
161 int rtcio_num = rtc_io_num_map[gpio_num];
162 if ((rtc_io_mask & BIT(rtcio_num)) == 0) {
163 continue;
164 }
165 rtcio_hal_hold_disable(rtcio_num);
166 rtc_io_mask &= ~BIT(rtcio_num);
167 }
168 #endif
169
170 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
171 uint32_t dl_io_mask = SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK;
172 gpio_hal_context_t gpio_hal = {
173 .dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
174 };
175 while (dl_io_mask) {
176 int gpio_num = __builtin_ffs(dl_io_mask) - 1;
177 bool wakeup_io_enabled = gpio_hal_deepsleep_wakeup_is_enabled(&gpio_hal, gpio_num);
178 if (wakeup_io_enabled) {
179 // Disable the wakeup before releasing hold, such that wakeup status can reflect the correct wakeup pin
180 gpio_hal_deepsleep_wakeup_disable(&gpio_hal, gpio_num);
181 gpio_hal_hold_dis(&gpio_hal, gpio_num);
182 }
183 dl_io_mask &= ~BIT(gpio_num);
184 }
185 #endif
186 }
187
188 #if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND || CONFIG_PM_SLP_DISABLE_GPIO
189 ESP_SYSTEM_INIT_FN(esp_sleep_startup_init, BIT(0), 105)
190 {
191 /* If the TOP domain is powered off, the GPIO will also be powered off during sleep,
192 and all configurations in the sleep state of GPIO will not take effect.*/
193 #if !CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
194 // Configure to isolate (disable the Input/Output/Pullup/Pulldown
195 // function of the pin) all GPIO pins in sleep state
196 esp_sleep_config_gpio_isolate();
197 #endif
198 // Enable automatic switching of GPIO configuration
199 esp_sleep_enable_gpio_switch(true);
200 return ESP_OK;
201 }
202 #endif
203
