1 /** Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 #pragma once 16 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /** Configuration registers */ 24 /** Type of gpio_out_drt register 25 * Dedicated GPIO Directive Output register 26 */ 27 typedef union { 28 struct { 29 /** gpio_out_drt_vlaue : WO; bitpos: [7:0]; default: 0; 30 * This register is used to configure directive output value of 8-channel dedicated 31 * gpio. 32 */ 33 uint32_t gpio_out_drt_vlaue: 8; 34 uint32_t reserved8: 24; 35 }; 36 uint32_t val; 37 } dedic_gpio_out_drt_reg_t; 38 39 /** Type of gpio_out_msk register 40 * Dedicated GPIO Mask Output register 41 */ 42 typedef union { 43 struct { 44 /** gpio_out_value : WO; bitpos: [7:0]; default: 0; 45 * This register is used to configure masked output value of 8-channel dedicated gpio. 46 */ 47 uint32_t gpio_out_value: 8; 48 /** gpio_out_msk : WO; bitpos: [15:8]; default: 0; 49 * This register is used to configure channels which would be masked. 1: corresponding 50 * channel's output would be masked. 51 */ 52 uint32_t gpio_out_msk: 8; 53 uint32_t reserved16: 16; 54 }; 55 uint32_t val; 56 } dedic_gpio_out_msk_reg_t; 57 58 /** Type of gpio_out_idv register 59 * Dedicated GPIO Individual Output register 60 */ 61 typedef union { 62 struct { 63 /** gpio_out_idv_ch0 : WO; bitpos: [1:0]; default: 0; 64 * Configure channel 0 output value. 0: hold output value; 1: set output value; 2: 65 * clear output value; 3: inverse output value. 66 */ 67 uint32_t gpio_out_idv_ch0: 2; 68 /** gpio_out_idv_ch1 : WO; bitpos: [3:2]; default: 0; 69 * Configure channel 1 output value. 0: hold output value; 1: set output value; 2: 70 * clear output value; 3: inverse output value. 71 */ 72 uint32_t gpio_out_idv_ch1: 2; 73 /** gpio_out_idv_ch2 : WO; bitpos: [5:4]; default: 0; 74 * Configure channel 2 output value. 0: hold output value; 1: set output value; 2: 75 * clear output value; 3: inverse output value. 76 */ 77 uint32_t gpio_out_idv_ch2: 2; 78 /** gpio_out_idv_ch3 : WO; bitpos: [7:6]; default: 0; 79 * Configure channel 3 output value. 0: hold output value; 1: set output value; 2: 80 * clear output value; 3: inverse output value. 81 */ 82 uint32_t gpio_out_idv_ch3: 2; 83 /** gpio_out_idv_ch4 : WO; bitpos: [9:8]; default: 0; 84 * Configure channel 4 output value. 0: hold output value; 1: set output value; 2: 85 * clear output value; 3: inverse output value. 86 */ 87 uint32_t gpio_out_idv_ch4: 2; 88 /** gpio_out_idv_ch5 : WO; bitpos: [11:10]; default: 0; 89 * Configure channel 5 output value. 0: hold output value; 1: set output value; 2: 90 * clear output value; 3: inverse output value. 91 */ 92 uint32_t gpio_out_idv_ch5: 2; 93 /** gpio_out_idv_ch6 : WO; bitpos: [13:12]; default: 0; 94 * Configure channel 6 output value. 0: hold output value; 1: set output value; 2: 95 * clear output value; 3: inverse output value. 96 */ 97 uint32_t gpio_out_idv_ch6: 2; 98 /** gpio_out_idv_ch7 : WO; bitpos: [15:14]; default: 0; 99 * Configure channel 7 output value. 0: hold output value; 1: set output value; 2: 100 * clear output value; 3: inverse output value. 101 */ 102 uint32_t gpio_out_idv_ch7: 2; 103 uint32_t reserved16: 16; 104 }; 105 uint32_t val; 106 } dedic_gpio_out_idv_reg_t; 107 108 /** Type of gpio_out_cpu register 109 * Dedicated GPIO Output Mode Select register 110 */ 111 typedef union { 112 struct { 113 /** gpio_out_cpu_sel0 : R/W; bitpos: [0]; default: 0; 114 * Select gpio out value configured by registers or CPU instructors for channel 0. 1: 115 * select CPU instructors. 116 */ 117 uint32_t gpio_out_cpu_sel0: 1; 118 /** gpio_out_cpu_sel1 : R/W; bitpos: [1]; default: 0; 119 * Select gpio out value configured by registers or CPU instructors for channel 1. 1: 120 * select CPU instructors. 121 */ 122 uint32_t gpio_out_cpu_sel1: 1; 123 /** gpio_out_cpu_sel2 : R/W; bitpos: [2]; default: 0; 124 * Select gpio out value configured by registers or CPU instructors for channel 2. 1: 125 * select CPU instructors. 126 */ 127 uint32_t gpio_out_cpu_sel2: 1; 128 /** gpio_out_cpu_sel3 : R/W; bitpos: [3]; default: 0; 129 * Select gpio out value configured by registers or CPU instructors for channel 3. 1: 130 * select CPU instructors. 131 */ 132 uint32_t gpio_out_cpu_sel3: 1; 133 /** gpio_out_cpu_sel4 : R/W; bitpos: [4]; default: 0; 134 * Select gpio out value configured by registers or CPU instructors for channel 4. 1: 135 * select CPU instructors. 136 */ 137 uint32_t gpio_out_cpu_sel4: 1; 138 /** gpio_out_cpu_sel5 : R/W; bitpos: [5]; default: 0; 139 * Select gpio out value configured by registers or CPU instructors for channel 5. 1: 140 * select CPU instructors. 141 */ 142 uint32_t gpio_out_cpu_sel5: 1; 143 /** gpio_out_cpu_sel6 : R/W; bitpos: [6]; default: 0; 144 * Select gpio out value configured by registers or CPU instructors for channel 6. 1: 145 * select CPU instructors. 146 */ 147 uint32_t gpio_out_cpu_sel6: 1; 148 /** gpio_out_cpu_sel7 : R/W; bitpos: [7]; default: 0; 149 * Select gpio out value configured by registers or CPU instructors for channel 7. 1: 150 * select CPU instructors. 151 */ 152 uint32_t gpio_out_cpu_sel7: 1; 153 uint32_t reserved8: 24; 154 }; 155 uint32_t val; 156 } dedic_gpio_out_cpu_reg_t; 157 158 /** Type of gpio_in_dly register 159 * Dedicated GPIO Input Delay Configuration register 160 */ 161 typedef union { 162 struct { 163 /** gpio_in_dly_ch0 : R/W; bitpos: [1:0]; default: 0; 164 * Configure gpio 0 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 165 * 3: three clock delay. 166 */ 167 uint32_t gpio_in_dly_ch0: 2; 168 /** gpio_in_dly_ch1 : R/W; bitpos: [3:2]; default: 0; 169 * Configure gpio 1 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 170 * 3: three clock delay. 171 */ 172 uint32_t gpio_in_dly_ch1: 2; 173 /** gpio_in_dly_ch2 : R/W; bitpos: [5:4]; default: 0; 174 * Configure gpio 2 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 175 * 3: three clock delay. 176 */ 177 uint32_t gpio_in_dly_ch2: 2; 178 /** gpio_in_dly_ch3 : R/W; bitpos: [7:6]; default: 0; 179 * Configure gpio 3 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 180 * 3: three clock delay. 181 */ 182 uint32_t gpio_in_dly_ch3: 2; 183 /** gpio_in_dly_ch4 : R/W; bitpos: [9:8]; default: 0; 184 * Configure gpio 4 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 185 * 3: three clock delay. 186 */ 187 uint32_t gpio_in_dly_ch4: 2; 188 /** gpio_in_dly_ch5 : R/W; bitpos: [11:10]; default: 0; 189 * Configure gpio 5 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 190 * 3: three clock delay. 191 */ 192 uint32_t gpio_in_dly_ch5: 2; 193 /** gpio_in_dly_ch6 : R/W; bitpos: [13:12]; default: 0; 194 * Configure gpio 6 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 195 * 3: three clock delay. 196 */ 197 uint32_t gpio_in_dly_ch6: 2; 198 /** gpio_in_dly_ch7 : R/W; bitpos: [15:14]; default: 0; 199 * Configure gpio 7 input delay. 0: No delay; 1: one clock delay; 2: two clock delay; 200 * 3: three clock delay. 201 */ 202 uint32_t gpio_in_dly_ch7: 2; 203 uint32_t reserved16: 16; 204 }; 205 uint32_t val; 206 } dedic_gpio_in_dly_reg_t; 207 208 /** Type of gpio_intr_rcgn register 209 * Dedicated GPIO Interrupts Generate Mode register 210 */ 211 typedef union { 212 struct { 213 /** gpio_intr_mode_ch0 : R/W; bitpos: [2:0]; default: 0; 214 * Configure channel 0 interrupt generate mode. 215 * 0/1: do not generate interrupt; 216 * 2: low level trigger; 217 * 3: high level trigger; 218 * 4: falling edge trigger; 219 * 5: raising edge trigger; 220 * 6/7: falling and raising edge trigger. 221 */ 222 uint32_t gpio_intr_mode_ch0: 3; 223 /** gpio_intr_mode_ch1 : R/W; bitpos: [5:3]; default: 0; 224 * Configure channel 1 interrupt generate mode. 225 * 0/1: do not generate interrupt; 226 * 2: low level trigger; 227 * 3: high level trigger; 228 * 4: falling edge trigger; 229 * 5: raising edge trigger; 230 * 6/7: falling and raising edge trigger. 231 */ 232 uint32_t gpio_intr_mode_ch1: 3; 233 /** gpio_intr_mode_ch2 : R/W; bitpos: [8:6]; default: 0; 234 * Configure channel 2 interrupt generate mode. 235 * 0/1: do not generate interrupt; 236 * 2: low level trigger; 237 * 3: high level trigger; 238 * 4: falling edge trigger; 239 * 5: raising edge trigger; 240 * 6/7: falling and raising edge trigger. 241 */ 242 uint32_t gpio_intr_mode_ch2: 3; 243 /** gpio_intr_mode_ch3 : R/W; bitpos: [11:9]; default: 0; 244 * Configure channel 3 interrupt generate mode. 245 * 0/1: do not generate interrupt; 246 * 2: low level trigger; 247 * 3: high level trigger; 248 * 4: falling edge trigger; 249 * 5: raising edge trigger; 250 * 6/7: falling and raising edge trigger. 251 */ 252 uint32_t gpio_intr_mode_ch3: 3; 253 /** gpio_intr_mode_ch4 : R/W; bitpos: [14:12]; default: 0; 254 * Configure channel 4 interrupt generate mode. 255 * 0/1: do not generate interrupt; 256 * 2: low level trigger; 257 * 3: high level trigger; 258 * 4: falling edge trigger; 259 * 5: raising edge trigger; 260 * 6/7: falling and raising edge trigger. 261 */ 262 uint32_t gpio_intr_mode_ch4: 3; 263 /** gpio_intr_mode_ch5 : R/W; bitpos: [17:15]; default: 0; 264 * Configure channel 5 interrupt generate mode. 265 * 0/1: do not generate interrupt; 266 * 2: low level trigger; 267 * 3: high level trigger; 268 * 4: falling edge trigger; 269 * 5: raising edge trigger; 270 * 6/7: falling and raising edge trigger. 271 */ 272 uint32_t gpio_intr_mode_ch5: 3; 273 /** gpio_intr_mode_ch6 : R/W; bitpos: [20:18]; default: 0; 274 * Configure channel 6 interrupt generate mode. 275 * 0/1: do not generate interrupt; 276 * 2: low level trigger; 277 * 3: high level trigger; 278 * 4: falling edge trigger; 279 * 5: raising edge trigger; 280 * 6/7: falling and raising edge trigger. 281 */ 282 uint32_t gpio_intr_mode_ch6: 3; 283 /** gpio_intr_mode_ch7 : R/W; bitpos: [23:21]; default: 0; 284 * Configure channel 7 interrupt generate mode. 285 * 0/1: do not generate interrupt; 286 * 2: low level trigger; 287 * 3: high level trigger; 288 * 4: falling edge trigger; 289 * 5: raising edge trigger; 290 * 6/7: falling and raising edge trigger. 291 */ 292 uint32_t gpio_intr_mode_ch7: 3; 293 uint32_t reserved24: 8; 294 }; 295 uint32_t val; 296 } dedic_gpio_intr_rcgn_reg_t; 297 298 299 /** Status registers */ 300 /** Type of gpio_out_scan register 301 * Dedicated GPIO Output Status register 302 */ 303 typedef union { 304 struct { 305 /** gpio_out_status : RO; bitpos: [7:0]; default: 0; 306 * gpio out value configured by DEDIC_GPIO_OUT_DRT_REG, DEDIC_GPIO_OUT_MSK_REG, 307 * DEDIC_GPIO_OUT_IDV_REG. 308 */ 309 uint32_t gpio_out_status: 8; 310 uint32_t reserved8: 24; 311 }; 312 uint32_t val; 313 } dedic_gpio_out_scan_reg_t; 314 315 /** Type of gpio_in_scan register 316 * Dedicated GPIO Input Status register 317 */ 318 typedef union { 319 struct { 320 /** gpio_in_status : RO; bitpos: [7:0]; default: 0; 321 * gpio in value after configured by DEDIC_GPIO_IN_DLY_REG. 322 */ 323 uint32_t gpio_in_status: 8; 324 uint32_t reserved8: 24; 325 }; 326 uint32_t val; 327 } dedic_gpio_in_scan_reg_t; 328 329 330 /** Interrupt registers */ 331 /** Type of gpio_intr_raw register 332 * Raw interrupt status 333 */ 334 typedef union { 335 struct { 336 /** gpio0_int_raw : RO; bitpos: [0]; default: 0; 337 * This interrupt raw bit turns to high level when dedicated GPIO 0 has level/edge 338 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 339 */ 340 uint32_t gpio0_int_raw: 1; 341 /** gpio1_int_raw : RO; bitpos: [1]; default: 0; 342 * This interrupt raw bit turns to high level when dedicated GPIO 1 has level/edge 343 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 344 */ 345 uint32_t gpio1_int_raw: 1; 346 /** gpio2_int_raw : RO; bitpos: [2]; default: 0; 347 * This interrupt raw bit turns to high level when dedicated GPIO 2 has level/edge 348 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 349 */ 350 uint32_t gpio2_int_raw: 1; 351 /** gpio3_int_raw : RO; bitpos: [3]; default: 0; 352 * This interrupt raw bit turns to high level when dedicated GPIO 3 has level/edge 353 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 354 */ 355 uint32_t gpio3_int_raw: 1; 356 /** gpio4_int_raw : RO; bitpos: [4]; default: 0; 357 * This interrupt raw bit turns to high level when dedicated GPIO 4 has level/edge 358 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 359 */ 360 uint32_t gpio4_int_raw: 1; 361 /** gpio5_int_raw : RO; bitpos: [5]; default: 0; 362 * This interrupt raw bit turns to high level when dedicated GPIO 5 has level/edge 363 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 364 */ 365 uint32_t gpio5_int_raw: 1; 366 /** gpio6_int_raw : RO; bitpos: [6]; default: 0; 367 * This interrupt raw bit turns to high level when dedicated GPIO 6 has level/edge 368 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 369 */ 370 uint32_t gpio6_int_raw: 1; 371 /** gpio7_int_raw : RO; bitpos: [7]; default: 0; 372 * This interrupt raw bit turns to high level when dedicated GPIO 7 has level/edge 373 * change configured by DEDIC_GPIO_INTR_RCGN_REG. 374 */ 375 uint32_t gpio7_int_raw: 1; 376 uint32_t reserved8: 24; 377 }; 378 uint32_t val; 379 } dedic_gpio_intr_raw_reg_t; 380 381 /** Type of gpio_intr_rls register 382 * Interrupt enable bits 383 */ 384 typedef union { 385 struct { 386 /** gpio0_int_ena : R/W; bitpos: [0]; default: 0; 387 * This enable bit for reg_gpio0_int_st register. 388 */ 389 uint32_t gpio0_int_ena: 1; 390 /** gpio1_int_ena : R/W; bitpos: [1]; default: 0; 391 * This enable bit for reg_gpio1_int_st register. 392 */ 393 uint32_t gpio1_int_ena: 1; 394 /** gpio2_int_ena : R/W; bitpos: [2]; default: 0; 395 * This enable bit for reg_gpio2_int_st register. 396 */ 397 uint32_t gpio2_int_ena: 1; 398 /** gpio3_int_ena : R/W; bitpos: [3]; default: 0; 399 * This enable bit for reg_gpio3_int_st register. 400 */ 401 uint32_t gpio3_int_ena: 1; 402 /** gpio4_int_ena : R/W; bitpos: [4]; default: 0; 403 * This enable bit for reg_gpio4_int_st register. 404 */ 405 uint32_t gpio4_int_ena: 1; 406 /** gpio5_int_ena : R/W; bitpos: [5]; default: 0; 407 * This enable bit for reg_gpio5_int_st register. 408 */ 409 uint32_t gpio5_int_ena: 1; 410 /** gpio6_int_ena : R/W; bitpos: [6]; default: 0; 411 * This enable bit for reg_gpio6_int_st register. 412 */ 413 uint32_t gpio6_int_ena: 1; 414 /** gpio7_int_ena : R/W; bitpos: [7]; default: 0; 415 * This enable bit for reg_gpio7_int_st register. 416 */ 417 uint32_t gpio7_int_ena: 1; 418 uint32_t reserved8: 24; 419 }; 420 uint32_t val; 421 } dedic_gpio_intr_rls_reg_t; 422 423 /** Type of gpio_intr_st register 424 * Masked interrupt status 425 */ 426 typedef union { 427 struct { 428 /** gpio0_int_st : RO; bitpos: [0]; default: 0; 429 * This is the status bit for reg_gpio0_int_raw when reg_gpio0_int_ena is set to 1. 430 */ 431 uint32_t gpio0_int_st: 1; 432 /** gpio1_int_st : RO; bitpos: [1]; default: 0; 433 * This is the status bit for reg_gpio1_int_raw when reg_gpio1_int_ena is set to 1. 434 */ 435 uint32_t gpio1_int_st: 1; 436 /** gpio2_int_st : RO; bitpos: [2]; default: 0; 437 * This is the status bit for reg_gpio2_int_raw when reg_gpio2_int_ena is set to 1. 438 */ 439 uint32_t gpio2_int_st: 1; 440 /** gpio3_int_st : RO; bitpos: [3]; default: 0; 441 * This is the status bit for reg_gpio3_int_raw when reg_gpio3_int_ena is set to 1. 442 */ 443 uint32_t gpio3_int_st: 1; 444 /** gpio4_int_st : RO; bitpos: [4]; default: 0; 445 * This is the status bit for reg_gpio4_int_raw when reg_gpio4_int_ena is set to 1. 446 */ 447 uint32_t gpio4_int_st: 1; 448 /** gpio5_int_st : RO; bitpos: [5]; default: 0; 449 * This is the status bit for reg_gpio5_int_raw when reg_gpio5_int_ena is set to 1. 450 */ 451 uint32_t gpio5_int_st: 1; 452 /** gpio6_int_st : RO; bitpos: [6]; default: 0; 453 * This is the status bit for reg_gpio6_int_raw when reg_gpio6_int_ena is set to 1. 454 */ 455 uint32_t gpio6_int_st: 1; 456 /** gpio7_int_st : RO; bitpos: [7]; default: 0; 457 * This is the status bit for reg_gpio7_int_raw when reg_gpio7_int_ena is set to 1. 458 */ 459 uint32_t gpio7_int_st: 1; 460 uint32_t reserved8: 24; 461 }; 462 uint32_t val; 463 } dedic_gpio_intr_st_reg_t; 464 465 /** Type of gpio_intr_clr register 466 * Interrupt clear bits 467 */ 468 typedef union { 469 struct { 470 /** gpio0_int_clr : WO; bitpos: [0]; default: 0; 471 * Set this bit to clear the reg_gpio0_int_raw interrupt. 472 */ 473 uint32_t gpio0_int_clr: 1; 474 /** gpio1_int_clr : WO; bitpos: [1]; default: 0; 475 * Set this bit to clear the reg_gpio1_int_raw interrupt. 476 */ 477 uint32_t gpio1_int_clr: 1; 478 /** gpio2_int_clr : WO; bitpos: [2]; default: 0; 479 * Set this bit to clear the reg_gpio2_int_raw interrupt. 480 */ 481 uint32_t gpio2_int_clr: 1; 482 /** gpio3_int_clr : WO; bitpos: [3]; default: 0; 483 * Set this bit to clear the reg_gpio3_int_raw interrupt. 484 */ 485 uint32_t gpio3_int_clr: 1; 486 /** gpio4_int_clr : WO; bitpos: [4]; default: 0; 487 * Set this bit to clear the reg_gpio4_int_raw interrupt. 488 */ 489 uint32_t gpio4_int_clr: 1; 490 /** gpio5_int_clr : WO; bitpos: [5]; default: 0; 491 * Set this bit to clear the reg_gpio5_int_raw interrupt. 492 */ 493 uint32_t gpio5_int_clr: 1; 494 /** gpio6_int_clr : WO; bitpos: [6]; default: 0; 495 * Set this bit to clear the reg_gpio6_int_raw interrupt. 496 */ 497 uint32_t gpio6_int_clr: 1; 498 /** gpio7_int_clr : WO; bitpos: [7]; default: 0; 499 * Set this bit to clear the reg_gpio7_int_raw interrupt. 500 */ 501 uint32_t gpio7_int_clr: 1; 502 uint32_t reserved8: 24; 503 }; 504 uint32_t val; 505 } dedic_gpio_intr_clr_reg_t; 506 507 typedef struct { 508 volatile dedic_gpio_out_drt_reg_t gpio_out_drt; 509 volatile dedic_gpio_out_msk_reg_t gpio_out_msk; 510 volatile dedic_gpio_out_idv_reg_t gpio_out_idv; 511 volatile dedic_gpio_out_scan_reg_t gpio_out_scan; 512 volatile dedic_gpio_out_cpu_reg_t gpio_out_cpu; 513 volatile dedic_gpio_in_dly_reg_t gpio_in_dly; 514 volatile dedic_gpio_in_scan_reg_t gpio_in_scan; 515 volatile dedic_gpio_intr_rcgn_reg_t gpio_intr_rcgn; 516 volatile dedic_gpio_intr_raw_reg_t gpio_intr_raw; 517 volatile dedic_gpio_intr_rls_reg_t gpio_intr_rls; 518 volatile dedic_gpio_intr_st_reg_t gpio_intr_st; 519 volatile dedic_gpio_intr_clr_reg_t gpio_intr_clr; 520 } dedic_dev_t; 521 522 _Static_assert(sizeof(dedic_dev_t) == 0x30, "dedic_dev_t should occupy 0x30 bytes in memory"); 523 524 extern dedic_dev_t DEDIC_GPIO; 525 526 #ifdef __cplusplus 527 } 528 #endif 529
