1/* 2 * Copyright (c) 2017-2019 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7#include "skeleton.dtsi" 8#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h> 9#include <zephyr/dt-bindings/i2c/i2c.h> 10#include <zephyr/dt-bindings/pcie/pcie.h> 11 12/ { 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "intel,apollo-lake", "intel,x86_64"; 20 d-cache-line-size = <64>; 21 reg = <0>; 22 }; 23 24 }; 25 26 dram0: memory@0 { 27 device_type = "memory"; 28 reg = <0x0 DT_DRAM_SIZE>; 29 }; 30 31 intc: ioapic@fec00000 { 32 compatible = "intel,ioapic"; 33 #address-cells = <1>; 34 #interrupt-cells = <3>; 35 reg = <0xfec00000 0x1000>; 36 interrupt-controller; 37 }; 38 39 intc_loapic: loapic@fee00000 { 40 compatible = "intel,loapic"; 41 reg = <0xfee00000 0x1000>; 42 interrupt-controller; 43 #interrupt-cells = <3>; 44 #address-cells = <1>; 45 }; 46 47 pcie0: pcie0 { 48 #address-cells = <1>; 49 #size-cells = <1>; 50 compatible = "pcie-controller"; 51 acpi-hid = "PNP0A08"; 52 ranges; 53 54 uart0: uart0 { 55 compatible = "ns16550"; 56 57 vendor-id = <0x8086>; 58 device-id = <0x5abc>; 59 60 reg-shift = <2>; 61 clock-frequency = <1843200>; 62 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 63 interrupt-parent = <&intc>; 64 status = "okay"; 65 current-speed = <115200>; 66 }; 67 68 uart1: uart1 { 69 compatible = "ns16550"; 70 71 vendor-id = <0x8086>; 72 device-id = <0x5abe>; 73 74 reg-shift = <2>; 75 clock-frequency = <1843200>; 76 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 77 interrupt-parent = <&intc>; 78 79 status = "okay"; 80 current-speed = <115200>; 81 }; 82 83 uart2: uart2 { 84 compatible = "ns16550"; 85 86 vendor-id = <0x8086>; 87 device-id = <0x5ac0>; 88 89 reg-shift = <2>; 90 clock-frequency = <1843200>; 91 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 92 interrupt-parent = <&intc>; 93 94 status = "okay"; 95 current-speed = <115200>; 96 }; 97 98 uart3: uart3 { 99 compatible = "ns16550"; 100 101 vendor-id = <0x8086>; 102 device-id = <0x5aee>; 103 104 reg-shift = <2>; 105 clock-frequency = <1843200>; 106 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 107 interrupt-parent = <&intc>; 108 109 status = "okay"; 110 current-speed = <115200>; 111 }; 112 113 i2c0: i2c0 { 114 compatible = "snps,designware-i2c"; 115 clock-frequency = <I2C_BITRATE_STANDARD>; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 vendor-id = <0x8086>; 119 device-id = <0x5aac>; 120 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 121 interrupt-parent = <&intc>; 122 123 status = "okay"; 124 }; 125 126 i2c1: i2c1 { 127 compatible = "snps,designware-i2c"; 128 clock-frequency = <I2C_BITRATE_STANDARD>; 129 #address-cells = <1>; 130 #size-cells = <0>; 131 vendor-id = <0x8086>; 132 device-id = <0x5aae>; 133 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 134 interrupt-parent = <&intc>; 135 136 status = "okay"; 137 }; 138 139 i2c2: i2c2 { 140 compatible = "snps,designware-i2c"; 141 clock-frequency = <I2C_BITRATE_STANDARD>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 vendor-id = <0x8086>; 145 device-id = <0x5ab0>; 146 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 147 interrupt-parent = <&intc>; 148 149 status = "okay"; 150 }; 151 152 i2c3: i2c3 { 153 compatible = "snps,designware-i2c"; 154 clock-frequency = <I2C_BITRATE_STANDARD>; 155 #address-cells = <1>; 156 #size-cells = <0>; 157 vendor-id = <0x8006>; 158 device-id = <0x5ab2>; 159 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 160 interrupt-parent = <&intc>; 161 162 status = "okay"; 163 }; 164 165 i2c4: i2c4 { 166 compatible = "snps,designware-i2c"; 167 clock-frequency = <I2C_BITRATE_STANDARD>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 vendor-id = <0x8086>; 171 device-id = <0x5ab4>; 172 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 173 interrupt-parent = <&intc>; 174 175 status = "okay"; 176 }; 177 178 i2c5: i2c5{ 179 compatible = "snps,designware-i2c"; 180 clock-frequency = <I2C_BITRATE_STANDARD>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 vendor-id = <0x8086>; 184 device-id = <0x5ab6>; 185 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 186 interrupt-parent = <&intc>; 187 188 status = "okay"; 189 }; 190 191 i2c6: i2c6 { 192 compatible = "snps,designware-i2c"; 193 clock-frequency = <I2C_BITRATE_STANDARD>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 vendor-id = <0x8086>; 197 device-id = <0x5ab8>; 198 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 199 interrupt-parent = <&intc>; 200 201 status = "okay"; 202 }; 203 204 i2c7: i2c7 { 205 compatible = "snps,designware-i2c"; 206 clock-frequency = <I2C_BITRATE_STANDARD>; 207 #address-cells = <1>; 208 #size-cells = <0>; 209 vendor-id = <0x8086>; 210 device-id = <0x5aba>; 211 interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 212 interrupt-parent = <&intc>; 213 214 status = "okay"; 215 }; 216 }; 217 218 soc { 219 #address-cells = <1>; 220 #size-cells = <1>; 221 compatible = "simple-bus"; 222 ranges; 223 224 vtd: vtd@fed65000 { 225 compatible = "intel,vt-d"; 226 227 reg = <0xfed65000 0x1000>; 228 229 status = "okay"; 230 }; 231 232 gpio_n_000_031: gpio@d0c50000 { 233 compatible = "intel,gpio"; 234 reg = <0xd0c50000 0x1000>; 235 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 236 interrupt-parent = <&intc>; 237 238 gpio-controller; 239 #gpio-cells = <2>; 240 241 ngpios = <32>; 242 pin-offset = <0>; 243 244 status = "okay"; 245 }; 246 247 gpio_n_032_063: gpio@d0c50001 { 248 compatible = "intel,gpio"; 249 reg = <0xd0c50001 0x1000>; 250 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 251 interrupt-parent = <&intc>; 252 253 gpio-controller; 254 #gpio-cells = <2>; 255 256 ngpios = <32>; 257 pin-offset = <32>; 258 259 status = "okay"; 260 }; 261 262 gpio_n_064_077: gpio@d0c50002 { 263 compatible = "intel,gpio"; 264 reg = <0xd0c50002 0x1000>; 265 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 266 interrupt-parent = <&intc>; 267 268 gpio-controller; 269 #gpio-cells = <2>; 270 271 ngpios = <14>; 272 pin-offset = <64>; 273 274 status = "okay"; 275 }; 276 277 gpio_nw_000_031: gpio@d0c40000 { 278 compatible = "intel,gpio"; 279 reg = <0xd0c40000 0x1000>; 280 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 281 interrupt-parent = <&intc>; 282 283 gpio-controller; 284 #gpio-cells = <2>; 285 286 ngpios = <32>; 287 pin-offset = <0>; 288 289 status = "okay"; 290 }; 291 292 gpio_nw_032_063: gpio@d0c40001 { 293 compatible = "intel,gpio"; 294 reg = <0xd0c40001 0x1000>; 295 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 296 interrupt-parent = <&intc>; 297 298 gpio-controller; 299 #gpio-cells = <2>; 300 301 ngpios = <32>; 302 pin-offset = <32>; 303 304 status = "okay"; 305 }; 306 307 gpio_nw_064_076: gpio@d0c40002 { 308 compatible = "intel,gpio"; 309 reg = <0xd0c40002 0x1000>; 310 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 311 interrupt-parent = <&intc>; 312 313 gpio-controller; 314 #gpio-cells = <2>; 315 316 ngpios = <13>; 317 pin-offset = <64>; 318 319 status = "okay"; 320 }; 321 322 gpio_w_000_031: gpio@d0c70000 { 323 compatible = "intel,gpio"; 324 reg = <0xd0c70000 0x1000>; 325 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 326 interrupt-parent = <&intc>; 327 328 gpio-controller; 329 #gpio-cells = <2>; 330 331 ngpios = <32>; 332 pin-offset = <0>; 333 334 status = "okay"; 335 }; 336 337 gpio_w_032_046: gpio@d0c70001 { 338 compatible = "intel,gpio"; 339 reg = <0xd0c70001 0x1000>; 340 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 341 interrupt-parent = <&intc>; 342 343 gpio-controller; 344 #gpio-cells = <2>; 345 346 ngpios = <15>; 347 pin-offset = <32>; 348 349 status = "okay"; 350 }; 351 352 gpio_sw_000_031: gpio@d0c00000 { 353 compatible = "intel,gpio"; 354 reg = <0xd0c00000 0x1000>; 355 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 356 interrupt-parent = <&intc>; 357 358 gpio-controller; 359 #gpio-cells = <2>; 360 361 ngpios = <32>; 362 pin-offset = <0>; 363 364 status = "okay"; 365 }; 366 367 368 gpio_sw_032_042: gpio@d0c00001 { 369 compatible = "intel,gpio"; 370 reg = <0xd0c00001 0x1000>; 371 interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>; 372 interrupt-parent = <&intc>; 373 374 gpio-controller; 375 #gpio-cells = <2>; 376 377 ngpios = <11>; 378 pin-offset = <32>; 379 380 status = "okay"; 381 }; 382 383 hpet: hpet@fed00000 { 384 compatible = "intel,hpet"; 385 reg = <0xfed00000 0x400>; 386 interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; 387 interrupt-parent = <&intc>; 388 389 status = "okay"; 390 }; 391 392 rtc: counter: rtc@70 { 393 compatible = "motorola,mc146818"; 394 reg = <0x70 0x0D 0x71 0x0D>; 395 interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; 396 interrupt-parent = <&intc>; 397 alarms-count = <1>; 398 399 status = "okay"; 400 }; 401 }; 402 403 gpio_n: gpio-north { 404 /* n north 78 */ 405 compatible = "intel,apollo-lake-gpio"; 406 #gpio-cells = <2>; 407 gpio-map-mask = <0xffffffff 0xffffffc0>; 408 gpio-map-pass-thru = <0 0x3f>; 409 gpio-map = 410 <0 0 &gpio_n_000_031 0 0>, 411 <1 0 &gpio_n_000_031 1 0>, 412 <2 0 &gpio_n_000_031 2 0>, 413 <3 0 &gpio_n_000_031 3 0>, 414 <4 0 &gpio_n_000_031 4 0>, 415 <5 0 &gpio_n_000_031 5 0>, 416 <6 0 &gpio_n_000_031 6 0>, 417 <7 0 &gpio_n_000_031 7 0>, 418 <8 0 &gpio_n_000_031 8 0>, 419 <9 0 &gpio_n_000_031 9 0>, 420 <10 0 &gpio_n_000_031 10 0>, 421 <11 0 &gpio_n_000_031 11 0>, 422 <12 0 &gpio_n_000_031 12 0>, 423 <13 0 &gpio_n_000_031 13 0>, 424 <14 0 &gpio_n_000_031 14 0>, 425 <15 0 &gpio_n_000_031 15 0>, 426 <16 0 &gpio_n_000_031 16 0>, 427 <17 0 &gpio_n_000_031 17 0>, 428 <18 0 &gpio_n_000_031 18 0>, 429 <19 0 &gpio_n_000_031 19 0>, 430 <20 0 &gpio_n_000_031 20 0>, 431 <21 0 &gpio_n_000_031 21 0>, 432 <22 0 &gpio_n_000_031 22 0>, 433 <23 0 &gpio_n_000_031 23 0>, 434 <24 0 &gpio_n_000_031 24 0>, 435 <25 0 &gpio_n_000_031 25 0>, 436 <26 0 &gpio_n_000_031 26 0>, 437 <27 0 &gpio_n_000_031 27 0>, 438 <28 0 &gpio_n_000_031 28 0>, 439 <29 0 &gpio_n_000_031 29 0>, 440 <30 0 &gpio_n_000_031 30 0>, 441 <31 0 &gpio_n_000_031 31 0>, 442 <32 0 &gpio_n_032_063 0 0>, 443 <33 0 &gpio_n_032_063 1 0>, 444 <34 0 &gpio_n_032_063 2 0>, 445 <35 0 &gpio_n_032_063 3 0>, 446 <36 0 &gpio_n_032_063 4 0>, 447 <37 0 &gpio_n_032_063 5 0>, 448 <38 0 &gpio_n_032_063 6 0>, 449 <39 0 &gpio_n_032_063 7 0>, 450 <40 0 &gpio_n_032_063 8 0>, 451 <41 0 &gpio_n_032_063 9 0>, 452 <42 0 &gpio_n_032_063 10 0>, 453 <43 0 &gpio_n_032_063 11 0>, 454 <44 0 &gpio_n_032_063 12 0>, 455 <45 0 &gpio_n_032_063 13 0>, 456 <46 0 &gpio_n_032_063 14 0>, 457 <47 0 &gpio_n_032_063 15 0>, 458 <48 0 &gpio_n_032_063 16 0>, 459 <49 0 &gpio_n_032_063 17 0>, 460 <50 0 &gpio_n_032_063 18 0>, 461 <51 0 &gpio_n_032_063 19 0>, 462 <52 0 &gpio_n_032_063 20 0>, 463 <53 0 &gpio_n_032_063 21 0>, 464 <54 0 &gpio_n_032_063 22 0>, 465 <55 0 &gpio_n_032_063 23 0>, 466 <56 0 &gpio_n_032_063 24 0>, 467 <57 0 &gpio_n_032_063 25 0>, 468 <58 0 &gpio_n_032_063 26 0>, 469 <59 0 &gpio_n_032_063 27 0>, 470 <60 0 &gpio_n_032_063 28 0>, 471 <61 0 &gpio_n_032_063 29 0>, 472 <62 0 &gpio_n_032_063 30 0>, 473 <63 0 &gpio_n_032_063 31 0>, 474 <64 0 &gpio_n_064_077 0 0>, 475 <65 0 &gpio_n_064_077 1 0>, 476 <66 0 &gpio_n_064_077 2 0>, 477 <67 0 &gpio_n_064_077 3 0>, 478 <68 0 &gpio_n_064_077 4 0>, 479 <69 0 &gpio_n_064_077 5 0>, 480 <70 0 &gpio_n_064_077 6 0>, 481 <71 0 &gpio_n_064_077 7 0>, 482 <72 0 &gpio_n_064_077 8 0>, 483 <73 0 &gpio_n_064_077 9 0>, 484 <74 0 &gpio_n_064_077 10 0>, 485 <75 0 &gpio_n_064_077 11 0>, 486 <76 0 &gpio_n_064_077 12 0>, 487 <77 0 &gpio_n_064_077 13 0>; 488 }; 489 490 gpio_nw: gpio-northwest { 491 /* nw northwest 77 */ 492 compatible = "intel,apollo-lake-gpio"; 493 #gpio-cells = <2>; 494 gpio-map-mask = <0xffffffff 0xffffffc0>; 495 gpio-map-pass-thru = <0 0x3f>; 496 gpio-map = 497 <0 0 &gpio_nw_000_031 0 0>, 498 <1 0 &gpio_nw_000_031 1 0>, 499 <2 0 &gpio_nw_000_031 2 0>, 500 <3 0 &gpio_nw_000_031 3 0>, 501 <4 0 &gpio_nw_000_031 4 0>, 502 <5 0 &gpio_nw_000_031 5 0>, 503 <6 0 &gpio_nw_000_031 6 0>, 504 <7 0 &gpio_nw_000_031 7 0>, 505 <8 0 &gpio_nw_000_031 8 0>, 506 <9 0 &gpio_nw_000_031 9 0>, 507 <10 0 &gpio_nw_000_031 10 0>, 508 <11 0 &gpio_nw_000_031 11 0>, 509 <12 0 &gpio_nw_000_031 12 0>, 510 <13 0 &gpio_nw_000_031 13 0>, 511 <14 0 &gpio_nw_000_031 14 0>, 512 <15 0 &gpio_nw_000_031 15 0>, 513 <16 0 &gpio_nw_000_031 16 0>, 514 <17 0 &gpio_nw_000_031 17 0>, 515 <18 0 &gpio_nw_000_031 18 0>, 516 <19 0 &gpio_nw_000_031 19 0>, 517 <20 0 &gpio_nw_000_031 20 0>, 518 <21 0 &gpio_nw_000_031 21 0>, 519 <22 0 &gpio_nw_000_031 22 0>, 520 <23 0 &gpio_nw_000_031 23 0>, 521 <24 0 &gpio_nw_000_031 24 0>, 522 <25 0 &gpio_nw_000_031 25 0>, 523 <26 0 &gpio_nw_000_031 26 0>, 524 <27 0 &gpio_nw_000_031 27 0>, 525 <28 0 &gpio_nw_000_031 28 0>, 526 <29 0 &gpio_nw_000_031 29 0>, 527 <30 0 &gpio_nw_000_031 30 0>, 528 <31 0 &gpio_nw_000_031 31 0>, 529 <32 0 &gpio_nw_032_063 0 0>, 530 <33 0 &gpio_nw_032_063 1 0>, 531 <34 0 &gpio_nw_032_063 2 0>, 532 <35 0 &gpio_nw_032_063 3 0>, 533 <36 0 &gpio_nw_032_063 4 0>, 534 <37 0 &gpio_nw_032_063 5 0>, 535 <38 0 &gpio_nw_032_063 6 0>, 536 <39 0 &gpio_nw_032_063 7 0>, 537 <40 0 &gpio_nw_032_063 8 0>, 538 <41 0 &gpio_nw_032_063 9 0>, 539 <42 0 &gpio_nw_032_063 10 0>, 540 <43 0 &gpio_nw_032_063 11 0>, 541 <44 0 &gpio_nw_032_063 12 0>, 542 <45 0 &gpio_nw_032_063 13 0>, 543 <46 0 &gpio_nw_032_063 14 0>, 544 <47 0 &gpio_nw_032_063 15 0>, 545 <48 0 &gpio_nw_032_063 16 0>, 546 <49 0 &gpio_nw_032_063 17 0>, 547 <50 0 &gpio_nw_032_063 18 0>, 548 <51 0 &gpio_nw_032_063 19 0>, 549 <52 0 &gpio_nw_032_063 20 0>, 550 <53 0 &gpio_nw_032_063 21 0>, 551 <54 0 &gpio_nw_032_063 22 0>, 552 <55 0 &gpio_nw_032_063 23 0>, 553 <56 0 &gpio_nw_032_063 24 0>, 554 <57 0 &gpio_nw_032_063 25 0>, 555 <58 0 &gpio_nw_032_063 26 0>, 556 <59 0 &gpio_nw_032_063 27 0>, 557 <60 0 &gpio_nw_032_063 28 0>, 558 <61 0 &gpio_nw_032_063 29 0>, 559 <62 0 &gpio_nw_032_063 30 0>, 560 <63 0 &gpio_nw_032_063 31 0>, 561 <64 0 &gpio_nw_064_076 0 0>, 562 <65 0 &gpio_nw_064_076 1 0>, 563 <66 0 &gpio_nw_064_076 2 0>, 564 <67 0 &gpio_nw_064_076 3 0>, 565 <68 0 &gpio_nw_064_076 4 0>, 566 <69 0 &gpio_nw_064_076 5 0>, 567 <70 0 &gpio_nw_064_076 6 0>, 568 <71 0 &gpio_nw_064_076 7 0>, 569 <72 0 &gpio_nw_064_076 8 0>, 570 <73 0 &gpio_nw_064_076 9 0>, 571 <74 0 &gpio_nw_064_076 10 0>, 572 <75 0 &gpio_nw_064_076 11 0>, 573 <76 0 &gpio_nw_064_076 12 0>; 574 }; 575 576 gpio_w: gpio-west { 577 /* w west 47 */ 578 compatible = "intel,apollo-lake-gpio"; 579 #gpio-cells = <2>; 580 gpio-map-mask = <0xffffffff 0xffffffc0>; 581 gpio-map-pass-thru = <0 0x3f>; 582 gpio-map = 583 <0 0 &gpio_w_000_031 0 0>, 584 <1 0 &gpio_w_000_031 1 0>, 585 <2 0 &gpio_w_000_031 2 0>, 586 <3 0 &gpio_w_000_031 3 0>, 587 <4 0 &gpio_w_000_031 4 0>, 588 <5 0 &gpio_w_000_031 5 0>, 589 <6 0 &gpio_w_000_031 6 0>, 590 <7 0 &gpio_w_000_031 7 0>, 591 <8 0 &gpio_w_000_031 8 0>, 592 <9 0 &gpio_w_000_031 9 0>, 593 <10 0 &gpio_w_000_031 10 0>, 594 <11 0 &gpio_w_000_031 11 0>, 595 <12 0 &gpio_w_000_031 12 0>, 596 <13 0 &gpio_w_000_031 13 0>, 597 <14 0 &gpio_w_000_031 14 0>, 598 <15 0 &gpio_w_000_031 15 0>, 599 <16 0 &gpio_w_000_031 16 0>, 600 <17 0 &gpio_w_000_031 17 0>, 601 <18 0 &gpio_w_000_031 18 0>, 602 <19 0 &gpio_w_000_031 19 0>, 603 <20 0 &gpio_w_000_031 20 0>, 604 <21 0 &gpio_w_000_031 21 0>, 605 <22 0 &gpio_w_000_031 22 0>, 606 <23 0 &gpio_w_000_031 23 0>, 607 <24 0 &gpio_w_000_031 24 0>, 608 <25 0 &gpio_w_000_031 25 0>, 609 <26 0 &gpio_w_000_031 26 0>, 610 <27 0 &gpio_w_000_031 27 0>, 611 <28 0 &gpio_w_000_031 28 0>, 612 <29 0 &gpio_w_000_031 29 0>, 613 <30 0 &gpio_w_000_031 30 0>, 614 <31 0 &gpio_w_000_031 31 0>, 615 <32 0 &gpio_w_032_046 0 0>, 616 <33 0 &gpio_w_032_046 1 0>, 617 <34 0 &gpio_w_032_046 2 0>, 618 <35 0 &gpio_w_032_046 3 0>, 619 <36 0 &gpio_w_032_046 4 0>, 620 <37 0 &gpio_w_032_046 5 0>, 621 <38 0 &gpio_w_032_046 6 0>, 622 <39 0 &gpio_w_032_046 7 0>, 623 <40 0 &gpio_w_032_046 8 0>, 624 <41 0 &gpio_w_032_046 9 0>, 625 <42 0 &gpio_w_032_046 10 0>, 626 <43 0 &gpio_w_032_046 11 0>, 627 <44 0 &gpio_w_032_046 12 0>, 628 <45 0 &gpio_w_032_046 13 0>, 629 <46 0 &gpio_w_032_046 14 0>; 630 }; 631 632 gpio_sw: gpio-southwest { 633 /* sw southwest 42 */ 634 compatible = "intel,apollo-lake-gpio"; 635 #gpio-cells = <2>; 636 gpio-map-mask = <0xffffffff 0xffffffc0>; 637 gpio-map-pass-thru = <0 0x3f>; 638 gpio-map = 639 <0 0 &gpio_sw_000_031 0 0>, 640 <1 0 &gpio_sw_000_031 1 0>, 641 <2 0 &gpio_sw_000_031 2 0>, 642 <3 0 &gpio_sw_000_031 3 0>, 643 <4 0 &gpio_sw_000_031 4 0>, 644 <5 0 &gpio_sw_000_031 5 0>, 645 <6 0 &gpio_sw_000_031 6 0>, 646 <7 0 &gpio_sw_000_031 7 0>, 647 <8 0 &gpio_sw_000_031 8 0>, 648 <9 0 &gpio_sw_000_031 9 0>, 649 <10 0 &gpio_sw_000_031 10 0>, 650 <11 0 &gpio_sw_000_031 11 0>, 651 <12 0 &gpio_sw_000_031 12 0>, 652 <13 0 &gpio_sw_000_031 13 0>, 653 <14 0 &gpio_sw_000_031 14 0>, 654 <15 0 &gpio_sw_000_031 15 0>, 655 <16 0 &gpio_sw_000_031 16 0>, 656 <17 0 &gpio_sw_000_031 17 0>, 657 <18 0 &gpio_sw_000_031 18 0>, 658 <19 0 &gpio_sw_000_031 19 0>, 659 <20 0 &gpio_sw_000_031 20 0>, 660 <21 0 &gpio_sw_000_031 21 0>, 661 <22 0 &gpio_sw_000_031 22 0>, 662 <23 0 &gpio_sw_000_031 23 0>, 663 <24 0 &gpio_sw_000_031 24 0>, 664 <25 0 &gpio_sw_000_031 25 0>, 665 <26 0 &gpio_sw_000_031 26 0>, 666 <27 0 &gpio_sw_000_031 27 0>, 667 <28 0 &gpio_sw_000_031 28 0>, 668 <29 0 &gpio_sw_000_031 29 0>, 669 <30 0 &gpio_sw_000_031 30 0>, 670 <31 0 &gpio_sw_000_031 31 0>, 671 <32 0 &gpio_sw_032_042 0 0>, 672 <33 0 &gpio_sw_032_042 1 0>, 673 <34 0 &gpio_sw_032_042 2 0>, 674 <35 0 &gpio_sw_032_042 3 0>, 675 <36 0 &gpio_sw_032_042 4 0>, 676 <37 0 &gpio_sw_032_042 5 0>, 677 <38 0 &gpio_sw_032_042 6 0>, 678 <39 0 &gpio_sw_032_042 7 0>, 679 <40 0 &gpio_sw_032_042 8 0>, 680 <41 0 &gpio_sw_032_042 9 0>, 681 <42 0 &gpio_sw_032_042 10 0>; 682 }; 683}; 684
