1 /*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*******************************************************************************
8 * NOTICE
9 * The hal is not public api, don't use in application code.
10 * See readme.md in hal/include/hal/readme.md
11 ******************************************************************************/
12
13 // The LL layer for ESP32 GPIO register operations
14
15 #pragma once
16
17 #include <stdbool.h>
18 #include "soc/soc.h"
19 #include "soc/gpio_periph.h"
20 #include "soc/gpio_struct.h"
21 #include "soc/rtc_cntl_reg.h"
22 #include "soc/rtc_io_reg.h"
23 #include "hal/gpio_types.h"
24 #include "hal/misc.h"
25
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29
30 // Get GPIO hardware instance with giving gpio num
31 #define GPIO_LL_GET_HW(num) (((num) == 0) ? (&GPIO) : NULL)
32
33 #define GPIO_LL_APP_CPU_INTR_ENA (BIT(0))
34 #define GPIO_LL_APP_CPU_NMI_INTR_ENA (BIT(1))
35 #define GPIO_LL_PRO_CPU_INTR_ENA (BIT(2))
36 #define GPIO_LL_PRO_CPU_NMI_INTR_ENA (BIT(3))
37 #define GPIO_LL_SDIO_EXT_INTR_ENA (BIT(4))
38
39 /**
40 * @brief Enable pull-up on GPIO.
41 *
42 * @param hw Peripheral GPIO hardware instance address.
43 * @param gpio_num GPIO number
44 */
gpio_ll_pullup_en(gpio_dev_t * hw,gpio_num_t gpio_num)45 static inline void gpio_ll_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
46 {
47 REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
48 }
49
50 /**
51 * @brief Disable pull-up on GPIO.
52 *
53 * @param hw Peripheral GPIO hardware instance address.
54 * @param gpio_num GPIO number
55 */
gpio_ll_pullup_dis(gpio_dev_t * hw,gpio_num_t gpio_num)56 static inline void gpio_ll_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
57 {
58 REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU);
59 }
60
61 /**
62 * @brief Return pull-up status on GPIO.
63 *
64 * @param hw Peripheral GPIO hardware instance address.
65 * @param gpio_num GPIO number
66 * @return if GPIO gpio_num`s FUN_PU is true
67 */
gpio_ll_pullup_is_enabled(gpio_dev_t * hw,gpio_num_t gpio_num)68 static inline bool gpio_ll_pullup_is_enabled(gpio_dev_t *hw, gpio_num_t gpio_num)
69 {
70 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PU) ? true : false;
71 }
72
73 /**
74 * @brief Enable pull-down on GPIO.
75 *
76 * @param hw Peripheral GPIO hardware instance address.
77 * @param gpio_num GPIO number
78 */
gpio_ll_pulldown_en(gpio_dev_t * hw,gpio_num_t gpio_num)79 static inline void gpio_ll_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
80 {
81 REG_SET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
82 }
83
84 /**
85 * @brief Disable pull-down on GPIO.
86 *
87 * @param hw Peripheral GPIO hardware instance address.
88 * @param gpio_num GPIO number
89 */
gpio_ll_pulldown_dis(gpio_dev_t * hw,gpio_num_t gpio_num)90 static inline void gpio_ll_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
91 {
92 REG_CLR_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD);
93 }
94
95 /**
96 * @brief Return pull-down status on GPIO.
97 *
98 * @param hw Peripheral GPIO hardware instance address.
99 * @param gpio_num GPIO number
100 * @return if GPIO gpio_num`s FUN_PD is true
101 */
gpio_ll_pulldown_is_enabled(gpio_dev_t * hw,gpio_num_t gpio_num)102 static inline bool gpio_ll_pulldown_is_enabled(gpio_dev_t *hw, gpio_num_t gpio_num)
103 {
104 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], FUN_PD) ? true : false;
105 }
106
107 /**
108 * @brief Enable GPIO pin used for wakeup from sleep.
109 *
110 * @param hw Peripheral GPIO hardware instance address.
111 * @param gpio_num GPIO number
112 */
gpio_ll_sleep_sel_en(gpio_dev_t * hw,gpio_num_t gpio_num)113 static inline void gpio_ll_sleep_sel_en(gpio_dev_t *hw, gpio_num_t gpio_num)
114 {
115 PIN_SLP_SEL_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
116 }
117
118 /**
119 * @brief Disable GPIO pin used for wakeup from sleep.
120 *
121 * @param hw Peripheral GPIO hardware instance address.
122 * @param gpio_num GPIO number
123 */
gpio_ll_sleep_sel_dis(gpio_dev_t * hw,gpio_num_t gpio_num)124 static inline void gpio_ll_sleep_sel_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
125 {
126 PIN_SLP_SEL_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
127 }
128
129 /**
130 * @brief Return slp-sel status on GPIO.
131 *
132 * @param hw Peripheral GPIO hardware instance address.
133 * @param gpio_num GPIO number
134 * @return if GPIO gpio_num`s SLP_SEL is true
135 */
gpio_ll_sleep_sel_is_enabled(gpio_dev_t * hw,gpio_num_t gpio_num)136 static inline bool gpio_ll_sleep_sel_is_enabled(gpio_dev_t *hw, gpio_num_t gpio_num)
137 {
138 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_SEL) ? true : false;
139 }
140
141 /**
142 * @brief Disable GPIO pull-up in sleep mode.
143 *
144 * @param hw Peripheral GPIO hardware instance address.
145 * @param gpio_num GPIO number
146 */
gpio_ll_sleep_pullup_dis(gpio_dev_t * hw,gpio_num_t gpio_num)147 static inline void gpio_ll_sleep_pullup_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
148 {
149 PIN_SLP_PULLUP_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
150 }
151
152 /**
153 * @brief Enable GPIO pull-up in sleep mode.
154 *
155 * @param hw Peripheral GPIO hardware instance address.
156 * @param gpio_num GPIO number
157 */
gpio_ll_sleep_pullup_en(gpio_dev_t * hw,gpio_num_t gpio_num)158 static inline void gpio_ll_sleep_pullup_en(gpio_dev_t *hw, gpio_num_t gpio_num)
159 {
160 PIN_SLP_PULLUP_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
161 }
162
163 /**
164 * @brief Return slp-pull-up status on GPIO.
165 *
166 * @param hw Peripheral GPIO hardware instance address.
167 * @param gpio_num GPIO number
168 * @return if GPIO gpio_num`s SLP_PU is true
169 */
gpio_ll_sleep_pullup_is_enabled(gpio_dev_t * hw,gpio_num_t gpio_num)170 static inline bool gpio_ll_sleep_pullup_is_enabled(gpio_dev_t *hw, gpio_num_t gpio_num)
171 {
172 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_PU) ? true : false;
173 }
174
175 /**
176 * @brief Enable GPIO pull-down in sleep mode.
177 *
178 * @param hw Peripheral GPIO hardware instance address.
179 * @param gpio_num GPIO number
180 */
gpio_ll_sleep_pulldown_en(gpio_dev_t * hw,gpio_num_t gpio_num)181 static inline void gpio_ll_sleep_pulldown_en(gpio_dev_t *hw, gpio_num_t gpio_num)
182 {
183 PIN_SLP_PULLDOWN_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
184 }
185
186 /**
187 * @brief Disable GPIO pull-down in sleep mode.
188 *
189 * @param hw Peripheral GPIO hardware instance address.
190 * @param gpio_num GPIO number
191 */
gpio_ll_sleep_pulldown_dis(gpio_dev_t * hw,gpio_num_t gpio_num)192 static inline void gpio_ll_sleep_pulldown_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
193 {
194 PIN_SLP_PULLDOWN_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
195 }
196
197 /**
198 * @brief Return slp-pull-down status on GPIO.
199 *
200 * @param hw Peripheral GPIO hardware instance address.
201 * @param gpio_num GPIO number
202 * @return if GPIO gpio_num`s SLP_PD is true
203 */
gpio_ll_sleep_pulldown_is_enabled(gpio_dev_t * hw,gpio_num_t gpio_num)204 static inline bool gpio_ll_sleep_pulldown_is_enabled(gpio_dev_t *hw, gpio_num_t gpio_num)
205 {
206 return REG_GET_BIT(GPIO_PIN_MUX_REG[gpio_num], SLP_PD) ? true : false;
207 }
208
209 /**
210 * @brief GPIO set interrupt trigger type
211 *
212 * @param hw Peripheral GPIO hardware instance address.
213 * @param gpio_num GPIO number. If you want to set the trigger type of e.g. of GPIO16, gpio_num should be GPIO_NUM_16 (16);
214 * @param intr_type Interrupt type, select from gpio_int_type_t
215 */
gpio_ll_set_intr_type(gpio_dev_t * hw,gpio_num_t gpio_num,gpio_int_type_t intr_type)216 static inline void gpio_ll_set_intr_type(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
217 {
218 hw->pin[gpio_num].int_type = intr_type;
219 }
220
221 /**
222 * @brief Get GPIO interrupt status
223 *
224 * @param hw Peripheral GPIO hardware instance address.
225 * @param core_id interrupt core id
226 * @param status interrupt status
227 */
gpio_ll_get_intr_status(gpio_dev_t * hw,uint32_t core_id,uint32_t * status)228 static inline void gpio_ll_get_intr_status(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
229 {
230 *status = (core_id == 0) ? hw->pcpu_int : hw->acpu_int;
231 }
232
233 /**
234 * @brief Get GPIO interrupt status high
235 *
236 * @param hw Peripheral GPIO hardware instance address.
237 * @param core_id interrupt core id
238 * @param status interrupt status high
239 */
gpio_ll_get_intr_status_high(gpio_dev_t * hw,uint32_t core_id,uint32_t * status)240 static inline void gpio_ll_get_intr_status_high(gpio_dev_t *hw, uint32_t core_id, uint32_t *status)
241 {
242 *status = (core_id == 0) ? HAL_FORCE_READ_U32_REG_FIELD(hw->pcpu_int1, intr) : HAL_FORCE_READ_U32_REG_FIELD(hw->acpu_int1, intr);
243 }
244
245 /**
246 * @brief Clear GPIO interrupt status
247 *
248 * @param hw Peripheral GPIO hardware instance address.
249 * @param mask interrupt status clear mask
250 */
gpio_ll_clear_intr_status(gpio_dev_t * hw,uint32_t mask)251 static inline void gpio_ll_clear_intr_status(gpio_dev_t *hw, uint32_t mask)
252 {
253 hw->status_w1tc = mask;
254 }
255
256 /**
257 * @brief Clear GPIO interrupt status high
258 *
259 * @param hw Peripheral GPIO hardware instance address.
260 * @param mask interrupt status high clear mask
261 */
gpio_ll_clear_intr_status_high(gpio_dev_t * hw,uint32_t mask)262 static inline void gpio_ll_clear_intr_status_high(gpio_dev_t *hw, uint32_t mask)
263 {
264 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->status1_w1tc, intr_st, mask);
265 }
266
267 /**
268 * @brief Enable GPIO module interrupt signal
269 *
270 * @param hw Peripheral GPIO hardware instance address.
271 * @param core_id Interrupt enabled CPU to corresponding ID
272 * @param gpio_num GPIO number. If you want to enable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
273 */
gpio_ll_intr_enable_on_core(gpio_dev_t * hw,uint32_t core_id,gpio_num_t gpio_num)274 static inline void gpio_ll_intr_enable_on_core(gpio_dev_t *hw, uint32_t core_id, gpio_num_t gpio_num)
275 {
276 if (core_id == 0) {
277 hw->pin[gpio_num].int_ena = GPIO_LL_PRO_CPU_INTR_ENA; //enable pro cpu intr
278 } else {
279 hw->pin[gpio_num].int_ena = GPIO_LL_APP_CPU_INTR_ENA; //enable pro cpu intr
280 }
281 }
282
283 /**
284 * @brief Disable GPIO module interrupt signal
285 *
286 * @param hw Peripheral GPIO hardware instance address.
287 * @param gpio_num GPIO number. If you want to disable the interrupt of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
288 */
gpio_ll_intr_disable(gpio_dev_t * hw,gpio_num_t gpio_num)289 static inline void gpio_ll_intr_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
290 {
291 hw->pin[gpio_num].int_ena = 0; //disable GPIO intr
292 }
293
294 /**
295 * @brief Disable input mode on GPIO.
296 *
297 * @param hw Peripheral GPIO hardware instance address.
298 * @param gpio_num GPIO number
299 */
gpio_ll_input_disable(gpio_dev_t * hw,gpio_num_t gpio_num)300 static inline void gpio_ll_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
301 {
302 PIN_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
303 }
304
305 /**
306 * @brief Enable input mode on GPIO.
307 *
308 * @param hw Peripheral GPIO hardware instance address.
309 * @param gpio_num GPIO number
310 */
gpio_ll_input_enable(gpio_dev_t * hw,gpio_num_t gpio_num)311 static inline void gpio_ll_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
312 {
313 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
314 }
315
316 /**
317 * @brief Disable output mode on GPIO.
318 *
319 * @param hw Peripheral GPIO hardware instance address.
320 * @param gpio_num GPIO number
321 */
gpio_ll_output_disable(gpio_dev_t * hw,gpio_num_t gpio_num)322 static inline void gpio_ll_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
323 {
324 if (gpio_num < 32) {
325 hw->enable_w1tc = (0x1 << gpio_num);
326 } else {
327 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1tc, data, (0x1 << (gpio_num - 32)));
328 }
329
330 // Ensure no other output signal is routed via GPIO matrix to this pin
331 REG_WRITE(GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio_num * 4),
332 SIG_GPIO_OUT_IDX);
333 }
334
335 /**
336 * @brief Enable output mode on GPIO.
337 *
338 * @param hw Peripheral GPIO hardware instance address.
339 * @param gpio_num GPIO number
340 */
gpio_ll_output_enable(gpio_dev_t * hw,gpio_num_t gpio_num)341 static inline void gpio_ll_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
342 {
343 if (gpio_num < 32) {
344 hw->enable_w1ts = (0x1 << gpio_num);
345 } else {
346 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->enable1_w1ts, data, (0x1 << (gpio_num - 32)));
347 }
348 }
349
350 /**
351 * @brief Disable GPIO input in sleep mode.
352 *
353 * @param hw Peripheral GPIO hardware instance address.
354 * @param gpio_num GPIO number
355 */
gpio_ll_sleep_input_disable(gpio_dev_t * hw,gpio_num_t gpio_num)356 static inline void gpio_ll_sleep_input_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
357 {
358 PIN_SLP_INPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
359 }
360
361 /**
362 * @brief Enable GPIO input in sleep mode.
363 *
364 * @param hw Peripheral GPIO hardware instance address.
365 * @param gpio_num GPIO number
366 */
gpio_ll_sleep_input_enable(gpio_dev_t * hw,gpio_num_t gpio_num)367 static inline void gpio_ll_sleep_input_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
368 {
369 PIN_SLP_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
370 }
371
372 /**
373 * @brief Disable GPIO output in sleep mode.
374 *
375 * @param hw Peripheral GPIO hardware instance address.
376 * @param gpio_num GPIO number
377 */
gpio_ll_sleep_output_disable(gpio_dev_t * hw,gpio_num_t gpio_num)378 static inline void gpio_ll_sleep_output_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
379 {
380 PIN_SLP_OUTPUT_DISABLE(GPIO_PIN_MUX_REG[gpio_num]);
381 }
382
383 /**
384 * @brief Enable GPIO output in sleep mode.
385 *
386 * @param hw Peripheral GPIO hardware instance address.
387 * @param gpio_num GPIO number
388 */
gpio_ll_sleep_output_enable(gpio_dev_t * hw,gpio_num_t gpio_num)389 static inline void gpio_ll_sleep_output_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
390 {
391 PIN_SLP_OUTPUT_ENABLE(GPIO_PIN_MUX_REG[gpio_num]);
392 }
393
394 /**
395 * @brief Disable open-drain mode on GPIO.
396 *
397 * @param hw Peripheral GPIO hardware instance address.
398 * @param gpio_num GPIO number
399 */
gpio_ll_od_disable(gpio_dev_t * hw,gpio_num_t gpio_num)400 static inline void gpio_ll_od_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
401 {
402 hw->pin[gpio_num].pad_driver = 0;
403 }
404
405 /**
406 * @brief Enable open-drain mode on GPIO.
407 *
408 * @param hw Peripheral GPIO hardware instance address.
409 * @param gpio_num GPIO number
410 */
gpio_ll_od_enable(gpio_dev_t * hw,gpio_num_t gpio_num)411 static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
412 {
413 hw->pin[gpio_num].pad_driver = 1;
414 }
415
416 /**
417 * @brief GPIO set output level
418 *
419 * @param hw Peripheral GPIO hardware instance address.
420 * @param gpio_num GPIO number. If you want to set the output level of e.g. GPIO16, gpio_num should be GPIO_NUM_16 (16);
421 * @param level Output level. 0: low ; 1: high
422 */
gpio_ll_set_level(gpio_dev_t * hw,gpio_num_t gpio_num,uint32_t level)423 static inline void gpio_ll_set_level(gpio_dev_t *hw, gpio_num_t gpio_num, uint32_t level)
424 {
425 if (level) {
426 if (gpio_num < 32) {
427 hw->out_w1ts = (1 << gpio_num);
428 } else {
429 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1ts, data, (1 << (gpio_num - 32)));
430 }
431 } else {
432 if (gpio_num < 32) {
433 hw->out_w1tc = (1 << gpio_num);
434 } else {
435 HAL_FORCE_MODIFY_U32_REG_FIELD(hw->out1_w1tc, data, (1 << (gpio_num - 32)));
436 }
437 }
438 }
439
440 /**
441 * @brief GPIO get input level
442 *
443 * @warning If the pad is not configured for input (or input and output) the returned value is always 0.
444 *
445 * @param hw Peripheral GPIO hardware instance address.
446 * @param gpio_num GPIO number. If you want to get the logic level of e.g. pin GPIO16, gpio_num should be GPIO_NUM_16 (16);
447 *
448 * @return
449 * - 0 the GPIO input level is 0
450 * - 1 the GPIO input level is 1
451 */
gpio_ll_get_level(gpio_dev_t * hw,gpio_num_t gpio_num)452 static inline int gpio_ll_get_level(gpio_dev_t *hw, gpio_num_t gpio_num)
453 {
454 if (gpio_num < 32) {
455 return (hw->in >> gpio_num) & 0x1;
456 } else {
457 return (HAL_FORCE_READ_U32_REG_FIELD(hw->in1, data) >> (gpio_num - 32)) & 0x1;
458 }
459 }
460
461 /**
462 * @brief Enable GPIO wake-up function.
463 *
464 * @param hw Peripheral GPIO hardware instance address.
465 * @param gpio_num GPIO number.
466 * @param intr_type GPIO wake-up type. Only GPIO_INTR_LOW_LEVEL or GPIO_INTR_HIGH_LEVEL can be used.
467 */
gpio_ll_wakeup_enable(gpio_dev_t * hw,gpio_num_t gpio_num,gpio_int_type_t intr_type)468 static inline void gpio_ll_wakeup_enable(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_int_type_t intr_type)
469 {
470 hw->pin[gpio_num].int_type = intr_type;
471 hw->pin[gpio_num].wakeup_enable = 0x1;
472 }
473
474 /**
475 * @brief Disable GPIO wake-up function.
476 *
477 * @param hw Peripheral GPIO hardware instance address.
478 * @param gpio_num GPIO number
479 */
gpio_ll_wakeup_disable(gpio_dev_t * hw,gpio_num_t gpio_num)480 static inline void gpio_ll_wakeup_disable(gpio_dev_t *hw, gpio_num_t gpio_num)
481 {
482 hw->pin[gpio_num].wakeup_enable = 0;
483 }
484
485 /**
486 * @brief Set GPIO pad drive capability
487 *
488 * @param hw Peripheral GPIO hardware instance address.
489 * @param gpio_num GPIO number, only support output GPIOs
490 * @param strength Drive capability of the pad
491 */
gpio_ll_set_drive_capability(gpio_dev_t * hw,gpio_num_t gpio_num,gpio_drive_cap_t strength)492 static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t strength)
493 {
494 SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, strength, FUN_DRV_S);
495 }
496
497 /**
498 * @brief Get GPIO pad drive capability
499 *
500 * @param hw Peripheral GPIO hardware instance address.
501 * @param gpio_num GPIO number, only support output GPIOs
502 * @param strength Pointer to accept drive capability of the pad
503 */
gpio_ll_get_drive_capability(gpio_dev_t * hw,gpio_num_t gpio_num,gpio_drive_cap_t * strength)504 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
505 {
506 *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
507 }
508
509 /**
510 * @brief Enable all digital gpio pad hold function during Deep-sleep.
511 *
512 * @param hw Peripheral GPIO hardware instance address.
513 */
gpio_ll_deep_sleep_hold_en(gpio_dev_t * hw)514 static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
515 {
516 SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
517 }
518
519 /**
520 * @brief Disable all digital gpio pad hold function during Deep-sleep.
521 *
522 * @param hw Peripheral GPIO hardware instance address.
523 */
gpio_ll_deep_sleep_hold_dis(gpio_dev_t * hw)524 static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
525 {
526 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN_M);
527 }
528
529 /**
530 * @brief Enable gpio pad hold function.
531 *
532 * @param hw Peripheral GPIO hardware instance address.
533 * @param gpio_num GPIO number, only support output GPIOs
534 */
gpio_ll_hold_en(gpio_dev_t * hw,gpio_num_t gpio_num)535 static inline void gpio_ll_hold_en(gpio_dev_t *hw, gpio_num_t gpio_num)
536 {
537 SET_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
538 }
539
540 /**
541 * @brief Disable gpio pad hold function.
542 *
543 * @param hw Peripheral GPIO hardware instance address.
544 * @param gpio_num GPIO number, only support output GPIOs
545 */
gpio_ll_hold_dis(gpio_dev_t * hw,gpio_num_t gpio_num)546 static inline void gpio_ll_hold_dis(gpio_dev_t *hw, gpio_num_t gpio_num)
547 {
548 CLEAR_PERI_REG_MASK(RTC_IO_DIG_PAD_HOLD_REG, GPIO_HOLD_MASK[gpio_num]);
549 }
550
551 /**
552 * @brief Set pad input to a peripheral signal through the IOMUX.
553 *
554 * @param hw Peripheral GPIO hardware instance address.
555 * @param gpio_num GPIO number of the pad.
556 * @param signal_idx Peripheral signal id to input. One of the ``*_IN_IDX`` signals in ``soc/gpio_sig_map.h``.
557 */
gpio_ll_iomux_in(gpio_dev_t * hw,uint32_t gpio,uint32_t signal_idx)558 static inline void gpio_ll_iomux_in(gpio_dev_t *hw, uint32_t gpio, uint32_t signal_idx)
559 {
560 hw->func_in_sel_cfg[signal_idx].sig_in_sel = 0;
561 PIN_INPUT_ENABLE(GPIO_PIN_MUX_REG[gpio]);
562 }
563
564 /**
565 * @brief Select a function for the pin in the IOMUX
566 *
567 * @param pin_name Pin name to configure
568 * @param func Function to assign to the pin
569 */
gpio_ll_iomux_func_sel(uint32_t pin_name,uint32_t func)570 static inline __attribute__((always_inline)) void gpio_ll_iomux_func_sel(uint32_t pin_name, uint32_t func)
571 {
572 PIN_FUNC_SELECT(pin_name, func);
573 }
574
575 /**
576 * @brief Set peripheral output to an GPIO pad through the IOMUX.
577 *
578 * @param hw Peripheral GPIO hardware instance address.
579 * @param gpio_num gpio_num GPIO number of the pad.
580 * @param func The function number of the peripheral pin to output pin.
581 * One of the ``FUNC_X_*`` of specified pin (X) in ``soc/io_mux_reg.h``.
582 * @param oen_inv True if the output enable needs to be inverted, otherwise False.
583 */
gpio_ll_iomux_out(gpio_dev_t * hw,uint8_t gpio_num,int func,uint32_t oen_inv)584 static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func, uint32_t oen_inv)
585 {
586 hw->func_out_sel_cfg[gpio_num].oen_sel = 0;
587 hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv;
588 gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
589 }
590
591 #ifdef __cplusplus
592 }
593 #endif
594
