1/*
2 * Copyright (c) 2024 Microchip Technology Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/gpio/gpio.h>
9#include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
10#include <freq.h>
11#include <mem.h>
12
13/ {
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			device_type = "cpu";
20			compatible = "arm,cortex-m4";
21			reg = <0>;
22		};
23	};
24
25	soc {
26		ecs: ecs@4000fc00 {
27			reg = <0x4000fc00 0x200>;
28			status = "disabled";
29		};
30		pcr: pcr@40080100 {
31			reg = <0x40080100 0x100 0x4000a400 0x100>;
32			reg-names = "pcrr", "vbatr";
33			interrupts = <174 0>;
34			status = "disabled";
35		};
36		ecia: ecia@4000e000 {
37			reg = <0x4000e000 0x400>;
38			#address-cells = <1>;
39			#size-cells = <1>;
40			status = "disabled";
41
42			ranges = <0x0 0x4000e000 0x400>;
43
44			girq8: girq8@0 {
45				reg = <0x0 0x14>;
46				interrupts = <0 1>;
47				status = "disabled";
48			};
49			girq9: girq9@14 {
50				reg = <0x14 0x14>;
51				interrupts = <1 1>;
52				status = "disabled";
53			};
54			girq10: girq10@28 {
55				reg = <0x28 0x14>;
56				interrupts = <2 1>;
57				status = "disabled";
58			};
59			girq11: girq11@3c {
60				reg = <0x3c 0x14>;
61				interrupts = <3 1>;
62				status = "disabled";
63			};
64			girq12: girq12@50 {
65				reg = <0x50 0x14>;
66				interrupts = <4 1>;
67				status = "disabled";
68			};
69			girq13: girq13@64 {
70				reg = <0x64 0x14>;
71				interrupts = <5 1>;
72				status = "disabled";
73			};
74			girq14: girq14@78 {
75				reg = <0x78 0x14>;
76				interrupts = <6 1>;
77				status = "disabled";
78			};
79			girq15: girq15@8c {
80				reg = <0x8c 0x14>;
81				interrupts = <7 1>;
82				status = "disabled";
83			};
84			girq16: girq16@a0 {
85				reg = <0xa0 0x14>;
86				interrupts = <8 1>;
87				status = "disabled";
88			};
89			girq17: girq17@b4 {
90				reg = <0xb4 0x14>;
91				interrupts = <9 1>;
92				status = "disabled";
93			};
94			girq18: girq18@c8 {
95				reg = <0xc8 0x14>;
96				interrupts = <10 1>;
97				status = "disabled";
98			};
99			girq19: girq19@dc {
100				reg = <0xdc 0x14>;
101				interrupts = <11 1>;
102				status = "disabled";
103			};
104			girq20: girq20@f0 {
105				reg = <0xf0 0x14>;
106				interrupts = <12 1>;
107				status = "disabled";
108			};
109			girq21: girq21@104 {
110				reg = <0x104 0x14>;
111				interrupts = <13 1>;
112				status = "disabled";
113			};
114			girq22: girq22@118 {
115				reg = <0x118 0x14>;
116				interrupts = <255 0>;
117				status = "disabled";
118			};
119			girq23: girq23@12c {
120				reg = <0x12c 0x14>;
121				interrupts = <14 1>;
122				status = "disabled";
123			};
124			girq24: girq24@140 {
125				reg = <0x140 0x14>;
126				interrupts = <15 1>;
127				status = "disabled";
128			};
129			girq25: girq25@154 {
130				reg = <0x154 0x14>;
131				interrupts = <16 1>;
132				status = "disabled";
133			};
134			girq26: girq26@168 {
135				reg = <0x168 0x14>;
136				interrupts = <17 1>;
137				status = "disabled";
138			};
139		};
140		pinctrl: pin-controller@40081000 {
141			compatible = "microchip,mec5-pinctrl";
142			#address-cells = <1>;
143			#size-cells = <1>;
144			reg = <0x40081000 0x1000>;
145
146			gpio_000_036: gpio@40081000 {
147				compatible = "microchip,mec5-gpio";
148				reg = < 0x40081000 0x80 0x40081300 0x04
149					0x40081380 0x04 0x400813fc 0x04>;
150				interrupts = <3 2>;
151				gpio-controller;
152				#gpio-cells=<2>;
153			};
154			gpio_040_076: gpio@40081080 {
155				compatible = "microchip,mec5-gpio";
156				reg = < 0x40081080 0x80 0x40081304 0x04
157					0x40081384 0x04 0x400813f8 0x4>;
158				interrupts = <2 2>;
159				gpio-controller;
160				#gpio-cells=<2>;
161			};
162			gpio_100_136: gpio@40081100 {
163				compatible = "microchip,mec5-gpio";
164				reg = < 0x40081100 0x80 0x40081308 0x04
165					0x40081388 0x04 0x400813f4 0x04>;
166				gpio-controller;
167				interrupts = <1 2>;
168				#gpio-cells=<2>;
169			};
170			gpio_140_176: gpio@40081180 {
171				compatible = "microchip,mec5-gpio";
172				reg = < 0x40081180 0x80 0x4008130c 0x04
173					0x4008138c 0x04 0x400813f0 0x04>;
174				gpio-controller;
175				interrupts = <0 2>;
176				#gpio-cells=<2>;
177			};
178			gpio_200_236: gpio@40081200 {
179				compatible = "microchip,mec5-gpio";
180				reg = < 0x40081200 0x80 0x40081310 0x04
181					0x40081390 0x04 0x400813ec 0x04>;
182				gpio-controller;
183				interrupts = <4 2>;
184				#gpio-cells=<2>;
185			};
186			gpio_240_276: gpio@40081280 {
187				compatible = "microchip,mec5-gpio";
188				reg = < 0x40081280 0x80 0x40081314 0x04
189					0x40081394 0x04 0x400813e8 0x04>;
190				gpio-controller;
191				interrupts = <17 2>;
192				#gpio-cells=<2>;
193			};
194		};
195		uart0: uart@400f2400 {
196			reg = <0x400f2400 0x400>;
197			interrupts = <40 1>;
198			status = "disabled";
199		};
200		uart1: uart@400f2800 {
201			reg = <0x400f2800 0x400>;
202			interrupts = <41 1>;
203			status = "disabled";
204		};
205		wdog: watchdog@40000400 {
206			reg = <0x40000400 0x400>;
207			interrupts = <171 0>;
208			status = "disabled";
209		};
210		rtimer: timer@40007400 {
211			reg = <0x40007400 0x10>;
212			interrupts = <111 0>;
213			clock-frequency = <32768>;
214			max-value = <0xffffffff>;
215			status = "disabled";
216		};
217		timer0: timer@40000c00 {
218			reg = <0x40000c00 0x20>;
219			interrupts = <136 0>;
220			clock-frequency = <48000000>;
221			prescaler = <0>;
222			max-value = <0xffff>;
223			status = "disabled";
224		};
225		timer1: timer@40000c20 {
226			reg = <0x40000c20 0x20>;
227			interrupts = <137 0>;
228			clock-frequency = <48000000>;
229			prescaler = <0>;
230			max-value = <0xffff>;
231			status = "disabled";
232		};
233		timer2: timer@40000c40 {
234			reg = <0x40000c40 0x20>;
235			interrupts = <138 0>;
236			clock-frequency = <48000000>;
237			prescaler = <0>;
238			max-value = <0xffff>;
239			status = "disabled";
240		};
241		timer3: timer@40000c60 {
242			reg = <0x40000c60 0x20>;
243			interrupts = <139 0>;
244			clock-frequency = <48000000>;
245			prescaler = <0>;
246			max-value = <0xffff>;
247			status = "disabled";
248		};
249		timer4: timer@40000c80 {
250			reg = <0x40000c80 0x20>;
251			interrupts = <140 0>;
252			clock-frequency = <48000000>;
253			prescaler = <0>;
254			max-value = <0xffffffff>;
255			status = "disabled";
256		};
257		timer5: timer@40000ca0 {
258			reg = <0x40000ca0 0x20>;
259			interrupts = <141 0>;
260			clock-frequency = <48000000>;
261			prescaler = <0>;
262			max-value = <0xffffffff>;
263			status = "disabled";
264		};
265		cntr0: timer@40000d00 {
266			reg = <0x40000d00 0x20>;
267			interrupts = <142 0>;
268			status = "disabled";
269		};
270		cntr1: timer@40000d20 {
271			reg = <0x40000d20 0x20>;
272			interrupts = <143 0>;
273			status = "disabled";
274		};
275		cntr2: timer@40000d40 {
276			reg = <0x40000d40 0x20>;
277			interrupts = <144 0>;
278			status = "disabled";
279		};
280		cntr3: timer@40000d60 {
281			reg = <0x40000d60 0x20>;
282			interrupts = <145 0>;
283			status = "disabled";
284		};
285		cctmr0: timer@40001000 {
286			reg = <0x40001000 0x40>;
287			interrupts = <146 0>, <147 0>, <148 0>, <149 0>,
288				     <150 0>, <151 0>, <152 0>, <153 0>,
289				     <154 0>;
290			status = "disabled";
291		};
292		hibtimer0: timer@40009800 {
293			reg = <0x40009800 0x20>;
294			interrupts = <112 0>;
295			status = "disabled";
296		};
297		hibtimer1: timer@40009820 {
298			reg = <0x40009820 0x20>;
299			interrupts = <113 0>;
300			status = "disabled";
301		};
302		weektmr0: timer@4000ac80 {
303			reg = <0x4000ac80 0x80>;
304			interrupts = <114 0>, <115 0>, <116 0>,
305				     <117 0>, <118 0>;
306			status = "disabled";
307		};
308		rtc0: rtc@400f5000 {
309			reg = <0x400f5000 0x100>;
310			interrupts = <119 3>, <120 3>;
311			status = "disabled";
312		};
313		bbram: bb-ram@4000a800 {
314			reg = <0x4000a800 0x100>;
315			reg-names = "memory";
316			status = "disabled";
317		};
318		vci0: vci@4000ae00 {
319			reg = <0x4000ae00 0x40>;
320			interrupts = <121 0>, <122 0>, <123 0>,
321				     <124 0>, <125 0>;
322			status = "disabled";
323		};
324		i2c_smb_0: i2c@40004000 {
325			reg = <0x40004000 0x80>;
326			clock-frequency = <I2C_BITRATE_STANDARD>;
327			interrupts = <20 1>;
328			#address-cells = <1>;
329			#size-cells = <0>;
330			status = "disabled";
331		};
332		i2c_smb_1: i2c@40004400 {
333			reg = <0x40004400 0x80>;
334			clock-frequency = <I2C_BITRATE_STANDARD>;
335			interrupts = <21 1>;
336			#address-cells = <1>;
337			#size-cells = <0>;
338			status = "disabled";
339		};
340		i2c_smb_2: i2c@40004800 {
341			reg = <0x40004800 0x80>;
342			clock-frequency = <I2C_BITRATE_STANDARD>;
343			interrupts = <22 1>;
344			#address-cells = <1>;
345			#size-cells = <0>;
346			status = "disabled";
347		};
348		i2c_smb_3: i2c@40004c00 {
349			reg = <0x40004C00 0x80>;
350			clock-frequency = <I2C_BITRATE_STANDARD>;
351			interrupts = <23 1>;
352			#address-cells = <1>;
353			#size-cells = <0>;
354			status = "disabled";
355		};
356		i2c_smb_4: i2c@40005000 {
357			reg = <0x40005000 0x80>;
358			clock-frequency = <I2C_BITRATE_STANDARD>;
359			interrupts = <158 1>;
360			#address-cells = <1>;
361			#size-cells = <0>;
362			status = "disabled";
363		};
364		ps2_0: ps2@40009000 {
365			reg = <0x40009000 0x40>;
366			interrupts = <100 1>;
367			#address-cells = <1>;
368			#size-cells = <0>;
369			status = "disabled";
370		};
371		pwm0: pwm@40005800 {
372			reg = <0x40005800 0x10>;
373			status = "disabled";
374			#pwm-cells = <3>;
375		};
376		pwm1: pwm@40005810 {
377			reg = <0x40005810 0x10>;
378			status = "disabled";
379			#pwm-cells = <3>;
380		};
381		pwm2: pwm@40005820 {
382			reg = <0x40005820 0x10>;
383			status = "disabled";
384			#pwm-cells = <3>;
385		};
386		pwm3: pwm@40005830 {
387			reg = <0x40005830 0x10>;
388			status = "disabled";
389			#pwm-cells = <3>;
390		};
391		pwm4: pwm@40005840 {
392			reg = <0x40005840 0x10>;
393			status = "disabled";
394			#pwm-cells = <3>;
395		};
396		pwm5: pwm@40005850 {
397			reg = <0x40005850 0x10>;
398			status = "disabled";
399			#pwm-cells = <3>;
400		};
401		pwm6: pwm@40005860 {
402			reg = <0x40005860 0x10>;
403			status = "disabled";
404			#pwm-cells = <3>;
405		};
406		pwm7: pwm@40005870 {
407			reg = <0x40005870 0x10>;
408			status = "disabled";
409			#pwm-cells = <3>;
410		};
411		pwm8: pwm@40005880 {
412			reg = <0x40005880 0x10>;
413			status = "disabled";
414			#pwm-cells = <3>;
415		};
416		tach0: tach@40006000 {
417			reg = <0x40006000 0x10>;
418			interrupts = <71 4>;
419			#address-cells = <1>;
420			#size-cells = <0>;
421			status = "disabled";
422		};
423		tach1: tach@40006010 {
424			reg = <0x40006010 0x10>;
425			interrupts = <72 4>;
426			#address-cells = <1>;
427			#size-cells = <0>;
428			status = "disabled";
429		};
430		tach2: tach@40006020 {
431			reg = <0x40006020 0x10>;
432			interrupts = <73 4>;
433			#address-cells = <1>;
434			#size-cells = <0>;
435			status = "disabled";
436		};
437		tach3: tach@40006030 {
438			reg = <0x40006030 0x10>;
439			interrupts = <159 4>;
440			#address-cells = <1>;
441			#size-cells = <0>;
442			status = "disabled";
443		};
444		rpmfan0: rpmfan@4000a000 {
445			reg = <0x4000a000 0x80>;
446			interrupts = <74 1>, <75 1>;
447			status = "disabled";
448		};
449		rpmfan1: rpmfan@4000a080 {
450			reg = <0x4000a080 0x80>;
451			interrupts = <76 1>, <77 1>;
452			status = "disabled";
453		};
454		adc0: adc@40007c00 {
455			reg = <0x40007c00 0x90>;
456			interrupts = <78 0>, <79 0>;
457			interrupt-names = "single", "repeat";
458			status = "disabled";
459			#io-channel-cells = <1>;
460			clktime = <32>;
461		};
462		peci0: peci@40006400 {
463			reg = <0x40006400 0x80>;
464			interrupts = <70 4>;
465			#address-cells = <1>;
466			#size-cells = <0>;
467			status = "disabled";
468		};
469		qspi0: spi@40070000 {
470			reg = <0x40070000 0x400>;
471			interrupts = <91 2>;
472			clock-frequency = <12000000>;
473			#address-cells = <1>;
474			#size-cells = <0>;
475			status = "disabled";
476		};
477		prochot0: prochot@40003400 {
478			reg = <0x40003400 0x20>;
479			interrupts = <87 0>;
480			status = "disabled";
481		};
482		rcid0: rcid@40001400 {
483			reg = <0x40001400 0x80>;
484			interrupts = <80 0>;
485			status = "disabled";
486		};
487		rcid1: rcid@40001480 {
488			reg = <0x40001480 0x80>;
489			interrupts = <81 0>;
490			status = "disabled";
491		};
492		rcid2: rcid@40001500 {
493			reg = <0x40001500 0x80>;
494			interrupts = <82 0>;
495			status = "disabled";
496		};
497		bbled0: bbled@4000b800 {
498			reg = <0x4000b800 0x100>;
499			interrupts = <83 0>;
500			status = "disabled";
501		};
502		bbled1: bbled@4000b900 {
503			reg = <0x4000b900 0x100>;
504			interrupts = <84 0>;
505			status = "disabled";
506		};
507		bbled2: bbled@4000ba00 {
508			reg = <0x4000ba00 0x100>;
509			interrupts = <85 0>;
510			status = "disabled";
511		};
512		bbled3: bbled@4000bb00 {
513			reg = <0x4000bb00 0x100>;
514			interrupts = <86 0>;
515			status = "disabled";
516		};
517		bclink0: bclink@4000cd00 {
518			reg = <0x4000cd00 0x20>;
519			interrupts = <96 0>, <97 0>;
520			status = "disabled";
521		};
522		tfdp0: tfdp@40008c00 {
523			reg = <0x40008c00 0x10>;
524			status = "disabled";
525		};
526		glblcfg0: glblcfg@400fff00 {
527			reg = <0x400fff00 0x40>;
528			status = "disabled";
529		};
530		espi0: espi@400f3400 {
531			#address-cells = <1>;
532			#size-cells = <1>;
533			reg = < 0x400f3400 0x400
534				0x400f3800 0x400
535				0x400f9c00 0x400>;
536			reg-names = "io", "mem", "vw";
537			interrupts = <103 3>, <104 3>, <105 3>, <106 3>,
538				     <107 3>, <108 3>, <109 3>, <110 2>,
539				     <156 3>, <15 3>, <16 3>;
540			interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up",
541					  "oob_dn", "fc", "erst", "vw_chan_en",
542					  "vwct_0_6", "vwct_7_10";
543			status = "disabled";
544
545			/* Devices accessible to the Host via Logical Device mechanism.
546			 * Some devices are capable of having their registers mapped to
547			 * Host I/O or memory address space. Some devices are capable
548			 * of generating Serial IRQ to the Host over eSPI.
549			 */
550			mbox0: mbox@400f0000 {
551				reg = <0x400f0000 0x200>;
552				interrupts = <60 3>;
553				status = "disabled";
554			};
555			kbc0: kbc@400f0400 {
556				reg = <0x400f0400 0x400>, <0x400f2000 0x400>;
557				interrupts = <59 3>, <58 3>;
558				interrupt-names = "ibf", "obe";
559				status = "disabled";
560			};
561			acpi_ec0: acpi_ec@400f0800 {
562				reg = <0x400f0800 0x400>;
563				interrupts = <45 3>, <46 3>;
564				interrupt-names = "ibf", "obe";
565				status = "disabled";
566			};
567			acpi_ec1: acpi_ec@400f0c00 {
568				reg = <0x400f0c00 0x400>;
569				interrupts = <47 3>, <48 3>;
570				interrupt-names = "ibf", "obe";
571				status = "disabled";
572			};
573			acpi_ec2: acpi_ec@400f1000 {
574				reg = <0x400f1000 0x400>;
575				interrupts = <49 3>, <50 3>;
576				interrupt-names = "ibf", "obe";
577				status = "disabled";
578			};
579			acpi_ec3: acpi_ec@400f1400 {
580				reg = <0x400f1400 0x400>;
581				interrupts = <51 3>, <52 3>;
582				interrupt-names = "ibf", "obe";
583				status = "disabled";
584			};
585			acpi_ec4: acpi_ec@400f1800 {
586				reg = <0x400f1800 0x400>;
587				interrupts = <53 3>, <54 3>;
588				interrupt-names = "ibf", "obe";
589				status = "disabled";
590			};
591			acpi_pm1: acpi_pm1@400f1c00 {
592				reg = <0x400f1c00 0x400>;
593				interrupts = <55 3>, <56 3>, <57 3>;
594				interrupt-names = "ctl", "en", "sts";
595				status = "disabled";
596			};
597			glue: glue_logic@400f3c00 {
598				reg = <0x400f3c00 0x200>;
599				interrupts = <172 1>;
600				status = "disabled";
601			};
602			emi0: emi@400f4000 {
603				reg = <0x400f4000 0x400>;
604				interrupts = <42 3>;
605				status = "disabled";
606			};
607			emi1: emi@400f4400 {
608				reg = <0x400f4400 0x400>;
609				interrupts = <43 3>;
610				status = "disabled";
611			};
612			emi2: emi@400f4800 {
613				reg = <0x400f4800 0x400>;
614				interrupts = <44 3>;
615				status = "disabled";
616			};
617			/* Capture Host writes to a 4-byte I/O range
618			 * plus a one byte alias I/O location which maps
619			 * to one of the 4-byte locations.
620			 */
621			p80bd0: p80bd@400f8000 {
622				reg = <0x400f8000 0x400>;
623				interrupts = <62 0>;
624				status = "disabled";
625			};
626		};
627		/* eSPI target attached flash controller.
628		 * When this device is fully activated via its driver, it takes
629		 * ownership of the QSPI controller. EC access to QSPI
630		 * registers is discarded by hardware.
631		 */
632		espi_taf0: espi_taf@40008000 {
633			reg = <0x40008000 0x400>, <0x40070000 0x400>, <0x40071000 0x400>;
634			reg-names = "tafbr", "tafqspi", "tafcomm";
635			interrupts = <166 3>, <167 3>;
636			interrupt-names = "done", "err";
637			status = "disabled";
638		};
639	};
640};
641
642&nvic {
643	arm,num-irq-priority-bits = <3>;
644};
645
646&systick {
647	status = "disabled";
648};
649