1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2017 Intel Corporation. All rights reserved.
4 *
5 * Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
6 */
7
8 #ifndef __SOF_DRIVERS_DMIC_H__
9 #define __SOF_DRIVERS_DMIC_H__
10
11 #if CONFIG_INTEL_DMIC
12
13 /* Let find up to 50 mode candidates to choose from */
14 #define DMIC_MAX_MODES 50
15
16 /* Minimum OSR is always applied for 48 kHz and less sample rates */
17 #define DMIC_MIN_OSR 50
18
19 /* These are used as guideline for configuring > 48 kHz sample rates. The
20 * minimum OSR can be relaxed down to 40 (use 3.84 MHz clock for 96 kHz).
21 */
22 #define DMIC_HIGH_RATE_MIN_FS 64000
23 #define DMIC_HIGH_RATE_OSR_MIN 40
24
25 /* HW FIR pipeline needs 5 additional cycles per channel for internal
26 * operations. This is used in MAX filter length check.
27 */
28 #define DMIC_FIR_PIPELINE_OVERHEAD 5
29
30 /* The microphones create a low frequecy thump sound when clock is enabled.
31 * The unmute linear gain ramp chacteristic is defined here.
32 * NOTE: Do not set any of these to 0.
33 */
34 #define DMIC_UNMUTE_RAMP_US 1000 /* 1 ms (in microseconds) */
35 #define DMIC_UNMUTE_CIC 1 /* Unmute CIC at 1 ms */
36 #define DMIC_UNMUTE_FIR 2 /* Unmute FIR at 2 ms */
37
38 #if CONFIG_TIGERLAKE
39 #define DMIC_HW_VERSION 1
40 #define DMIC_HW_CONTROLLERS 2
41 #define DMIC_HW_FIFOS 2
42 #endif
43
44 /* For NHLT DMIC configuration parsing */
45 #define DMIC_HW_CONTROLLERS_MAX 4
46 #define DMIC_HW_FIFOS_MAX 2
47
48 #endif
49
50 #if DMIC_HW_VERSION
51
52 #include <ipc/dai-intel.h>
53 #include <sof/audio/format.h>
54 #include <rtos/bit.h>
55 #include <sof/lib/dai.h>
56 #include <rtos/wait.h>
57 #include <stdint.h>
58
59 /* Parameters used in modes computation */
60 #define DMIC_HW_BITS_CIC 26
61 #define DMIC_HW_BITS_FIR_COEF 20
62 #define DMIC_HW_BITS_FIR_GAIN 20
63 #define DMIC_HW_BITS_FIR_INPUT 22
64 #define DMIC_HW_BITS_FIR_OUTPUT 24
65 #define DMIC_HW_BITS_FIR_INTERNAL 26
66 #define DMIC_HW_BITS_GAIN_OUTPUT 22
67 #define DMIC_HW_FIR_LENGTH_MAX 250
68 #define DMIC_HW_CIC_SHIFT_MIN -8
69 #define DMIC_HW_CIC_SHIFT_MAX 4
70 #define DMIC_HW_FIR_SHIFT_MIN 0
71 #define DMIC_HW_FIR_SHIFT_MAX 8
72 #define DMIC_HW_CIC_DECIM_MIN 5
73 #define DMIC_HW_CIC_DECIM_MAX 31 /* Note: Limited by BITS_CIC */
74 #define DMIC_HW_FIR_DECIM_MIN 2
75 #define DMIC_HW_FIR_DECIM_MAX 20 /* Note: Practical upper limit */
76 #define DMIC_HW_SENS_Q28 Q_CONVERT_FLOAT(1.0, 28) /* Q1.28 */
77 #define DMIC_HW_PDM_CLK_MIN 100000 /* Note: Practical min value */
78 #define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
79 #define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
80
81 /* DMIC register offsets */
82
83 /* Global registers */
84 #define OUTCONTROL0 0x0000
85 #define OUTSTAT0 0x0004
86 #define OUTDATA0 0x0008
87 #define OUTCONTROL1 0x0100
88 #define OUTSTAT1 0x0104
89 #define OUTDATA1 0x0108
90 #define PDM0 0x1000
91 #define PDM0_COEFFICIENT_A 0x1400
92 #define PDM0_COEFFICIENT_B 0x1800
93 #define PDM1 0x2000
94 #define PDM1_COEFFICIENT_A 0x2400
95 #define PDM1_COEFFICIENT_B 0x2800
96 #define PDM2 0x3000
97 #define PDM2_COEFFICIENT_A 0x3400
98 #define PDM2_COEFFICIENT_B 0x3800
99 #define PDM3 0x4000
100 #define PDM3_COEFFICIENT_A 0x4400
101 #define PDM3_COEFFICIENT_B 0x4800
102 #define PDM_COEF_RAM_A_LENGTH 0x0400
103 #define PDM_COEF_RAM_B_LENGTH 0x0400
104
105 /* Local registers in each PDMx */
106 #define CIC_CONTROL 0x000
107 #define CIC_CONFIG 0x004
108 #define MIC_CONTROL 0x00c
109 #define FIR_CONTROL_A 0x020
110 #define FIR_CONFIG_A 0x024
111 #define DC_OFFSET_LEFT_A 0x028
112 #define DC_OFFSET_RIGHT_A 0x02c
113 #define OUT_GAIN_LEFT_A 0x030
114 #define OUT_GAIN_RIGHT_A 0x034
115 #define FIR_CONTROL_B 0x040
116 #define FIR_CONFIG_B 0x044
117 #define DC_OFFSET_LEFT_B 0x048
118 #define DC_OFFSET_RIGHT_B 0x04c
119 #define OUT_GAIN_LEFT_B 0x050
120 #define OUT_GAIN_RIGHT_B 0x054
121
122 /* Register bits */
123
124 /* OUTCONTROLx IPM bit fields style */
125 #if DMIC_HW_VERSION == 1 || (DMIC_HW_VERSION == 2 && DMIC_HW_CONTROLLERS <= 2)
126 #define DMIC_IPM_VER1
127 #elif DMIC_HW_VERSION == 2 && DMIC_HW_CONTROLLERS > 2
128 #define DMIC_IPM_VER2
129 #else
130 #error Not supported HW version
131 #endif
132
133 #define OUTCONTROL0_BFTH_MAX 4 /* Max depth 16 */
134
135 #if defined DMIC_IPM_VER1
136 /* OUTCONTROL0 bits */
137 #define OUTCONTROL0_TIE_BIT BIT(27)
138 #define OUTCONTROL0_SIP_BIT BIT(26)
139 #define OUTCONTROL0_FINIT_BIT BIT(25)
140 #define OUTCONTROL0_FCI_BIT BIT(24)
141 #define OUTCONTROL0_TIE(x) SET_BIT(27, x)
142 #define OUTCONTROL0_SIP(x) SET_BIT(26, x)
143 #define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
144 #define OUTCONTROL0_FCI(x) SET_BIT(24, x)
145 #define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
146 #define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
147 #define OUTCONTROL0_IPM(x) SET_BITS(17, 16, x)
148 #define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
149
150 #define OUTCONTROL0_TIE_GET(x) GET_BIT(27, x)
151 #define OUTCONTROL0_SIP_GET(x) GET_BIT(26, x)
152 #define OUTCONTROL0_FINIT_GET(x) GET_BIT(25, x)
153 #define OUTCONTROL0_FCI_GET(x) GET_BIT(24, x)
154 #define OUTCONTROL0_BFTH_GET(x) GET_BITS(23, 20, x)
155 #define OUTCONTROL0_OF_GET(x) GET_BITS(19, 18, x)
156 #define OUTCONTROL0_IPM_GET(x) GET_BITS(17, 16, x)
157 #define OUTCONTROL0_TH_GET(x) GET_BITS(5, 0, x)
158
159 /* OUTCONTROL1 bits */
160 #define OUTCONTROL1_TIE_BIT BIT(27)
161 #define OUTCONTROL1_SIP_BIT BIT(26)
162 #define OUTCONTROL1_FINIT_BIT BIT(25)
163 #define OUTCONTROL1_FCI_BIT BIT(24)
164 #define OUTCONTROL1_TIE(x) SET_BIT(27, x)
165 #define OUTCONTROL1_SIP(x) SET_BIT(26, x)
166 #define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
167 #define OUTCONTROL1_FCI(x) SET_BIT(24, x)
168 #define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
169 #define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
170 #define OUTCONTROL1_IPM(x) SET_BITS(17, 16, x)
171 #define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
172
173 #define OUTCONTROL1_TIE_GET(x) GET_BIT(27, x)
174 #define OUTCONTROL1_SIP_GET(x) GET_BIT(26, x)
175 #define OUTCONTROL1_FINIT_GET(x) GET_BIT(25, x)
176 #define OUTCONTROL1_FCI_GET(x) GET_BIT(24, x)
177 #define OUTCONTROL1_BFTH_GET(x) GET_BITS(23, 20, x)
178 #define OUTCONTROL1_OF_GET(x) GET_BITS(19, 18, x)
179 #define OUTCONTROL1_IPM_GET(x) GET_BITS(17, 16, x)
180 #define OUTCONTROL1_TH_GET(x) GET_BITS(5, 0, x)
181 #endif
182
183 #if defined DMIC_IPM_VER2
184 /* OUTCONTROL0 bits */
185 #define OUTCONTROL0_TIE_BIT BIT(27)
186 #define OUTCONTROL0_SIP_BIT BIT(26)
187 #define OUTCONTROL0_FINIT_BIT BIT(25)
188 #define OUTCONTROL0_FCI_BIT BIT(24)
189 #define OUTCONTROL0_TIE(x) SET_BIT(27, x)
190 #define OUTCONTROL0_SIP(x) SET_BIT(26, x)
191 #define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
192 #define OUTCONTROL0_FCI(x) SET_BIT(24, x)
193 #define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
194 #define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
195 #define OUTCONTROL0_IPM(x) SET_BITS(17, 15, x)
196 #define OUTCONTROL0_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
197 #define OUTCONTROL0_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
198 #define OUTCONTROL0_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
199 #define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
200 #define OUTCONTROL0_IPM_SOURCE_MODE(x) SET_BIT(6, x)
201 #define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
202 #define OUTCONTROL0_TIE_GET(x) GET_BIT(27, x)
203 #define OUTCONTROL0_SIP_GET(x) GET_BIT(26, x)
204 #define OUTCONTROL0_FINIT_GET(x) GET_BIT(25, x)
205 #define OUTCONTROL0_FCI_GET(x) GET_BIT(24, x)
206 #define OUTCONTROL0_BFTH_GET(x) GET_BITS(23, 20, x)
207 #define OUTCONTROL0_OF_GET(x) GET_BITS(19, 18, x)
208 #define OUTCONTROL0_IPM_GET(x) GET_BITS(17, 15, x)
209 #define OUTCONTROL0_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
210 #define OUTCONTROL0_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
211 #define OUTCONTROL0_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
212 #define OUTCONTROL0_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
213 #define OUTCONTROL0_IPM_SOURCE_MODE_GET(x) GET_BIT(6, x)
214 #define OUTCONTROL0_TH_GET(x) GET_BITS(5, 0, x)
215
216 /* OUTCONTROL1 bits */
217 #define OUTCONTROL1_TIE_BIT BIT(27)
218 #define OUTCONTROL1_SIP_BIT BIT(26)
219 #define OUTCONTROL1_FINIT_BIT BIT(25)
220 #define OUTCONTROL1_FCI_BIT BIT(24)
221 #define OUTCONTROL1_TIE(x) SET_BIT(27, x)
222 #define OUTCONTROL1_SIP(x) SET_BIT(26, x)
223 #define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
224 #define OUTCONTROL1_FCI(x) SET_BIT(24, x)
225 #define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
226 #define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
227 #define OUTCONTROL1_IPM(x) SET_BITS(17, 15, x)
228 #define OUTCONTROL1_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
229 #define OUTCONTROL1_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
230 #define OUTCONTROL1_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
231 #define OUTCONTROL1_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
232 #define OUTCONTROL1_IPM_SOURCE_MODE(x) SET_BIT(6, x)
233 #define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
234 #define OUTCONTROL1_TIE_GET(x) GET_BIT(27, x)
235 #define OUTCONTROL1_SIP_GET(x) GET_BIT(26, x)
236 #define OUTCONTROL1_FINIT_GET(x) GET_BIT(25, x)
237 #define OUTCONTROL1_FCI_GET(x) GET_BIT(24, x)
238 #define OUTCONTROL1_BFTH_GET(x) GET_BITS(23, 20, x)
239 #define OUTCONTROL1_OF_GET(x) GET_BITS(19, 18, x)
240 #define OUTCONTROL1_IPM_GET(x) GET_BITS(17, 15, x)
241 #define OUTCONTROL1_IPM_SOURCE_1_GET(x) GET_BITS(14, 13, x)
242 #define OUTCONTROL1_IPM_SOURCE_2_GET(x) GET_BITS(12, 11, x)
243 #define OUTCONTROL1_IPM_SOURCE_3_GET(x) GET_BITS(10, 9, x)
244 #define OUTCONTROL1_IPM_SOURCE_4_GET(x) GET_BITS(8, 7, x)
245 #define OUTCONTROL1_IPM_SOURCE_MODE_GET(x) GET_BIT(6, x)
246 #define OUTCONTROL1_TH_GET(x) GET_BITS(5, 0, x)
247
248 #define OUTCONTROLX_IPM_NUMSOURCES 4
249
250 #endif
251
252 /* OUTSTAT0 bits */
253 #define OUTSTAT0_AFE_BIT BIT(31)
254 #define OUTSTAT0_ASNE_BIT BIT(29)
255 #define OUTSTAT0_RFS_BIT BIT(28)
256 #define OUTSTAT0_ROR_BIT BIT(27)
257 #define OUTSTAT0_FL_MASK MASK(6, 0)
258
259 /* OUTSTAT1 bits */
260 #define OUTSTAT1_AFE_BIT BIT(31)
261 #define OUTSTAT1_ASNE_BIT BIT(29)
262 #define OUTSTAT1_RFS_BIT BIT(28)
263 #define OUTSTAT1_ROR_BIT BIT(27)
264 #define OUTSTAT1_FL_MASK MASK(6, 0)
265
266 /* CIC_CONTROL bits */
267 #define CIC_CONTROL_SOFT_RESET_BIT BIT(16)
268 #define CIC_CONTROL_CIC_START_B_BIT BIT(15)
269 #define CIC_CONTROL_CIC_START_A_BIT BIT(14)
270 #define CIC_CONTROL_MIC_B_POLARITY_BIT BIT(3)
271 #define CIC_CONTROL_MIC_A_POLARITY_BIT BIT(2)
272 #define CIC_CONTROL_MIC_MUTE_BIT BIT(1)
273 #define CIC_CONTROL_STEREO_MODE_BIT BIT(0)
274
275 #define CIC_CONTROL_SOFT_RESET(x) SET_BIT(16, x)
276 #define CIC_CONTROL_CIC_START_B(x) SET_BIT(15, x)
277 #define CIC_CONTROL_CIC_START_A(x) SET_BIT(14, x)
278 #define CIC_CONTROL_MIC_B_POLARITY(x) SET_BIT(3, x)
279 #define CIC_CONTROL_MIC_A_POLARITY(x) SET_BIT(2, x)
280 #define CIC_CONTROL_MIC_MUTE(x) SET_BIT(1, x)
281 #define CIC_CONTROL_STEREO_MODE(x) SET_BIT(0, x)
282
283 #define CIC_CONTROL_SOFT_RESET_GET(x) GET_BIT(16, x)
284 #define CIC_CONTROL_CIC_START_B_GET(x) GET_BIT(15, x)
285 #define CIC_CONTROL_CIC_START_A_GET(x) GET_BIT(14, x)
286 #define CIC_CONTROL_MIC_B_POLARITY_GET(x) GET_BIT(3, x)
287 #define CIC_CONTROL_MIC_A_POLARITY_GET(x) GET_BIT(2, x)
288 #define CIC_CONTROL_MIC_MUTE_GET(x) GET_BIT(1, x)
289 #define CIC_CONTROL_STEREO_MODE_GET(x) GET_BIT(0, x)
290
291 /* CIC_CONFIG bits */
292 #define CIC_CONFIG_CIC_SHIFT(x) SET_BITS(27, 24, x)
293 #define CIC_CONFIG_COMB_COUNT(x) SET_BITS(15, 8, x)
294
295 /* CIC_CONFIG masks */
296 #define CIC_CONFIG_CIC_SHIFT_MASK MASK(27, 24)
297 #define CIC_CONFIG_COMB_COUNT_MASK MASK(15, 8)
298
299 #define CIC_CONFIG_CIC_SHIFT_GET(x) GET_BITS(27, 24, x)
300 #define CIC_CONFIG_COMB_COUNT_GET(x) GET_BITS(15, 8, x)
301
302 /* MIC_CONTROL bits */
303 #define MIC_CONTROL_PDM_EN_B_BIT BIT(1)
304 #define MIC_CONTROL_PDM_EN_A_BIT BIT(0)
305 #define MIC_CONTROL_PDM_CLKDIV(x) SET_BITS(15, 8, x)
306 #define MIC_CONTROL_PDM_SKEW(x) SET_BITS(7, 4, x)
307 #define MIC_CONTROL_CLK_EDGE(x) SET_BIT(3, x)
308 #define MIC_CONTROL_PDM_EN_B(x) SET_BIT(1, x)
309 #define MIC_CONTROL_PDM_EN_A(x) SET_BIT(0, x)
310
311 /* MIC_CONTROL masks */
312 #define MIC_CONTROL_PDM_CLKDIV_MASK MASK(15, 8)
313
314 #define MIC_CONTROL_PDM_CLKDIV_GET(x) GET_BITS(15, 8, x)
315 #define MIC_CONTROL_PDM_SKEW_GET(x) GET_BITS(7, 4, x)
316 #define MIC_CONTROL_PDM_CLK_EDGE_GET(x) GET_BIT(3, x)
317 #define MIC_CONTROL_PDM_EN_B_GET(x) GET_BIT(1, x)
318 #define MIC_CONTROL_PDM_EN_A_GET(x) GET_BIT(0, x)
319
320 /* FIR_CONTROL_A bits */
321 #define FIR_CONTROL_A_START_BIT BIT(7)
322 #define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
323 #define FIR_CONTROL_A_MUTE_BIT BIT(1)
324 #define FIR_CONTROL_A_START(x) SET_BIT(7, x)
325 #define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
326 #define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
327 #define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
328 #define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
329
330 #define FIR_CONTROL_A_START_GET(x) GET_BIT(7, x)
331 #define FIR_CONTROL_A_ARRAY_START_EN_GET(x) GET_BIT(6, x)
332 #define FIR_CONTROL_A_DCCOMP_GET(x) GET_BIT(4, x)
333 #define FIR_CONTROL_A_MUTE_GET(x) GET_BIT(1, x)
334 #define FIR_CONTROL_A_STEREO_GET(x) GET_BIT(0, x)
335
336 /* FIR_CONFIG_A bits */
337 #define FIR_CONFIG_A_FIR_DECIMATION(x) SET_BITS(20, 16, x)
338 #define FIR_CONFIG_A_FIR_SHIFT(x) SET_BITS(11, 8, x)
339 #define FIR_CONFIG_A_FIR_LENGTH(x) SET_BITS(7, 0, x)
340
341 #define FIR_CONFIG_A_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
342 #define FIR_CONFIG_A_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
343 #define FIR_CONFIG_A_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
344
345 /* DC offset compensation time constants */
346 #define DCCOMP_TC0 0
347 #define DCCOMP_TC1 1
348 #define DCCOMP_TC2 2
349 #define DCCOMP_TC3 3
350 #define DCCOMP_TC4 4
351 #define DCCOMP_TC5 5
352 #define DCCOMP_TC6 6
353 #define DCCOMP_TC7 7
354
355 /* DC_OFFSET_LEFT_A bits */
356 #define DC_OFFSET_LEFT_A_DC_OFFS(x) SET_BITS(21, 0, x)
357
358 /* DC_OFFSET_RIGHT_A bits */
359 #define DC_OFFSET_RIGHT_A_DC_OFFS(x) SET_BITS(21, 0, x)
360
361 /* OUT_GAIN_LEFT_A bits */
362 #define OUT_GAIN_LEFT_A_GAIN(x) SET_BITS(19, 0, x)
363
364 /* OUT_GAIN_RIGHT_A bits */
365 #define OUT_GAIN_RIGHT_A_GAIN(x) SET_BITS(19, 0, x)
366
367 /* FIR_CONTROL_B bits */
368 #define FIR_CONTROL_B_START_BIT BIT(7)
369 #define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
370 #define FIR_CONTROL_B_MUTE_BIT BIT(1)
371 #define FIR_CONTROL_B_START(x) SET_BIT(7, x)
372 #define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
373 #define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
374 #define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
375 #define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
376
377 #define FIR_CONTROL_B_START_GET(x) GET_BIT(7, x)
378 #define FIR_CONTROL_B_ARRAY_START_EN_GET(x) GET_BIT(6, x)
379 #define FIR_CONTROL_B_DCCOMP_GET(x) GET_BIT(4, x)
380 #define FIR_CONTROL_B_MUTE_GET(x) GET_BIT(1, x)
381 #define FIR_CONTROL_B_STEREO_GET(x) GET_BIT(0, x)
382
383 /* FIR_CONFIG_B bits */
384 #define FIR_CONFIG_B_FIR_DECIMATION(x) SET_BITS(20, 16, x)
385 #define FIR_CONFIG_B_FIR_SHIFT(x) SET_BITS(11, 8, x)
386 #define FIR_CONFIG_B_FIR_LENGTH(x) SET_BITS(7, 0, x)
387
388 #define FIR_CONFIG_B_FIR_DECIMATION_GET(x) GET_BITS(20, 16, x)
389 #define FIR_CONFIG_B_FIR_SHIFT_GET(x) GET_BITS(11, 8, x)
390 #define FIR_CONFIG_B_FIR_LENGTH_GET(x) GET_BITS(7, 0, x)
391
392 /* DC_OFFSET_LEFT_B bits */
393 #define DC_OFFSET_LEFT_B_DC_OFFS(x) SET_BITS(21, 0, x)
394
395 /* DC_OFFSET_RIGHT_B bits */
396 #define DC_OFFSET_RIGHT_B_DC_OFFS(x) SET_BITS(21, 0, x)
397
398 /* OUT_GAIN_LEFT_B bits */
399 #define OUT_GAIN_LEFT_B_GAIN(x) SET_BITS(19, 0, x)
400
401 /* OUT_GAIN_RIGHT_B bits */
402 #define OUT_GAIN_RIGHT_B_GAIN(x) SET_BITS(19, 0, x)
403
404 /* FIR coefficients */
405 #define FIR_COEF_A(x) SET_BITS(19, 0, x)
406 #define FIR_COEF_B(x) SET_BITS(19, 0, x)
407
408 /* Used for scaling FIR coefficients for HW */
409 #define DMIC_HW_FIR_COEF_MAX ((1 << (DMIC_HW_BITS_FIR_COEF - 1)) - 1)
410 #define DMIC_HW_FIR_COEF_Q (DMIC_HW_BITS_FIR_COEF - 1)
411
412 /* Internal precision in gains computation, e.g. Q4.28 in int32_t */
413 #define DMIC_FIR_SCALE_Q 28
414
415 /* Used in unmute ramp values calculation */
416 #define DMIC_HW_FIR_GAIN_MAX ((1 << (DMIC_HW_BITS_FIR_GAIN - 1)) - 1)
417
418 /* Hardwired log ramp parameters. The first value is the initial gain in
419 * decibels. The default ramp time is provided by 1st order equation
420 * ramp time = coef * samplerate + offset. The default ramp is 200 ms for
421 * 48 kHz and 400 ms for 16 kHz.
422 */
423 #define LOGRAMP_START_DB Q_CONVERT_FLOAT(-90, DB2LIN_FIXED_INPUT_QY)
424 #define LOGRAMP_TIME_COEF_Q15 -205 /* dy/dx (16000,400) (48000,200) */
425 #define LOGRAMP_TIME_OFFS_Q0 500 /* Offset for line slope */
426
427 /* Limits for ramp time from topology */
428 #define LOGRAMP_TIME_MIN_MS 10 /* Min. 10 ms */
429 #define LOGRAMP_TIME_MAX_MS 1000 /* Max. 1s */
430
431 /* Simplify log ramp step calculation equation with this constant term */
432 #define LOGRAMP_CONST_TERM ((int32_t) \
433 ((int64_t)-LOGRAMP_START_DB * DMIC_UNMUTE_RAMP_US / 1000))
434
435 /* Fractional shift for gain update. Gain format is Q2.30. */
436 #define Q_SHIFT_GAIN_X_GAIN_COEF \
437 (Q_SHIFT_BITS_32(30, DB2LIN_FIXED_OUTPUT_QY, 30))
438
439 #define dmic_irq(dmic) dmic->plat_data.irq
440 #define dmic_irq_name(dmic) dmic->plat_data.irq_name
441
442 /* Common data for all DMIC DAI instances */
443 struct dmic_global_shared {
444 struct sof_ipc_dai_dmic_params prm[DMIC_HW_FIFOS]; /* Configuration requests */
445 uint32_t active_fifos_mask; /* Bits (dai->index) are set to indicate active FIFO */
446 uint32_t pause_mask; /* Bits (dai->index) are set to indicate driver pause */
447 };
448
449 /* DMIC private data */
450 struct dmic_pdata {
451 struct dmic_global_shared *global; /* Common data for all DMIC DAI instances */
452 uint16_t enable[DMIC_HW_CONTROLLERS]; /* Mic 0 and 1 enable bits array for PDMx */
453 uint32_t state; /* Driver component state */
454 int32_t startcount; /* Counter that controls HW unmute */
455 int32_t gain_coef; /* Gain update constant */
456 int32_t gain; /* Gain value to be applied to HW */
457 int32_t unmute_ramp_time_ms; /* Unmute ramp time in milliseconds */
458 int irq; /* Interrupt number used */
459 enum sof_ipc_frame dai_format; /* PCM format s32_le etc. */
460 int dai_channels; /* Channels count */
461 int dai_rate; /* Sample rate in Hz */
462 };
463
464 struct decim_modes {
465 int16_t clkdiv[DMIC_MAX_MODES];
466 int16_t mcic[DMIC_MAX_MODES];
467 int16_t mfir[DMIC_MAX_MODES];
468 int num_of_modes;
469 };
470
471 struct matched_modes {
472 int16_t clkdiv[DMIC_MAX_MODES];
473 int16_t mcic[DMIC_MAX_MODES];
474 int16_t mfir_a[DMIC_MAX_MODES];
475 int16_t mfir_b[DMIC_MAX_MODES];
476 int num_of_modes;
477 };
478
479 struct dmic_configuration {
480 struct pdm_decim *fir_a;
481 struct pdm_decim *fir_b;
482 int clkdiv;
483 int mcic;
484 int mfir_a;
485 int mfir_b;
486 int cic_shift;
487 int fir_a_shift;
488 int fir_b_shift;
489 int fir_a_length;
490 int fir_b_length;
491 int32_t fir_a_scale;
492 int32_t fir_b_scale;
493 };
494
495 struct nhlt_dmic_gateway_attributes {
496 uint32_t dw;
497 };
498
499 struct nhlt_dmic_ts_group {
500 uint32_t ts_group[4];
501 };
502
503 struct nhlt_dmic_clock_on_delay {
504 uint32_t clock_on_delay;
505 };
506
507 struct nhlt_dmic_channel_ctrl_mask {
508 uint32_t channel_ctrl_mask;
509 };
510
511 struct nhlt_pdm_ctrl_mask {
512 uint32_t pdm_ctrl_mask;
513 };
514
515 struct nhlt_pdm_ctrl_cfg {
516 uint32_t cic_control;
517 uint32_t cic_config;
518 uint32_t reserved0;
519 uint32_t mic_control;
520 uint32_t pdm_sdw_map;
521 uint32_t reuse_fir_from_pdm;
522 uint32_t reserved1[2];
523 };
524
525 struct nhlt_pdm_ctrl_fir_cfg {
526 uint32_t fir_control;
527 uint32_t fir_config;
528 int32_t dc_offset_left;
529 int32_t dc_offset_right;
530 int32_t out_gain_left;
531 int32_t out_gain_right;
532 uint32_t reserved[2];
533 };
534
535 struct nhlt_pdm_fir_coeffs {
536 int32_t fir_coeffs[0];
537 };
538
539 int dmic_set_config_computed(struct dai *dai);
540 int dmic_get_hw_params_computed(struct dai *dai, struct sof_ipc_stream_params *params, int dir);
541 int dmic_set_config_nhlt(struct dai *dai, const void *spec_config);
542 int dmic_get_hw_params_nhlt(struct dai *dai, struct sof_ipc_stream_params *params, int dir);
543
544 extern const struct dai_driver dmic_driver;
545
dmic_get_unmute_ramp_from_samplerate(int rate)546 static inline int dmic_get_unmute_ramp_from_samplerate(int rate)
547 {
548 int32_t time_ms;
549
550 time_ms = sat_int32(Q_MULTSR_32X32((int64_t)rate, LOGRAMP_TIME_COEF_Q15, 0, 15, 0) +
551 LOGRAMP_TIME_OFFS_Q0);
552 if (time_ms > LOGRAMP_TIME_MAX_MS)
553 return LOGRAMP_TIME_MAX_MS;
554
555 if (time_ms < LOGRAMP_TIME_MIN_MS)
556 return LOGRAMP_TIME_MIN_MS;
557
558 return time_ms;
559 }
560
561 #endif /* DMIC_HW_VERSION */
562 #endif /* __SOF_DRIVERS_DMIC_H__ */
563
