1 /* 2 * Copyright (c) 2021-2023, The TrustedFirmware-M Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef CC3XX_REG_DEFS_H 9 #define CC3XX_REG_DEFS_H 10 11 #include <stdint.h> 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 #ifndef __IM 18 #define __IM volatile const /*! Defines 'read only' structure member permissions */ 19 #endif /* __IM */ 20 21 #ifndef __OM 22 #define __OM volatile /*! Defines 'write only' structure member permissions */ 23 #endif /* __OM */ 24 25 #ifndef __IOM 26 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ 27 #endif /* __IOM */ 28 29 #ifndef __PACKED_STRUCT 30 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 31 #endif /* __PACKED_STRUCT */ 32 33 #ifndef __PACKED_UNION 34 #define __PACKED_UNION union __attribute__((packed, aligned(1))) 35 #endif /* __PACKED_UNION */ 36 37 #ifndef __ALIGNED 38 #define __ALIGNED(x) __attribute__((aligned(x))) 39 #endif /* __ALIGNED */ 40 41 __PACKED_STRUCT __ALIGNED(4) _cc3xx_reg_map_t { 42 /* PKA block */ 43 __PACKED_STRUCT { 44 __IOM uint32_t memory_map[32]; 45 /*!< Offset: 0x0 (RW) */ 46 __IOM uint32_t opcode; 47 /*!< Offset: 0x80 (RW) */ 48 __IOM uint32_t n_np_t0_t1_addr; 49 /*!< Offset: 0x84 (RW) */ 50 __IM uint32_t pka_status; 51 /*!< Offset: 0x88 (RO) */ 52 __OM uint32_t pka_sw_reset; 53 /*!< Offset: 0x8C (WO) */ 54 __IOM uint32_t pka_l[8]; 55 /*!< Offset: 0x90 (RW) */ 56 __IM uint32_t pka_pipe_rdy; 57 /*!< Offset: 0xB0 (RO) */ 58 __IM uint32_t pka_done; 59 /*!< Offset: 0xB4 (RO) */ 60 __IOM uint32_t pka_mon_select; 61 /*!< Offset: 0xB8 (RW) */ 62 __IOM uint32_t pka_mongo_sel; 63 /*!< Offset: 0xBC (RW) */ 64 __IOM uint32_t pka_ram_enc; 65 /*!< Offset: 0xC0 (RW) */ 66 __IM uint32_t pka_version; 67 /*!< Offset: 0xC4 (RO) */ 68 uint8_t _reserved_1[8]; 69 /*!< Offset: 0xC8-0xCC Reserved */ 70 __IM uint32_t pka_mon_read; 71 /*!< Offset: 0xD0 (RO) */ 72 __OM uint32_t pka_sram_addr; 73 /*!< Offset: 0xD4 (WO) */ 74 __OM uint32_t pka_sram_wdata; 75 /*!< Offset: 0xD8 (WO) */ 76 __IOM uint32_t pka_sram_rdata; 77 /*!< Offset: 0xDC (RW) */ 78 __OM uint32_t pka_sram_wr_clr; 79 /*!< Offset: 0xE0 (WO) */ 80 __OM uint32_t pka_sram_raddr; 81 /*!< Offset: 0xE4 (WO) */ 82 uint8_t _reserved_2[8]; 83 /*!< Offset: 0xE8-0xEC Reserved */ 84 __OM uint32_t pka_word_access; 85 /*!< Offset: 0xF0 (WO) */ 86 uint8_t _reserved_3[4]; 87 /*!< Offset: 0xF4 Reserved */ 88 __OM uint32_t pka_buff_addr; 89 /*!< Offset: 0xF8 (WO) */ 90 uint8_t _reserved_4[4]; 91 /*!< Offset: 0xFC Reserved */ 92 } pka; 93 94 /* RNG block */ 95 __PACKED_STRUCT { 96 __IOM uint32_t rng_imr; 97 /*!< Offset: 0x100 (RW) */ 98 __IM uint32_t rng_isr; 99 /*!< Offset: 0x104 (RO) */ 100 __OM uint32_t rng_icr; 101 /*!< Offset: 0x108 (WO) */ 102 __IOM uint32_t trng_config; 103 /*!< Offset: 0x10C (RW) */ 104 __IM uint32_t trng_valid; 105 /*!< Offset: 0x110 (RO) */ 106 __IM uint32_t ehr_data[6]; 107 /*!< Offset: 0x114 (RO) */ 108 __IOM uint32_t rnd_source_enable; 109 /*!< Offset: 0x12C (RW) */ 110 __IOM uint32_t sample_cnt1; 111 /*!< Offset: 0x130 (RW) */ 112 __IOM uint32_t autocorr_statistic; 113 /*!< Offset: 0x134 (RW) */ 114 __IOM uint32_t trng_debug_control; 115 /*!< Offset: 0x138 (RW) */ 116 uint8_t _reserved_0[4]; 117 /*!< Offset: 0x13C Reserved */ 118 __IOM uint32_t rng_sw_reset; 119 /*!< Offset: 0x140 (RW) */ 120 uint8_t _reserved_1[112]; 121 /*!< Offset: 0x144-0x1B0 Reserved */ 122 __IM uint32_t rng_debug_en_input; 123 /*!< Offset: 0x1B4 (RO) */ 124 __IM uint32_t rng_busy; 125 /*!< Offset: 0x1B8 (RO) */ 126 __OM uint32_t rst_bits_counter; 127 /*!< Offset: 0x1BC (WO) */ 128 __IM uint32_t rng_version; 129 /*!< Offset: 0x1C0 (RO) */ 130 __OM uint32_t rng_clk_enable; 131 /*!< Offset: 0x1C4 (WO) */ 132 __IOM uint32_t rng_dma_enable; 133 /*!< Offset: 0x1C8 (RW) */ 134 __IOM uint32_t rng_dma_src_mask; 135 /*!< Offset: 0x1CC (RW) */ 136 __IOM uint32_t rng_dma_sram_addr; 137 /*!< Offset: 0x1D0 (RW) */ 138 __IOM uint32_t rng_dma_samples_num; 139 /*!< Offset: 0x1D4 (RW) */ 140 __IOM uint32_t rng_watchdog_val; 141 /*!< Offset: 0x1D8 (RW) */ 142 __IM uint32_t rng_dma_status; 143 /*!< Offset: 0x1DC (RO) */ 144 uint8_t _reserved_2[416]; 145 /*!< Offset: 0x1E0-0x380 Reserved */ 146 } rng; 147 148 /* ChaCha block */ 149 __PACKED_STRUCT { 150 __IOM uint32_t chacha_control_reg; 151 /*!< offset: 0x380 (RW) */ 152 __IM uint32_t chacha_version; 153 /*!< offset: 0x384 (RO) */ 154 __OM uint32_t chacha_key[8]; 155 /*!< offset: 0x388 (WO) */ 156 __IOM uint32_t chacha_iv[2]; 157 /*!< offset: 0x3a8 (RW) */ 158 __IM uint32_t chacha_busy; 159 /*!< offset: 0x3b0 (RO) */ 160 __IM uint32_t chacha_hw_flags; 161 /*!< offset: 0x3b4 (RO) */ 162 __IOM uint32_t chacha_block_cnt_lsb; 163 /*!< offset: 0x3b8 (RW) */ 164 __IOM uint32_t chacha_block_cnt_msb; 165 /*!< offset: 0x3bc (RW) */ 166 __OM uint32_t chacha_sw_reset; 167 /*!< offset: 0x3c0 (WO) */ 168 __IM uint32_t chacha_for_poly_key[8]; 169 /*!< offset: 0x3c4 (RO) */ 170 __IOM uint32_t chacha_byte_word_order_cntl_reg; 171 /*!< Offset: 0x3E4 (RW) */ 172 __IM uint32_t chacha_debug_reg; 173 /*!< offset: 0x3E8 (RO) */ 174 uint8_t _reserved_0[20]; 175 /*!< Offset: 0x3EC-0x3FC Reserved */ 176 } chacha; 177 178 /* AES block */ 179 __PACKED_STRUCT { 180 __OM uint32_t aes_key_0[8]; 181 /*!< Offset: 0x400 (WO) */ 182 __OM uint32_t aes_key_1[8]; 183 /*!< Offset: 0x420 (WO) */ 184 __IOM uint32_t aes_iv_0[4]; 185 /*!< Offset: 0x440 (RW) */ 186 __IOM uint32_t aes_iv_1[4]; 187 /*!< Offset: 0x450 (RW) */ 188 __IOM uint32_t aes_ctr_0[4]; 189 /*!< Offset: 0x460 (RW) */ 190 __IM uint32_t aes_busy; 191 /*!< Offset: 0x470 (RO) */ 192 uint8_t _reserved_0[4]; 193 /*!< Offset: 0x474 Reserved */ 194 __OM uint32_t aes_sk; 195 /*!< Offset: 0x478 (WO) */ 196 __OM uint32_t aes_cmac_init; 197 /*!< Offset: 0x47C (WO) */ 198 uint8_t _reserved_1[52]; 199 /*!< Offset: 0x480-0x4B0 Reserved */ 200 __OM uint32_t aes_sk1; 201 /*!< Offset: 0x4B4 (WO) */ 202 uint8_t _reserved_2[4]; 203 /*!< Offset: 0x4B8 Reserved */ 204 __IOM uint32_t aes_remaining_bytes; 205 /*!< Offset: 0x4BC (RW) */ 206 __IOM uint32_t aes_control; 207 /*!< Offset: 0x4C0 (RW) */ 208 uint8_t _reserved_3[4]; 209 /*!< Offset: 0x4C4 Reserved */ 210 __IM uint32_t aes_hw_flags; 211 /*!< Offset: 0x4C8 (RO) */ 212 uint8_t _reserved_4[12]; 213 /*!< Offset: 0x4CC-0x4D4 Reserved */ 214 __PACKED_UNION { 215 __IOM uint32_t aes_rbg_seed; 216 /*!< Offset: 0x4D8 (RW) */ 217 __IOM uint32_t aes_ctr_no_increment; 218 /*!< Offset: 0x4D8 (RW) */ 219 }; 220 uint8_t _reserved_5[20]; 221 /*!< Offset: 0x4DC-0x4EC Reserved */ 222 __IOM uint32_t aes_dfa_is_on; 223 /*!< Offset: 0x4F0 (RW) */ 224 uint8_t _reserved_6[4]; 225 /*!< Offset: 0x4F4 Reserved */ 226 __IM uint32_t aes_dfa_err_status; 227 /*!< Offset: 0x4F8 (RO) */ 228 __IM uint32_t aes_rbg_seeding_rdy; 229 /*!< Offset: 0x4FC (RO) */ 230 uint8_t _reserved_7[36]; 231 /*!< Offset: 0x500-0x520 Reserved */ 232 __OM uint32_t aes_cmac_size0_kick; 233 /*!< Offset: 0x524 (WO) */ 234 uint8_t _reserved_8[28]; 235 /*!< Offset: 0x528-0x540 Reserved */ 236 __IOM uint32_t aes_dummy_rounds_enable; 237 /*!< Offset: 0x544 (RW) */ 238 uint8_t _reserved_9[248]; 239 /*!< Offset: 0x548-0x63C Reserved */ 240 } aes; 241 242 /* Hash block */ 243 __PACKED_STRUCT { 244 __IOM uint32_t hash_h[9]; 245 /*!< Offset: 0x640 (RW) */ 246 uint8_t _reserved_0[32]; 247 /*!< Offset: 0x664-0x680 Reserved */ 248 __OM uint32_t auto_hw_padding; 249 /*!< Offset: 0x684 (WO) */ 250 __IOM uint32_t hash_xor_din; 251 /*!< Offset: 0x688 (RW) */ 252 uint8_t _reserved_1[8]; 253 /*!< Offset: 0x68C-0x690 Reserved */ 254 __OM uint32_t load_init_state; 255 /*!< Offset: 0x694 (WO) */ 256 uint8_t _reserved_2[12]; 257 /*!< Offset: 0x698-0x6A0 Reserved */ 258 __OM uint32_t hash_sel_aes_mac; 259 /*!< Offset: 0x6A4 (WO) */ 260 uint8_t _reserved_3[264]; 261 /*!< Offset: 0x6A8-0x6FC Reserved */ 262 __IM uint32_t hash_version; 263 /*!< Offset: 0x7B0 (RO) */ 264 uint8_t _reserved_4[12]; 265 /*!< Offset: 0x7B4-0x7BC Reserved */ 266 __IOM uint32_t hash_control; 267 /*!< Offset: 0x7C0 (RW) */ 268 __IOM uint32_t hash_pad_en; 269 /*!< Offset: 0x7C4 (RW) */ 270 __IOM uint32_t hash_pad_cfg; 271 /*!< Offset: 0x7C8 (RW) */ 272 __IOM uint32_t hash_cur_len[2]; 273 /*!< Offset: 0x7CC (RW) */ 274 uint8_t _reserved_5[8]; 275 /*!< Offset: 0x7D0-0x7D8 Reserved */ 276 __IM uint32_t hash_param; 277 /*!< Offset: 0x7DC (RO) */ 278 uint8_t _reserved_6[4]; 279 /*!< Offset: 0x7E0 Reserved */ 280 __OM uint32_t hash_aes_sw_reset; 281 /*!< Offset: 0x7E4 (WO) */ 282 __IOM uint32_t hash_endianess; 283 /*!< Offset: 0x7E8 (RW) */ 284 uint8_t _reserved_7[36]; 285 /*!< Offset: 0x7E4-0x80C Reserved */ 286 } hash; 287 288 /* Misc Block */ 289 __PACKED_STRUCT { 290 __IOM uint32_t aes_clk_enable; 291 /*!< Offset: 0x810 (RW) */ 292 uint8_t _reserved_0[4]; 293 /*!< Offset: 0x814 Reserved */ 294 __IOM uint32_t hash_clk_enable; 295 /*!< Offset: 0x818 (RW) */ 296 __IOM uint32_t pka_clk_enable; 297 /*!< Offset: 0x81C (RW) */ 298 __IOM uint32_t dma_clk_enable; 299 /*!< Offset: 0x820 (RW) */ 300 __IM uint32_t clk_status; 301 /*!< Offset: 0x824 (RO) */ 302 uint8_t _reserved_1[48]; 303 /*!< Offset: 0x828-0x854 Reserved */ 304 __OM uint32_t chacha_clk_enable; 305 /*!< Offset: 0x858 (WO) */ 306 uint8_t _reserved_2[164]; 307 /*!< Offset: 0x85C-0x8FC Reserved */ 308 } misc; 309 310 /* CC_CTL Block */ 311 __PACKED_STRUCT { 312 __OM uint32_t crypto_ctl; 313 /*!< Offset: 0x900 (WO) */ 314 uint8_t _reserved_0[12]; 315 /*!< Offset: 0x904-0x90C Reserved */ 316 __IM uint32_t crypto_busy; 317 /*!< Offset: 0x910 (RO) */ 318 uint8_t _reserved_1[8]; 319 /*!< Offset: 0x914-0x918 Reserved */ 320 __IM uint32_t hash_busy; 321 /*!< Offset: 0x91C (RO) */ 322 uint8_t _reserved_2[16]; 323 /*!< Offset: 0x920-0x92C Reserved */ 324 __IOM uint32_t context_id; 325 /*!< Offset: 0x930 (RW) */ 326 uint8_t _reserved_3[44]; 327 /*!< Offset: 0x85C-0x8FC Reserved */ 328 } cc_ctl; 329 330 /* GHash block */ 331 __PACKED_STRUCT { 332 __OM uint32_t ghash_subkey_0[4]; 333 /*!< Offset: 0x960 (WO) */ 334 __IOM uint32_t ghash_iv_0[4]; 335 /*!< Offset: 0x970 (RW) */ 336 __IM uint32_t ghash_busy; 337 /*!< Offset: 0x980 (RO) */ 338 __OM uint32_t ghash_init; 339 /*!< Offset: 0x984 (WO) */ 340 uint8_t _reserved_0[120]; 341 /*!< Offset: 0x988-0x9FC Reserved */ 342 } ghash; 343 344 /* Host_RGF block */ 345 __PACKED_STRUCT { 346 __IM uint32_t host_rgf_irr; 347 /*!< Offset: 0xA00 (RO) */ 348 __IOM uint32_t host_rgf_imr; 349 /*!< Offset: 0xA04 (RW) */ 350 __OM uint32_t host_rgf_icr; 351 /*!< Offset: 0xA08 (WO) */ 352 __IOM uint32_t host_rgf_endian; 353 /*!< Offset: 0xA0C (RW) */ 354 uint8_t _reserved_0[20]; 355 /*!< Offset: 0xA10-0xA20 Reserved */ 356 __IM uint32_t host_rgf_signature; 357 /*!< Offset: 0xA24 (RO) */ 358 __IM uint32_t host_boot; 359 /*!< Offset: 0xA28 (RO) */ 360 uint8_t _reserved_1[12]; 361 /*!< Offset: 0xA2C-0xA34 Reserved */ 362 __IOM uint32_t host_cryptokey_sel; 363 /*!< Offset: 0xA38 (RW) */ 364 uint8_t _reserved_2[60]; 365 /*!< Offset: 0xA3C-0xA78 Reserved */ 366 __IOM uint32_t host_core_clk_gating_enable; 367 /*!< Offset: 0xA78 (RW) */ 368 __IM uint32_t host_cc_is_idle; 369 /*!< Offset: 0xA7C (RO) */ 370 __IOM uint32_t host_powerdown; 371 /*!< Offset: 0xA80 (RW) */ 372 __IM uint32_t host_remove_ghash_engine; 373 /*!< Offset: 0xA84 (RO) */ 374 __IM uint32_t host_remove_chacha_engine; 375 /*!< Offset: 0xA88 (RO) */ 376 __IOM uint32_t host_sf_dynamic_cntl; 377 /*!< Offset: 0xA8C (RW) */ 378 __IM uint32_t host_sf_ready; 379 /*!< Offset: 0xA90 (RO) */ 380 uint8_t _reserved_3[108]; 381 /*!< Offset: 0xA94-0xAFC Reserved */ 382 } host_rgf; 383 384 /* AHB block */ 385 __PACKED_STRUCT { 386 __IOM uint32_t ahbm_singles; 387 /*!< Offset: 0xB00 (RW) */ 388 __IOM uint32_t ahbm_hprot; 389 /*!< Offset: 0xB04 (RW) */ 390 __IOM uint32_t ahbm_hmastlock; 391 /*!< Offset: 0xB08 (RW) */ 392 __IOM uint32_t ahbm_hnonsec; 393 /*!< Offset: 0xB0C (RW) */ 394 uint8_t _reserved_0[240]; 395 /*!< Offset: 0xB10-0xBF4 Reserved */ 396 } ahb; 397 398 /* DIN block */ 399 __PACKED_STRUCT { 400 __OM uint32_t din_buffer; 401 /*!< Offset: 0xC00 (WO) */ 402 uint8_t _reserved_0[28]; 403 /*!< Offset: 0xC04-0xC1C Reserved */ 404 __IM uint32_t din_mem_dma_busy; 405 /*!< Offset: 0xC20 (RO) */ 406 uint8_t _reserved_1[4]; 407 /*!< Offset: 0xC24 Reserved */ 408 __OM uint32_t src_lli_word0; 409 /*!< Offset: 0xC28 (WO) */ 410 __OM uint32_t src_lli_word1; 411 /*!< Offset: 0xC2C (WO) */ 412 __IOM uint32_t sram_src_addr; 413 /*!< Offset: 0xC30 (RW) */ 414 __IOM uint32_t din_sram_bytes_len; 415 /*!< Offset: 0xC34 (RW) */ 416 __IM uint32_t din_sram_dma_busy; 417 /*!< Offset: 0xC38 (RO) */ 418 uint8_t _reserved_2[12]; 419 /*!< Offset: 0xC3C-0xC44 Reserved */ 420 __OM uint32_t din_cpu_data_size; 421 /*!< Offset: 0xC48 (WO) */ 422 uint8_t _reserved_3[4]; 423 /*!< Offset: 0xC4C Reserved */ 424 __IM uint32_t fifo_in_empty; 425 /*!< Offset: 0xC50 (RO) */ 426 uint8_t _reserved_4[4]; 427 /*!< Offset: 0xC54 Reserved */ 428 __OM uint32_t din_fifo_rst_pntr; 429 /*!< Offset: 0xC58 (WO) */ 430 uint8_t _reserved_5[164]; 431 /*!< Offset: 0xC5C-0xCFC Reserved */ 432 } din; 433 434 /* DOUT block */ 435 __PACKED_STRUCT { 436 __IM uint32_t dout_buffer; 437 /*!< Offset: 0xD00 (RO) */ 438 uint8_t _reserved_0[28]; 439 /*!< Offset: 0xD04-0xD1C Reserved */ 440 __IM uint32_t dout_mem_dma_busy; 441 /*!< Offset: 0xD20 (RO) */ 442 uint8_t _reserved_1[4]; 443 /*!< Offset: 0xD24 Reserved */ 444 __OM uint32_t dst_lli_word0; 445 /*!< Offset: 0xD28 (WO) */ 446 __IOM uint32_t dst_lli_word1; 447 /*!< Offset: 0xD2C (RW) */ 448 __IOM uint32_t sram_dest_addr; 449 /*!< Offset: 0xD30 (RW) */ 450 __IOM uint32_t dout_sram_bytes_len; 451 /*!< Offset: 0xD34 (RW) */ 452 __IM uint32_t dout_sram_dma_busy; 453 /*!< Offset: 0xD38 (RO) */ 454 uint8_t _reserved_2[8]; 455 /*!< Offset: 0xD3C-0xD40 Reserved */ 456 __OM uint32_t read_align_last; 457 /*!< Offset: 0xD44 (WO) */ 458 uint8_t _reserved_3[8]; 459 /*!< Offset: 0xD48-0xD4C Reserved */ 460 __IM uint32_t dout_fifo_empty; 461 /*!< Offset: 0xD50 (RO) */ 462 uint8_t _reserved_4[428]; 463 /*!< Offset: 0xD54-0xEFC Reserved */ 464 } dout; 465 466 /* Host_SRAM block */ 467 __PACKED_STRUCT { 468 __IOM uint32_t sram_data; 469 /*!< Offset: 0x0F00 (RW) */ 470 __OM uint32_t sram_addr; 471 /*!< Offset: 0x0F04 (WO) */ 472 __IM uint32_t sram_data_ready; 473 /*!< Offset: 0x0F08 (RO) */ 474 uint8_t _reserved_0[196]; 475 /*!< Offset: 0xF08-0xFCC Reserved */ 476 } host_sram; 477 478 /* ID_Registers block */ 479 __PACKED_STRUCT { 480 __IM uint32_t peripheral_id_4; 481 /*!< Offset: 0xFD0 (RO) */ 482 __IM uint32_t pidreserved0; 483 /*!< Offset: 0xFD4 (RO) */ 484 __IM uint32_t pidreserved1; 485 /*!< Offset: 0xFD8 (RO) */ 486 __IM uint32_t pidreserved2; 487 /*!< Offset: 0xFDC (RO) */ 488 __IM uint32_t peripheral_id_0; 489 /*!< Offset: 0xFE0 (RO) */ 490 __IM uint32_t peripheral_id_1; 491 /*!< Offset: 0xFE4 (RO) */ 492 __IM uint32_t peripheral_id_2; 493 /*!< Offset: 0xFE8 (RO) */ 494 __IM uint32_t peripheral_id_3; 495 /*!< Offset: 0xFEC (RO) */ 496 __IM uint32_t component_id_0; 497 /*!< Offset: 0xFF0 (RO) */ 498 __IM uint32_t component_id_1; 499 /*!< Offset: 0xFF4 (RO) */ 500 uint8_t _reserved_0[3592]; 501 /*!< Offset: 0xFF8-0x1DFC Reserved */ 502 } id; 503 504 /* AO block */ 505 __PACKED_STRUCT { 506 __IOM uint32_t host_dcu_en[4]; 507 /*!< Offset: 0x1E00 (RW) */ 508 __IOM uint32_t host_dcu_lock[4]; 509 /*!< Offset: 0x1E10 (RW) */ 510 __IM uint32_t ao_icv_dcu_restriction_mask[4]; 511 /*!< Offset: 0x1E20 (RO) */ 512 __IM uint32_t ao_cc_sec_debug_reset; 513 /*!< Offset: 0x1E30 (RO) */ 514 __IOM uint32_t host_ao_lock_bits; 515 /*!< Offset: 0x1E34 (RW) */ 516 __IOM uint32_t ao_apb_filtering; 517 /*!< Offset: 0x1E38 (RW) */ 518 __IM uint32_t ao_cc_gppc; 519 /*!< Offset: 0x1E3C (RO) */ 520 __OM uint32_t host_rgf_cc_sw_rst; 521 /*!< Offset: 0x1E40 (WO) */ 522 __IM uint32_t dcu_debug_bits[4]; 523 /*!< Offset: 0x1E44 (RO) */ 524 __IM uint32_t ao_permanent_disable_mask[4]; 525 /*!< Offset: 0x1E54 (RO) */ 526 uint8_t _reserved_0[160]; 527 /*!< Offset: 0x1E58-0x1EFC Reserved */ 528 } ao; 529 530 /* NVM block */ 531 __PACKED_STRUCT { 532 __IM uint32_t aib_fuse_prog_completed; 533 /*!< Offset: 0x1F04 (RO) */ 534 __IM uint32_t nvm_debug_status; 535 /*!< Offset: 0x1F08 (RO) */ 536 __IM uint32_t lcs_is_valid; 537 /*!< Offset: 0x1F0C (RO) */ 538 __IM uint32_t nvm_is_idle; 539 /*!< Offset: 0x1F10 (RO) */ 540 __IM uint32_t lcs_reg; 541 /*!< Offset: 0x1F14 (RO) */ 542 __OM uint32_t host_shadow_kdr_reg; 543 /*!< Offset: 0x1F18 (WO) */ 544 __OM uint32_t host_shadow_kcp_reg; 545 /*!< Offset: 0x1F1C (WO) */ 546 __OM uint32_t host_shadow_kce_reg; 547 /*!< Offset: 0x1F20 (WO) */ 548 __OM uint32_t host_shadow_kpicv_reg; 549 /*!< Offset: 0x1F24 (WO) */ 550 __OM uint32_t host_shadow_kceicv_reg; 551 /*!< Offset: 0x1F28 (WO) */ 552 __IM uint32_t otp_addr_width_def; 553 /*!< Offset: 0x1F2C (RO) */ 554 __IM uint32_t gp_param; 555 /*!< Offset: 0x1F30 (RO) */ 556 uint8_t _reserved_0[204]; 557 /*!< Offset: 0x1F34-0x1FFC Reserved */ 558 } nvm; 559 560 __PACKED_STRUCT { 561 __IOM uint32_t huk[8]; 562 __IOM uint32_t icv_provisioning_key[4]; 563 __IOM uint32_t icv_code_encryption_key[4]; 564 __IOM uint32_t icv_programmed_flags[1]; 565 __PACKED_UNION { 566 __IOM uint32_t rot_public_key[8]; 567 __PACKED_STRUCT { 568 __IOM uint32_t icv_rot_public_key[4]; 569 __IOM uint32_t oem_rot_public_key[4]; 570 }; 571 }; 572 __IOM uint32_t oem_provisioning_secret[4]; 573 __IOM uint32_t oem_code_encryption_key[4]; 574 __IOM uint32_t oem_programmed_flags[1]; 575 __PACKED_UNION { 576 __IOM uint32_t nv_counter[5]; 577 __PACKED_STRUCT { 578 __IOM uint32_t icv_nv_counter[2]; 579 __IOM uint32_t oem_nv_counter[3]; 580 }; 581 }; 582 __IOM uint32_t general_purpose_configuration_flags[1]; 583 __IOM uint32_t dcu_debug_lock_mask[4]; 584 __IOM uint32_t general_purpose_code_data[]; 585 } otp; 586 }; 587 588 #ifdef __cplusplus 589 } 590 #endif 591 592 #endif /* CC3XX_REG_DEFS_H */ 593
