1 /* 2 * Copyright (c) 2016 Intel Corporation 3 * Copyright (c) 2023 Nordic Semiconductor ASA 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #ifndef ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_ 9 #define ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_ 10 11 #include <stdint.h> 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /* 18 * This file describes register set for the DesignWare USB 2.0 controller IP, 19 * other known names are OTG_FS, OTG_HS. 20 */ 21 22 /* USB IN EP Register block type */ 23 struct usb_dw_in_ep_reg { 24 volatile uint32_t diepctl; 25 uint32_t reserved; 26 volatile uint32_t diepint; 27 uint32_t reserved1; 28 volatile uint32_t dieptsiz; 29 volatile uint32_t diepdma; 30 volatile uint32_t dtxfsts; 31 uint32_t reserved2; 32 }; 33 34 /* USB OUT EP Register block type */ 35 struct usb_dw_out_ep_reg { 36 volatile uint32_t doepctl; 37 uint32_t reserved; 38 volatile uint32_t doepint; 39 uint32_t reserved1; 40 volatile uint32_t doeptsiz; 41 volatile uint32_t doepdma; 42 uint32_t reserved2; 43 uint32_t reserved3; 44 }; 45 46 /* USB Register block type */ 47 struct usb_dw_reg { 48 volatile uint32_t gotgctl; 49 volatile uint32_t gotgint; 50 volatile uint32_t gahbcfg; 51 volatile uint32_t gusbcfg; 52 volatile uint32_t grstctl; 53 volatile uint32_t gintsts; 54 volatile uint32_t gintmsk; 55 volatile uint32_t grxstsr; 56 volatile uint32_t grxstsp; 57 volatile uint32_t grxfsiz; 58 volatile uint32_t gnptxfsiz; 59 uint32_t reserved[3]; 60 volatile uint32_t ggpio; 61 volatile uint32_t guid; 62 volatile uint32_t gsnpsid; 63 volatile uint32_t ghwcfg1; 64 volatile uint32_t ghwcfg2; 65 volatile uint32_t ghwcfg3; 66 volatile uint32_t ghwcfg4; 67 volatile uint32_t gdfifocfg; 68 uint32_t reserved1[43]; 69 volatile uint32_t dieptxf1; 70 volatile uint32_t dieptxf2; 71 volatile uint32_t dieptxf3; 72 volatile uint32_t dieptxf4; 73 volatile uint32_t dieptxf5; 74 /* Host mode register 0x0400 .. 0x0670 */ 75 uint32_t reserved2[442]; 76 /* Device mode register 0x0800 .. 0x0D00 */ 77 volatile uint32_t dcfg; 78 volatile uint32_t dctl; 79 volatile uint32_t dsts; 80 uint32_t reserved3; 81 volatile uint32_t diepmsk; 82 volatile uint32_t doepmsk; 83 volatile uint32_t daint; 84 volatile uint32_t daintmsk; 85 uint32_t reserved4[2]; 86 volatile uint32_t dvbusdis; 87 volatile uint32_t dvbuspulse; 88 volatile uint32_t dthrctl; 89 volatile uint32_t diepempmsk; 90 uint32_t reserved5[50]; 91 struct usb_dw_in_ep_reg in_ep_reg[16]; 92 struct usb_dw_out_ep_reg out_ep_reg[16]; 93 }; 94 95 /* 96 * With the maximum number of supported endpoints, register set 97 * of the controller can occupy the region up to 0x0D00. 98 */ 99 BUILD_ASSERT(sizeof(struct usb_dw_reg) <= 0x0D00); 100 101 /* AHB configuration register, offset: 0x0008 */ 102 #define USB_DW_GAHBCFG_DMA_EN BIT(5) 103 #define USB_DW_GAHBCFG_GLB_INTR_MASK BIT(0) 104 105 /* USB configuration register, offset: 0x000C */ 106 #define USB_DW_GUSBCFG_FORCEDEVMODE BIT(30) 107 #define USB_DW_GUSBCFG_FORCEHSTMODE BIT(29) 108 #define USB_DW_GUSBCFG_PHY_IF_MASK BIT(3) 109 #define USB_DW_GUSBCFG_PHY_IF_8_BIT 0 110 #define USB_DW_GUSBCFG_PHY_IF_16_BIT BIT(3) 111 112 /* Reset register, offset: 0x0010 */ 113 #define USB_DW_GRSTCTL_AHB_IDLE BIT(31) 114 #define USB_DW_GRSTCTL_TX_FNUM_OFFSET 6 115 #define USB_DW_GRSTCTL_TX_FFLSH BIT(5) 116 #define USB_DW_GRSTCTL_C_SFT_RST BIT(0) 117 118 /* Core interrupt register, offset: 0x0014 */ 119 #define USB_DW_GINTSTS_WK_UP_INT BIT(31) 120 #define USB_DW_GINTSTS_OEP_INT BIT(19) 121 #define USB_DW_GINTSTS_IEP_INT BIT(18) 122 #define USB_DW_GINTSTS_ENUM_DONE BIT(13) 123 #define USB_DW_GINTSTS_USB_RST BIT(12) 124 #define USB_DW_GINTSTS_USB_SUSP BIT(11) 125 #define USB_DW_GINTSTS_RX_FLVL BIT(4) 126 #define USB_DW_GINTSTS_OTG_INT BIT(2) 127 128 /* Status read and pop registers (device mode), offset: 0x001C 0x0020 */ 129 #define USB_DW_GRXSTSR_PKT_STS_MASK (0xF << 17) 130 #define USB_DW_GRXSTSR_PKT_STS_OFFSET 17 131 #define USB_DW_GRXSTSR_PKT_STS_OUT_DATA 2 132 #define USB_DW_GRXSTSR_PKT_STS_OUT_DATA_DONE 3 133 #define USB_DW_GRXSTSR_PKT_STS_SETUP_DONE 4 134 #define USB_DW_GRXSTSR_PKT_STS_SETUP 6 135 #define USB_DW_GRXSTSR_PKT_CNT_MASK (0x7FF << 4) 136 #define USB_DW_GRXSTSR_PKT_CNT_OFFSET 4 137 #define USB_DW_GRXSTSR_EP_NUM_MASK (0xF << 0) 138 139 /* Application (vendor) general purpose registers, offset: 0x0038 */ 140 #define USB_DW_GGPIO_STM32_VBDEN BIT(21) 141 #define USB_DW_GGPIO_STM32_PWRDWN BIT(16) 142 143 /* GHWCFG1 register, offset: 0x0044 */ 144 #define USB_DW_GHWCFG1_EPDIR_MASK(i) (0x3 << (i * 2)) 145 #define USB_DW_GHWCFG1_EPDIR_SHIFT(i) (i * 2) 146 #define USB_DW_GHWCFG1_OUTENDPT 2 147 #define USB_DW_GHWCFG1_INENDPT 1 148 #define USB_DW_GHWCFG1_BDIR 0 149 150 /* GHWCFG2 register, offset: 0x0048 */ 151 #define USB_DW_GHWCFG2_NUMDEVEPS_MASK (0xF << 10) 152 #define USB_DW_GHWCFG2_NUMDEVEPS_SHIFT 10 153 #define USB_DW_GHWCFG2_FSPHYTYPE_MASK (0x3 << 8) 154 #define USB_DW_GHWCFG2_FSPHYTYPE_SHIFT 8 155 #define USB_DW_GHWCFG2_FSPHYTYPE_FSPLUSULPI 3 156 #define USB_DW_GHWCFG2_FSPHYTYPE_FSPLUSUTMI 2 157 #define USB_DW_GHWCFG2_FSPHYTYPE_FS 1 158 #define USB_DW_GHWCFG2_FSPHYTYPE_NO_FS 0 159 #define USB_DW_GHWCFG2_HSPHYTYPE_MASK (0x3 << 6) 160 #define USB_DW_GHWCFG2_HSPHYTYPE_SHIFT 6 161 #define USB_DW_GHWCFG2_HSPHYTYPE_UTMIPLUSULPI 3 162 #define USB_DW_GHWCFG2_HSPHYTYPE_ULPI 2 163 #define USB_DW_GHWCFG2_HSPHYTYPE_UTMIPLUS 1 164 #define USB_DW_GHWCFG2_HSPHYTYPE_NO_HS 0 165 166 /* GHWCFG3 register, offset: 0x004C */ 167 #define USB_DW_GHWCFG3_DFIFODEPTH_MASK (0xFFFFU << 16) 168 #define USB_DW_GHWCFG3_DFIFODEPTH_SHIFT 16 169 170 /* GHWCFG4 register, offset: 0x0050 */ 171 #define USB_DW_GHWCFG4_INEPS_MASK (0xF << 26) 172 #define USB_DW_GHWCFG4_INEPS_SHIFT 26 173 #define USB_DW_GHWCFG4_DEDFIFOMODE BIT(25) 174 175 /* Device configuration registers, offset: 0x0800 */ 176 #define USB_DW_DCFG_DEV_ADDR_MASK (0x7F << 4) 177 #define USB_DW_DCFG_DEV_ADDR_OFFSET 4 178 #define USB_DW_DCFG_DEV_SPD_USB2_HS 0 179 #define USB_DW_DCFG_DEV_SPD_USB2_FS 1 180 #define USB_DW_DCFG_DEV_SPD_LS 2 181 #define USB_DW_DCFG_DEV_SPD_FS 3 182 183 /* Device control register, offset 0x0804 */ 184 #define USB_DW_DCTL_SFT_DISCON BIT(1) 185 186 /* Device status register, offset 0x0808 */ 187 #define USB_DW_DSTS_ENUM_SPD_MASK (0x3 << 1) 188 #define USB_DW_DSTS_ENUM_SPD_OFFSET 1 189 #define USB_DW_DSTS_ENUM_LS 2 190 #define USB_DW_DSTS_ENUM_FS 3 191 192 /* Device all endpoints interrupt register, offset 0x0818 */ 193 #define USB_DW_DAINT_OUT_EP_INT(ep) (0x10000 << (ep)) 194 #define USB_DW_DAINT_IN_EP_INT(ep) (1 << (ep)) 195 196 /* 197 * Device IN/OUT endpoint control register 198 * IN endpoint offsets 0x0900 + (0x20 * n), n = 0 .. x, 199 * offset 0x0900 and 0x0B00 are hardcoded to control type. 200 * 201 * REVISE: Better own definitions for DIEPTCTL0, DOEPTCTL0... 202 */ 203 #define USB_DW_DEPCTL_EP_ENA BIT(31) 204 #define USB_DW_DEPCTL_EP_DIS BIT(30) 205 #define USB_DW_DEPCTL_SETDOPID BIT(28) 206 #define USB_DW_DEPCTL_SNAK BIT(27) 207 #define USB_DW_DEPCTL_CNAK BIT(26) 208 #define USB_DW_DEPCTL_STALL BIT(21) 209 #define USB_DW_DEPCTL_TXFNUM_OFFSET 22 210 #define USB_DW_DEPCTL_TXFNUM_MASK (0xF << 22) 211 #define USB_DW_DEPCTL_EP_TYPE_MASK (0x3 << 18) 212 #define USB_DW_DEPCTL_EP_TYPE_OFFSET 18 213 #define USB_DW_DEPCTL_EP_TYPE_INTERRUPT 3 214 #define USB_DW_DEPCTL_EP_TYPE_BULK 2 215 #define USB_DW_DEPCTL_EP_TYPE_ISO 1 216 #define USB_DW_DEPCTL_EP_TYPE_CONTROL 0 217 #define USB_DW_DEPCTL_USB_ACT_EP BIT(15) 218 #define USB_DW_DEPCTL0_MSP_MASK 0x3 219 #define USB_DW_DEPCTL0_MSP_8 3 220 #define USB_DW_DEPCTL0_MSP_16 2 221 #define USB_DW_DEPCTL0_MSP_32 1 222 #define USB_DW_DEPCTL0_MSP_64 0 223 #define USB_DW_DEPCTLn_MSP_MASK 0x3FF 224 #define USB_DW_DEPCTL_MSP_OFFSET 0 225 226 /* 227 * Device IN endpoint interrupt register 228 * offsets 0x0908 + (0x20 * n), n = 0 .. x 229 */ 230 #define USB_DW_DIEPINT_TX_FEMP BIT(7) 231 #define USB_DW_DIEPINT_XFER_COMPL BIT(0) 232 233 /* 234 * Device OUT endpoint interrupt register 235 * offsets 0x0B08 + (0x20 * n), n = 0 .. x 236 */ 237 #define USB_DW_DOEPINT_SET_UP BIT(3) 238 #define USB_DW_DOEPINT_XFER_COMPL BIT(0) 239 240 /* 241 * Device IN/OUT endpoint transfer size register 242 * IN at offsets 0x0910 + (0x20 * n), n = 0 .. x, 243 * OUT at offsets 0x0B10 + (0x20 * n), n = 0 .. x 244 * 245 * REVISE: Better own definitions for DIEPTSIZ0, DOEPTSIZ0... 246 */ 247 #define USB_DW_DEPTSIZ_PKT_CNT_OFFSET 19 248 #define USB_DW_DIEPTSIZ0_PKT_CNT_MASK (0x3 << 19) 249 #define USB_DW_DIEPTSIZn_PKT_CNT_MASK (0x3FF << 19) 250 #define USB_DW_DOEPTSIZn_PKT_CNT_MASK (0x3FF << 19) 251 #define USB_DW_DOEPTSIZ0_PKT_CNT_MASK (0x1 << 19) 252 #define USB_DW_DOEPTSIZ_SUP_CNT_OFFSET 29 253 #define USB_DW_DOEPTSIZ_SUP_CNT_MASK (0x3 << 29) 254 #define USB_DW_DEPTSIZ_XFER_SIZE_OFFSET 0 255 #define USB_DW_DEPTSIZ0_XFER_SIZE_MASK 0x7F 256 #define USB_DW_DEPTSIZn_XFER_SIZE_MASK 0x7FFFF 257 258 /* 259 * Device IN endpoint transmit FIFO status register, 260 * offsets 0x0918 + (0x20 * n), n = 0 .. x 261 */ 262 #define USB_DW_DTXFSTS_TXF_SPC_AVAIL_MASK 0xFFFF 263 264 #ifdef __cplusplus 265 } 266 #endif 267 268 #endif /* ZEPHYR_DRIVERS_USB_DEVICE_USB_DW_REGISTERS_H_ */ 269
