1 /* 2 * Copyright 2016-2017 NXP 3 * 4 * Redistribution and use in source and binary forms, with or without modification, 5 * are permitted provided that the following conditions are met: 6 * 7 * o Redistributions of source code must retain the above copyright notice, this list 8 * of conditions and the following disclaimer. 9 * 10 * o Redistributions in binary form must reproduce the above copyright notice, this 11 * list of conditions and the following disclaimer in the documentation and/or 12 * other materials provided with the distribution. 13 * 14 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "fsl_xcvr.h" 31 32 /******************************************************************************* 33 * Definitions 34 ******************************************************************************/ 35 36 /******************************************************************************* 37 * Prototypes 38 ******************************************************************************/ 39 40 /******************************************************************************* 41 * Variables 42 ******************************************************************************/ 43 44 /******************************************************************************* 45 * Code 46 ******************************************************************************/ 47 /* MODE only configuration */ 48 const xcvr_mode_config_t gfsk_bt_0p7_h_0p5_mode_config = 49 { 50 .radio_mode = GFSK_BT_0p7_h_0p5, 51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, 52 53 /* XCVR_MISC configs */ 54 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | 55 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | 56 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, 57 .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | 58 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | 59 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), 60 61 /* XCVR_PHY configs */ 62 .phy_pre_ref0_init = 0x79CDEB39, 63 .phy_pre_ref1_init = 0xCE77DEF7, 64 .phy_pre_ref2_init = 0x0000CEB7, 65 66 .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | 67 XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 68 XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | 69 XCVR_PHY_CFG1_BSM_EN_BLE(0) | 70 XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | 71 XCVR_PHY_CFG1_CTS_THRESH(0xb0) | 72 XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), 73 74 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) 75 #if !RADIO_IS_GEN_2P1 76 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) 77 #endif /* !RADIO_IS_GEN_2P1 */ 78 , 79 80 /* XCVR_RX_DIG configs */ 81 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 82 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ 83 XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), 84 85 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 86 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ 87 88 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), 89 90 /* XCVR_TSM configs */ 91 #if (DATA_PADDING_EN) 92 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), 93 #else 94 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), 95 #endif /* (DATA_PADDING_EN) */ 96 97 /* XCVR_TX_DIG configs */ 98 .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | 99 XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | 100 XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | 101 XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(1) | /* Use GFSK Manual Filter Coeffs */ 102 XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | 103 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | 104 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | 105 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | 106 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), 107 .tx_gfsk_coeff1_26mhz = (27U) << 0 | /* Coeff 2/13 */ 108 (276U) << 7 | /* Coeff 6/9 */ 109 (62U) << 16 | /* Coef 3/12 */ 110 (326U) << 23, /* Coeff 7/8 */ 111 .tx_gfsk_coeff2_26mhz = (3U) << 0 | /* Coeff 0/15 */ 112 (10U) << 8 | /* Coeff 1/14 */ 113 (121U) << 16 | /* Coeff 4/11 */ 114 (198U) << 24, /* Coeff 5/10 */ 115 .tx_gfsk_coeff1_32mhz = (1U) << 0 | /* Coeff 2/13 */ 116 (330U) << 7 | /* Coeff 6/9 */ 117 (7U) << 16 | /* Coef 3/12 */ 118 (510U) << 23, /* Coeff 7/8 */ 119 .tx_gfsk_coeff2_32mhz = (0U) << 0 | /* Coeff 0/15 */ 120 (0U) << 8 | /* Coeff 1/14 */ 121 (37U) << 16 | /* Coeff 4/11 */ 122 (138U) << 24, /* Coeff 5/10 */ 123 }; 124 125 /* MODE & DATA RATE combined configuration */ 126 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_1mbps_config = 127 { 128 .radio_mode = GFSK_BT_0p7_h_0p5, 129 .data_rate = DR_1MBPS, 130 131 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 132 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 133 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 134 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(3) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(3), /* BBA_BW_SEL and BBA2_BW_SEL */ 135 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 136 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(3), /*TZA_BW_SEL */ 137 138 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 139 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , 140 141 /* AGC configs */ 142 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(11) | 143 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 144 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 145 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 146 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 147 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 148 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | 149 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 150 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 151 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 152 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 153 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 154 155 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 156 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0001, 157 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0000, 158 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, 159 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF8, 160 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFF1, 161 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFEF, 162 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF4, 163 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0004, 164 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, 165 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0041, 166 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x005E, 167 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, 168 169 /* 32MHz Channel Filter */ 170 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, 171 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0002, 172 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0000, 173 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, 174 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFF2, 175 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFEB, 176 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFED, 177 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFFD, 178 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x001B, 179 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0041, 180 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0065, 181 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x007A, 182 183 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 184 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | 185 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | 186 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 187 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 188 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 189 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | 190 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , 191 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 192 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 193 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 194 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 195 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | 196 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , 197 198 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 199 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 200 }; 201 202 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_500kbps_config = 203 { 204 .radio_mode = GFSK_BT_0p7_h_0p5, 205 .data_rate = DR_500KBPS, 206 207 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 208 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 209 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 210 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 211 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 212 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 213 214 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 215 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , 216 217 /* AGC configs */ 218 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | 219 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 220 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 221 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 222 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 223 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 224 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | 225 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 226 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 227 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 228 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 229 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 230 231 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 232 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, 233 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFF, 234 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, 235 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFFA, 236 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0x000A, 237 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0x0019, 238 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0009, 239 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFDB, 240 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0xFFC1, 241 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0xFFF6, 242 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0072, 243 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x00DD, 244 245 /* 32MHz Channel Filter */ 246 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, 247 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0003, 248 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFFC, 249 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF4, 250 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFFD, 251 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0x0016, 252 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x001A, 253 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFEC, 254 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFBC, 255 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0xFFE0, 256 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, 257 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x00ED, 258 259 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 260 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | 261 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | 262 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 263 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 264 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 265 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | 266 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , 267 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 268 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 269 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 270 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 271 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | 272 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , 273 274 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 275 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 276 }; 277 278 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p7_h_0p5_250kbps_config = 279 { 280 .radio_mode = GFSK_BT_0p7_h_0p5, 281 .data_rate = DR_250KBPS, 282 283 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 284 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 285 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 286 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 287 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 288 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 289 290 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 291 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , 292 293 /* AGC configs */ 294 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | 295 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 296 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 297 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 298 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 299 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 300 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | 301 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 302 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | 303 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 304 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 305 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 306 307 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 308 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0000, 309 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, 310 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0x0006, 311 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0x0005, 312 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFFE, 313 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF1, 314 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFE6, 315 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0xFFEA, 316 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0005, 317 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0036, 318 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x006B, 319 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x008D, 320 321 /* 32MHz Channel Filter */ 322 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFF, 323 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0000, 324 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0004, 325 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0x0008, 326 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0x0004, 327 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF8, 328 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE6, 329 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFE2, 330 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0xFFFA, 331 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x002E, 332 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x006D, 333 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0098, 334 335 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 336 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | 337 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | 338 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 339 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 340 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 341 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | 342 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , 343 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 344 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 345 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 346 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 347 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | 348 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , 349 350 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 351 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 352 }; 353 354
