1 /* 2 * Copyright 2016-2017 NXP 3 * 4 * Redistribution and use in source and binary forms, with or without modification, 5 * are permitted provided that the following conditions are met: 6 * 7 * o Redistributions of source code must retain the above copyright notice, this list 8 * of conditions and the following disclaimer. 9 * 10 * o Redistributions in binary form must reproduce the above copyright notice, this 11 * list of conditions and the following disclaimer in the documentation and/or 12 * other materials provided with the distribution. 13 * 14 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its 15 * contributors may be used to endorse or promote products derived from this 16 * software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include "fsl_xcvr.h" 31 32 /******************************************************************************* 33 * Definitions 34 ******************************************************************************/ 35 36 /******************************************************************************* 37 * Prototypes 38 ******************************************************************************/ 39 40 /******************************************************************************* 41 * Variables 42 ******************************************************************************/ 43 44 /******************************************************************************* 45 * Code 46 ******************************************************************************/ 47 /* MODE only configuration */ 48 const xcvr_mode_config_t gfsk_bt_0p5_h_0p5_mode_config = 49 { 50 .radio_mode = GFSK_BT_0p5_h_0p5, 51 .scgc5_clock_ena_bits = SIM_SCGC5_PHYDIG_MASK | SIM_SCGC5_GEN_FSK_MASK, 52 53 /* XCVR_MISC configs */ 54 .xcvr_ctrl.mask = XCVR_CTRL_XCVR_CTRL_PROTOCOL_MASK | 55 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC_MASK | 56 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL_MASK, 57 .xcvr_ctrl.init = XCVR_CTRL_XCVR_CTRL_PROTOCOL(8) | 58 XCVR_CTRL_XCVR_CTRL_TGT_PWR_SRC(7) | 59 XCVR_CTRL_XCVR_CTRL_DEMOD_SEL(1), 60 61 .phy_pre_ref0_init = RW0PS(0, 0x19) | 62 RW0PS(1, 0x19U) | 63 RW0PS(2, 0x1AU) | 64 RW0PS(3, 0x1BU) | 65 RW0PS(4, 0x1CU) | 66 RW0PS(5, 0x1CU) | 67 RW0PS(6, 0x1DU & 0x3U), /* Phase info #6 overlaps two initialization words */ 68 .phy_pre_ref1_init = (0x1D) >> 2 | /* Phase info #6 overlaps two initialization words - manually compute the shift*/ 69 RW1PS(7, 0x1EU) | 70 RW1PS(8, 0x1EU) | 71 RW1PS(9, 0x1EU) | 72 RW1PS(10, 0x1DU) | 73 RW1PS(11, 0x1CU) | 74 RW1PS(12, 0x1CU & 0xFU), /* Phase info #12 overlaps two initialization words */ 75 .phy_pre_ref2_init = (0x1C) >> 4 | /* Phase info #12 overlaps two initialization words - manually compute the shift*/ 76 RW2PS(13, 0x1BU) | 77 RW2PS(14, 0x1AU) | 78 RW2PS(15, 0x19U), 79 80 .phy_cfg1_init = XCVR_PHY_CFG1_AA_PLAYBACK(1) | 81 XCVR_PHY_CFG1_AA_OUTPUT_SEL(1) | 82 XCVR_PHY_CFG1_FSK_BIT_INVERT(0) | 83 XCVR_PHY_CFG1_BSM_EN_BLE(0) | 84 XCVR_PHY_CFG1_DEMOD_CLK_MODE(0) | 85 XCVR_PHY_CFG1_CTS_THRESH(205) | 86 XCVR_PHY_CFG1_FSK_FTS_TIMEOUT(2), 87 88 .phy_el_cfg_init = XCVR_PHY_EL_CFG_EL_ENABLE(1) 89 #if !RADIO_IS_GEN_2P1 90 | XCVR_PHY_EL_CFG_EL_ZB_ENABLE(0) 91 #endif /* !RADIO_IS_GEN_2P1 */ 92 , 93 /* XCVR_RX_DIG configs */ 94 .rx_dig_ctrl_init_26mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 95 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1) | /* Depends on protocol */ 96 XCVR_RX_DIG_RX_DIG_CTRL_RX_SRC_RATE(0), 97 98 .rx_dig_ctrl_init_32mhz = XCVR_RX_DIG_RX_DIG_CTRL_RX_FSK_ZB_SEL(0) | /* Depends on protocol */ 99 XCVR_RX_DIG_RX_DIG_CTRL_RX_DC_RESID_EN(1), /* Depends on protocol */ 100 101 .agc_ctrl_0_init = XCVR_RX_DIG_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(0xFF), 102 103 /* XCVR_TSM configs */ 104 #if (DATA_PADDING_EN) 105 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT+TX_DIG_EN_TX_HI_ADJ), 106 #else 107 .tsm_timing_35_init = B0(TX_DIG_EN_ASSERT), 108 #endif /* (DATA_PADDING_EN) */ 109 110 /* XCVR_TX_DIG configs */ 111 .tx_gfsk_ctrl = XCVR_TX_DIG_GFSK_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(0x4000) | 112 XCVR_TX_DIG_GFSK_CTRL_GFSK_MI(1) | 113 XCVR_TX_DIG_GFSK_CTRL_GFSK_MLD(0) | 114 XCVR_TX_DIG_GFSK_CTRL_GFSK_FLD(0) | 115 XCVR_TX_DIG_GFSK_CTRL_GFSK_MOD_INDEX_SCALING(0) | 116 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_OVRD_EN(0) | 117 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_0_OVRD(0) | 118 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_1_OVRD(0) | 119 XCVR_TX_DIG_GFSK_CTRL_TX_IMAGE_FILTER_2_OVRD(0), 120 .tx_gfsk_coeff1_26mhz = 0, 121 .tx_gfsk_coeff2_26mhz = 0, 122 .tx_gfsk_coeff1_32mhz = 0, 123 .tx_gfsk_coeff2_32mhz = 0, 124 }; 125 126 /* MODE & DATA RATE combined configuration */ 127 128 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_1mbps_config = 129 { 130 .radio_mode = GFSK_BT_0p5_h_0p5, 131 .data_rate = DR_1MBPS, 132 133 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 134 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 135 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 136 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(4) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(4), /* BBA_BW_SEL and BBA2_BW_SEL */ 137 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 138 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(4), /*TZA_BW_SEL */ 139 140 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 141 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0xA) , 142 143 /* AGC configs */ 144 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(10) | 145 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 146 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 147 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 148 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 149 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 150 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(12) | 151 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 152 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 153 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 154 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 155 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 156 157 /* BLE 26MHz Channel Filter */ 158 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 159 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0xFFFA, 160 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFF6, 161 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF1, 162 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFEE, 163 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEF, 164 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFF6, 165 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0x0004, 166 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0017, 167 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x002F, 168 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, 169 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0059, 170 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0063, 171 172 /* BLE 32MHz Channel Filter */ 173 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0xFFFA, 174 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFF5, 175 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFEF, 176 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFEB, 177 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEB, 178 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFF2, 179 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0x0000, 180 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x0015, 181 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0030, 182 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x004A, 183 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x005F, 184 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x006B, 185 186 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 187 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(0) | 188 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(0) | 189 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 190 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 191 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 192 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(0) | 193 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(0) , 194 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 195 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 196 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 197 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 198 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(0) | 199 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(0) , 200 201 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 202 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 203 }; 204 205 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_500kbps_config = 206 { 207 .radio_mode = GFSK_BT_0p5_h_0p5, 208 .data_rate = DR_500KBPS, 209 210 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 211 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 212 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 213 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 214 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 215 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 216 217 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 218 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x8) , 219 220 /* AGC configs */ 221 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(15) | 222 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 223 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 224 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 225 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 226 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 227 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | 228 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 229 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 230 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 231 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 232 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 233 234 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 235 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0004, 236 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0x0003, 237 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFFE, 238 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF5, 239 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, 240 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFE8, 241 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFEE, 242 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x0001, 243 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0020, 244 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0045, 245 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0065, 246 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0079, 247 248 /* 32MHz */ 249 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0005, 250 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0x0006, 251 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0x0003, 252 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFFA, 253 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEF, 254 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFE6, 255 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFE7, 256 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0xFFF8, 257 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0019, 258 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0042, 259 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0069, 260 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0080, 261 262 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 263 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | 264 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | 265 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 266 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 267 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 268 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | 269 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , 270 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 271 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 272 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 273 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 274 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | 275 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , 276 277 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 278 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 279 }; 280 281 const xcvr_mode_datarate_config_t xcvr_GFSK_BT_0p5_h_0p5_250kbps_config = 282 { 283 .radio_mode = GFSK_BT_0p5_h_0p5, 284 .data_rate = DR_250KBPS, 285 286 .ana_sy_ctrl2.mask = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM_MASK, 287 .ana_sy_ctrl2.init = XCVR_ANALOG_SY_CTRL_2_SY_VCO_KVM(0), /* VCO KVM */ 288 .ana_rx_bba.mask = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL_MASK | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL_MASK, 289 .ana_rx_bba.init = XCVR_ANALOG_RX_BBA_RX_BBA_BW_SEL(5) | XCVR_ANALOG_RX_BBA_RX_BBA2_BW_SEL(5), /* BBA_BW_SEL and BBA2_BW_SEL */ 290 .ana_rx_tza.mask = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL_MASK, 291 .ana_rx_tza.init = XCVR_ANALOG_RX_TZA_RX_TZA_BW_SEL(5), /* TZA_BW_SEL */ 292 293 .phy_cfg2_init = XCVR_PHY_CFG2_PHY_FIFO_PRECHG(8) | 294 XCVR_PHY_CFG2_X2_DEMOD_GAIN(0x6) , 295 296 /* AGC configs */ 297 .agc_ctrl_2_init_26mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(18) | 298 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 299 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(6) | 300 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 301 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 302 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 303 .agc_ctrl_2_init_32mhz = XCVR_RX_DIG_AGC_CTRL_2_BBA_GAIN_SETTLE_TIME(22) | 304 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_LO(5) | 305 XCVR_RX_DIG_AGC_CTRL_2_BBA_PDET_SEL_HI(2) | 306 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_LO(3) | 307 XCVR_RX_DIG_AGC_CTRL_2_TZA_PDET_SEL_HI(7) | 308 XCVR_RX_DIG_AGC_CTRL_2_AGC_FAST_EXPIRE(5), 309 310 /* All constant values are represented as 16 bits, register writes will remove unused bits */ 311 .rx_chf_coeffs_26mhz.rx_chf_coef_0 = 0x0002, 312 .rx_chf_coeffs_26mhz.rx_chf_coef_1 = 0xFFFD, 313 .rx_chf_coeffs_26mhz.rx_chf_coef_2 = 0xFFF8, 314 .rx_chf_coeffs_26mhz.rx_chf_coef_3 = 0xFFF1, 315 .rx_chf_coeffs_26mhz.rx_chf_coef_4 = 0xFFEC, 316 .rx_chf_coeffs_26mhz.rx_chf_coef_5 = 0xFFED, 317 .rx_chf_coeffs_26mhz.rx_chf_coef_6 = 0xFFF7, 318 .rx_chf_coeffs_26mhz.rx_chf_coef_7 = 0x000B, 319 .rx_chf_coeffs_26mhz.rx_chf_coef_8 = 0x0027, 320 .rx_chf_coeffs_26mhz.rx_chf_coef_9 = 0x0046, 321 .rx_chf_coeffs_26mhz.rx_chf_coef_10 = 0x0060, 322 .rx_chf_coeffs_26mhz.rx_chf_coef_11 = 0x0070, 323 324 /* 32MHz Channel Filter */ 325 .rx_chf_coeffs_32mhz.rx_chf_coef_0 = 0x0002, 326 .rx_chf_coeffs_32mhz.rx_chf_coef_1 = 0xFFFD, 327 .rx_chf_coeffs_32mhz.rx_chf_coef_2 = 0xFFF8, 328 .rx_chf_coeffs_32mhz.rx_chf_coef_3 = 0xFFF1, 329 .rx_chf_coeffs_32mhz.rx_chf_coef_4 = 0xFFEC, 330 .rx_chf_coeffs_32mhz.rx_chf_coef_5 = 0xFFED, 331 .rx_chf_coeffs_32mhz.rx_chf_coef_6 = 0xFFF6, 332 .rx_chf_coeffs_32mhz.rx_chf_coef_7 = 0x000A, 333 .rx_chf_coeffs_32mhz.rx_chf_coef_8 = 0x0027, 334 .rx_chf_coeffs_32mhz.rx_chf_coef_9 = 0x0046, 335 .rx_chf_coeffs_32mhz.rx_chf_coef_10 = 0x0061, 336 .rx_chf_coeffs_32mhz.rx_chf_coef_11 = 0x0071, 337 338 .rx_rccal_ctrl_0 = XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_OFFSET(0) | 339 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_MANUAL(31) | 340 XCVR_RX_DIG_RX_RCCAL_CTRL0_BBA_RCCAL_DIS(1) | 341 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_SMP_DLY(0) | 342 XCVR_RX_DIG_RX_RCCAL_CTRL0_RCCAL_COMP_INV(0) | 343 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_OFFSET(0) | 344 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_MANUAL(31) | 345 XCVR_RX_DIG_RX_RCCAL_CTRL0_TZA_RCCAL_DIS(1) , 346 .rx_rccal_ctrl_1 = XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_OFFSET(0) | 347 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_MANUAL(0) | 348 XCVR_RX_DIG_RX_RCCAL_CTRL1_ADC_RCCAL_DIS(0) | 349 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_OFFSET(0) | 350 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_MANUAL(31) | 351 XCVR_RX_DIG_RX_RCCAL_CTRL1_BBA2_RCCAL_DIS(1) , 352 353 .tx_fsk_scale_26mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1627) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x09d9), 354 .tx_fsk_scale_32mhz = XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_0(0x1800) | XCVR_TX_DIG_FSK_SCALE_FSK_MODULATION_SCALE_1(0x0800), 355 }; 356 357
