1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CONTEXT_H 8 #define CONTEXT_H 9 10 #include <lib/el3_runtime/cpu_data.h> 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * Constants that allow assembler code to access members of and the 'gp_regs' 15 * structure at their correct offsets. 16 ******************************************************************************/ 17 #define CTX_GPREGS_OFFSET U(0x0) 18 #define CTX_GPREG_X0 U(0x0) 19 #define CTX_GPREG_X1 U(0x8) 20 #define CTX_GPREG_X2 U(0x10) 21 #define CTX_GPREG_X3 U(0x18) 22 #define CTX_GPREG_X4 U(0x20) 23 #define CTX_GPREG_X5 U(0x28) 24 #define CTX_GPREG_X6 U(0x30) 25 #define CTX_GPREG_X7 U(0x38) 26 #define CTX_GPREG_X8 U(0x40) 27 #define CTX_GPREG_X9 U(0x48) 28 #define CTX_GPREG_X10 U(0x50) 29 #define CTX_GPREG_X11 U(0x58) 30 #define CTX_GPREG_X12 U(0x60) 31 #define CTX_GPREG_X13 U(0x68) 32 #define CTX_GPREG_X14 U(0x70) 33 #define CTX_GPREG_X15 U(0x78) 34 #define CTX_GPREG_X16 U(0x80) 35 #define CTX_GPREG_X17 U(0x88) 36 #define CTX_GPREG_X18 U(0x90) 37 #define CTX_GPREG_X19 U(0x98) 38 #define CTX_GPREG_X20 U(0xa0) 39 #define CTX_GPREG_X21 U(0xa8) 40 #define CTX_GPREG_X22 U(0xb0) 41 #define CTX_GPREG_X23 U(0xb8) 42 #define CTX_GPREG_X24 U(0xc0) 43 #define CTX_GPREG_X25 U(0xc8) 44 #define CTX_GPREG_X26 U(0xd0) 45 #define CTX_GPREG_X27 U(0xd8) 46 #define CTX_GPREG_X28 U(0xe0) 47 #define CTX_GPREG_X29 U(0xe8) 48 #define CTX_GPREG_LR U(0xf0) 49 #define CTX_GPREG_SP_EL0 U(0xf8) 50 #define CTX_GPREGS_END U(0x100) 51 52 /******************************************************************************* 53 * Constants that allow assembler code to access members of and the 'el3_state' 54 * structure at their correct offsets. Note that some of the registers are only 55 * 32-bits wide but are stored as 64-bit values for convenience 56 ******************************************************************************/ 57 #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) 58 #define CTX_SCR_EL3 U(0x0) 59 #define CTX_ESR_EL3 U(0x8) 60 #define CTX_RUNTIME_SP U(0x10) 61 #define CTX_SPSR_EL3 U(0x18) 62 #define CTX_ELR_EL3 U(0x20) 63 #define CTX_PMCR_EL0 U(0x28) 64 #define CTX_IS_IN_EL3 U(0x30) 65 #define CTX_MPAM3_EL3 U(0x38) 66 /* Constants required in supporting nested exception in EL3 */ 67 #define CTX_SAVED_ELR_EL3 U(0x40) 68 /* 69 * General purpose flag, to save various EL3 states 70 * FFH mode : Used to identify if handling nested exception 71 * KFH mode : Used as counter value 72 */ 73 #define CTX_NESTED_EA_FLAG U(0x48) 74 #if FFH_SUPPORT 75 #define CTX_SAVED_ESR_EL3 U(0x50) 76 #define CTX_SAVED_SPSR_EL3 U(0x58) 77 #define CTX_SAVED_GPREG_LR U(0x60) 78 #define CTX_EL3STATE_END U(0x70) /* Align to the next 16 byte boundary */ 79 #else 80 #define CTX_EL3STATE_END U(0x50) /* Align to the next 16 byte boundary */ 81 #endif 82 83 /******************************************************************************* 84 * Constants that allow assembler code to access members of and the 85 * 'el1_sys_regs' structure at their correct offsets. Note that some of the 86 * registers are only 32-bits wide but are stored as 64-bit values for 87 * convenience 88 ******************************************************************************/ 89 #define CTX_EL1_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) 90 #define CTX_SPSR_EL1 U(0x0) 91 #define CTX_ELR_EL1 U(0x8) 92 #define CTX_SCTLR_EL1 U(0x10) 93 #define CTX_TCR_EL1 U(0x18) 94 #define CTX_CPACR_EL1 U(0x20) 95 #define CTX_CSSELR_EL1 U(0x28) 96 #define CTX_SP_EL1 U(0x30) 97 #define CTX_ESR_EL1 U(0x38) 98 #define CTX_TTBR0_EL1 U(0x40) 99 #define CTX_TTBR1_EL1 U(0x48) 100 #define CTX_MAIR_EL1 U(0x50) 101 #define CTX_AMAIR_EL1 U(0x58) 102 #define CTX_ACTLR_EL1 U(0x60) 103 #define CTX_TPIDR_EL1 U(0x68) 104 #define CTX_TPIDR_EL0 U(0x70) 105 #define CTX_TPIDRRO_EL0 U(0x78) 106 #define CTX_PAR_EL1 U(0x80) 107 #define CTX_FAR_EL1 U(0x88) 108 #define CTX_AFSR0_EL1 U(0x90) 109 #define CTX_AFSR1_EL1 U(0x98) 110 #define CTX_CONTEXTIDR_EL1 U(0xa0) 111 #define CTX_VBAR_EL1 U(0xa8) 112 113 /* 114 * If the platform is AArch64-only, there is no need to save and restore these 115 * AArch32 registers. 116 */ 117 #if CTX_INCLUDE_AARCH32_REGS 118 #define CTX_SPSR_ABT U(0xb0) /* Align to the next 16 byte boundary */ 119 #define CTX_SPSR_UND U(0xb8) 120 #define CTX_SPSR_IRQ U(0xc0) 121 #define CTX_SPSR_FIQ U(0xc8) 122 #define CTX_DACR32_EL2 U(0xd0) 123 #define CTX_IFSR32_EL2 U(0xd8) 124 #define CTX_AARCH32_END U(0xe0) /* Align to the next 16 byte boundary */ 125 #else 126 #define CTX_AARCH32_END U(0xb0) /* Align to the next 16 byte boundary */ 127 #endif /* CTX_INCLUDE_AARCH32_REGS */ 128 129 /* 130 * If the timer registers aren't saved and restored, we don't have to reserve 131 * space for them in the context 132 */ 133 #if NS_TIMER_SWITCH 134 #define CTX_CNTP_CTL_EL0 (CTX_AARCH32_END + U(0x0)) 135 #define CTX_CNTP_CVAL_EL0 (CTX_AARCH32_END + U(0x8)) 136 #define CTX_CNTV_CTL_EL0 (CTX_AARCH32_END + U(0x10)) 137 #define CTX_CNTV_CVAL_EL0 (CTX_AARCH32_END + U(0x18)) 138 #define CTX_CNTKCTL_EL1 (CTX_AARCH32_END + U(0x20)) 139 #define CTX_TIMER_SYSREGS_END (CTX_AARCH32_END + U(0x30)) /* Align to the next 16 byte boundary */ 140 #else 141 #define CTX_TIMER_SYSREGS_END CTX_AARCH32_END 142 #endif /* NS_TIMER_SWITCH */ 143 144 #if CTX_INCLUDE_MTE_REGS 145 #define CTX_TFSRE0_EL1 (CTX_TIMER_SYSREGS_END + U(0x0)) 146 #define CTX_TFSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x8)) 147 #define CTX_RGSR_EL1 (CTX_TIMER_SYSREGS_END + U(0x10)) 148 #define CTX_GCR_EL1 (CTX_TIMER_SYSREGS_END + U(0x18)) 149 150 /* Align to the next 16 byte boundary */ 151 #define CTX_MTE_REGS_END (CTX_TIMER_SYSREGS_END + U(0x20)) 152 #else 153 #define CTX_MTE_REGS_END CTX_TIMER_SYSREGS_END 154 #endif /* CTX_INCLUDE_MTE_REGS */ 155 156 /* 157 * End of system registers. 158 */ 159 #define CTX_EL1_SYSREGS_END CTX_MTE_REGS_END 160 161 /* 162 * EL2 register set 163 */ 164 165 #if CTX_INCLUDE_EL2_REGS 166 /* For later discussion 167 * ICH_AP0R<n>_EL2 168 * ICH_AP1R<n>_EL2 169 * AMEVCNTVOFF0<n>_EL2 170 * AMEVCNTVOFF1<n>_EL2 171 * ICH_LR<n>_EL2 172 */ 173 #define CTX_EL2_SYSREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 174 175 #define CTX_ACTLR_EL2 U(0x0) 176 #define CTX_AFSR0_EL2 U(0x8) 177 #define CTX_AFSR1_EL2 U(0x10) 178 #define CTX_AMAIR_EL2 U(0x18) 179 #define CTX_CNTHCTL_EL2 U(0x20) 180 #define CTX_CNTVOFF_EL2 U(0x28) 181 #define CTX_CPTR_EL2 U(0x30) 182 #define CTX_DBGVCR32_EL2 U(0x38) 183 #define CTX_ELR_EL2 U(0x40) 184 #define CTX_ESR_EL2 U(0x48) 185 #define CTX_FAR_EL2 U(0x50) 186 #define CTX_HACR_EL2 U(0x58) 187 #define CTX_HCR_EL2 U(0x60) 188 #define CTX_HPFAR_EL2 U(0x68) 189 #define CTX_HSTR_EL2 U(0x70) 190 #define CTX_ICC_SRE_EL2 U(0x78) 191 #define CTX_ICH_HCR_EL2 U(0x80) 192 #define CTX_ICH_VMCR_EL2 U(0x88) 193 #define CTX_MAIR_EL2 U(0x90) 194 #define CTX_MDCR_EL2 U(0x98) 195 #define CTX_PMSCR_EL2 U(0xa0) 196 #define CTX_SCTLR_EL2 U(0xa8) 197 #define CTX_SPSR_EL2 U(0xb0) 198 #define CTX_SP_EL2 U(0xb8) 199 #define CTX_TCR_EL2 U(0xc0) 200 #define CTX_TPIDR_EL2 U(0xc8) 201 #define CTX_TTBR0_EL2 U(0xd0) 202 #define CTX_VBAR_EL2 U(0xd8) 203 #define CTX_VMPIDR_EL2 U(0xe0) 204 #define CTX_VPIDR_EL2 U(0xe8) 205 #define CTX_VTCR_EL2 U(0xf0) 206 #define CTX_VTTBR_EL2 U(0xf8) 207 208 // Only if MTE registers in use 209 #define CTX_TFSR_EL2 U(0x100) 210 211 #define CTX_MPAM2_EL2 U(0x108) 212 #define CTX_MPAMHCR_EL2 U(0x110) 213 #define CTX_MPAMVPM0_EL2 U(0x118) 214 #define CTX_MPAMVPM1_EL2 U(0x120) 215 #define CTX_MPAMVPM2_EL2 U(0x128) 216 #define CTX_MPAMVPM3_EL2 U(0x130) 217 #define CTX_MPAMVPM4_EL2 U(0x138) 218 #define CTX_MPAMVPM5_EL2 U(0x140) 219 #define CTX_MPAMVPM6_EL2 U(0x148) 220 #define CTX_MPAMVPM7_EL2 U(0x150) 221 #define CTX_MPAMVPMV_EL2 U(0x158) 222 223 // Starting with Armv8.6 224 #define CTX_HDFGRTR_EL2 U(0x160) 225 #define CTX_HAFGRTR_EL2 U(0x168) 226 #define CTX_HDFGWTR_EL2 U(0x170) 227 #define CTX_HFGITR_EL2 U(0x178) 228 #define CTX_HFGRTR_EL2 U(0x180) 229 #define CTX_HFGWTR_EL2 U(0x188) 230 #define CTX_CNTPOFF_EL2 U(0x190) 231 232 // Starting with Armv8.4 233 #define CTX_CONTEXTIDR_EL2 U(0x198) 234 #define CTX_TTBR1_EL2 U(0x1a0) 235 #define CTX_VDISR_EL2 U(0x1a8) 236 #define CTX_VSESR_EL2 U(0x1b0) 237 #define CTX_VNCR_EL2 U(0x1b8) 238 #define CTX_TRFCR_EL2 U(0x1c0) 239 240 // Starting with Armv8.5 241 #define CTX_SCXTNUM_EL2 U(0x1c8) 242 243 // Register for FEAT_HCX 244 #define CTX_HCRX_EL2 U(0x1d0) 245 246 // Starting with Armv8.9 247 #define CTX_TCR2_EL2 U(0x1d8) 248 #define CTX_POR_EL2 U(0x1e0) 249 #define CTX_PIRE0_EL2 U(0x1e8) 250 #define CTX_PIR_EL2 U(0x1f0) 251 #define CTX_S2PIR_EL2 U(0x1f8) 252 #define CTX_GCSCR_EL2 U(0x200) 253 #define CTX_GCSPR_EL2 U(0x208) 254 255 /* Align to the next 16 byte boundary */ 256 #define CTX_EL2_SYSREGS_END U(0x210) 257 258 #endif /* CTX_INCLUDE_EL2_REGS */ 259 260 /******************************************************************************* 261 * Constants that allow assembler code to access members of and the 'fp_regs' 262 * structure at their correct offsets. 263 ******************************************************************************/ 264 #if CTX_INCLUDE_EL2_REGS 265 # define CTX_FPREGS_OFFSET (CTX_EL2_SYSREGS_OFFSET + CTX_EL2_SYSREGS_END) 266 #else 267 # define CTX_FPREGS_OFFSET (CTX_EL1_SYSREGS_OFFSET + CTX_EL1_SYSREGS_END) 268 #endif 269 #if CTX_INCLUDE_FPREGS 270 #define CTX_FP_Q0 U(0x0) 271 #define CTX_FP_Q1 U(0x10) 272 #define CTX_FP_Q2 U(0x20) 273 #define CTX_FP_Q3 U(0x30) 274 #define CTX_FP_Q4 U(0x40) 275 #define CTX_FP_Q5 U(0x50) 276 #define CTX_FP_Q6 U(0x60) 277 #define CTX_FP_Q7 U(0x70) 278 #define CTX_FP_Q8 U(0x80) 279 #define CTX_FP_Q9 U(0x90) 280 #define CTX_FP_Q10 U(0xa0) 281 #define CTX_FP_Q11 U(0xb0) 282 #define CTX_FP_Q12 U(0xc0) 283 #define CTX_FP_Q13 U(0xd0) 284 #define CTX_FP_Q14 U(0xe0) 285 #define CTX_FP_Q15 U(0xf0) 286 #define CTX_FP_Q16 U(0x100) 287 #define CTX_FP_Q17 U(0x110) 288 #define CTX_FP_Q18 U(0x120) 289 #define CTX_FP_Q19 U(0x130) 290 #define CTX_FP_Q20 U(0x140) 291 #define CTX_FP_Q21 U(0x150) 292 #define CTX_FP_Q22 U(0x160) 293 #define CTX_FP_Q23 U(0x170) 294 #define CTX_FP_Q24 U(0x180) 295 #define CTX_FP_Q25 U(0x190) 296 #define CTX_FP_Q26 U(0x1a0) 297 #define CTX_FP_Q27 U(0x1b0) 298 #define CTX_FP_Q28 U(0x1c0) 299 #define CTX_FP_Q29 U(0x1d0) 300 #define CTX_FP_Q30 U(0x1e0) 301 #define CTX_FP_Q31 U(0x1f0) 302 #define CTX_FP_FPSR U(0x200) 303 #define CTX_FP_FPCR U(0x208) 304 #if CTX_INCLUDE_AARCH32_REGS 305 #define CTX_FP_FPEXC32_EL2 U(0x210) 306 #define CTX_FPREGS_END U(0x220) /* Align to the next 16 byte boundary */ 307 #else 308 #define CTX_FPREGS_END U(0x210) /* Align to the next 16 byte boundary */ 309 #endif 310 #else 311 #define CTX_FPREGS_END U(0) 312 #endif 313 314 /******************************************************************************* 315 * Registers related to CVE-2018-3639 316 ******************************************************************************/ 317 #define CTX_CVE_2018_3639_OFFSET (CTX_FPREGS_OFFSET + CTX_FPREGS_END) 318 #define CTX_CVE_2018_3639_DISABLE U(0) 319 #define CTX_CVE_2018_3639_END U(0x10) /* Align to the next 16 byte boundary */ 320 321 /******************************************************************************* 322 * Registers related to ARMv8.3-PAuth. 323 ******************************************************************************/ 324 #define CTX_PAUTH_REGS_OFFSET (CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_END) 325 #if CTX_INCLUDE_PAUTH_REGS 326 #define CTX_PACIAKEY_LO U(0x0) 327 #define CTX_PACIAKEY_HI U(0x8) 328 #define CTX_PACIBKEY_LO U(0x10) 329 #define CTX_PACIBKEY_HI U(0x18) 330 #define CTX_PACDAKEY_LO U(0x20) 331 #define CTX_PACDAKEY_HI U(0x28) 332 #define CTX_PACDBKEY_LO U(0x30) 333 #define CTX_PACDBKEY_HI U(0x38) 334 #define CTX_PACGAKEY_LO U(0x40) 335 #define CTX_PACGAKEY_HI U(0x48) 336 #define CTX_PAUTH_REGS_END U(0x50) /* Align to the next 16 byte boundary */ 337 #else 338 #define CTX_PAUTH_REGS_END U(0) 339 #endif /* CTX_INCLUDE_PAUTH_REGS */ 340 341 /******************************************************************************* 342 * Registers initialised in a per-world context. 343 ******************************************************************************/ 344 #define CTX_CPTR_EL3 U(0x0) 345 #define CTX_ZCR_EL3 U(0x8) 346 #define CTX_GLOBAL_EL3STATE_END U(0x10) 347 348 #ifndef __ASSEMBLER__ 349 350 #include <stdint.h> 351 352 #include <lib/cassert.h> 353 354 /* 355 * Common constants to help define the 'cpu_context' structure and its 356 * members below. 357 */ 358 #define DWORD_SHIFT U(3) 359 #define DEFINE_REG_STRUCT(name, num_regs) \ 360 typedef struct name { \ 361 uint64_t ctx_regs[num_regs]; \ 362 } __aligned(16) name##_t 363 364 /* Constants to determine the size of individual context structures */ 365 #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) 366 #define CTX_EL1_SYSREGS_ALL (CTX_EL1_SYSREGS_END >> DWORD_SHIFT) 367 #if CTX_INCLUDE_EL2_REGS 368 # define CTX_EL2_SYSREGS_ALL (CTX_EL2_SYSREGS_END >> DWORD_SHIFT) 369 #endif 370 #if CTX_INCLUDE_FPREGS 371 # define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) 372 #endif 373 #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) 374 #define CTX_CVE_2018_3639_ALL (CTX_CVE_2018_3639_END >> DWORD_SHIFT) 375 #if CTX_INCLUDE_PAUTH_REGS 376 # define CTX_PAUTH_REGS_ALL (CTX_PAUTH_REGS_END >> DWORD_SHIFT) 377 #endif 378 379 /* 380 * AArch64 general purpose register context structure. Usually x0-x18, 381 * lr are saved as the compiler is expected to preserve the remaining 382 * callee saved registers if used by the C runtime and the assembler 383 * does not touch the remaining. But in case of world switch during 384 * exception handling, we need to save the callee registers too. 385 */ 386 DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); 387 388 /* 389 * AArch64 EL1 system register context structure for preserving the 390 * architectural state during world switches. 391 */ 392 DEFINE_REG_STRUCT(el1_sysregs, CTX_EL1_SYSREGS_ALL); 393 394 395 /* 396 * AArch64 EL2 system register context structure for preserving the 397 * architectural state during world switches. 398 */ 399 #if CTX_INCLUDE_EL2_REGS 400 DEFINE_REG_STRUCT(el2_sysregs, CTX_EL2_SYSREGS_ALL); 401 #endif 402 403 /* 404 * AArch64 floating point register context structure for preserving 405 * the floating point state during switches from one security state to 406 * another. 407 */ 408 #if CTX_INCLUDE_FPREGS 409 DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); 410 #endif 411 412 /* 413 * Miscellaneous registers used by EL3 firmware to maintain its state 414 * across exception entries and exits 415 */ 416 DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); 417 418 /* Function pointer used by CVE-2018-3639 dynamic mitigation */ 419 DEFINE_REG_STRUCT(cve_2018_3639, CTX_CVE_2018_3639_ALL); 420 421 /* Registers associated to ARMv8.3-PAuth */ 422 #if CTX_INCLUDE_PAUTH_REGS 423 DEFINE_REG_STRUCT(pauth, CTX_PAUTH_REGS_ALL); 424 #endif 425 426 /* 427 * Macros to access members of any of the above structures using their 428 * offsets 429 */ 430 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) 431 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ 432 = (uint64_t) (val)) 433 434 /* 435 * Top-level context structure which is used by EL3 firmware to preserve 436 * the state of a core at the next lower EL in a given security state and 437 * save enough EL3 meta data to be able to return to that EL and security 438 * state. The context management library will be used to ensure that 439 * SP_EL3 always points to an instance of this structure at exception 440 * entry and exit. 441 */ 442 typedef struct cpu_context { 443 gp_regs_t gpregs_ctx; 444 el3_state_t el3state_ctx; 445 el1_sysregs_t el1_sysregs_ctx; 446 #if CTX_INCLUDE_EL2_REGS 447 el2_sysregs_t el2_sysregs_ctx; 448 #endif 449 #if CTX_INCLUDE_FPREGS 450 fp_regs_t fpregs_ctx; 451 #endif 452 cve_2018_3639_t cve_2018_3639_ctx; 453 #if CTX_INCLUDE_PAUTH_REGS 454 pauth_t pauth_ctx; 455 #endif 456 } cpu_context_t; 457 458 /* 459 * Per-World Context. 460 * It stores registers whose values can be shared across CPUs. 461 */ 462 typedef struct per_world_context { 463 uint64_t ctx_cptr_el3; 464 uint64_t ctx_zcr_el3; 465 } per_world_context_t; 466 467 extern per_world_context_t per_world_context[CPU_DATA_CONTEXT_NUM]; 468 469 /* Macros to access members of the 'cpu_context_t' structure */ 470 #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) 471 #if CTX_INCLUDE_FPREGS 472 # define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) 473 #endif 474 #define get_el1_sysregs_ctx(h) (&((cpu_context_t *) h)->el1_sysregs_ctx) 475 #if CTX_INCLUDE_EL2_REGS 476 # define get_el2_sysregs_ctx(h) (&((cpu_context_t *) h)->el2_sysregs_ctx) 477 #endif 478 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) 479 #define get_cve_2018_3639_ctx(h) (&((cpu_context_t *) h)->cve_2018_3639_ctx) 480 #if CTX_INCLUDE_PAUTH_REGS 481 # define get_pauth_ctx(h) (&((cpu_context_t *) h)->pauth_ctx) 482 #endif 483 484 /* 485 * Compile time assertions related to the 'cpu_context' structure to 486 * ensure that the assembler and the compiler view of the offsets of 487 * the structure members is the same. 488 */ 489 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), 490 assert_core_context_gp_offset_mismatch); 491 CASSERT(CTX_EL1_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el1_sysregs_ctx), 492 assert_core_context_el1_sys_offset_mismatch); 493 #if CTX_INCLUDE_EL2_REGS 494 CASSERT(CTX_EL2_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, el2_sysregs_ctx), 495 assert_core_context_el2_sys_offset_mismatch); 496 #endif 497 #if CTX_INCLUDE_FPREGS 498 CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), 499 assert_core_context_fp_offset_mismatch); 500 #endif 501 CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), 502 assert_core_context_el3state_offset_mismatch); 503 CASSERT(CTX_CVE_2018_3639_OFFSET == __builtin_offsetof(cpu_context_t, cve_2018_3639_ctx), 504 assert_core_context_cve_2018_3639_offset_mismatch); 505 #if CTX_INCLUDE_PAUTH_REGS 506 CASSERT(CTX_PAUTH_REGS_OFFSET == __builtin_offsetof(cpu_context_t, pauth_ctx), 507 assert_core_context_pauth_offset_mismatch); 508 #endif 509 510 /* 511 * Helper macro to set the general purpose registers that correspond to 512 * parameters in an aapcs_64 call i.e. x0-x7 513 */ 514 #define set_aapcs_args0(ctx, x0) do { \ 515 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ 516 } while (0) 517 #define set_aapcs_args1(ctx, x0, x1) do { \ 518 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ 519 set_aapcs_args0(ctx, x0); \ 520 } while (0) 521 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ 522 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ 523 set_aapcs_args1(ctx, x0, x1); \ 524 } while (0) 525 #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ 526 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ 527 set_aapcs_args2(ctx, x0, x1, x2); \ 528 } while (0) 529 #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ 530 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ 531 set_aapcs_args3(ctx, x0, x1, x2, x3); \ 532 } while (0) 533 #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ 534 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ 535 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ 536 } while (0) 537 #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ 538 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ 539 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ 540 } while (0) 541 #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ 542 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ 543 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ 544 } while (0) 545 546 /******************************************************************************* 547 * Function prototypes 548 ******************************************************************************/ 549 void el1_sysregs_context_save(el1_sysregs_t *regs); 550 void el1_sysregs_context_restore(el1_sysregs_t *regs); 551 552 #if CTX_INCLUDE_FPREGS 553 void fpregs_context_save(fp_regs_t *regs); 554 void fpregs_context_restore(fp_regs_t *regs); 555 #endif 556 557 #endif /* __ASSEMBLER__ */ 558 559 #endif /* CONTEXT_H */ 560
