1 /*
2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef ARCH_HELPERS_H
8 #define ARCH_HELPERS_H
9
10 #include <cdefs.h>
11 #include <stdbool.h>
12 #include <stdint.h>
13 #include <string.h>
14
15 #include <arch.h>
16
17 /**********************************************************************
18 * Macros which create inline functions to read or write CPU system
19 * registers
20 *********************************************************************/
21
22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
23 static inline u_register_t read_ ## _name(void) \
24 { \
25 u_register_t v; \
26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
27 return v; \
28 }
29
30 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
31 static inline void write_ ## _name(u_register_t v) \
32 { \
33 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
34 }
35
36 #define SYSREG_WRITE_CONST(reg_name, v) \
37 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
38
39 /* Define read function for system register */
40 #define DEFINE_SYSREG_READ_FUNC(_name) \
41 _DEFINE_SYSREG_READ_FUNC(_name, _name)
42
43 /* Define read & write function for system register */
44 #define DEFINE_SYSREG_RW_FUNCS(_name) \
45 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
46 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
47
48 /* Define read & write function for renamed system register */
49 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
50 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
51 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
52
53 /* Define read function for renamed system register */
54 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
55 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
56
57 /* Define write function for renamed system register */
58 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
60
61 /**********************************************************************
62 * Macros to create inline functions for system instructions
63 *********************************************************************/
64
65 /* Define function for simple system instruction */
66 #define DEFINE_SYSOP_FUNC(_op) \
67 static inline void _op(void) \
68 { \
69 __asm__ (#_op); \
70 }
71
72 /* Define function for system instruction with register parameter */
73 #define DEFINE_SYSOP_PARAM_FUNC(_op) \
74 static inline void _op(uint64_t v) \
75 { \
76 __asm__ (#_op " %0" : : "r" (v)); \
77 }
78
79 /* Define function for system instruction with type specifier */
80 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
81 static inline void _op ## _type(void) \
82 { \
83 __asm__ (#_op " " #_type : : : "memory"); \
84 }
85
86 /* Define function for system instruction with register parameter */
87 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
88 static inline void _op ## _type(uint64_t v) \
89 { \
90 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
91 }
92
93 /*******************************************************************************
94 * TLB maintenance accessor prototypes
95 ******************************************************************************/
96
97 #if ERRATA_A57_813419 || ERRATA_A76_1286807
98 /*
99 * Define function for TLBI instruction with type specifier that implements
100 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
101 * Cortex-A76.
102 */
103 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
104 static inline void tlbi ## _type(void) \
105 { \
106 __asm__("tlbi " #_type "\n" \
107 "dsb ish\n" \
108 "tlbi " #_type); \
109 }
110
111 /*
112 * Define function for TLBI instruction with register parameter that implements
113 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
114 * Cortex-A76.
115 */
116 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
117 static inline void tlbi ## _type(uint64_t v) \
118 { \
119 __asm__("tlbi " #_type ", %0\n" \
120 "dsb ish\n" \
121 "tlbi " #_type ", %0" : : "r" (v)); \
122 }
123 #endif /* ERRATA_A57_813419 */
124
125 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
126 /*
127 * Define function for DC instruction with register parameter that enables
128 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
129 */
130 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
131 static inline void dc ## _name(uint64_t v) \
132 { \
133 __asm__("dc " #_type ", %0" : : "r" (v)); \
134 }
135 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
136
137 #if ERRATA_A57_813419
138 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
139 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
140 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
141 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
142 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
143 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
144 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
145 #elif ERRATA_A76_1286807
146 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
147 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
148 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
149 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
150 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
151 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
152 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
153 #else
154 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
158 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
159 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
160 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
161 #endif
162
163 #if ERRATA_A57_813419
164 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
165 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
166 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
167 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
168 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
169 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
170 #elif ERRATA_A76_1286807
171 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
172 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
173 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
174 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
175 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
176 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
177 #else
178 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
179 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
180 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
184 #endif
185
186 /*******************************************************************************
187 * Cache maintenance accessor prototypes
188 ******************************************************************************/
189 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
190 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
191 #if ERRATA_A53_827319
192 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
193 #else
194 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
195 #endif
196 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
197 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
198 #else
199 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
200 #endif
201 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
202 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
203 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
204 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
205 #else
206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
207 #endif
208 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
209
210 /*******************************************************************************
211 * Address translation accessor prototypes
212 ******************************************************************************/
213 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
214 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
215 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
216 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
217 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
218 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
219 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
220
221 /*******************************************************************************
222 * Strip Pointer Authentication Code
223 ******************************************************************************/
224 DEFINE_SYSOP_PARAM_FUNC(xpaci)
225
226 void flush_dcache_range(uintptr_t addr, size_t size);
227 void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
228 void clean_dcache_range(uintptr_t addr, size_t size);
229 void inv_dcache_range(uintptr_t addr, size_t size);
230 bool is_dcache_enabled(void);
231
232 void dcsw_op_louis(u_register_t op_type);
233 void dcsw_op_all(u_register_t op_type);
234
235 void disable_mmu_el1(void);
236 void disable_mmu_el3(void);
237 void disable_mpu_el2(void);
238 void disable_mmu_icache_el1(void);
239 void disable_mmu_icache_el3(void);
240 void disable_mpu_icache_el2(void);
241
242 /*******************************************************************************
243 * Misc. accessor prototypes
244 ******************************************************************************/
245
246 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
247 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
248
249 DEFINE_SYSREG_RW_FUNCS(par_el1)
DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)250 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
251 DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1)
252 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1)
253 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
254 DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1)
255 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1)
256 DEFINE_SYSREG_READ_FUNC(id_afr0_el1)
257 DEFINE_SYSREG_READ_FUNC(CurrentEl)
258 DEFINE_SYSREG_READ_FUNC(ctr_el0)
259 DEFINE_SYSREG_RW_FUNCS(daif)
260 DEFINE_SYSREG_RW_FUNCS(spsr_el1)
261 DEFINE_SYSREG_RW_FUNCS(spsr_el2)
262 DEFINE_SYSREG_RW_FUNCS(spsr_el3)
263 DEFINE_SYSREG_RW_FUNCS(elr_el1)
264 DEFINE_SYSREG_RW_FUNCS(elr_el2)
265 DEFINE_SYSREG_RW_FUNCS(elr_el3)
266 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
267 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
268 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
269
270 DEFINE_SYSOP_FUNC(wfi)
271 DEFINE_SYSOP_FUNC(wfe)
272 DEFINE_SYSOP_FUNC(sev)
273 DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
274 DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
275 DEFINE_SYSOP_TYPE_FUNC(dmb, st)
276 DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
277 DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
278 DEFINE_SYSOP_TYPE_FUNC(dsb, osh)
279 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
280 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
281 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst)
282 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
283 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
284 DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
285 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
286 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
287 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
288 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
289 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
290 DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
291 DEFINE_SYSOP_FUNC(isb)
292
293 static inline void enable_irq(void)
294 {
295 /*
296 * The compiler memory barrier will prevent the compiler from
297 * scheduling non-volatile memory access after the write to the
298 * register.
299 *
300 * This could happen if some initialization code issues non-volatile
301 * accesses to an area used by an interrupt handler, in the assumption
302 * that it is safe as the interrupts are disabled at the time it does
303 * that (according to program order). However, non-volatile accesses
304 * are not necessarily in program order relatively with volatile inline
305 * assembly statements (and volatile accesses).
306 */
307 COMPILER_BARRIER();
308 write_daifclr(DAIF_IRQ_BIT);
309 isb();
310 }
311
enable_fiq(void)312 static inline void enable_fiq(void)
313 {
314 COMPILER_BARRIER();
315 write_daifclr(DAIF_FIQ_BIT);
316 isb();
317 }
318
enable_serror(void)319 static inline void enable_serror(void)
320 {
321 COMPILER_BARRIER();
322 write_daifclr(DAIF_ABT_BIT);
323 isb();
324 }
325
enable_debug_exceptions(void)326 static inline void enable_debug_exceptions(void)
327 {
328 COMPILER_BARRIER();
329 write_daifclr(DAIF_DBG_BIT);
330 isb();
331 }
332
disable_irq(void)333 static inline void disable_irq(void)
334 {
335 COMPILER_BARRIER();
336 write_daifset(DAIF_IRQ_BIT);
337 isb();
338 }
339
disable_fiq(void)340 static inline void disable_fiq(void)
341 {
342 COMPILER_BARRIER();
343 write_daifset(DAIF_FIQ_BIT);
344 isb();
345 }
346
disable_serror(void)347 static inline void disable_serror(void)
348 {
349 COMPILER_BARRIER();
350 write_daifset(DAIF_ABT_BIT);
351 isb();
352 }
353
disable_debug_exceptions(void)354 static inline void disable_debug_exceptions(void)
355 {
356 COMPILER_BARRIER();
357 write_daifset(DAIF_DBG_BIT);
358 isb();
359 }
360
361 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
362 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
363
364 /*******************************************************************************
365 * System register accessor prototypes
366 ******************************************************************************/
367 DEFINE_SYSREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)368 DEFINE_SYSREG_READ_FUNC(mpidr_el1)
369 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
370 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr1_el1)
371
372 DEFINE_SYSREG_RW_FUNCS(scr_el3)
373 DEFINE_SYSREG_RW_FUNCS(hcr_el2)
374
375 DEFINE_SYSREG_RW_FUNCS(vbar_el1)
376 DEFINE_SYSREG_RW_FUNCS(vbar_el2)
377 DEFINE_SYSREG_RW_FUNCS(vbar_el3)
378
379 DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
380 DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
381 DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
382
383 DEFINE_SYSREG_RW_FUNCS(actlr_el1)
384 DEFINE_SYSREG_RW_FUNCS(actlr_el2)
385 DEFINE_SYSREG_RW_FUNCS(actlr_el3)
386
387 DEFINE_SYSREG_RW_FUNCS(esr_el1)
388 DEFINE_SYSREG_RW_FUNCS(esr_el2)
389 DEFINE_SYSREG_RW_FUNCS(esr_el3)
390
391 DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
392 DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
393 DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
394
395 DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
396 DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
397 DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
398
399 DEFINE_SYSREG_RW_FUNCS(far_el1)
400 DEFINE_SYSREG_RW_FUNCS(far_el2)
401 DEFINE_SYSREG_RW_FUNCS(far_el3)
402
403 DEFINE_SYSREG_RW_FUNCS(mair_el1)
404 DEFINE_SYSREG_RW_FUNCS(mair_el2)
405 DEFINE_SYSREG_RW_FUNCS(mair_el3)
406
407 DEFINE_SYSREG_RW_FUNCS(amair_el1)
408 DEFINE_SYSREG_RW_FUNCS(amair_el2)
409 DEFINE_SYSREG_RW_FUNCS(amair_el3)
410
411 DEFINE_SYSREG_READ_FUNC(rvbar_el1)
412 DEFINE_SYSREG_READ_FUNC(rvbar_el2)
413 DEFINE_SYSREG_READ_FUNC(rvbar_el3)
414
415 DEFINE_SYSREG_RW_FUNCS(rmr_el1)
416 DEFINE_SYSREG_RW_FUNCS(rmr_el2)
417 DEFINE_SYSREG_RW_FUNCS(rmr_el3)
418
419 DEFINE_SYSREG_RW_FUNCS(tcr_el1)
420 DEFINE_SYSREG_RW_FUNCS(tcr_el2)
421 DEFINE_SYSREG_RW_FUNCS(tcr_el3)
422
423 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
424 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
425 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
426
427 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
428
429 DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
430
431 DEFINE_SYSREG_RW_FUNCS(cptr_el2)
432 DEFINE_SYSREG_RW_FUNCS(cptr_el3)
433
434 DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
435 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
436 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
437 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
438 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
439 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
440 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
441 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
442 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
443 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
444 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
445 DEFINE_SYSREG_READ_FUNC(cntpct_el0)
446 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
447
448 DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
449
450 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
451 CNTP_CTL_ENABLE_MASK)
452 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
453 CNTP_CTL_IMASK_MASK)
454 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
455 CNTP_CTL_ISTATUS_MASK)
456
457 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
458 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
459
460 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
461 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
462
463 DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
464
465 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
466
467 DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
468 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
469
470 DEFINE_SYSREG_READ_FUNC(isr_el1)
471
472 DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
473 DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
474 DEFINE_SYSREG_RW_FUNCS(hstr_el2)
475 DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
476
477 /* GICv3 System Registers */
478
479 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
480 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
481 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
482 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
483 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
484 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
485 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
486 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
487 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
488 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
489 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
490 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
491 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
492 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
493 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
494 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
495
496 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
497 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
498 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0)
499 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
500 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
501 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
502 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
503 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
504
505 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
506 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
507 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
508 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
509
510 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
511
512 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
513 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
514
515 DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
516 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3)
517
518 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
519 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
520
521 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
522 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
523 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
524 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
525 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
526 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
527
528 /* Armv8.2 Registers */
529 DEFINE_RENAME_SYSREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
530
531 /* Armv8.3 Pointer Authentication Registers */
532 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
533 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
534
535 /* Armv8.4 Data Independent Timing Register */
536 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
537
538 /* Armv8.5 MTE Registers */
539 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
540 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
541 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
542 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
543
544 /* Armv8.5 FEAT_RNG Registers */
545 DEFINE_SYSREG_READ_FUNC(rndr)
546 DEFINE_SYSREG_READ_FUNC(rndrrs)
547
548 /* FEAT_HCX Register */
549 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
550
551 /* DynamIQ Shared Unit power management */
552 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
553
554 /* CPU Power/Performance Management registers */
555 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3)
556 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3)
557
558 /* Armv9.2 RME Registers */
559 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
560 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
561
562 #define IS_IN_EL(x) \
563 (GET_EL(read_CurrentEl()) == MODE_EL##x)
564
565 #define IS_IN_EL1() IS_IN_EL(1)
566 #define IS_IN_EL2() IS_IN_EL(2)
567 #define IS_IN_EL3() IS_IN_EL(3)
568
569 static inline unsigned int get_current_el(void)
570 {
571 return GET_EL(read_CurrentEl());
572 }
573
get_current_el_maybe_constant(void)574 static inline unsigned int get_current_el_maybe_constant(void)
575 {
576 #if defined(IMAGE_AT_EL1)
577 return 1;
578 #elif defined(IMAGE_AT_EL2)
579 return 2; /* no use-case in TF-A */
580 #elif defined(IMAGE_AT_EL3)
581 return 3;
582 #else
583 /*
584 * If we do not know which exception level this is being built for
585 * (e.g. built for library), fall back to run-time detection.
586 */
587 return get_current_el();
588 #endif
589 }
590
591 /*
592 * Check if an EL is implemented from AA64PFR0 register fields.
593 */
el_implemented(unsigned int el)594 static inline uint64_t el_implemented(unsigned int el)
595 {
596 if (el > 3U) {
597 return EL_IMPL_NONE;
598 } else {
599 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
600
601 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
602 }
603 }
604
605 /*
606 * TLBIPAALLOS instruction
607 * (TLB Inivalidate GPT Information by PA,
608 * All Entries, Outer Shareable)
609 */
tlbipaallos(void)610 static inline void tlbipaallos(void)
611 {
612 __asm__("SYS #6,c8,c1,#4");
613 }
614
615 /*
616 * Invalidate TLBs of GPT entries by Physical address, last level.
617 *
618 * @pa: the starting address for the range
619 * of invalidation
620 * @size: size of the range of invalidation
621 */
622 void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
623
624
625 /* Previously defined accessor functions with incomplete register names */
626
627 #define read_current_el() read_CurrentEl()
628
629 #define dsb() dsbsy()
630
631 #define read_midr() read_midr_el1()
632
633 #define read_mpidr() read_mpidr_el1()
634
635 #define read_scr() read_scr_el3()
636 #define write_scr(_v) write_scr_el3(_v)
637
638 #define read_hcr() read_hcr_el2()
639 #define write_hcr(_v) write_hcr_el2(_v)
640
641 #define read_cpacr() read_cpacr_el1()
642 #define write_cpacr(_v) write_cpacr_el1(_v)
643
644 #define read_clusterpwrdn() read_clusterpwrdn_el1()
645 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
646
647 #if ERRATA_SPECULATIVE_AT
648 /*
649 * Assuming SCTLR.M bit is already enabled
650 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits
651 * 2. Execute AT instruction for lower EL1/0
652 * 3. Disable page table walk by setting TCR_EL1.EPDx bits
653 */
654 #define AT(_at_inst, _va) \
655 { \
656 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
657 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \
658 isb(); \
659 _at_inst(_va); \
660 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \
661 isb(); \
662 }
663 #else
664 #define AT(_at_inst, _va) _at_inst(_va);
665 #endif
666
667 #endif /* ARCH_HELPERS_H */
668
