1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdint.h>
8 #include <sys/param.h>
9 #include "soc/soc.h"
10 #include "soc/rtc.h"
11 #include "soc/rtc_cntl_reg.h"
12 #include "soc/dport_reg.h"
13 #include "soc/gpio_reg.h"
14 #include "soc/syscon_reg.h"
15 #include "soc/spi_mem_reg.h"
16 #include "soc/extmem_reg.h"
17 #include "soc/syscon_reg.h"
18 #include "regi2c_ctrl.h"
19 #include "soc/regi2c_lp_bias.h"
20 #include "soc/regi2c_ulp.h"
21 #include "soc/regi2c_dig_reg.h"
22 #include "esp_hw_log.h"
23 #include "esp_err.h"
24 #include "esp_attr.h"
25 #include "esp_private/mspi_timing_tuning.h"
26 #include "hal/efuse_hal.h"
27 #include "hal/efuse_ll.h"
28 #ifndef BOOTLOADER_BUILD
29 #include "esp_private/sar_periph_ctrl.h"
30 #endif
31
32 #define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
33
34 static const char *TAG = "rtcinit";
35
36 static void set_ocode_by_efuse(int calib_version);
37 static void calibrate_ocode(void);
38 static void rtc_set_stored_dbias(void);
39
40 // Initial values are used for bootloader, and these variables will be re-assigned based on efuse values during application startup
41 uint32_t g_dig_dbias_pvt_240m = 28;
42 uint32_t g_rtc_dbias_pvt_240m = 28;
43 uint32_t g_dig_dbias_pvt_non_240m = 27;
44 uint32_t g_rtc_dbias_pvt_non_240m = 27;
45
rtc_init(rtc_config_t cfg)46 void rtc_init(rtc_config_t cfg)
47 {
48 /**
49 * When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup
50 * from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and
51 * NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs
52 * and finally triggle RTC WDT. So need to clear modem Force PD.
53 *
54 * No worry about the power consumption, Because modem Force PD will be set at the end of this function.
55 */
56 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
57 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
58
59 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0);
60 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0);
61 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
62 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
63 REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
64
65 /* Moved from rtc sleep to rtc init to save sleep function running time */
66 // set shortest possible sleep time limit
67 REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
68
69 // set wifi timer
70 rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
71 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
72 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
73 // set bt timer
74 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, rtc_init_cfg.bt_powerup_cycles);
75 REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, rtc_init_cfg.bt_wait_cycles);
76
77 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, rtc_init_cfg.cpu_top_powerup_cycles);
78 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, rtc_init_cfg.cpu_top_wait_cycles);
79
80 // set rtc peri timer
81 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles);
82 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles);
83 // set digital wrap timer
84 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
85 REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
86
87 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, rtc_init_cfg.dg_peri_powerup_cycles);
88 REG_SET_FIELD(RTC_CNTL_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, rtc_init_cfg.dg_peri_wait_cycles);
89
90 /* Reset RTC bias to default value (needed if waking up from deep sleep) */
91 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, RTC_CNTL_DBIAS_1V10);
92 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, RTC_CNTL_DBIAS_1V10);
93 /* Set the wait time to the default value. */
94 REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
95
96 if (cfg.cali_ocode) {
97 uint32_t blk_ver_major = efuse_ll_get_blk_version_major(); // IDF-5366
98 //default blk_ver_major will fallback to using the self-calibration way for OCode
99 bool ocode_efuse_cali = (blk_ver_major == 1);
100 if (ocode_efuse_cali) {
101 set_ocode_by_efuse(blk_ver_major);
102 } else {
103 calibrate_ocode();
104 }
105 }
106
107 //LDO dbias initialization
108 rtc_set_stored_dbias();
109
110 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, g_rtc_dbias_pvt_non_240m);
111 REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, g_dig_dbias_pvt_non_240m);
112
113 if (cfg.clkctl_init) {
114 //clear CMMU clock force on
115 CLEAR_PERI_REG_MASK(EXTMEM_CACHE_MMU_POWER_CTRL_REG, EXTMEM_CACHE_MMU_MEM_FORCE_ON);
116 //clear clkgate force on
117 REG_WRITE(SYSCON_CLKGATE_FORCE_ON_REG, 0);
118 //clear tag clock force on
119 CLEAR_PERI_REG_MASK(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_DCACHE_TAG_MEM_FORCE_ON);
120 CLEAR_PERI_REG_MASK(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_ICACHE_TAG_MEM_FORCE_ON);
121 //clear register clock force on
122 CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
123 CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
124 }
125
126 if (cfg.pwrctl_init) {
127 CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
128 //cancel xtal force pu if no need to force power up
129 //cannot cancel xtal force pu if pll is force power on
130 if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
131 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
132 } else {
133 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
134 }
135
136 //open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo is low.
137 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
138
139 //cancel bbpll force pu if setting no force power up
140 if (!cfg.bbpll_fpu) {
141 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
142 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
143 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
144 } else {
145 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
146 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
147 SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
148 }
149 //cancel RTC REG force PU
150 CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU);
151 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
152 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
153
154 CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO);
155
156 if (cfg.rtc_dboost_fpd) {
157 SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
158 } else {
159 CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
160 }
161 //clear i2c_reset_protect pd force, need tested in low temperature.
162 CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_I2C_RESET_POR_FORCE_PD);
163
164 /* If this mask is enabled, all soc memories cannot enter power down mode */
165 /* We should control soc memory power down mode from RTC, so we will not touch this register any more */
166 CLEAR_PERI_REG_MASK(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK);
167 /* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
168 /* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
169 rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0);
170 rtc_sleep_pu(pu_cfg);
171
172 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
173 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | RTC_CNTL_DG_WRAP_FORCE_ISO);
174
175 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_WIFI_FORCE_ISO);
176 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
177
178 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | RTC_CNTL_BT_FORCE_ISO);
179 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU);
180
181 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO);
182 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU);
183
184 REG_CLR_BIT(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO);
185 REG_CLR_BIT(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU);
186
187 REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
188 REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_ISO);
189 REG_CLR_BIT(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU);
190
191 //cancel digital PADS force no iso
192 if (cfg.cpu_waiti_clk_gate) {
193 CLEAR_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
194 } else {
195 SET_PERI_REG_MASK(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPU_WAIT_MODE_FORCE_ON);
196 }
197 /*if SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/
198 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
199 CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
200 }
201 /* force power down modem(wifi and ble) power domain */
202 SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
203 SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
204
205 REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
206 REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
207
208 #ifndef BOOTLOADER_BUILD
209 //initialise SAR related peripheral register settings
210 sar_periph_ctrl_init();
211 #endif
212 }
213
rtc_vddsdio_get_config(void)214 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
215 {
216 rtc_vddsdio_config_t result;
217 uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
218 result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
219 result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
220 result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
221 if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
222 // Get configuration from RTC
223 result.force = 1;
224 result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
225 result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
226 return result;
227 } else {
228 result.force = 0;
229 }
230 // Otherwise, VDD_SDIO is controlled by bootstrapping pin
231 uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
232 result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
233 result.enable = 1;
234 return result;
235 }
236
rtc_vddsdio_set_config(rtc_vddsdio_config_t config)237 void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
238 {
239 uint32_t val = 0;
240 val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
241 val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
242 val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
243 val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
244 val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
245 val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
246 val |= RTC_CNTL_SDIO_PD_EN;
247 REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
248 }
249
set_ocode_by_efuse(int calib_version)250 static void set_ocode_by_efuse(int calib_version)
251 {
252 assert(calib_version == 1);
253 // use efuse ocode.
254 uint32_t ocode = efuse_ll_get_ocode();
255 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
256 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
257 }
258
259 /**
260 * TODO: IDF-4141
261 * 1. This function will change the system clock source to XTAL. Under lower frequency (e.g. XTAL), MSPI timing tuning configures should be modified accordingly.
262 * 2. RTC related should be done before SPI0 initialisation
263 */
calibrate_ocode(void)264 static void calibrate_ocode(void)
265 {
266 #if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
267 /**
268 * Background:
269 * 1. Following code will switch the system clock to XTAL first, to self-calibrate the OCode.
270 * 2. For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
271 * Certain delay will be added to the MSPI RX direction.
272 *
273 * When CPU clock switches down, the delay should be cleared. Therefore here we call this function to remove the delays.
274 */
275 mspi_timing_change_speed_mode_cache_safe(true);
276 #endif // #if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
277 /*
278 Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL).
279 Method:
280 1. read current cpu config, save in old_config;
281 2. switch cpu to xtal because PLL will be closed when o-code calibration;
282 3. begin o-code calibration;
283 4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
284 5. set cpu to old-config.
285 */
286 soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
287 rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
288 if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
289 cal_clk = RTC_CAL_32K_XTAL;
290 } else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
291 cal_clk = RTC_CAL_8MD256;
292 }
293
294 uint64_t max_delay_time_us = 10000;
295 uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
296 uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
297 uint64_t cycle0 = rtc_time_get();
298 uint64_t timeout_cycle = cycle0 + max_delay_cycle;
299 uint64_t cycle1 = 0;
300
301 rtc_cpu_freq_config_t old_config;
302 rtc_clk_cpu_freq_get_config(&old_config);
303 rtc_clk_cpu_freq_set_xtal();
304
305 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
306 REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
307 bool odone_flag = 0;
308 bool bg_odone_flag = 0;
309 while (1) {
310 odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
311 bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
312 cycle1 = rtc_time_get();
313 if (odone_flag && bg_odone_flag) {
314 break;
315 }
316 if (cycle1 >= timeout_cycle) {
317 ESP_HW_LOGW(TAG, "o_code calibration fail\n");
318 break;
319 }
320 }
321 rtc_clk_cpu_freq_set_config(&old_config);
322 #if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
323 //System clock is switched back to PLL. Here we switch to the MSPI high speed mode, add the delays back
324 mspi_timing_change_speed_mode_cache_safe(false);
325 #endif // #if !defined(BOOTLOADER_BUILD) && !defined(CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
326 }
327
get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver)328 static uint32_t get_dig_dbias_by_efuse(uint8_t pvt_scheme_ver)
329 {
330 assert(pvt_scheme_ver == 1);
331 return efuse_ll_get_dig_dbias_hvt();
332 }
333
get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver,uint32_t dig_dbias)334 static uint32_t get_rtc_dbias_by_efuse(uint8_t pvt_scheme_ver, uint32_t dig_dbias)
335 {
336 assert(pvt_scheme_ver == 1);
337 uint32_t rtc_dbias = 0;
338 signed int k_rtc_ldo = efuse_ll_get_k_rtc_ldo();
339 signed int k_dig_ldo = efuse_ll_get_k_dig_ldo();
340 signed int v_rtc_bias20 = efuse_ll_get_v_rtc_dbias20();
341 signed int v_dig_bias20 = efuse_ll_get_v_dig_dbias20();
342 k_rtc_ldo = ((k_rtc_ldo & BIT(6)) != 0)? -(k_rtc_ldo & 0x3f): (uint8_t)k_rtc_ldo;
343 k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
344 v_rtc_bias20 = ((v_rtc_bias20 & BIT(7)) != 0)? -(v_rtc_bias20 & 0x7f): (uint8_t)v_rtc_bias20;
345 v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
346
347 uint32_t v_rtc_dbias20_real_mul10000 = V_RTC_MID_MUL10000 + v_rtc_bias20 * 10000 / 500;
348 uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
349 signed int k_rtc_ldo_real_mul10000 = K_RTC_MID_MUL10000 + k_rtc_ldo;
350 signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
351 uint32_t v_dig_nearest_1v15_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
352 for (rtc_dbias = 15; rtc_dbias < 31; rtc_dbias++) {
353 uint32_t v_rtc_nearest_1v15_mul10000 = 0;
354 v_rtc_nearest_1v15_mul10000 = v_rtc_dbias20_real_mul10000 + k_rtc_ldo_real_mul10000 * (rtc_dbias - 20);
355 if (v_rtc_nearest_1v15_mul10000 >= v_dig_nearest_1v15_mul10000 - 250) {
356 break;
357 }
358 }
359 return rtc_dbias;
360 }
361
get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver)362 static uint32_t get_dig1v3_dbias_by_efuse(uint8_t pvt_scheme_ver)
363 {
364 assert(pvt_scheme_ver == 1);
365 signed int k_dig_ldo = efuse_ll_get_k_dig_ldo();
366 signed int v_dig_bias20 = efuse_ll_get_v_dig_dbias20();
367 k_dig_ldo = ((k_dig_ldo & BIT(6)) != 0)? -(k_dig_ldo & 0x3f): (uint8_t)k_dig_ldo;
368 v_dig_bias20 = ((v_dig_bias20 & BIT(7)) != 0)? -(v_dig_bias20 & 0x7f): (uint8_t)v_dig_bias20;
369
370 uint32_t v_dig_dbias20_real_mul10000 = V_DIG_MID_MUL10000 + v_dig_bias20 * 10000 / 500;
371 signed int k_dig_ldo_real_mul10000 = K_DIG_MID_MUL10000 + k_dig_ldo;
372 uint32_t dig_dbias =15;
373 for (dig_dbias = 15; dig_dbias < 31; dig_dbias++) {
374 uint32_t v_dig_nearest_1v3_mul10000 = 0;
375 v_dig_nearest_1v3_mul10000 = v_dig_dbias20_real_mul10000 + k_dig_ldo_real_mul10000 * (dig_dbias - 20);
376 if (v_dig_nearest_1v3_mul10000 >= 13000) {
377 break;
378 }
379 }
380 return dig_dbias;
381 }
382
rtc_set_stored_dbias(void)383 static void rtc_set_stored_dbias(void)
384 {
385 /*
386 1. a reasonable dig_dbias which by scanning pvt to make 240 CPU run successful stored in efuse;
387 2. also we store some value in efuse, include:
388 k_rtc_ldo (slope of rtc voltage & rtc_dbias);
389 k_dig_ldo (slope of digital voltage & digital_dbias);
390 v_rtc_bias20 (rtc voltage when rtc dbais is 20);
391 v_dig_bias20 (digital voltage when digital dbais is 20).
392 3. a reasonable rtc_dbias can be calculated by a certion formula.
393 4. save these values for reuse
394 */
395 uint8_t blk_minor = efuse_ll_get_blk_version_minor();
396 uint8_t blk_major = efuse_ll_get_blk_version_major();
397 uint8_t pvt_scheme_ver = 0;
398 if ( (blk_major <= 1 && blk_minor == 1) || blk_major > 1 || (blk_major == 1 && blk_minor >= 2) ) {
399 /* PVT supported after blk_ver 1.2 */
400 pvt_scheme_ver = 1;
401 }
402
403 if (pvt_scheme_ver == 1) {
404 uint32_t dig1v3_dbias = get_dig1v3_dbias_by_efuse(pvt_scheme_ver);
405 uint32_t dig_dbias = get_dig_dbias_by_efuse(pvt_scheme_ver);
406 if (dig_dbias != 0) {
407 g_dig_dbias_pvt_240m = MIN(dig1v3_dbias, dig_dbias + 3);
408 g_dig_dbias_pvt_non_240m = MIN(dig1v3_dbias, dig_dbias + 2);
409 g_rtc_dbias_pvt_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_240m);
410 g_rtc_dbias_pvt_non_240m = get_rtc_dbias_by_efuse(pvt_scheme_ver, g_dig_dbias_pvt_non_240m);
411 } else {
412 ESP_HW_LOGD(TAG, "not burn core voltage in efuse or burn wrong voltage value in blk version: 0%d\n", pvt_scheme_ver);
413 }
414 } else {
415 ESP_HW_LOGD(TAG, "core voltage not decided in efuse, use default value.");
416 }
417 }
418
