1 /** 2 * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: configure_register */ 14 /** Type of out_data register 15 * need des 16 */ 17 typedef union { 18 struct { 19 /** out_data : R/W/WTC; bitpos: [7:0]; default: 0; 20 * set lp gpio output data 21 */ 22 uint32_t out_data:8; 23 uint32_t reserved_8:24; 24 }; 25 uint32_t val; 26 } lp_io_out_data_reg_t; 27 28 /** Type of out_data_w1ts register 29 * need des 30 */ 31 typedef union { 32 struct { 33 /** out_data_w1ts : WT; bitpos: [7:0]; default: 0; 34 * set one time output data 35 */ 36 uint32_t out_data_w1ts:8; 37 uint32_t reserved_8:24; 38 }; 39 uint32_t val; 40 } lp_io_out_data_w1ts_reg_t; 41 42 /** Type of out_data_w1tc register 43 * need des 44 */ 45 typedef union { 46 struct { 47 /** out_data_w1tc : WT; bitpos: [7:0]; default: 0; 48 * clear one time output data 49 */ 50 uint32_t out_data_w1tc:8; 51 uint32_t reserved_8:24; 52 }; 53 uint32_t val; 54 } lp_io_out_data_w1tc_reg_t; 55 56 /** Type of out_enable register 57 * need des 58 */ 59 typedef union { 60 struct { 61 /** enable : R/W/WTC; bitpos: [7:0]; default: 0; 62 * set lp gpio output data 63 */ 64 uint32_t enable:8; 65 uint32_t reserved_8:24; 66 }; 67 uint32_t val; 68 } lp_io_out_enable_reg_t; 69 70 /** Type of out_enable_w1ts register 71 * need des 72 */ 73 typedef union { 74 struct { 75 /** enable_w1ts : WT; bitpos: [7:0]; default: 0; 76 * set one time output data 77 */ 78 uint32_t enable_w1ts:8; 79 uint32_t reserved_8:24; 80 }; 81 uint32_t val; 82 } lp_io_out_enable_w1ts_reg_t; 83 84 /** Type of out_enable_w1tc register 85 * need des 86 */ 87 typedef union { 88 struct { 89 /** enable_w1tc : WT; bitpos: [7:0]; default: 0; 90 * clear one time output data 91 */ 92 uint32_t enable_w1tc:8; 93 uint32_t reserved_8:24; 94 }; 95 uint32_t val; 96 } lp_io_out_enable_w1tc_reg_t; 97 98 /** Type of status register 99 * need des 100 */ 101 typedef union { 102 struct { 103 /** status_interrupt : R/W/WTC; bitpos: [7:0]; default: 0; 104 * set lp gpio output data 105 */ 106 uint32_t status_interrupt:8; 107 uint32_t reserved_8:24; 108 }; 109 uint32_t val; 110 } lp_io_status_reg_t; 111 112 /** Type of status_w1ts register 113 * need des 114 */ 115 typedef union { 116 struct { 117 /** status_w1ts : WT; bitpos: [7:0]; default: 0; 118 * set one time output data 119 */ 120 uint32_t status_w1ts:8; 121 uint32_t reserved_8:24; 122 }; 123 uint32_t val; 124 } lp_io_status_w1ts_reg_t; 125 126 /** Type of status_w1tc register 127 * need des 128 */ 129 typedef union { 130 struct { 131 /** status_w1tc : WT; bitpos: [7:0]; default: 0; 132 * clear one time output data 133 */ 134 uint32_t status_w1tc:8; 135 uint32_t reserved_8:24; 136 }; 137 uint32_t val; 138 } lp_io_status_w1tc_reg_t; 139 140 /** Type of in register 141 * need des 142 */ 143 typedef union { 144 struct { 145 /** in_data_next : RO; bitpos: [7:0]; default: 0; 146 * need des 147 */ 148 uint32_t in_data_next:8; 149 uint32_t reserved_8:24; 150 }; 151 uint32_t val; 152 } lp_io_in_reg_t; 153 154 /** Type of pin register 155 * need des 156 */ 157 typedef union { 158 struct { 159 /** sync_bypass : R/W; bitpos: [1:0]; default: 0; 160 * need des 161 */ 162 uint32_t sync_bypass:2; 163 /** pad_driver : R/W; bitpos: [2]; default: 0; 164 * need des 165 */ 166 uint32_t pad_driver:1; 167 /** edge_wakeup_clr : WT; bitpos: [3]; default: 0; 168 * need des 169 */ 170 uint32_t edge_wakeup_clr:1; 171 uint32_t reserved_4:3; 172 /** int_type : R/W; bitpos: [9:7]; default: 0; 173 * need des 174 */ 175 uint32_t int_type:3; 176 /** wakeup_enable : R/W; bitpos: [10]; default: 0; 177 * need des 178 */ 179 uint32_t wakeup_enable:1; 180 /** filter_en : R/W; bitpos: [11]; default: 0; 181 * need des 182 */ 183 uint32_t filter_en:1; 184 uint32_t reserved_12:20; 185 }; 186 uint32_t val; 187 } lp_io_pin_reg_t; 188 189 /** Type of gpio register 190 * need des 191 */ 192 typedef union { 193 struct { 194 /** mcu_oe : R/W; bitpos: [0]; default: 0; 195 * need des 196 */ 197 uint32_t mcu_oe:1; 198 /** slp_sel : R/W; bitpos: [1]; default: 0; 199 * need des 200 */ 201 uint32_t slp_sel:1; 202 /** mcu_wpd : R/W; bitpos: [2]; default: 0; 203 * need des 204 */ 205 uint32_t mcu_wpd:1; 206 /** mcu_wpu : R/W; bitpos: [3]; default: 0; 207 * need des 208 */ 209 uint32_t mcu_wpu:1; 210 /** mcu_ie : R/W; bitpos: [4]; default: 0; 211 * need des 212 */ 213 uint32_t mcu_ie:1; 214 /** mcu_drv : R/W; bitpos: [6:5]; default: 0; 215 * need des 216 */ 217 uint32_t mcu_drv:2; 218 /** fun_wpd : R/W; bitpos: [7]; default: 0; 219 * need des 220 */ 221 uint32_t fun_wpd:1; 222 /** fun_wpu : R/W; bitpos: [8]; default: 0; 223 * need des 224 */ 225 uint32_t fun_wpu:1; 226 /** fun_ie : R/W; bitpos: [9]; default: 0; 227 * need des 228 */ 229 uint32_t fun_ie:1; 230 /** fun_drv : R/W; bitpos: [11:10]; default: 0; 231 * need des 232 */ 233 uint32_t fun_drv:2; 234 /** mcu_sel : R/W; bitpos: [14:12]; default: 0; 235 * need des 236 */ 237 uint32_t mcu_sel:3; 238 uint32_t reserved_15:17; 239 }; 240 uint32_t val; 241 } lp_io_gpio_reg_t; 242 243 /** Type of status_interrupt register 244 * need des 245 */ 246 typedef union { 247 struct { 248 /** status_interrupt_next : RO; bitpos: [7:0]; default: 0; 249 * need des 250 */ 251 uint32_t status_interrupt_next:8; 252 uint32_t reserved_8:24; 253 }; 254 uint32_t val; 255 } lp_io_status_interrupt_reg_t; 256 257 /** Type of debug_sel0 register 258 * need des 259 */ 260 typedef union { 261 struct { 262 /** debug_sel0 : R/W; bitpos: [6:0]; default: 0; 263 * need des 264 */ 265 uint32_t debug_sel0:7; 266 /** debug_sel1 : R/W; bitpos: [13:7]; default: 0; 267 * need des 268 */ 269 uint32_t debug_sel1:7; 270 /** debug_sel2 : R/W; bitpos: [20:14]; default: 0; 271 * need des 272 */ 273 uint32_t debug_sel2:7; 274 /** debug_sel3 : R/W; bitpos: [27:21]; default: 0; 275 * need des 276 */ 277 uint32_t debug_sel3:7; 278 uint32_t reserved_28:4; 279 }; 280 uint32_t val; 281 } lp_io_debug_sel0_reg_t; 282 283 /** Type of debug_sel1 register 284 * need des 285 */ 286 typedef union { 287 struct { 288 /** debug_sel4 : R/W; bitpos: [6:0]; default: 0; 289 * need des 290 */ 291 uint32_t debug_sel4:7; 292 uint32_t reserved_7:25; 293 }; 294 uint32_t val; 295 } lp_io_debug_sel1_reg_t; 296 297 /** Type of lpi2c register 298 * need des 299 */ 300 typedef union { 301 struct { 302 uint32_t reserved_0:30; 303 /** lp_i2c_sda_ie : R/W; bitpos: [30]; default: 1; 304 * need des 305 */ 306 uint32_t lp_i2c_sda_ie:1; 307 /** lp_i2c_scl_ie : R/W; bitpos: [31]; default: 1; 308 * need des 309 */ 310 uint32_t lp_i2c_scl_ie:1; 311 }; 312 uint32_t val; 313 } lp_io_lpi2c_reg_t; 314 315 /** Type of date register 316 * need des 317 */ 318 typedef union { 319 struct { 320 /** lp_io_date : R/W; bitpos: [30:0]; default: 35660032; 321 * need des 322 */ 323 uint32_t lp_io_date:31; 324 /** clk_en : R/W; bitpos: [31]; default: 0; 325 * need des 326 */ 327 uint32_t clk_en:1; 328 }; 329 uint32_t val; 330 } lp_io_date_reg_t; 331 332 333 typedef struct lp_io_dev_t { 334 volatile lp_io_out_data_reg_t out_data; 335 volatile lp_io_out_data_w1ts_reg_t out_data_w1ts; 336 volatile lp_io_out_data_w1tc_reg_t out_data_w1tc; 337 volatile lp_io_out_enable_reg_t out_enable; 338 volatile lp_io_out_enable_w1ts_reg_t out_enable_w1ts; 339 volatile lp_io_out_enable_w1tc_reg_t out_enable_w1tc; 340 volatile lp_io_status_reg_t status; 341 volatile lp_io_status_w1ts_reg_t status_w1ts; 342 volatile lp_io_status_w1tc_reg_t status_w1tc; 343 volatile lp_io_in_reg_t in; 344 volatile lp_io_pin_reg_t pin[8]; 345 volatile lp_io_gpio_reg_t gpio[8]; 346 volatile lp_io_status_interrupt_reg_t status_interrupt; 347 volatile lp_io_debug_sel0_reg_t debug_sel0; 348 volatile lp_io_debug_sel1_reg_t debug_sel1; 349 volatile lp_io_lpi2c_reg_t lpi2c; 350 uint32_t reserved_078[225]; 351 volatile lp_io_date_reg_t date; 352 } lp_io_dev_t; 353 354 extern lp_io_dev_t LP_IO; 355 356 #ifndef __cplusplus 357 _Static_assert(sizeof(lp_io_dev_t) == 0x400, "Invalid size of lp_io_dev_t structure"); 358 #endif 359 360 #ifdef __cplusplus 361 } 362 #endif 363