1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 /* 8 * This file has been automatically generated 9 * Tool Version: 1.0.0 10 * Generation Date: 2023-08-01 11 */ 12 13 #ifndef _SEDI_I2C_REGS_H_ 14 #define _SEDI_I2C_REGS_H_ 15 16 #include <sedi_reg_defs.h> 17 18 19 /* ********* I2C CON *********** 20 * 21 * Register of SEDI I2C 22 * CON: I2C Control Register 23 * AddressOffset : 0x0 24 * AccessType : RW 25 * WritableBitMask: 0xfef 26 * ResetValue : (uint32_t)0x67 27 */ 28 SEDI_REG_DEFINE(I2C, CON, 0x0, RW, (uint32_t)0xfef, (uint32_t)0x67); 29 30 /* 31 * Bit Field of Register CON 32 * MASTER_MODE: 33 * BitOffset : 0 34 * BitWidth : 1 35 * AccessType: RW 36 * ResetValue: (uint32_t)0x1 37 */ 38 SEDI_RBF_DEFINE(I2C, CON, MASTER_MODE, 0, 1, RW, (uint32_t)0x1); 39 SEDI_RBFV_DEFINE(I2C, CON, MASTER_MODE, DISABLED, 0x0); 40 SEDI_RBFV_DEFINE(I2C, CON, MASTER_MODE, ENABLED, 0x1); 41 42 /* 43 * Bit Field of Register CON 44 * SPEED: 45 * BitOffset : 1 46 * BitWidth : 2 47 * AccessType: RW 48 * ResetValue: (uint32_t)0x3 49 */ 50 SEDI_RBF_DEFINE(I2C, CON, SPEED, 1, 2, RW, (uint32_t)0x3); 51 SEDI_RBFV_DEFINE(I2C, CON, SPEED, FAST, 0x2); 52 SEDI_RBFV_DEFINE(I2C, CON, SPEED, HIGH, 0x3); 53 SEDI_RBFV_DEFINE(I2C, CON, SPEED, STANDARD, 0x1); 54 55 /* 56 * Bit Field of Register CON 57 * IC_10BITADDR_SLAVE: 58 * BitOffset : 3 59 * BitWidth : 1 60 * AccessType: RW 61 * ResetValue: (uint32_t)0x0 62 */ 63 SEDI_RBF_DEFINE(I2C, CON, IC_10BITADDR_SLAVE, 3, 1, RW, (uint32_t)0x0); 64 SEDI_RBFV_DEFINE(I2C, CON, IC_10BITADDR_SLAVE, ADDR_10BITS, 0x1); 65 SEDI_RBFV_DEFINE(I2C, CON, IC_10BITADDR_SLAVE, ADDR_7BITS, 0x0); 66 67 /* 68 * Bit Field of Register CON 69 * IC_10BITADDR_MASTER_rd_only: 70 * BitOffset : 4 71 * BitWidth : 1 72 * AccessType: RO 73 * ResetValue: (uint32_t)0x0 74 */ 75 SEDI_RBF_DEFINE(I2C, CON, IC_10BITADDR_MASTER_rd_only, 4, 1, RO, (uint32_t)0x0); 76 SEDI_RBFV_DEFINE(I2C, CON, IC_10BITADDR_MASTER_rd_only, ADDR_10BITS, 0x1); 77 SEDI_RBFV_DEFINE(I2C, CON, IC_10BITADDR_MASTER_rd_only, ADDR_7BITS, 0x0); 78 79 /* 80 * Bit Field of Register CON 81 * IC_RESTART_EN: 82 * BitOffset : 5 83 * BitWidth : 1 84 * AccessType: RW 85 * ResetValue: (uint32_t)0x1 86 */ 87 SEDI_RBF_DEFINE(I2C, CON, IC_RESTART_EN, 5, 1, RW, (uint32_t)0x1); 88 SEDI_RBFV_DEFINE(I2C, CON, IC_RESTART_EN, DISABLED, 0x0); 89 SEDI_RBFV_DEFINE(I2C, CON, IC_RESTART_EN, ENABLED, 0x1); 90 91 /* 92 * Bit Field of Register CON 93 * IC_SLAVE_DISABLE: 94 * BitOffset : 6 95 * BitWidth : 1 96 * AccessType: RW 97 * ResetValue: (uint32_t)0x1 98 */ 99 SEDI_RBF_DEFINE(I2C, CON, IC_SLAVE_DISABLE, 6, 1, RW, (uint32_t)0x1); 100 SEDI_RBFV_DEFINE(I2C, CON, IC_SLAVE_DISABLE, SLAVE_DISABLED, 0x1); 101 SEDI_RBFV_DEFINE(I2C, CON, IC_SLAVE_DISABLE, SLAVE_ENABLED, 0x0); 102 103 /* 104 * Bit Field of Register CON 105 * STOP_DET_IFADDRESSED: 106 * BitOffset : 7 107 * BitWidth : 1 108 * AccessType: RW 109 * ResetValue: (uint32_t)0x0 110 */ 111 SEDI_RBF_DEFINE(I2C, CON, STOP_DET_IFADDRESSED, 7, 1, RW, (uint32_t)0x0); 112 SEDI_RBFV_DEFINE(I2C, CON, STOP_DET_IFADDRESSED, DISABLED, 0x0); 113 SEDI_RBFV_DEFINE(I2C, CON, STOP_DET_IFADDRESSED, ENABLED, 0x1); 114 115 /* 116 * Bit Field of Register CON 117 * TX_EMPTY_CTRL: 118 * BitOffset : 8 119 * BitWidth : 1 120 * AccessType: RW 121 * ResetValue: (uint32_t)0x0 122 */ 123 SEDI_RBF_DEFINE(I2C, CON, TX_EMPTY_CTRL, 8, 1, RW, (uint32_t)0x0); 124 SEDI_RBFV_DEFINE(I2C, CON, TX_EMPTY_CTRL, DISABLED, 0x0); 125 SEDI_RBFV_DEFINE(I2C, CON, TX_EMPTY_CTRL, ENABLED, 0x1); 126 127 /* 128 * Bit Field of Register CON 129 * RX_FIFO_FULL_HLD_CTRL: 130 * BitOffset : 9 131 * BitWidth : 1 132 * AccessType: RW 133 * ResetValue: (uint32_t)0x0 134 */ 135 SEDI_RBF_DEFINE(I2C, CON, RX_FIFO_FULL_HLD_CTRL, 9, 1, RW, (uint32_t)0x0); 136 SEDI_RBFV_DEFINE(I2C, CON, RX_FIFO_FULL_HLD_CTRL, DISABLED, 0x0); 137 SEDI_RBFV_DEFINE(I2C, CON, RX_FIFO_FULL_HLD_CTRL, ENABLED, 0x1); 138 139 /* 140 * Bit Field of Register CON 141 * STOP_DET_IF_MASTER_ACTIVE: 142 * BitOffset : 10 143 * BitWidth : 1 144 * AccessType: RW 145 * ResetValue: (uint32_t)0x0 146 */ 147 SEDI_RBF_DEFINE(I2C, CON, STOP_DET_IF_MASTER_ACTIVE, 10, 1, RW, (uint32_t)0x0); 148 SEDI_RBFV_DEFINE(I2C, CON, STOP_DET_IF_MASTER_ACTIVE, DISABLED, 0x0); 149 SEDI_RBFV_DEFINE(I2C, CON, STOP_DET_IF_MASTER_ACTIVE, ENABLED, 0x1); 150 151 /* 152 * Bit Field of Register CON 153 * BUS_CLEAR_FEATURE_CTRL: 154 * BitOffset : 11 155 * BitWidth : 1 156 * AccessType: RW 157 * ResetValue: (uint32_t)0x0 158 */ 159 SEDI_RBF_DEFINE(I2C, CON, BUS_CLEAR_FEATURE_CTRL, 11, 1, RW, (uint32_t)0x0); 160 SEDI_RBFV_DEFINE(I2C, CON, BUS_CLEAR_FEATURE_CTRL, DISABLED, 0x0); 161 SEDI_RBFV_DEFINE(I2C, CON, BUS_CLEAR_FEATURE_CTRL, ENABLED, 0x1); 162 163 /* 164 * Bit Field of Register CON 165 * RSVD_IC_CON_1: 166 * BitOffset : 12 167 * BitWidth : 4 168 * AccessType: RO 169 * ResetValue: (uint32_t)0x0 170 */ 171 SEDI_RBF_DEFINE(I2C, CON, RSVD_IC_CON_1, 12, 4, RO, (uint32_t)0x0); 172 173 /* 174 * Bit Field of Register CON 175 * RSVD_OPTIONAL_SAR_CTRL: 176 * BitOffset : 16 177 * BitWidth : 1 178 * AccessType: RO 179 * ResetValue: (uint32_t)0x0 180 */ 181 SEDI_RBF_DEFINE(I2C, CON, RSVD_OPTIONAL_SAR_CTRL, 16, 1, RO, (uint32_t)0x0); 182 SEDI_RBFV_DEFINE(I2C, CON, RSVD_OPTIONAL_SAR_CTRL, 0, 0); 183 SEDI_RBFV_DEFINE(I2C, CON, RSVD_OPTIONAL_SAR_CTRL, 1, 1); 184 185 /* 186 * Bit Field of Register CON 187 * RSVD_SMBUS_SLAVE_QUICK_EN: 188 * BitOffset : 17 189 * BitWidth : 1 190 * AccessType: RO 191 * ResetValue: (uint32_t)0x0 192 */ 193 SEDI_RBF_DEFINE(I2C, CON, RSVD_SMBUS_SLAVE_QUICK_EN, 17, 1, RO, (uint32_t)0x0); 194 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_SLAVE_QUICK_EN, 0, 0); 195 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_SLAVE_QUICK_EN, 1, 1); 196 197 /* 198 * Bit Field of Register CON 199 * RSVD_SMBUS_ARP_EN: 200 * BitOffset : 18 201 * BitWidth : 1 202 * AccessType: RO 203 * ResetValue: (uint32_t)0x0 204 */ 205 SEDI_RBF_DEFINE(I2C, CON, RSVD_SMBUS_ARP_EN, 18, 1, RO, (uint32_t)0x0); 206 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_ARP_EN, 0, 0); 207 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_ARP_EN, 1, 1); 208 209 /* 210 * Bit Field of Register CON 211 * RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN: 212 * BitOffset : 19 213 * BitWidth : 1 214 * AccessType: RO 215 * ResetValue: (uint32_t)0x0 216 */ 217 SEDI_RBF_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN, 19, 1, RO, (uint32_t)0x0); 218 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN, 0, 0); 219 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR_EN, 1, 1); 220 221 /* 222 * Bit Field of Register CON 223 * RSVD_SMBUS_PERSISTENT_SLV_ADDR2_EN: 224 * BitOffset : 20 225 * BitWidth : 1 226 * AccessType: RO 227 * ResetValue: (uint32_t)0x0 228 */ 229 SEDI_RBF_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR2_EN, 20, 1, RO, (uint32_t)0x0); 230 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR2_EN, 0, 0); 231 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR2_EN, 1, 1); 232 233 /* 234 * Bit Field of Register CON 235 * RSVD_SMBUS_PERSISTENT_SLV_ADDR3_EN: 236 * BitOffset : 21 237 * BitWidth : 1 238 * AccessType: RO 239 * ResetValue: (uint32_t)0x0 240 */ 241 SEDI_RBF_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR3_EN, 21, 1, RO, (uint32_t)0x0); 242 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR3_EN, 0, 0); 243 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR3_EN, 1, 1); 244 245 /* 246 * Bit Field of Register CON 247 * RSVD_SMBUS_PERSISTENT_SLV_ADDR4_EN: 248 * BitOffset : 22 249 * BitWidth : 1 250 * AccessType: RO 251 * ResetValue: (uint32_t)0x0 252 */ 253 SEDI_RBF_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR4_EN, 22, 1, RO, (uint32_t)0x0); 254 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR4_EN, 0, 0); 255 SEDI_RBFV_DEFINE(I2C, CON, RSVD_SMBUS_PERSISTENT_SLV_ADDR4_EN, 1, 1); 256 257 /* 258 * Bit Field of Register CON 259 * RSVD_IC_SAR2_SMBUS_ARP_EN: 260 * BitOffset : 23 261 * BitWidth : 1 262 * AccessType: RO 263 * ResetValue: (uint32_t)0x0 264 */ 265 SEDI_RBF_DEFINE(I2C, CON, RSVD_IC_SAR2_SMBUS_ARP_EN, 23, 1, RO, (uint32_t)0x0); 266 SEDI_RBFV_DEFINE(I2C, CON, RSVD_IC_SAR2_SMBUS_ARP_EN, 0, 0); 267 SEDI_RBFV_DEFINE(I2C, CON, RSVD_IC_SAR2_SMBUS_ARP_EN, 1, 1); 268 269 /* 270 * Bit Field of Register CON 271 * RSVD_IC_SAR3_SMBUS_ARP_EN: 272 * BitOffset : 24 273 * BitWidth : 1 274 * AccessType: RO 275 * ResetValue: (uint32_t)0x0 276 */ 277 SEDI_RBF_DEFINE(I2C, CON, RSVD_IC_SAR3_SMBUS_ARP_EN, 24, 1, RO, (uint32_t)0x0); 278 SEDI_RBFV_DEFINE(I2C, CON, RSVD_IC_SAR3_SMBUS_ARP_EN, 0, 0); 279 SEDI_RBFV_DEFINE(I2C, CON, RSVD_IC_SAR3_SMBUS_ARP_EN, 1, 1); 280 281 /* 282 * Bit Field of Register CON 283 * RSVD_IC_SAR4_SMBUS_ARP_EN: 284 * BitOffset : 25 285 * BitWidth : 1 286 * AccessType: RO 287 * ResetValue: (uint32_t)0x0 288 */ 289 SEDI_RBF_DEFINE(I2C, CON, RSVD_IC_SAR4_SMBUS_ARP_EN, 25, 1, RO, (uint32_t)0x0); 290 SEDI_RBFV_DEFINE(I2C, CON, RSVD_IC_SAR4_SMBUS_ARP_EN, 0, 0); 291 SEDI_RBFV_DEFINE(I2C, CON, RSVD_IC_SAR4_SMBUS_ARP_EN, 1, 1); 292 293 /* 294 * Bit Field of Register CON 295 * RSVD_IC_CON_2: 296 * BitOffset : 26 297 * BitWidth : 6 298 * AccessType: RO 299 * ResetValue: (uint32_t)0x0 300 */ 301 SEDI_RBF_DEFINE(I2C, CON, RSVD_IC_CON_2, 26, 6, RO, (uint32_t)0x0); 302 303 /* ********* I2C TAR *********** 304 * 305 * Register of SEDI I2C 306 * TAR: I2C Target Address Register 307 * AddressOffset : 0x4 308 * AccessType : RW 309 * WritableBitMask: 0x1fff 310 * ResetValue : (uint32_t)0x55 311 */ 312 SEDI_REG_DEFINE(I2C, TAR, 0x4, RW, (uint32_t)0x1fff, (uint32_t)0x55); 313 314 /* 315 * Bit Field of Register TAR 316 * IC_TAR: 317 * BitOffset : 0 318 * BitWidth : 10 319 * AccessType: RW 320 * ResetValue: (uint32_t)0x55 321 */ 322 SEDI_RBF_DEFINE(I2C, TAR, IC_TAR, 0, 10, RW, (uint32_t)0x55); 323 324 /* 325 * Bit Field of Register TAR 326 * GC_OR_START: 327 * BitOffset : 10 328 * BitWidth : 1 329 * AccessType: RW 330 * ResetValue: (uint32_t)0x0 331 */ 332 SEDI_RBF_DEFINE(I2C, TAR, GC_OR_START, 10, 1, RW, (uint32_t)0x0); 333 SEDI_RBFV_DEFINE(I2C, TAR, GC_OR_START, GENERAL_CALL, 0x0); 334 SEDI_RBFV_DEFINE(I2C, TAR, GC_OR_START, START_BYTE, 0x1); 335 336 /* 337 * Bit Field of Register TAR 338 * SPECIAL: 339 * BitOffset : 11 340 * BitWidth : 1 341 * AccessType: RW 342 * ResetValue: (uint32_t)0x0 343 */ 344 SEDI_RBF_DEFINE(I2C, TAR, SPECIAL, 11, 1, RW, (uint32_t)0x0); 345 SEDI_RBFV_DEFINE(I2C, TAR, SPECIAL, DISABLED, 0x0); 346 SEDI_RBFV_DEFINE(I2C, TAR, SPECIAL, ENABLED, 0x1); 347 348 /* 349 * Bit Field of Register TAR 350 * IC_10BITADDR_MASTER: 351 * BitOffset : 12 352 * BitWidth : 1 353 * AccessType: RW 354 * ResetValue: (uint32_t)0x0 355 */ 356 SEDI_RBF_DEFINE(I2C, TAR, IC_10BITADDR_MASTER, 12, 1, RW, (uint32_t)0x0); 357 SEDI_RBFV_DEFINE(I2C, TAR, IC_10BITADDR_MASTER, ADDR_10BITS, 0x1); 358 SEDI_RBFV_DEFINE(I2C, TAR, IC_10BITADDR_MASTER, ADDR_7BITS, 0x0); 359 360 /* 361 * Bit Field of Register TAR 362 * RSVD_DEVICE_ID: 363 * BitOffset : 13 364 * BitWidth : 1 365 * AccessType: RO 366 * ResetValue: (uint32_t)0x0 367 */ 368 SEDI_RBF_DEFINE(I2C, TAR, RSVD_DEVICE_ID, 13, 1, RO, (uint32_t)0x0); 369 SEDI_RBFV_DEFINE(I2C, TAR, RSVD_DEVICE_ID, 0, 0); 370 SEDI_RBFV_DEFINE(I2C, TAR, RSVD_DEVICE_ID, 1, 1); 371 372 /* 373 * Bit Field of Register TAR 374 * RSVD_IC_TAR_1: 375 * BitOffset : 14 376 * BitWidth : 2 377 * AccessType: RO 378 * ResetValue: (uint32_t)0x0 379 */ 380 SEDI_RBF_DEFINE(I2C, TAR, RSVD_IC_TAR_1, 14, 2, RO, (uint32_t)0x0); 381 382 /* 383 * Bit Field of Register TAR 384 * RSVD_SMBUS_QUICK_CMD: 385 * BitOffset : 16 386 * BitWidth : 1 387 * AccessType: RO 388 * ResetValue: (uint32_t)0x0 389 */ 390 SEDI_RBF_DEFINE(I2C, TAR, RSVD_SMBUS_QUICK_CMD, 16, 1, RO, (uint32_t)0x0); 391 SEDI_RBFV_DEFINE(I2C, TAR, RSVD_SMBUS_QUICK_CMD, 0, 0); 392 SEDI_RBFV_DEFINE(I2C, TAR, RSVD_SMBUS_QUICK_CMD, 1, 1); 393 394 /* 395 * Bit Field of Register TAR 396 * RSVD_IC_TAR_2: 397 * BitOffset : 17 398 * BitWidth : 15 399 * AccessType: RO 400 * ResetValue: (uint32_t)0x0 401 */ 402 SEDI_RBF_DEFINE(I2C, TAR, RSVD_IC_TAR_2, 17, 15, RO, (uint32_t)0x0); 403 404 /* ********* I2C SAR *********** 405 * 406 * Register of SEDI I2C 407 * SAR: I2C Slave Address Register 408 * AddressOffset : 0x8 409 * AccessType : RW 410 * WritableBitMask: 0x3ff 411 * ResetValue : (uint32_t)0x55 412 */ 413 SEDI_REG_DEFINE(I2C, SAR, 0x8, RW, (uint32_t)0x3ff, (uint32_t)0x55); 414 415 /* 416 * Bit Field of Register SAR 417 * IC_SAR: 418 * BitOffset : 0 419 * BitWidth : 10 420 * AccessType: RW 421 * ResetValue: (uint32_t)0x55 422 */ 423 SEDI_RBF_DEFINE(I2C, SAR, IC_SAR, 0, 10, RW, (uint32_t)0x55); 424 425 /* 426 * Bit Field of Register SAR 427 * RSVD_IC_SAR: 428 * BitOffset : 10 429 * BitWidth : 22 430 * AccessType: RO 431 * ResetValue: (uint32_t)0x0 432 */ 433 SEDI_RBF_DEFINE(I2C, SAR, RSVD_IC_SAR, 10, 22, RO, (uint32_t)0x0); 434 435 /* ********* I2C HS_MADDR *********** 436 * 437 * Register of SEDI I2C 438 * HS_MADDR: I2C High Speed Master Mode Code Address Register 439 * AddressOffset : 0xc 440 * AccessType : RW 441 * WritableBitMask: 0x7 442 * ResetValue : (uint32_t)0x1 443 */ 444 SEDI_REG_DEFINE(I2C, HS_MADDR, 0xc, RW, (uint32_t)0x7, (uint32_t)0x1); 445 446 /* 447 * Bit Field of Register HS_MADDR 448 * IC_HS_MAR: 449 * BitOffset : 0 450 * BitWidth : 3 451 * AccessType: RW 452 * ResetValue: (uint32_t)0x1 453 */ 454 SEDI_RBF_DEFINE(I2C, HS_MADDR, IC_HS_MAR, 0, 3, RW, (uint32_t)0x1); 455 456 /* 457 * Bit Field of Register HS_MADDR 458 * RSVD_IC_HS_MAR: 459 * BitOffset : 3 460 * BitWidth : 29 461 * AccessType: RO 462 * ResetValue: (uint32_t)0x0 463 */ 464 SEDI_RBF_DEFINE(I2C, HS_MADDR, RSVD_IC_HS_MAR, 3, 29, RO, (uint32_t)0x0); 465 466 /* ********* I2C DATA_CMD *********** 467 * 468 * Register of SEDI I2C 469 * DATA_CMD: I2C Rx/Tx Data Buffer and Command Register 470 * AddressOffset : 0x10 471 * AccessType : RW 472 * WritableBitMask: 0x7ff 473 * ResetValue : (uint32_t)0x0 474 */ 475 SEDI_REG_DEFINE(I2C, DATA_CMD, 0x10, RW, (uint32_t)0x7ff, (uint32_t)0x0); 476 477 /* 478 * Bit Field of Register DATA_CMD 479 * DAT: 480 * BitOffset : 0 481 * BitWidth : 8 482 * AccessType: RW 483 * ResetValue: (uint32_t)0x0 484 */ 485 SEDI_RBF_DEFINE(I2C, DATA_CMD, DAT, 0, 8, RW, (uint32_t)0x0); 486 487 /* 488 * Bit Field of Register DATA_CMD 489 * CMD: 490 * BitOffset : 8 491 * BitWidth : 1 492 * AccessType: RW 493 * ResetValue: (uint32_t)0x0 494 */ 495 SEDI_RBF_DEFINE(I2C, DATA_CMD, CMD, 8, 1, RW, (uint32_t)0x0); 496 SEDI_RBFV_DEFINE(I2C, DATA_CMD, CMD, READ, 0x1); 497 SEDI_RBFV_DEFINE(I2C, DATA_CMD, CMD, WRITE, 0x0); 498 499 /* 500 * Bit Field of Register DATA_CMD 501 * STOP: 502 * BitOffset : 9 503 * BitWidth : 1 504 * AccessType: RW 505 * ResetValue: (uint32_t)0x0 506 */ 507 SEDI_RBF_DEFINE(I2C, DATA_CMD, STOP, 9, 1, RW, (uint32_t)0x0); 508 SEDI_RBFV_DEFINE(I2C, DATA_CMD, STOP, DISABLE, 0x0); 509 SEDI_RBFV_DEFINE(I2C, DATA_CMD, STOP, ENABLE, 0x1); 510 511 /* 512 * Bit Field of Register DATA_CMD 513 * RESTART: 514 * BitOffset : 10 515 * BitWidth : 1 516 * AccessType: RW 517 * ResetValue: (uint32_t)0x0 518 */ 519 SEDI_RBF_DEFINE(I2C, DATA_CMD, RESTART, 10, 1, RW, (uint32_t)0x0); 520 SEDI_RBFV_DEFINE(I2C, DATA_CMD, RESTART, DISABLE, 0x0); 521 SEDI_RBFV_DEFINE(I2C, DATA_CMD, RESTART, ENABLE, 0x1); 522 523 /* 524 * Bit Field of Register DATA_CMD 525 * FIRST_DATA_BYTE: 526 * BitOffset : 11 527 * BitWidth : 1 528 * AccessType: RO 529 * ResetValue: (uint32_t)0x0 530 */ 531 SEDI_RBF_DEFINE(I2C, DATA_CMD, FIRST_DATA_BYTE, 11, 1, RO, (uint32_t)0x0); 532 SEDI_RBFV_DEFINE(I2C, DATA_CMD, FIRST_DATA_BYTE, ACTIVE, 0x1); 533 SEDI_RBFV_DEFINE(I2C, DATA_CMD, FIRST_DATA_BYTE, INACTIVE, 0x0); 534 535 /* 536 * Bit Field of Register DATA_CMD 537 * RSVD_IC_DATA_CMD: 538 * BitOffset : 12 539 * BitWidth : 20 540 * AccessType: RO 541 * ResetValue: (uint32_t)0x0 542 */ 543 SEDI_RBF_DEFINE(I2C, DATA_CMD, RSVD_IC_DATA_CMD, 12, 20, RO, (uint32_t)0x0); 544 545 /* ********* I2C SS_SCL_HCNT *********** 546 * 547 * Register of SEDI I2C 548 * SS_SCL_HCNT: Standard Speed I2C Clock SCL High Count Register 549 * AddressOffset : 0x14 550 * AccessType : RW 551 * WritableBitMask: 0xffff 552 * ResetValue : (uint32_t)0x1e8 553 */ 554 SEDI_REG_DEFINE(I2C, SS_SCL_HCNT, 0x14, RW, (uint32_t)0xffff, (uint32_t)0x1e8); 555 556 /* 557 * Bit Field of Register SS_SCL_HCNT 558 * IC_SS_SCL_HCNT: 559 * BitOffset : 0 560 * BitWidth : 16 561 * AccessType: RW 562 * ResetValue: (uint32_t)0x1e8 563 */ 564 SEDI_RBF_DEFINE(I2C, SS_SCL_HCNT, IC_SS_SCL_HCNT, 0, 16, RW, (uint32_t)0x1e8); 565 566 /* 567 * Bit Field of Register SS_SCL_HCNT 568 * RSVD_IC_SS_SCL_HIGH_COUNT: 569 * BitOffset : 16 570 * BitWidth : 16 571 * AccessType: RO 572 * ResetValue: (uint32_t)0x0 573 */ 574 SEDI_RBF_DEFINE(I2C, SS_SCL_HCNT, RSVD_IC_SS_SCL_HIGH_COUNT, 16, 16, RO, (uint32_t)0x0); 575 576 /* ********* I2C SS_SCL_LCNT *********** 577 * 578 * Register of SEDI I2C 579 * SS_SCL_LCNT: Standard Speed I2C Clock SCL Low Count Register 580 * AddressOffset : 0x18 581 * AccessType : RW 582 * WritableBitMask: 0xffff 583 * ResetValue : (uint32_t)0x1f3 584 */ 585 SEDI_REG_DEFINE(I2C, SS_SCL_LCNT, 0x18, RW, (uint32_t)0xffff, (uint32_t)0x1f3); 586 587 /* 588 * Bit Field of Register SS_SCL_LCNT 589 * IC_SS_SCL_LCNT: 590 * BitOffset : 0 591 * BitWidth : 16 592 * AccessType: RW 593 * ResetValue: (uint32_t)0x1f3 594 */ 595 SEDI_RBF_DEFINE(I2C, SS_SCL_LCNT, IC_SS_SCL_LCNT, 0, 16, RW, (uint32_t)0x1f3); 596 597 /* 598 * Bit Field of Register SS_SCL_LCNT 599 * RSVD_IC_SS_SCL_LOW_COUNT: 600 * BitOffset : 16 601 * BitWidth : 16 602 * AccessType: RO 603 * ResetValue: (uint32_t)0x0 604 */ 605 SEDI_RBF_DEFINE(I2C, SS_SCL_LCNT, RSVD_IC_SS_SCL_LOW_COUNT, 16, 16, RO, (uint32_t)0x0); 606 607 /* ********* I2C FS_SCL_HCNT *********** 608 * 609 * Register of SEDI I2C 610 * FS_SCL_HCNT: Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register 611 * AddressOffset : 0x1c 612 * AccessType : RW 613 * WritableBitMask: 0xffff 614 * ResetValue : (uint32_t)0x71 615 */ 616 SEDI_REG_DEFINE(I2C, FS_SCL_HCNT, 0x1c, RW, (uint32_t)0xffff, (uint32_t)0x71); 617 618 /* 619 * Bit Field of Register FS_SCL_HCNT 620 * IC_FS_SCL_HCNT: 621 * BitOffset : 0 622 * BitWidth : 16 623 * AccessType: RW 624 * ResetValue: (uint32_t)0x71 625 */ 626 SEDI_RBF_DEFINE(I2C, FS_SCL_HCNT, IC_FS_SCL_HCNT, 0, 16, RW, (uint32_t)0x71); 627 628 /* 629 * Bit Field of Register FS_SCL_HCNT 630 * RSVD_IC_FS_SCL_HCNT: 631 * BitOffset : 16 632 * BitWidth : 16 633 * AccessType: RO 634 * ResetValue: (uint32_t)0x0 635 */ 636 SEDI_RBF_DEFINE(I2C, FS_SCL_HCNT, RSVD_IC_FS_SCL_HCNT, 16, 16, RO, (uint32_t)0x0); 637 638 /* ********* I2C FS_SCL_LCNT *********** 639 * 640 * Register of SEDI I2C 641 * FS_SCL_LCNT: Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register 642 * AddressOffset : 0x20 643 * AccessType : RW 644 * WritableBitMask: 0xffff 645 * ResetValue : (uint32_t)0x7c 646 */ 647 SEDI_REG_DEFINE(I2C, FS_SCL_LCNT, 0x20, RW, (uint32_t)0xffff, (uint32_t)0x7c); 648 649 /* 650 * Bit Field of Register FS_SCL_LCNT 651 * IC_FS_SCL_LCNT: 652 * BitOffset : 0 653 * BitWidth : 16 654 * AccessType: RW 655 * ResetValue: (uint32_t)0x7c 656 */ 657 SEDI_RBF_DEFINE(I2C, FS_SCL_LCNT, IC_FS_SCL_LCNT, 0, 16, RW, (uint32_t)0x7c); 658 659 /* 660 * Bit Field of Register FS_SCL_LCNT 661 * RSVD_IC_FS_SCL_LCNT: 662 * BitOffset : 16 663 * BitWidth : 16 664 * AccessType: RO 665 * ResetValue: (uint32_t)0x0 666 */ 667 SEDI_RBF_DEFINE(I2C, FS_SCL_LCNT, RSVD_IC_FS_SCL_LCNT, 16, 16, RO, (uint32_t)0x0); 668 669 /* ********* I2C HS_SCL_HCNT *********** 670 * 671 * Register of SEDI I2C 672 * HS_SCL_HCNT: High Speed I2C Clock SCL High Count Register 673 * AddressOffset : 0x24 674 * AccessType : RW 675 * WritableBitMask: 0xffff 676 * ResetValue : (uint32_t)0x29 677 */ 678 SEDI_REG_DEFINE(I2C, HS_SCL_HCNT, 0x24, RW, (uint32_t)0xffff, (uint32_t)0x29); 679 680 /* 681 * Bit Field of Register HS_SCL_HCNT 682 * IC_HS_SCL_HCNT: 683 * BitOffset : 0 684 * BitWidth : 16 685 * AccessType: RW 686 * ResetValue: (uint32_t)0x29 687 */ 688 SEDI_RBF_DEFINE(I2C, HS_SCL_HCNT, IC_HS_SCL_HCNT, 0, 16, RW, (uint32_t)0x29); 689 690 /* 691 * Bit Field of Register HS_SCL_HCNT 692 * RSVD_IC_HS_SCL_HCNT: 693 * BitOffset : 16 694 * BitWidth : 16 695 * AccessType: RO 696 * ResetValue: (uint32_t)0x0 697 */ 698 SEDI_RBF_DEFINE(I2C, HS_SCL_HCNT, RSVD_IC_HS_SCL_HCNT, 16, 16, RO, (uint32_t)0x0); 699 700 /* ********* I2C HS_SCL_LCNT *********** 701 * 702 * Register of SEDI I2C 703 * HS_SCL_LCNT: High Speed I2C Clock SCL Low Count Register 704 * AddressOffset : 0x28 705 * AccessType : RW 706 * WritableBitMask: 0xffff 707 * ResetValue : (uint32_t)0x32 708 */ 709 SEDI_REG_DEFINE(I2C, HS_SCL_LCNT, 0x28, RW, (uint32_t)0xffff, (uint32_t)0x32); 710 711 /* 712 * Bit Field of Register HS_SCL_LCNT 713 * IC_HS_SCL_LCNT: 714 * BitOffset : 0 715 * BitWidth : 16 716 * AccessType: RW 717 * ResetValue: (uint32_t)0x32 718 */ 719 SEDI_RBF_DEFINE(I2C, HS_SCL_LCNT, IC_HS_SCL_LCNT, 0, 16, RW, (uint32_t)0x32); 720 721 /* 722 * Bit Field of Register HS_SCL_LCNT 723 * RSVD_IC_HS_SCL_LOW_CNT: 724 * BitOffset : 16 725 * BitWidth : 16 726 * AccessType: RO 727 * ResetValue: (uint32_t)0x0 728 */ 729 SEDI_RBF_DEFINE(I2C, HS_SCL_LCNT, RSVD_IC_HS_SCL_LOW_CNT, 16, 16, RO, (uint32_t)0x0); 730 731 /* ********* I2C INTR_STAT *********** 732 * 733 * Register of SEDI I2C 734 * INTR_STAT: I2C Interrupt Status Register 735 * AddressOffset : 0x2c 736 * AccessType : RO 737 * WritableBitMask: 0x0 738 * ResetValue : (uint32_t)0x0 739 */ 740 SEDI_REG_DEFINE(I2C, INTR_STAT, 0x2c, RO, (uint32_t)0x0, (uint32_t)0x0); 741 742 /* 743 * Bit Field of Register INTR_STAT 744 * R_RX_UNDER: 745 * BitOffset : 0 746 * BitWidth : 1 747 * AccessType: RO 748 * ResetValue: (uint32_t)0x0 749 */ 750 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_RX_UNDER, 0, 1, RO, (uint32_t)0x0); 751 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_UNDER, ACTIVE, 0x1); 752 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_UNDER, INACTIVE, 0x0); 753 754 /* 755 * Bit Field of Register INTR_STAT 756 * R_RX_OVER: 757 * BitOffset : 1 758 * BitWidth : 1 759 * AccessType: RO 760 * ResetValue: (uint32_t)0x0 761 */ 762 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_RX_OVER, 1, 1, RO, (uint32_t)0x0); 763 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_OVER, ACTIVE, 0x1); 764 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_OVER, INACTIVE, 0x0); 765 766 /* 767 * Bit Field of Register INTR_STAT 768 * R_RX_FULL: 769 * BitOffset : 2 770 * BitWidth : 1 771 * AccessType: RO 772 * ResetValue: (uint32_t)0x0 773 */ 774 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_RX_FULL, 2, 1, RO, (uint32_t)0x0); 775 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_FULL, ACTIVE, 0x1); 776 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_FULL, INACTIVE, 0x0); 777 778 /* 779 * Bit Field of Register INTR_STAT 780 * R_TX_OVER: 781 * BitOffset : 3 782 * BitWidth : 1 783 * AccessType: RO 784 * ResetValue: (uint32_t)0x0 785 */ 786 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_TX_OVER, 3, 1, RO, (uint32_t)0x0); 787 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_TX_OVER, ACTIVE, 0x1); 788 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_TX_OVER, INACTIVE, 0x0); 789 790 /* 791 * Bit Field of Register INTR_STAT 792 * R_TX_EMPTY: 793 * BitOffset : 4 794 * BitWidth : 1 795 * AccessType: RO 796 * ResetValue: (uint32_t)0x0 797 */ 798 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_TX_EMPTY, 4, 1, RO, (uint32_t)0x0); 799 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_TX_EMPTY, ACTIVE, 0x1); 800 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_TX_EMPTY, INACTIVE, 0x0); 801 802 /* 803 * Bit Field of Register INTR_STAT 804 * R_RD_REQ: 805 * BitOffset : 5 806 * BitWidth : 1 807 * AccessType: RO 808 * ResetValue: (uint32_t)0x0 809 */ 810 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_RD_REQ, 5, 1, RO, (uint32_t)0x0); 811 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RD_REQ, ACTIVE, 0x1); 812 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RD_REQ, INACTIVE, 0x0); 813 814 /* 815 * Bit Field of Register INTR_STAT 816 * R_TX_ABRT: 817 * BitOffset : 6 818 * BitWidth : 1 819 * AccessType: RO 820 * ResetValue: (uint32_t)0x0 821 */ 822 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_TX_ABRT, 6, 1, RO, (uint32_t)0x0); 823 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_TX_ABRT, ACTIVE, 0x1); 824 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_TX_ABRT, INACTIVE, 0x0); 825 826 /* 827 * Bit Field of Register INTR_STAT 828 * R_RX_DONE: 829 * BitOffset : 7 830 * BitWidth : 1 831 * AccessType: RO 832 * ResetValue: (uint32_t)0x0 833 */ 834 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_RX_DONE, 7, 1, RO, (uint32_t)0x0); 835 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_DONE, ACTIVE, 0x1); 836 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RX_DONE, INACTIVE, 0x0); 837 838 /* 839 * Bit Field of Register INTR_STAT 840 * R_ACTIVITY: 841 * BitOffset : 8 842 * BitWidth : 1 843 * AccessType: RO 844 * ResetValue: (uint32_t)0x0 845 */ 846 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_ACTIVITY, 8, 1, RO, (uint32_t)0x0); 847 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_ACTIVITY, ACTIVE, 0x1); 848 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_ACTIVITY, INACTIVE, 0x0); 849 850 /* 851 * Bit Field of Register INTR_STAT 852 * R_STOP_DET: 853 * BitOffset : 9 854 * BitWidth : 1 855 * AccessType: RO 856 * ResetValue: (uint32_t)0x0 857 */ 858 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_STOP_DET, 9, 1, RO, (uint32_t)0x0); 859 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_STOP_DET, ACTIVE, 0x1); 860 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_STOP_DET, INACTIVE, 0x0); 861 862 /* 863 * Bit Field of Register INTR_STAT 864 * R_START_DET: 865 * BitOffset : 10 866 * BitWidth : 1 867 * AccessType: RO 868 * ResetValue: (uint32_t)0x0 869 */ 870 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_START_DET, 10, 1, RO, (uint32_t)0x0); 871 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_START_DET, ACTIVE, 0x1); 872 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_START_DET, INACTIVE, 0x0); 873 874 /* 875 * Bit Field of Register INTR_STAT 876 * R_GEN_CALL: 877 * BitOffset : 11 878 * BitWidth : 1 879 * AccessType: RO 880 * ResetValue: (uint32_t)0x0 881 */ 882 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_GEN_CALL, 11, 1, RO, (uint32_t)0x0); 883 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_GEN_CALL, ACTIVE, 0x1); 884 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_GEN_CALL, INACTIVE, 0x0); 885 886 /* 887 * Bit Field of Register INTR_STAT 888 * R_RESTART_DET: 889 * BitOffset : 12 890 * BitWidth : 1 891 * AccessType: RO 892 * ResetValue: (uint32_t)0x0 893 */ 894 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_RESTART_DET, 12, 1, RO, (uint32_t)0x0); 895 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RESTART_DET, ACTIVE, 0x1); 896 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_RESTART_DET, INACTIVE, 0x0); 897 898 /* 899 * Bit Field of Register INTR_STAT 900 * R_MASTER_ON_HOLD: 901 * BitOffset : 13 902 * BitWidth : 1 903 * AccessType: RO 904 * ResetValue: (uint32_t)0x0 905 */ 906 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_MASTER_ON_HOLD, 13, 1, RO, (uint32_t)0x0); 907 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_MASTER_ON_HOLD, ACTIVE, 0x1); 908 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_MASTER_ON_HOLD, INACTIVE, 0x0); 909 910 /* 911 * Bit Field of Register INTR_STAT 912 * R_SCL_STUCK_AT_LOW: 913 * BitOffset : 14 914 * BitWidth : 1 915 * AccessType: RO 916 * ResetValue: (uint32_t)0x0 917 */ 918 SEDI_RBF_DEFINE(I2C, INTR_STAT, R_SCL_STUCK_AT_LOW, 14, 1, RO, (uint32_t)0x0); 919 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_SCL_STUCK_AT_LOW, ACTIVE, 0x1); 920 SEDI_RBFV_DEFINE(I2C, INTR_STAT, R_SCL_STUCK_AT_LOW, INACTIVE, 0x0); 921 922 /* 923 * Bit Field of Register INTR_STAT 924 * RSVD_R_WR_REQ: 925 * BitOffset : 15 926 * BitWidth : 1 927 * AccessType: RO 928 * ResetValue: (uint32_t)0x0 929 */ 930 SEDI_RBF_DEFINE(I2C, INTR_STAT, RSVD_R_WR_REQ, 15, 1, RO, (uint32_t)0x0); 931 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_WR_REQ, 0, 0); 932 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_WR_REQ, 1, 1); 933 934 /* 935 * Bit Field of Register INTR_STAT 936 * RSVD_R_SLV_ADDR1_TAG: 937 * BitOffset : 16 938 * BitWidth : 1 939 * AccessType: RO 940 * ResetValue: (uint32_t)0x0 941 */ 942 SEDI_RBF_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR1_TAG, 16, 1, RO, (uint32_t)0x0); 943 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR1_TAG, 0, 0); 944 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR1_TAG, 1, 1); 945 946 /* 947 * Bit Field of Register INTR_STAT 948 * RSVD_R_SLV_ADDR2_TAG: 949 * BitOffset : 17 950 * BitWidth : 1 951 * AccessType: RO 952 * ResetValue: (uint32_t)0x0 953 */ 954 SEDI_RBF_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR2_TAG, 17, 1, RO, (uint32_t)0x0); 955 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR2_TAG, 0, 0); 956 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR2_TAG, 1, 1); 957 958 /* 959 * Bit Field of Register INTR_STAT 960 * RSVD_R_SLV_ADDR3_TAG: 961 * BitOffset : 18 962 * BitWidth : 1 963 * AccessType: RO 964 * ResetValue: (uint32_t)0x0 965 */ 966 SEDI_RBF_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR3_TAG, 18, 1, RO, (uint32_t)0x0); 967 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR3_TAG, 0, 0); 968 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR3_TAG, 1, 1); 969 970 /* 971 * Bit Field of Register INTR_STAT 972 * RSVD_R_SLV_ADDR4_TAG: 973 * BitOffset : 19 974 * BitWidth : 1 975 * AccessType: RO 976 * ResetValue: (uint32_t)0x0 977 */ 978 SEDI_RBF_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR4_TAG, 19, 1, RO, (uint32_t)0x0); 979 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR4_TAG, 0, 0); 980 SEDI_RBFV_DEFINE(I2C, INTR_STAT, RSVD_R_SLV_ADDR4_TAG, 1, 1); 981 982 /* 983 * Bit Field of Register INTR_STAT 984 * RSVD_IC_INTR_STAT: 985 * BitOffset : 20 986 * BitWidth : 12 987 * AccessType: RO 988 * ResetValue: (uint32_t)0x0 989 */ 990 SEDI_RBF_DEFINE(I2C, INTR_STAT, RSVD_IC_INTR_STAT, 20, 12, RO, (uint32_t)0x0); 991 992 /* ********* I2C INTR_MASK *********** 993 * 994 * Register of SEDI I2C 995 * INTR_MASK: I2C Interrupt Mask Register 996 * AddressOffset : 0x30 997 * AccessType : RW 998 * WritableBitMask: 0x7fff 999 * ResetValue : (uint32_t)0x48ff 1000 */ 1001 SEDI_REG_DEFINE(I2C, INTR_MASK, 0x30, RW, (uint32_t)0x7fff, (uint32_t)0x48ff); 1002 1003 /* 1004 * Bit Field of Register INTR_MASK 1005 * M_RX_UNDER: 1006 * BitOffset : 0 1007 * BitWidth : 1 1008 * AccessType: RW 1009 * ResetValue: (uint32_t)0x1 1010 */ 1011 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_RX_UNDER, 0, 1, RW, (uint32_t)0x1); 1012 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_UNDER, DISABLED, 0x1); 1013 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_UNDER, ENABLED, 0x0); 1014 1015 /* 1016 * Bit Field of Register INTR_MASK 1017 * M_RX_OVER: 1018 * BitOffset : 1 1019 * BitWidth : 1 1020 * AccessType: RW 1021 * ResetValue: (uint32_t)0x1 1022 */ 1023 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_RX_OVER, 1, 1, RW, (uint32_t)0x1); 1024 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_OVER, DISABLED, 0x1); 1025 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_OVER, ENABLED, 0x0); 1026 1027 /* 1028 * Bit Field of Register INTR_MASK 1029 * M_RX_FULL: 1030 * BitOffset : 2 1031 * BitWidth : 1 1032 * AccessType: RW 1033 * ResetValue: (uint32_t)0x1 1034 */ 1035 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_RX_FULL, 2, 1, RW, (uint32_t)0x1); 1036 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_FULL, DISABLED, 0x1); 1037 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_FULL, ENABLED, 0x0); 1038 1039 /* 1040 * Bit Field of Register INTR_MASK 1041 * M_TX_OVER: 1042 * BitOffset : 3 1043 * BitWidth : 1 1044 * AccessType: RW 1045 * ResetValue: (uint32_t)0x1 1046 */ 1047 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_TX_OVER, 3, 1, RW, (uint32_t)0x1); 1048 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_TX_OVER, DISABLED, 0x1); 1049 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_TX_OVER, ENABLED, 0x0); 1050 1051 /* 1052 * Bit Field of Register INTR_MASK 1053 * M_TX_EMPTY: 1054 * BitOffset : 4 1055 * BitWidth : 1 1056 * AccessType: RW 1057 * ResetValue: (uint32_t)0x1 1058 */ 1059 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_TX_EMPTY, 4, 1, RW, (uint32_t)0x1); 1060 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_TX_EMPTY, DISABLED, 0x1); 1061 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_TX_EMPTY, ENABLED, 0x0); 1062 1063 /* 1064 * Bit Field of Register INTR_MASK 1065 * M_RD_REQ: 1066 * BitOffset : 5 1067 * BitWidth : 1 1068 * AccessType: RW 1069 * ResetValue: (uint32_t)0x1 1070 */ 1071 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_RD_REQ, 5, 1, RW, (uint32_t)0x1); 1072 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RD_REQ, DISABLED, 0x1); 1073 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RD_REQ, ENABLED, 0x0); 1074 1075 /* 1076 * Bit Field of Register INTR_MASK 1077 * M_TX_ABRT: 1078 * BitOffset : 6 1079 * BitWidth : 1 1080 * AccessType: RW 1081 * ResetValue: (uint32_t)0x1 1082 */ 1083 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_TX_ABRT, 6, 1, RW, (uint32_t)0x1); 1084 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_TX_ABRT, DISABLED, 0x1); 1085 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_TX_ABRT, ENABLED, 0x0); 1086 1087 /* 1088 * Bit Field of Register INTR_MASK 1089 * M_RX_DONE: 1090 * BitOffset : 7 1091 * BitWidth : 1 1092 * AccessType: RW 1093 * ResetValue: (uint32_t)0x1 1094 */ 1095 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_RX_DONE, 7, 1, RW, (uint32_t)0x1); 1096 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_DONE, DISABLED, 0x1); 1097 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RX_DONE, ENABLED, 0x0); 1098 1099 /* 1100 * Bit Field of Register INTR_MASK 1101 * M_ACTIVITY: 1102 * BitOffset : 8 1103 * BitWidth : 1 1104 * AccessType: RW 1105 * ResetValue: (uint32_t)0x0 1106 */ 1107 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_ACTIVITY, 8, 1, RW, (uint32_t)0x0); 1108 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_ACTIVITY, DISABLED, 0x1); 1109 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_ACTIVITY, ENABLED, 0x0); 1110 1111 /* 1112 * Bit Field of Register INTR_MASK 1113 * M_STOP_DET: 1114 * BitOffset : 9 1115 * BitWidth : 1 1116 * AccessType: RW 1117 * ResetValue: (uint32_t)0x0 1118 */ 1119 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_STOP_DET, 9, 1, RW, (uint32_t)0x0); 1120 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_STOP_DET, DISABLED, 0x1); 1121 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_STOP_DET, ENABLED, 0x0); 1122 1123 /* 1124 * Bit Field of Register INTR_MASK 1125 * M_START_DET: 1126 * BitOffset : 10 1127 * BitWidth : 1 1128 * AccessType: RW 1129 * ResetValue: (uint32_t)0x0 1130 */ 1131 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_START_DET, 10, 1, RW, (uint32_t)0x0); 1132 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_START_DET, DISABLED, 0x1); 1133 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_START_DET, ENABLED, 0x0); 1134 1135 /* 1136 * Bit Field of Register INTR_MASK 1137 * M_GEN_CALL: 1138 * BitOffset : 11 1139 * BitWidth : 1 1140 * AccessType: RW 1141 * ResetValue: (uint32_t)0x1 1142 */ 1143 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_GEN_CALL, 11, 1, RW, (uint32_t)0x1); 1144 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_GEN_CALL, DISABLED, 0x1); 1145 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_GEN_CALL, ENABLED, 0x0); 1146 1147 /* 1148 * Bit Field of Register INTR_MASK 1149 * M_RESTART_DET: 1150 * BitOffset : 12 1151 * BitWidth : 1 1152 * AccessType: RW 1153 * ResetValue: (uint32_t)0x0 1154 */ 1155 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_RESTART_DET, 12, 1, RW, (uint32_t)0x0); 1156 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RESTART_DET, DISABLED, 0x1); 1157 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_RESTART_DET, ENABLED, 0x0); 1158 1159 /* 1160 * Bit Field of Register INTR_MASK 1161 * M_MASTER_ON_HOLD: 1162 * BitOffset : 13 1163 * BitWidth : 1 1164 * AccessType: RW 1165 * ResetValue: (uint32_t)0x0 1166 */ 1167 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_MASTER_ON_HOLD, 13, 1, RW, (uint32_t)0x0); 1168 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_MASTER_ON_HOLD, DISABLED, 0x1); 1169 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_MASTER_ON_HOLD, ENABLED, 0x0); 1170 1171 /* 1172 * Bit Field of Register INTR_MASK 1173 * M_SCL_STUCK_AT_LOW: 1174 * BitOffset : 14 1175 * BitWidth : 1 1176 * AccessType: RW 1177 * ResetValue: (uint32_t)0x1 1178 */ 1179 SEDI_RBF_DEFINE(I2C, INTR_MASK, M_SCL_STUCK_AT_LOW, 14, 1, RW, (uint32_t)0x1); 1180 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_SCL_STUCK_AT_LOW, DISABLED, 0x1); 1181 SEDI_RBFV_DEFINE(I2C, INTR_MASK, M_SCL_STUCK_AT_LOW, ENABLED, 0x0); 1182 1183 /* 1184 * Bit Field of Register INTR_MASK 1185 * RSVD_M_WR_REQ: 1186 * BitOffset : 15 1187 * BitWidth : 1 1188 * AccessType: RO 1189 * ResetValue: (uint32_t)0x0 1190 */ 1191 SEDI_RBF_DEFINE(I2C, INTR_MASK, RSVD_M_WR_REQ, 15, 1, RO, (uint32_t)0x0); 1192 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_WR_REQ, 0, 0); 1193 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_WR_REQ, 1, 1); 1194 1195 /* 1196 * Bit Field of Register INTR_MASK 1197 * RSVD_M_SLV_ADDR1_TAG: 1198 * BitOffset : 16 1199 * BitWidth : 1 1200 * AccessType: RO 1201 * ResetValue: (uint32_t)0x0 1202 */ 1203 SEDI_RBF_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR1_TAG, 16, 1, RO, (uint32_t)0x0); 1204 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR1_TAG, 0, 0); 1205 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR1_TAG, 1, 1); 1206 1207 /* 1208 * Bit Field of Register INTR_MASK 1209 * RSVD_M_SLV_ADDR2_TAG: 1210 * BitOffset : 17 1211 * BitWidth : 1 1212 * AccessType: RO 1213 * ResetValue: (uint32_t)0x0 1214 */ 1215 SEDI_RBF_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR2_TAG, 17, 1, RO, (uint32_t)0x0); 1216 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR2_TAG, 0, 0); 1217 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR2_TAG, 1, 1); 1218 1219 /* 1220 * Bit Field of Register INTR_MASK 1221 * RSVD_M_SLV_ADDR3_TAG: 1222 * BitOffset : 18 1223 * BitWidth : 1 1224 * AccessType: RO 1225 * ResetValue: (uint32_t)0x0 1226 */ 1227 SEDI_RBF_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR3_TAG, 18, 1, RO, (uint32_t)0x0); 1228 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR3_TAG, 0, 0); 1229 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR3_TAG, 1, 1); 1230 1231 /* 1232 * Bit Field of Register INTR_MASK 1233 * RSVD_M_SLV_ADDR4_TAG: 1234 * BitOffset : 19 1235 * BitWidth : 1 1236 * AccessType: RO 1237 * ResetValue: (uint32_t)0x0 1238 */ 1239 SEDI_RBF_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR4_TAG, 19, 1, RO, (uint32_t)0x0); 1240 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR4_TAG, 0, 0); 1241 SEDI_RBFV_DEFINE(I2C, INTR_MASK, RSVD_M_SLV_ADDR4_TAG, 1, 1); 1242 1243 /* 1244 * Bit Field of Register INTR_MASK 1245 * RSVD_IC_INTR_STAT: 1246 * BitOffset : 20 1247 * BitWidth : 12 1248 * AccessType: RO 1249 * ResetValue: (uint32_t)0x0 1250 */ 1251 SEDI_RBF_DEFINE(I2C, INTR_MASK, RSVD_IC_INTR_STAT, 20, 12, RO, (uint32_t)0x0); 1252 1253 /* ********* I2C RAW_INTR_STAT *********** 1254 * 1255 * Register of SEDI I2C 1256 * RAW_INTR_STAT: I2C Raw Interrupt Status Register 1257 * AddressOffset : 0x34 1258 * AccessType : RO 1259 * WritableBitMask: 0x0 1260 * ResetValue : (uint32_t)0x0 1261 */ 1262 SEDI_REG_DEFINE(I2C, RAW_INTR_STAT, 0x34, RO, (uint32_t)0x0, (uint32_t)0x0); 1263 1264 /* 1265 * Bit Field of Register RAW_INTR_STAT 1266 * RX_UNDER: 1267 * BitOffset : 0 1268 * BitWidth : 1 1269 * AccessType: RO 1270 * ResetValue: (uint32_t)0x0 1271 */ 1272 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RX_UNDER, 0, 1, RO, (uint32_t)0x0); 1273 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_UNDER, ACTIVE, 0x1); 1274 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_UNDER, INACTIVE, 0x0); 1275 1276 /* 1277 * Bit Field of Register RAW_INTR_STAT 1278 * RX_OVER: 1279 * BitOffset : 1 1280 * BitWidth : 1 1281 * AccessType: RO 1282 * ResetValue: (uint32_t)0x0 1283 */ 1284 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RX_OVER, 1, 1, RO, (uint32_t)0x0); 1285 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_OVER, ACTIVE, 0x1); 1286 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_OVER, INACTIVE, 0x0); 1287 1288 /* 1289 * Bit Field of Register RAW_INTR_STAT 1290 * RX_FULL: 1291 * BitOffset : 2 1292 * BitWidth : 1 1293 * AccessType: RO 1294 * ResetValue: (uint32_t)0x0 1295 */ 1296 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RX_FULL, 2, 1, RO, (uint32_t)0x0); 1297 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_FULL, ACTIVE, 0x1); 1298 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_FULL, INACTIVE, 0x0); 1299 1300 /* 1301 * Bit Field of Register RAW_INTR_STAT 1302 * TX_OVER: 1303 * BitOffset : 3 1304 * BitWidth : 1 1305 * AccessType: RO 1306 * ResetValue: (uint32_t)0x0 1307 */ 1308 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, TX_OVER, 3, 1, RO, (uint32_t)0x0); 1309 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, TX_OVER, ACTIVE, 0x1); 1310 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, TX_OVER, INACTIVE, 0x0); 1311 1312 /* 1313 * Bit Field of Register RAW_INTR_STAT 1314 * TX_EMPTY: 1315 * BitOffset : 4 1316 * BitWidth : 1 1317 * AccessType: RO 1318 * ResetValue: (uint32_t)0x0 1319 */ 1320 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, TX_EMPTY, 4, 1, RO, (uint32_t)0x0); 1321 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, TX_EMPTY, ACTIVE, 0x1); 1322 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, TX_EMPTY, INACTIVE, 0x0); 1323 1324 /* 1325 * Bit Field of Register RAW_INTR_STAT 1326 * RD_REQ: 1327 * BitOffset : 5 1328 * BitWidth : 1 1329 * AccessType: RO 1330 * ResetValue: (uint32_t)0x0 1331 */ 1332 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RD_REQ, 5, 1, RO, (uint32_t)0x0); 1333 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RD_REQ, ACTIVE, 0x1); 1334 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RD_REQ, INACTIVE, 0x0); 1335 1336 /* 1337 * Bit Field of Register RAW_INTR_STAT 1338 * TX_ABRT: 1339 * BitOffset : 6 1340 * BitWidth : 1 1341 * AccessType: RO 1342 * ResetValue: (uint32_t)0x0 1343 */ 1344 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, TX_ABRT, 6, 1, RO, (uint32_t)0x0); 1345 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, TX_ABRT, ACTIVE, 0x1); 1346 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, TX_ABRT, INACTIVE, 0x0); 1347 1348 /* 1349 * Bit Field of Register RAW_INTR_STAT 1350 * RX_DONE: 1351 * BitOffset : 7 1352 * BitWidth : 1 1353 * AccessType: RO 1354 * ResetValue: (uint32_t)0x0 1355 */ 1356 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RX_DONE, 7, 1, RO, (uint32_t)0x0); 1357 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_DONE, ACTIVE, 0x1); 1358 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RX_DONE, INACTIVE, 0x0); 1359 1360 /* 1361 * Bit Field of Register RAW_INTR_STAT 1362 * ACTIVITY: 1363 * BitOffset : 8 1364 * BitWidth : 1 1365 * AccessType: RO 1366 * ResetValue: (uint32_t)0x0 1367 */ 1368 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, ACTIVITY, 8, 1, RO, (uint32_t)0x0); 1369 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, ACTIVITY, ACTIVE, 0x1); 1370 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, ACTIVITY, INACTIVE, 0x0); 1371 1372 /* 1373 * Bit Field of Register RAW_INTR_STAT 1374 * STOP_DET: 1375 * BitOffset : 9 1376 * BitWidth : 1 1377 * AccessType: RO 1378 * ResetValue: (uint32_t)0x0 1379 */ 1380 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, STOP_DET, 9, 1, RO, (uint32_t)0x0); 1381 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, STOP_DET, ACTIVE, 0x1); 1382 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, STOP_DET, INACTIVE, 0x0); 1383 1384 /* 1385 * Bit Field of Register RAW_INTR_STAT 1386 * START_DET: 1387 * BitOffset : 10 1388 * BitWidth : 1 1389 * AccessType: RO 1390 * ResetValue: (uint32_t)0x0 1391 */ 1392 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, START_DET, 10, 1, RO, (uint32_t)0x0); 1393 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, START_DET, ACTIVE, 0x1); 1394 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, START_DET, INACTIVE, 0x0); 1395 1396 /* 1397 * Bit Field of Register RAW_INTR_STAT 1398 * GEN_CALL: 1399 * BitOffset : 11 1400 * BitWidth : 1 1401 * AccessType: RO 1402 * ResetValue: (uint32_t)0x0 1403 */ 1404 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, GEN_CALL, 11, 1, RO, (uint32_t)0x0); 1405 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, GEN_CALL, ACTIVE, 0x1); 1406 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, GEN_CALL, INACTIVE, 0x0); 1407 1408 /* 1409 * Bit Field of Register RAW_INTR_STAT 1410 * RESTART_DET: 1411 * BitOffset : 12 1412 * BitWidth : 1 1413 * AccessType: RO 1414 * ResetValue: (uint32_t)0x0 1415 */ 1416 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RESTART_DET, 12, 1, RO, (uint32_t)0x0); 1417 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RESTART_DET, ACTIVE, 0x1); 1418 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RESTART_DET, INACTIVE, 0x0); 1419 1420 /* 1421 * Bit Field of Register RAW_INTR_STAT 1422 * MASTER_ON_HOLD: 1423 * BitOffset : 13 1424 * BitWidth : 1 1425 * AccessType: RO 1426 * ResetValue: (uint32_t)0x0 1427 */ 1428 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, MASTER_ON_HOLD, 13, 1, RO, (uint32_t)0x0); 1429 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, MASTER_ON_HOLD, ACTIVE, 0x1); 1430 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, MASTER_ON_HOLD, INACTIVE, 0x0); 1431 1432 /* 1433 * Bit Field of Register RAW_INTR_STAT 1434 * SCL_STUCK_AT_LOW: 1435 * BitOffset : 14 1436 * BitWidth : 1 1437 * AccessType: RO 1438 * ResetValue: (uint32_t)0x0 1439 */ 1440 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, SCL_STUCK_AT_LOW, 14, 1, RO, (uint32_t)0x0); 1441 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, SCL_STUCK_AT_LOW, ACTIVE, 0x1); 1442 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, SCL_STUCK_AT_LOW, INACTIVE, 0x0); 1443 1444 /* 1445 * Bit Field of Register RAW_INTR_STAT 1446 * RSVD_WR_REQ: 1447 * BitOffset : 15 1448 * BitWidth : 1 1449 * AccessType: RO 1450 * ResetValue: (uint32_t)0x0 1451 */ 1452 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RSVD_WR_REQ, 15, 1, RO, (uint32_t)0x0); 1453 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_WR_REQ, 0, 0); 1454 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_WR_REQ, 1, 1); 1455 1456 /* 1457 * Bit Field of Register RAW_INTR_STAT 1458 * RSVD_SLV_ADDR1_TAG: 1459 * BitOffset : 16 1460 * BitWidth : 1 1461 * AccessType: RO 1462 * ResetValue: (uint32_t)0x0 1463 */ 1464 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR1_TAG, 16, 1, RO, (uint32_t)0x0); 1465 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR1_TAG, 0, 0); 1466 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR1_TAG, 1, 1); 1467 1468 /* 1469 * Bit Field of Register RAW_INTR_STAT 1470 * RSVD_SLV_ADDR2_TAG: 1471 * BitOffset : 17 1472 * BitWidth : 1 1473 * AccessType: RO 1474 * ResetValue: (uint32_t)0x0 1475 */ 1476 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR2_TAG, 17, 1, RO, (uint32_t)0x0); 1477 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR2_TAG, 0, 0); 1478 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR2_TAG, 1, 1); 1479 1480 /* 1481 * Bit Field of Register RAW_INTR_STAT 1482 * RSVD_SLV_ADDR3_TAG: 1483 * BitOffset : 18 1484 * BitWidth : 1 1485 * AccessType: RO 1486 * ResetValue: (uint32_t)0x0 1487 */ 1488 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR3_TAG, 18, 1, RO, (uint32_t)0x0); 1489 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR3_TAG, 0, 0); 1490 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR3_TAG, 1, 1); 1491 1492 /* 1493 * Bit Field of Register RAW_INTR_STAT 1494 * RSVD_SLV_ADDR4_TAG: 1495 * BitOffset : 19 1496 * BitWidth : 1 1497 * AccessType: RO 1498 * ResetValue: (uint32_t)0x0 1499 */ 1500 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR4_TAG, 19, 1, RO, (uint32_t)0x0); 1501 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR4_TAG, 0, 0); 1502 SEDI_RBFV_DEFINE(I2C, RAW_INTR_STAT, RSVD_SLV_ADDR4_TAG, 1, 1); 1503 1504 /* 1505 * Bit Field of Register RAW_INTR_STAT 1506 * RSVD_IC_RAW_INTR_STAT: 1507 * BitOffset : 20 1508 * BitWidth : 12 1509 * AccessType: RO 1510 * ResetValue: (uint32_t)0x0 1511 */ 1512 SEDI_RBF_DEFINE(I2C, RAW_INTR_STAT, RSVD_IC_RAW_INTR_STAT, 20, 12, RO, (uint32_t)0x0); 1513 1514 /* ********* I2C RX_TL *********** 1515 * 1516 * Register of SEDI I2C 1517 * RX_TL: I2C Receive FIFO Threshold Register 1518 * AddressOffset : 0x38 1519 * AccessType : RW 1520 * WritableBitMask: 0xff 1521 * ResetValue : (uint32_t)0x0 1522 */ 1523 SEDI_REG_DEFINE(I2C, RX_TL, 0x38, RW, (uint32_t)0xff, (uint32_t)0x0); 1524 1525 /* 1526 * Bit Field of Register RX_TL 1527 * RX_TL: 1528 * BitOffset : 0 1529 * BitWidth : 8 1530 * AccessType: RW 1531 * ResetValue: (uint32_t)0x0 1532 */ 1533 SEDI_RBF_DEFINE(I2C, RX_TL, RX_TL, 0, 8, RW, (uint32_t)0x0); 1534 1535 /* 1536 * Bit Field of Register RX_TL 1537 * RSVD_IC_RX_TL: 1538 * BitOffset : 8 1539 * BitWidth : 24 1540 * AccessType: RO 1541 * ResetValue: (uint32_t)0x0 1542 */ 1543 SEDI_RBF_DEFINE(I2C, RX_TL, RSVD_IC_RX_TL, 8, 24, RO, (uint32_t)0x0); 1544 1545 /* ********* I2C TX_TL *********** 1546 * 1547 * Register of SEDI I2C 1548 * TX_TL: I2C Transmit FIFO Threshold Register 1549 * AddressOffset : 0x3c 1550 * AccessType : RW 1551 * WritableBitMask: 0xff 1552 * ResetValue : (uint32_t)0x0 1553 */ 1554 SEDI_REG_DEFINE(I2C, TX_TL, 0x3c, RW, (uint32_t)0xff, (uint32_t)0x0); 1555 1556 /* 1557 * Bit Field of Register TX_TL 1558 * TX_TL: 1559 * BitOffset : 0 1560 * BitWidth : 8 1561 * AccessType: RW 1562 * ResetValue: (uint32_t)0x0 1563 */ 1564 SEDI_RBF_DEFINE(I2C, TX_TL, TX_TL, 0, 8, RW, (uint32_t)0x0); 1565 1566 /* 1567 * Bit Field of Register TX_TL 1568 * RSVD_IC_TX_TL: 1569 * BitOffset : 8 1570 * BitWidth : 24 1571 * AccessType: RO 1572 * ResetValue: (uint32_t)0x0 1573 */ 1574 SEDI_RBF_DEFINE(I2C, TX_TL, RSVD_IC_TX_TL, 8, 24, RO, (uint32_t)0x0); 1575 1576 /* ********* I2C CLR_INTR *********** 1577 * 1578 * Register of SEDI I2C 1579 * CLR_INTR: Clear Combined and Individual Interrupt Register 1580 * AddressOffset : 0x40 1581 * AccessType : RO 1582 * WritableBitMask: 0x0 1583 * ResetValue : (uint32_t)0x0 1584 */ 1585 SEDI_REG_DEFINE(I2C, CLR_INTR, 0x40, RO, (uint32_t)0x0, (uint32_t)0x0); 1586 1587 /* 1588 * Bit Field of Register CLR_INTR 1589 * CLR_INTR: 1590 * BitOffset : 0 1591 * BitWidth : 1 1592 * AccessType: RO 1593 * ResetValue: (uint32_t)0x0 1594 */ 1595 SEDI_RBF_DEFINE(I2C, CLR_INTR, CLR_INTR, 0, 1, RO, (uint32_t)0x0); 1596 SEDI_RBFV_DEFINE(I2C, CLR_INTR, CLR_INTR, 0, 0); 1597 SEDI_RBFV_DEFINE(I2C, CLR_INTR, CLR_INTR, 1, 1); 1598 1599 /* 1600 * Bit Field of Register CLR_INTR 1601 * RSVD_IC_CLR_INTR: 1602 * BitOffset : 1 1603 * BitWidth : 31 1604 * AccessType: RO 1605 * ResetValue: (uint32_t)0x0 1606 */ 1607 SEDI_RBF_DEFINE(I2C, CLR_INTR, RSVD_IC_CLR_INTR, 1, 31, RO, (uint32_t)0x0); 1608 1609 /* ********* I2C CLR_RX_UNDER *********** 1610 * 1611 * Register of SEDI I2C 1612 * CLR_RX_UNDER: Clear RX_UNDER Interrupt Register 1613 * AddressOffset : 0x44 1614 * AccessType : RO 1615 * WritableBitMask: 0x0 1616 * ResetValue : (uint32_t)0x0 1617 */ 1618 SEDI_REG_DEFINE(I2C, CLR_RX_UNDER, 0x44, RO, (uint32_t)0x0, (uint32_t)0x0); 1619 1620 /* 1621 * Bit Field of Register CLR_RX_UNDER 1622 * CLR_RX_UNDER: 1623 * BitOffset : 0 1624 * BitWidth : 1 1625 * AccessType: RO 1626 * ResetValue: (uint32_t)0x0 1627 */ 1628 SEDI_RBF_DEFINE(I2C, CLR_RX_UNDER, CLR_RX_UNDER, 0, 1, RO, (uint32_t)0x0); 1629 SEDI_RBFV_DEFINE(I2C, CLR_RX_UNDER, CLR_RX_UNDER, 0, 0); 1630 SEDI_RBFV_DEFINE(I2C, CLR_RX_UNDER, CLR_RX_UNDER, 1, 1); 1631 1632 /* 1633 * Bit Field of Register CLR_RX_UNDER 1634 * RSVD_IC_CLR_RX_UNDER: 1635 * BitOffset : 1 1636 * BitWidth : 31 1637 * AccessType: RO 1638 * ResetValue: (uint32_t)0x0 1639 */ 1640 SEDI_RBF_DEFINE(I2C, CLR_RX_UNDER, RSVD_IC_CLR_RX_UNDER, 1, 31, RO, (uint32_t)0x0); 1641 1642 /* ********* I2C CLR_RX_OVER *********** 1643 * 1644 * Register of SEDI I2C 1645 * CLR_RX_OVER: Clear RX_OVER Interrupt Register 1646 * AddressOffset : 0x48 1647 * AccessType : RO 1648 * WritableBitMask: 0x0 1649 * ResetValue : (uint32_t)0x0 1650 */ 1651 SEDI_REG_DEFINE(I2C, CLR_RX_OVER, 0x48, RO, (uint32_t)0x0, (uint32_t)0x0); 1652 1653 /* 1654 * Bit Field of Register CLR_RX_OVER 1655 * CLR_RX_OVER: 1656 * BitOffset : 0 1657 * BitWidth : 1 1658 * AccessType: RO 1659 * ResetValue: (uint32_t)0x0 1660 */ 1661 SEDI_RBF_DEFINE(I2C, CLR_RX_OVER, CLR_RX_OVER, 0, 1, RO, (uint32_t)0x0); 1662 SEDI_RBFV_DEFINE(I2C, CLR_RX_OVER, CLR_RX_OVER, 0, 0); 1663 SEDI_RBFV_DEFINE(I2C, CLR_RX_OVER, CLR_RX_OVER, 1, 1); 1664 1665 /* 1666 * Bit Field of Register CLR_RX_OVER 1667 * RSVD_IC_CLR_RX_OVER: 1668 * BitOffset : 1 1669 * BitWidth : 31 1670 * AccessType: RO 1671 * ResetValue: (uint32_t)0x0 1672 */ 1673 SEDI_RBF_DEFINE(I2C, CLR_RX_OVER, RSVD_IC_CLR_RX_OVER, 1, 31, RO, (uint32_t)0x0); 1674 1675 /* ********* I2C CLR_TX_OVER *********** 1676 * 1677 * Register of SEDI I2C 1678 * CLR_TX_OVER: Clear TX_OVER Interrupt Register 1679 * AddressOffset : 0x4c 1680 * AccessType : RO 1681 * WritableBitMask: 0x0 1682 * ResetValue : (uint32_t)0x0 1683 */ 1684 SEDI_REG_DEFINE(I2C, CLR_TX_OVER, 0x4c, RO, (uint32_t)0x0, (uint32_t)0x0); 1685 1686 /* 1687 * Bit Field of Register CLR_TX_OVER 1688 * CLR_TX_OVER: 1689 * BitOffset : 0 1690 * BitWidth : 1 1691 * AccessType: RO 1692 * ResetValue: (uint32_t)0x0 1693 */ 1694 SEDI_RBF_DEFINE(I2C, CLR_TX_OVER, CLR_TX_OVER, 0, 1, RO, (uint32_t)0x0); 1695 SEDI_RBFV_DEFINE(I2C, CLR_TX_OVER, CLR_TX_OVER, 0, 0); 1696 SEDI_RBFV_DEFINE(I2C, CLR_TX_OVER, CLR_TX_OVER, 1, 1); 1697 1698 /* 1699 * Bit Field of Register CLR_TX_OVER 1700 * RSVD_IC_CLR_TX_OVER: 1701 * BitOffset : 1 1702 * BitWidth : 31 1703 * AccessType: RO 1704 * ResetValue: (uint32_t)0x0 1705 */ 1706 SEDI_RBF_DEFINE(I2C, CLR_TX_OVER, RSVD_IC_CLR_TX_OVER, 1, 31, RO, (uint32_t)0x0); 1707 1708 /* ********* I2C CLR_RD_REQ *********** 1709 * 1710 * Register of SEDI I2C 1711 * CLR_RD_REQ: Clear RD_REQ Interrupt Register 1712 * AddressOffset : 0x50 1713 * AccessType : RO 1714 * WritableBitMask: 0x0 1715 * ResetValue : (uint32_t)0x0 1716 */ 1717 SEDI_REG_DEFINE(I2C, CLR_RD_REQ, 0x50, RO, (uint32_t)0x0, (uint32_t)0x0); 1718 1719 /* 1720 * Bit Field of Register CLR_RD_REQ 1721 * CLR_RD_REQ: 1722 * BitOffset : 0 1723 * BitWidth : 1 1724 * AccessType: RO 1725 * ResetValue: (uint32_t)0x0 1726 */ 1727 SEDI_RBF_DEFINE(I2C, CLR_RD_REQ, CLR_RD_REQ, 0, 1, RO, (uint32_t)0x0); 1728 SEDI_RBFV_DEFINE(I2C, CLR_RD_REQ, CLR_RD_REQ, 0, 0); 1729 SEDI_RBFV_DEFINE(I2C, CLR_RD_REQ, CLR_RD_REQ, 1, 1); 1730 1731 /* 1732 * Bit Field of Register CLR_RD_REQ 1733 * RSVD_IC_CLR_RD_REQ: 1734 * BitOffset : 1 1735 * BitWidth : 31 1736 * AccessType: RO 1737 * ResetValue: (uint32_t)0x0 1738 */ 1739 SEDI_RBF_DEFINE(I2C, CLR_RD_REQ, RSVD_IC_CLR_RD_REQ, 1, 31, RO, (uint32_t)0x0); 1740 1741 /* ********* I2C CLR_TX_ABRT *********** 1742 * 1743 * Register of SEDI I2C 1744 * CLR_TX_ABRT: Clear TX_ABRT Interrupt Register 1745 * AddressOffset : 0x54 1746 * AccessType : RO 1747 * WritableBitMask: 0x0 1748 * ResetValue : (uint32_t)0x0 1749 */ 1750 SEDI_REG_DEFINE(I2C, CLR_TX_ABRT, 0x54, RO, (uint32_t)0x0, (uint32_t)0x0); 1751 1752 /* 1753 * Bit Field of Register CLR_TX_ABRT 1754 * CLR_TX_ABRT: 1755 * BitOffset : 0 1756 * BitWidth : 1 1757 * AccessType: RO 1758 * ResetValue: (uint32_t)0x0 1759 */ 1760 SEDI_RBF_DEFINE(I2C, CLR_TX_ABRT, CLR_TX_ABRT, 0, 1, RO, (uint32_t)0x0); 1761 SEDI_RBFV_DEFINE(I2C, CLR_TX_ABRT, CLR_TX_ABRT, 0, 0); 1762 SEDI_RBFV_DEFINE(I2C, CLR_TX_ABRT, CLR_TX_ABRT, 1, 1); 1763 1764 /* 1765 * Bit Field of Register CLR_TX_ABRT 1766 * RSVD_IC_CLR_TX_ABRT: 1767 * BitOffset : 1 1768 * BitWidth : 31 1769 * AccessType: RO 1770 * ResetValue: (uint32_t)0x0 1771 */ 1772 SEDI_RBF_DEFINE(I2C, CLR_TX_ABRT, RSVD_IC_CLR_TX_ABRT, 1, 31, RO, (uint32_t)0x0); 1773 1774 /* ********* I2C CLR_RX_DONE *********** 1775 * 1776 * Register of SEDI I2C 1777 * CLR_RX_DONE: Clear RX_DONE Interrupt Register 1778 * AddressOffset : 0x58 1779 * AccessType : RO 1780 * WritableBitMask: 0x0 1781 * ResetValue : (uint32_t)0x0 1782 */ 1783 SEDI_REG_DEFINE(I2C, CLR_RX_DONE, 0x58, RO, (uint32_t)0x0, (uint32_t)0x0); 1784 1785 /* 1786 * Bit Field of Register CLR_RX_DONE 1787 * CLR_RX_DONE: 1788 * BitOffset : 0 1789 * BitWidth : 1 1790 * AccessType: RO 1791 * ResetValue: (uint32_t)0x0 1792 */ 1793 SEDI_RBF_DEFINE(I2C, CLR_RX_DONE, CLR_RX_DONE, 0, 1, RO, (uint32_t)0x0); 1794 SEDI_RBFV_DEFINE(I2C, CLR_RX_DONE, CLR_RX_DONE, 0, 0); 1795 SEDI_RBFV_DEFINE(I2C, CLR_RX_DONE, CLR_RX_DONE, 1, 1); 1796 1797 /* 1798 * Bit Field of Register CLR_RX_DONE 1799 * RSVD_IC_CLR_RX_DONE: 1800 * BitOffset : 1 1801 * BitWidth : 31 1802 * AccessType: RO 1803 * ResetValue: (uint32_t)0x0 1804 */ 1805 SEDI_RBF_DEFINE(I2C, CLR_RX_DONE, RSVD_IC_CLR_RX_DONE, 1, 31, RO, (uint32_t)0x0); 1806 1807 /* ********* I2C CLR_ACTIVITY *********** 1808 * 1809 * Register of SEDI I2C 1810 * CLR_ACTIVITY: Clear ACTIVITY Interrupt Register 1811 * AddressOffset : 0x5c 1812 * AccessType : RO 1813 * WritableBitMask: 0x0 1814 * ResetValue : (uint32_t)0x0 1815 */ 1816 SEDI_REG_DEFINE(I2C, CLR_ACTIVITY, 0x5c, RO, (uint32_t)0x0, (uint32_t)0x0); 1817 1818 /* 1819 * Bit Field of Register CLR_ACTIVITY 1820 * CLR_ACTIVITY: 1821 * BitOffset : 0 1822 * BitWidth : 1 1823 * AccessType: RO 1824 * ResetValue: (uint32_t)0x0 1825 */ 1826 SEDI_RBF_DEFINE(I2C, CLR_ACTIVITY, CLR_ACTIVITY, 0, 1, RO, (uint32_t)0x0); 1827 SEDI_RBFV_DEFINE(I2C, CLR_ACTIVITY, CLR_ACTIVITY, 0, 0); 1828 SEDI_RBFV_DEFINE(I2C, CLR_ACTIVITY, CLR_ACTIVITY, 1, 1); 1829 1830 /* 1831 * Bit Field of Register CLR_ACTIVITY 1832 * RSVD_IC_CLR_ACTIVITY: 1833 * BitOffset : 1 1834 * BitWidth : 31 1835 * AccessType: RO 1836 * ResetValue: (uint32_t)0x0 1837 */ 1838 SEDI_RBF_DEFINE(I2C, CLR_ACTIVITY, RSVD_IC_CLR_ACTIVITY, 1, 31, RO, (uint32_t)0x0); 1839 1840 /* ********* I2C CLR_STOP_DET *********** 1841 * 1842 * Register of SEDI I2C 1843 * CLR_STOP_DET: Clear STOP_DET Interrupt Register 1844 * AddressOffset : 0x60 1845 * AccessType : RO 1846 * WritableBitMask: 0x0 1847 * ResetValue : (uint32_t)0x0 1848 */ 1849 SEDI_REG_DEFINE(I2C, CLR_STOP_DET, 0x60, RO, (uint32_t)0x0, (uint32_t)0x0); 1850 1851 /* 1852 * Bit Field of Register CLR_STOP_DET 1853 * CLR_STOP_DET: 1854 * BitOffset : 0 1855 * BitWidth : 1 1856 * AccessType: RO 1857 * ResetValue: (uint32_t)0x0 1858 */ 1859 SEDI_RBF_DEFINE(I2C, CLR_STOP_DET, CLR_STOP_DET, 0, 1, RO, (uint32_t)0x0); 1860 SEDI_RBFV_DEFINE(I2C, CLR_STOP_DET, CLR_STOP_DET, 0, 0); 1861 SEDI_RBFV_DEFINE(I2C, CLR_STOP_DET, CLR_STOP_DET, 1, 1); 1862 1863 /* 1864 * Bit Field of Register CLR_STOP_DET 1865 * RSVD_IC_CLR_STOP_DET: 1866 * BitOffset : 1 1867 * BitWidth : 31 1868 * AccessType: RO 1869 * ResetValue: (uint32_t)0x0 1870 */ 1871 SEDI_RBF_DEFINE(I2C, CLR_STOP_DET, RSVD_IC_CLR_STOP_DET, 1, 31, RO, (uint32_t)0x0); 1872 1873 /* ********* I2C CLR_START_DET *********** 1874 * 1875 * Register of SEDI I2C 1876 * CLR_START_DET: Clear START_DET Interrupt Register 1877 * AddressOffset : 0x64 1878 * AccessType : RO 1879 * WritableBitMask: 0x0 1880 * ResetValue : (uint32_t)0x0 1881 */ 1882 SEDI_REG_DEFINE(I2C, CLR_START_DET, 0x64, RO, (uint32_t)0x0, (uint32_t)0x0); 1883 1884 /* 1885 * Bit Field of Register CLR_START_DET 1886 * CLR_START_DET: 1887 * BitOffset : 0 1888 * BitWidth : 1 1889 * AccessType: RO 1890 * ResetValue: (uint32_t)0x0 1891 */ 1892 SEDI_RBF_DEFINE(I2C, CLR_START_DET, CLR_START_DET, 0, 1, RO, (uint32_t)0x0); 1893 SEDI_RBFV_DEFINE(I2C, CLR_START_DET, CLR_START_DET, 0, 0); 1894 SEDI_RBFV_DEFINE(I2C, CLR_START_DET, CLR_START_DET, 1, 1); 1895 1896 /* 1897 * Bit Field of Register CLR_START_DET 1898 * RSVD_IC_CLR_START_DET: 1899 * BitOffset : 1 1900 * BitWidth : 31 1901 * AccessType: RO 1902 * ResetValue: (uint32_t)0x0 1903 */ 1904 SEDI_RBF_DEFINE(I2C, CLR_START_DET, RSVD_IC_CLR_START_DET, 1, 31, RO, (uint32_t)0x0); 1905 1906 /* ********* I2C CLR_GEN_CALL *********** 1907 * 1908 * Register of SEDI I2C 1909 * CLR_GEN_CALL: Clear GEN_CALL Interrupt Register 1910 * AddressOffset : 0x68 1911 * AccessType : RO 1912 * WritableBitMask: 0x0 1913 * ResetValue : (uint32_t)0x0 1914 */ 1915 SEDI_REG_DEFINE(I2C, CLR_GEN_CALL, 0x68, RO, (uint32_t)0x0, (uint32_t)0x0); 1916 1917 /* 1918 * Bit Field of Register CLR_GEN_CALL 1919 * CLR_GEN_CALL: 1920 * BitOffset : 0 1921 * BitWidth : 1 1922 * AccessType: RO 1923 * ResetValue: (uint32_t)0x0 1924 */ 1925 SEDI_RBF_DEFINE(I2C, CLR_GEN_CALL, CLR_GEN_CALL, 0, 1, RO, (uint32_t)0x0); 1926 SEDI_RBFV_DEFINE(I2C, CLR_GEN_CALL, CLR_GEN_CALL, 0, 0); 1927 SEDI_RBFV_DEFINE(I2C, CLR_GEN_CALL, CLR_GEN_CALL, 1, 1); 1928 1929 /* 1930 * Bit Field of Register CLR_GEN_CALL 1931 * RSVD_IC_CLR_GEN_CALL: 1932 * BitOffset : 1 1933 * BitWidth : 31 1934 * AccessType: RO 1935 * ResetValue: (uint32_t)0x0 1936 */ 1937 SEDI_RBF_DEFINE(I2C, CLR_GEN_CALL, RSVD_IC_CLR_GEN_CALL, 1, 31, RO, (uint32_t)0x0); 1938 1939 /* ********* I2C ENABLE *********** 1940 * 1941 * Register of SEDI I2C 1942 * ENABLE: I2C ENABLE Register 1943 * AddressOffset : 0x6c 1944 * AccessType : RW 1945 * WritableBitMask: 0xf 1946 * ResetValue : (uint32_t)0x0 1947 */ 1948 SEDI_REG_DEFINE(I2C, ENABLE, 0x6c, RW, (uint32_t)0xf, (uint32_t)0x0); 1949 1950 /* 1951 * Bit Field of Register ENABLE 1952 * ENABLE: 1953 * BitOffset : 0 1954 * BitWidth : 1 1955 * AccessType: RW 1956 * ResetValue: (uint32_t)0x0 1957 */ 1958 SEDI_RBF_DEFINE(I2C, ENABLE, ENABLE, 0, 1, RW, (uint32_t)0x0); 1959 SEDI_RBFV_DEFINE(I2C, ENABLE, ENABLE, DISABLED, 0x0); 1960 SEDI_RBFV_DEFINE(I2C, ENABLE, ENABLE, ENABLED, 0x1); 1961 1962 /* 1963 * Bit Field of Register ENABLE 1964 * ABORT: 1965 * BitOffset : 1 1966 * BitWidth : 1 1967 * AccessType: RW 1968 * ResetValue: (uint32_t)0x0 1969 */ 1970 SEDI_RBF_DEFINE(I2C, ENABLE, ABORT, 1, 1, RW, (uint32_t)0x0); 1971 SEDI_RBFV_DEFINE(I2C, ENABLE, ABORT, DISABLE, 0x0); 1972 SEDI_RBFV_DEFINE(I2C, ENABLE, ABORT, ENABLED, 0x1); 1973 1974 /* 1975 * Bit Field of Register ENABLE 1976 * TX_CMD_BLOCK: 1977 * BitOffset : 2 1978 * BitWidth : 1 1979 * AccessType: RW 1980 * ResetValue: (uint32_t)0x0 1981 */ 1982 SEDI_RBF_DEFINE(I2C, ENABLE, TX_CMD_BLOCK, 2, 1, RW, (uint32_t)0x0); 1983 SEDI_RBFV_DEFINE(I2C, ENABLE, TX_CMD_BLOCK, BLOCKED, 0x1); 1984 SEDI_RBFV_DEFINE(I2C, ENABLE, TX_CMD_BLOCK, NOT_BLOCKED, 0x0); 1985 1986 /* 1987 * Bit Field of Register ENABLE 1988 * SDA_STUCK_RECOVERY_ENABLE: 1989 * BitOffset : 3 1990 * BitWidth : 1 1991 * AccessType: RW 1992 * ResetValue: (uint32_t)0x0 1993 */ 1994 SEDI_RBF_DEFINE(I2C, ENABLE, SDA_STUCK_RECOVERY_ENABLE, 3, 1, RW, (uint32_t)0x0); 1995 SEDI_RBFV_DEFINE(I2C, ENABLE, SDA_STUCK_RECOVERY_ENABLE, SDA_STUCK_RECOVERY_DISABLED, 0x0); 1996 SEDI_RBFV_DEFINE(I2C, ENABLE, SDA_STUCK_RECOVERY_ENABLE, SDA_STUCK_RECOVERY_ENABLED, 0x1); 1997 1998 /* 1999 * Bit Field of Register ENABLE 2000 * RSVD_IC_ENABLE_1: 2001 * BitOffset : 4 2002 * BitWidth : 12 2003 * AccessType: RO 2004 * ResetValue: (uint32_t)0x0 2005 */ 2006 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_IC_ENABLE_1, 4, 12, RO, (uint32_t)0x0); 2007 2008 /* 2009 * Bit Field of Register ENABLE 2010 * RSVD_SMBUS_CLK_RESET: 2011 * BitOffset : 16 2012 * BitWidth : 1 2013 * AccessType: RO 2014 * ResetValue: (uint32_t)0x0 2015 */ 2016 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_SMBUS_CLK_RESET, 16, 1, RO, (uint32_t)0x0); 2017 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_SMBUS_CLK_RESET, 0, 0); 2018 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_SMBUS_CLK_RESET, 1, 1); 2019 2020 /* 2021 * Bit Field of Register ENABLE 2022 * RSVD_SMBUS_SUSPEND_EN: 2023 * BitOffset : 17 2024 * BitWidth : 1 2025 * AccessType: RO 2026 * ResetValue: (uint32_t)0x0 2027 */ 2028 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_SMBUS_SUSPEND_EN, 17, 1, RO, (uint32_t)0x0); 2029 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_SMBUS_SUSPEND_EN, 0, 0); 2030 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_SMBUS_SUSPEND_EN, 1, 1); 2031 2032 /* 2033 * Bit Field of Register ENABLE 2034 * RSVD_SMBUS_ALERT_EN: 2035 * BitOffset : 18 2036 * BitWidth : 1 2037 * AccessType: RO 2038 * ResetValue: (uint32_t)0x0 2039 */ 2040 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_SMBUS_ALERT_EN, 18, 1, RO, (uint32_t)0x0); 2041 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_SMBUS_ALERT_EN, 0, 0); 2042 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_SMBUS_ALERT_EN, 1, 1); 2043 2044 /* 2045 * Bit Field of Register ENABLE 2046 * RSVD_IC_SAR_EN: 2047 * BitOffset : 19 2048 * BitWidth : 1 2049 * AccessType: RO 2050 * ResetValue: (uint32_t)0x0 2051 */ 2052 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_IC_SAR_EN, 19, 1, RO, (uint32_t)0x0); 2053 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR_EN, 0, 0); 2054 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR_EN, 1, 1); 2055 2056 /* 2057 * Bit Field of Register ENABLE 2058 * RSVD_IC_SAR2_EN: 2059 * BitOffset : 20 2060 * BitWidth : 1 2061 * AccessType: RO 2062 * ResetValue: (uint32_t)0x0 2063 */ 2064 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_IC_SAR2_EN, 20, 1, RO, (uint32_t)0x0); 2065 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR2_EN, 0, 0); 2066 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR2_EN, 1, 1); 2067 2068 /* 2069 * Bit Field of Register ENABLE 2070 * RSVD_IC_SAR3_EN: 2071 * BitOffset : 21 2072 * BitWidth : 1 2073 * AccessType: RO 2074 * ResetValue: (uint32_t)0x0 2075 */ 2076 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_IC_SAR3_EN, 21, 1, RO, (uint32_t)0x0); 2077 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR3_EN, 0, 0); 2078 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR3_EN, 1, 1); 2079 2080 /* 2081 * Bit Field of Register ENABLE 2082 * RSVD_IC_SAR4_EN: 2083 * BitOffset : 22 2084 * BitWidth : 1 2085 * AccessType: RO 2086 * ResetValue: (uint32_t)0x0 2087 */ 2088 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_IC_SAR4_EN, 22, 1, RO, (uint32_t)0x0); 2089 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR4_EN, 0, 0); 2090 SEDI_RBFV_DEFINE(I2C, ENABLE, RSVD_IC_SAR4_EN, 1, 1); 2091 2092 /* 2093 * Bit Field of Register ENABLE 2094 * RSVD_IC_ENABLE_2: 2095 * BitOffset : 23 2096 * BitWidth : 9 2097 * AccessType: RO 2098 * ResetValue: (uint32_t)0x0 2099 */ 2100 SEDI_RBF_DEFINE(I2C, ENABLE, RSVD_IC_ENABLE_2, 23, 9, RO, (uint32_t)0x0); 2101 2102 /* ********* I2C STATUS *********** 2103 * 2104 * Register of SEDI I2C 2105 * STATUS: I2C STATUS Register 2106 * AddressOffset : 0x70 2107 * AccessType : RO 2108 * WritableBitMask: 0x0 2109 * ResetValue : (uint32_t)0x6 2110 */ 2111 SEDI_REG_DEFINE(I2C, STATUS, 0x70, RO, (uint32_t)0x0, (uint32_t)0x6); 2112 2113 /* 2114 * Bit Field of Register STATUS 2115 * ACTIVITY: 2116 * BitOffset : 0 2117 * BitWidth : 1 2118 * AccessType: RO 2119 * ResetValue: (uint32_t)0x0 2120 */ 2121 SEDI_RBF_DEFINE(I2C, STATUS, ACTIVITY, 0, 1, RO, (uint32_t)0x0); 2122 SEDI_RBFV_DEFINE(I2C, STATUS, ACTIVITY, ACTIVE, 0x1); 2123 SEDI_RBFV_DEFINE(I2C, STATUS, ACTIVITY, INACTIVE, 0x0); 2124 2125 /* 2126 * Bit Field of Register STATUS 2127 * TFNF: 2128 * BitOffset : 1 2129 * BitWidth : 1 2130 * AccessType: RO 2131 * ResetValue: (uint32_t)0x1 2132 */ 2133 SEDI_RBF_DEFINE(I2C, STATUS, TFNF, 1, 1, RO, (uint32_t)0x1); 2134 SEDI_RBFV_DEFINE(I2C, STATUS, TFNF, FULL, 0x0); 2135 SEDI_RBFV_DEFINE(I2C, STATUS, TFNF, NOT_FULL, 0x1); 2136 2137 /* 2138 * Bit Field of Register STATUS 2139 * TFE: 2140 * BitOffset : 2 2141 * BitWidth : 1 2142 * AccessType: RO 2143 * ResetValue: (uint32_t)0x1 2144 */ 2145 SEDI_RBF_DEFINE(I2C, STATUS, TFE, 2, 1, RO, (uint32_t)0x1); 2146 SEDI_RBFV_DEFINE(I2C, STATUS, TFE, EMPTY, 0x1); 2147 SEDI_RBFV_DEFINE(I2C, STATUS, TFE, NON_EMPTY, 0x0); 2148 2149 /* 2150 * Bit Field of Register STATUS 2151 * RFNE: 2152 * BitOffset : 3 2153 * BitWidth : 1 2154 * AccessType: RO 2155 * ResetValue: (uint32_t)0x0 2156 */ 2157 SEDI_RBF_DEFINE(I2C, STATUS, RFNE, 3, 1, RO, (uint32_t)0x0); 2158 SEDI_RBFV_DEFINE(I2C, STATUS, RFNE, EMPTY, 0x0); 2159 SEDI_RBFV_DEFINE(I2C, STATUS, RFNE, NOT_EMPTY, 0x1); 2160 2161 /* 2162 * Bit Field of Register STATUS 2163 * RFF: 2164 * BitOffset : 4 2165 * BitWidth : 1 2166 * AccessType: RO 2167 * ResetValue: (uint32_t)0x0 2168 */ 2169 SEDI_RBF_DEFINE(I2C, STATUS, RFF, 4, 1, RO, (uint32_t)0x0); 2170 SEDI_RBFV_DEFINE(I2C, STATUS, RFF, FULL, 0x1); 2171 SEDI_RBFV_DEFINE(I2C, STATUS, RFF, NOT_FULL, 0x0); 2172 2173 /* 2174 * Bit Field of Register STATUS 2175 * MST_ACTIVITY: 2176 * BitOffset : 5 2177 * BitWidth : 1 2178 * AccessType: RO 2179 * ResetValue: (uint32_t)0x0 2180 */ 2181 SEDI_RBF_DEFINE(I2C, STATUS, MST_ACTIVITY, 5, 1, RO, (uint32_t)0x0); 2182 SEDI_RBFV_DEFINE(I2C, STATUS, MST_ACTIVITY, ACTIVE, 0x1); 2183 SEDI_RBFV_DEFINE(I2C, STATUS, MST_ACTIVITY, IDLE, 0x0); 2184 2185 /* 2186 * Bit Field of Register STATUS 2187 * SLV_ACTIVITY: 2188 * BitOffset : 6 2189 * BitWidth : 1 2190 * AccessType: RO 2191 * ResetValue: (uint32_t)0x0 2192 */ 2193 SEDI_RBF_DEFINE(I2C, STATUS, SLV_ACTIVITY, 6, 1, RO, (uint32_t)0x0); 2194 SEDI_RBFV_DEFINE(I2C, STATUS, SLV_ACTIVITY, ACTIVE, 0x1); 2195 SEDI_RBFV_DEFINE(I2C, STATUS, SLV_ACTIVITY, IDLE, 0x0); 2196 2197 /* 2198 * Bit Field of Register STATUS 2199 * MST_HOLD_TX_FIFO_EMPTY: 2200 * BitOffset : 7 2201 * BitWidth : 1 2202 * AccessType: RO 2203 * ResetValue: (uint32_t)0x0 2204 */ 2205 SEDI_RBF_DEFINE(I2C, STATUS, MST_HOLD_TX_FIFO_EMPTY, 7, 1, RO, (uint32_t)0x0); 2206 SEDI_RBFV_DEFINE(I2C, STATUS, MST_HOLD_TX_FIFO_EMPTY, ACTIVE, 0x1); 2207 SEDI_RBFV_DEFINE(I2C, STATUS, MST_HOLD_TX_FIFO_EMPTY, INACTIVE, 0x0); 2208 2209 /* 2210 * Bit Field of Register STATUS 2211 * MST_HOLD_RX_FIFO_FULL: 2212 * BitOffset : 8 2213 * BitWidth : 1 2214 * AccessType: RO 2215 * ResetValue: (uint32_t)0x0 2216 */ 2217 SEDI_RBF_DEFINE(I2C, STATUS, MST_HOLD_RX_FIFO_FULL, 8, 1, RO, (uint32_t)0x0); 2218 SEDI_RBFV_DEFINE(I2C, STATUS, MST_HOLD_RX_FIFO_FULL, ACTIVE, 0x1); 2219 SEDI_RBFV_DEFINE(I2C, STATUS, MST_HOLD_RX_FIFO_FULL, INACTIVE, 0x0); 2220 2221 /* 2222 * Bit Field of Register STATUS 2223 * SLV_HOLD_TX_FIFO_EMPTY: 2224 * BitOffset : 9 2225 * BitWidth : 1 2226 * AccessType: RO 2227 * ResetValue: (uint32_t)0x0 2228 */ 2229 SEDI_RBF_DEFINE(I2C, STATUS, SLV_HOLD_TX_FIFO_EMPTY, 9, 1, RO, (uint32_t)0x0); 2230 SEDI_RBFV_DEFINE(I2C, STATUS, SLV_HOLD_TX_FIFO_EMPTY, ACTIVE, 0x1); 2231 SEDI_RBFV_DEFINE(I2C, STATUS, SLV_HOLD_TX_FIFO_EMPTY, INACTIVE, 0x0); 2232 2233 /* 2234 * Bit Field of Register STATUS 2235 * SLV_HOLD_RX_FIFO_FULL: 2236 * BitOffset : 10 2237 * BitWidth : 1 2238 * AccessType: RO 2239 * ResetValue: (uint32_t)0x0 2240 */ 2241 SEDI_RBF_DEFINE(I2C, STATUS, SLV_HOLD_RX_FIFO_FULL, 10, 1, RO, (uint32_t)0x0); 2242 SEDI_RBFV_DEFINE(I2C, STATUS, SLV_HOLD_RX_FIFO_FULL, ACTIVE, 0x1); 2243 SEDI_RBFV_DEFINE(I2C, STATUS, SLV_HOLD_RX_FIFO_FULL, INACTIVE, 0x0); 2244 2245 /* 2246 * Bit Field of Register STATUS 2247 * SDA_STUCK_NOT_RECOVERED: 2248 * BitOffset : 11 2249 * BitWidth : 1 2250 * AccessType: RO 2251 * ResetValue: (uint32_t)0x0 2252 */ 2253 SEDI_RBF_DEFINE(I2C, STATUS, SDA_STUCK_NOT_RECOVERED, 11, 1, RO, (uint32_t)0x0); 2254 SEDI_RBFV_DEFINE(I2C, STATUS, SDA_STUCK_NOT_RECOVERED, ACTIVE, 0x1); 2255 SEDI_RBFV_DEFINE(I2C, STATUS, SDA_STUCK_NOT_RECOVERED, INACTIVE, 0x0); 2256 2257 /* 2258 * Bit Field of Register STATUS 2259 * RSVD_SLV_ISO_SAR_DATA_CLK_STRETCH: 2260 * BitOffset : 12 2261 * BitWidth : 1 2262 * AccessType: RO 2263 * ResetValue: (uint32_t)0x0 2264 */ 2265 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SLV_ISO_SAR_DATA_CLK_STRETCH, 12, 1, RO, (uint32_t)0x0); 2266 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SLV_ISO_SAR_DATA_CLK_STRETCH, 0, 0); 2267 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SLV_ISO_SAR_DATA_CLK_STRETCH, 1, 1); 2268 2269 /* 2270 * Bit Field of Register STATUS 2271 * RSVD_IC_STATUS_1: 2272 * BitOffset : 13 2273 * BitWidth : 3 2274 * AccessType: RO 2275 * ResetValue: (uint32_t)0x0 2276 */ 2277 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_IC_STATUS_1, 13, 3, RO, (uint32_t)0x0); 2278 2279 /* 2280 * Bit Field of Register STATUS 2281 * RSVD_SMBUS_QUICK_CMD_BIT: 2282 * BitOffset : 16 2283 * BitWidth : 1 2284 * AccessType: RO 2285 * ResetValue: (uint32_t)0x0 2286 */ 2287 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_QUICK_CMD_BIT, 16, 1, RO, (uint32_t)0x0); 2288 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_QUICK_CMD_BIT, 0, 0); 2289 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_QUICK_CMD_BIT, 1, 1); 2290 2291 /* 2292 * Bit Field of Register STATUS 2293 * RSVD_SMBUS_SLAVE_ADDR_VALID: 2294 * BitOffset : 17 2295 * BitWidth : 1 2296 * AccessType: RO 2297 * ResetValue: (uint32_t)0x0 2298 */ 2299 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR_VALID, 17, 1, RO, (uint32_t)0x0); 2300 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR_VALID, 0, 0); 2301 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR_VALID, 1, 1); 2302 2303 /* 2304 * Bit Field of Register STATUS 2305 * RSVD_SMBUS_SLAVE_ADDR_RESOLVED: 2306 * BitOffset : 18 2307 * BitWidth : 1 2308 * AccessType: RO 2309 * ResetValue: (uint32_t)0x0 2310 */ 2311 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR_RESOLVED, 18, 1, RO, (uint32_t)0x0); 2312 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR_RESOLVED, 0, 0); 2313 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR_RESOLVED, 1, 1); 2314 2315 /* 2316 * Bit Field of Register STATUS 2317 * RSVD_SMBUS_SUSPEND_STATUS: 2318 * BitOffset : 19 2319 * BitWidth : 1 2320 * AccessType: RO 2321 * ResetValue: (uint32_t)0x0 2322 */ 2323 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SUSPEND_STATUS, 19, 1, RO, (uint32_t)0x0); 2324 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SUSPEND_STATUS, 0, 0); 2325 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SUSPEND_STATUS, 1, 1); 2326 2327 /* 2328 * Bit Field of Register STATUS 2329 * RSVD_SMBUS_ALERT_STATUS: 2330 * BitOffset : 20 2331 * BitWidth : 1 2332 * AccessType: RO 2333 * ResetValue: (uint32_t)0x0 2334 */ 2335 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_ALERT_STATUS, 20, 1, RO, (uint32_t)0x0); 2336 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_ALERT_STATUS, 0, 0); 2337 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_ALERT_STATUS, 1, 1); 2338 2339 /* 2340 * Bit Field of Register STATUS 2341 * RSVD_SMBUS_SLAVE_ADDR2_VALID: 2342 * BitOffset : 21 2343 * BitWidth : 1 2344 * AccessType: RO 2345 * ResetValue: (uint32_t)0x0 2346 */ 2347 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR2_VALID, 21, 1, RO, (uint32_t)0x0); 2348 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR2_VALID, 0, 0); 2349 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR2_VALID, 1, 1); 2350 2351 /* 2352 * Bit Field of Register STATUS 2353 * RSVD_SMBUS_SLAVE_ADDR2_RESOLVED: 2354 * BitOffset : 22 2355 * BitWidth : 1 2356 * AccessType: RO 2357 * ResetValue: (uint32_t)0x0 2358 */ 2359 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR2_RESOLVED, 22, 1, RO, (uint32_t)0x0); 2360 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR2_RESOLVED, 0, 0); 2361 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR2_RESOLVED, 1, 1); 2362 2363 /* 2364 * Bit Field of Register STATUS 2365 * RSVD_SMBUS_SLAVE_ADDR3_VALID: 2366 * BitOffset : 23 2367 * BitWidth : 1 2368 * AccessType: RO 2369 * ResetValue: (uint32_t)0x0 2370 */ 2371 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR3_VALID, 23, 1, RO, (uint32_t)0x0); 2372 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR3_VALID, 0, 0); 2373 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR3_VALID, 1, 1); 2374 2375 /* 2376 * Bit Field of Register STATUS 2377 * RSVD_SMBUS_SLAVE_ADDR3_RESOLVED: 2378 * BitOffset : 24 2379 * BitWidth : 1 2380 * AccessType: RO 2381 * ResetValue: (uint32_t)0x0 2382 */ 2383 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR3_RESOLVED, 24, 1, RO, (uint32_t)0x0); 2384 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR3_RESOLVED, 0, 0); 2385 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR3_RESOLVED, 1, 1); 2386 2387 /* 2388 * Bit Field of Register STATUS 2389 * RSVD_SMBUS_SLAVE_ADDR4_VALID: 2390 * BitOffset : 25 2391 * BitWidth : 1 2392 * AccessType: RO 2393 * ResetValue: (uint32_t)0x0 2394 */ 2395 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR4_VALID, 25, 1, RO, (uint32_t)0x0); 2396 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR4_VALID, 0, 0); 2397 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR4_VALID, 1, 1); 2398 2399 /* 2400 * Bit Field of Register STATUS 2401 * RSVD_SMBUS_SLAVE_ADDR4_RESOLVED: 2402 * BitOffset : 26 2403 * BitWidth : 1 2404 * AccessType: RO 2405 * ResetValue: (uint32_t)0x0 2406 */ 2407 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR4_RESOLVED, 26, 1, RO, (uint32_t)0x0); 2408 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR4_RESOLVED, 0, 0); 2409 SEDI_RBFV_DEFINE(I2C, STATUS, RSVD_SMBUS_SLAVE_ADDR4_RESOLVED, 1, 1); 2410 2411 /* 2412 * Bit Field of Register STATUS 2413 * RSVD_IC_STATUS_2: 2414 * BitOffset : 27 2415 * BitWidth : 5 2416 * AccessType: RO 2417 * ResetValue: (uint32_t)0x0 2418 */ 2419 SEDI_RBF_DEFINE(I2C, STATUS, RSVD_IC_STATUS_2, 27, 5, RO, (uint32_t)0x0); 2420 2421 /* ********* I2C TXFLR *********** 2422 * 2423 * Register of SEDI I2C 2424 * TXFLR: I2C Transmit FIFO Level Register 2425 * AddressOffset : 0x74 2426 * AccessType : RO 2427 * WritableBitMask: 0x0 2428 * ResetValue : (uint32_t)0x0 2429 */ 2430 SEDI_REG_DEFINE(I2C, TXFLR, 0x74, RO, (uint32_t)0x0, (uint32_t)0x0); 2431 2432 /* 2433 * Bit Field of Register TXFLR 2434 * TXFLR: 2435 * BitOffset : 0 2436 * BitWidth : 7 2437 * AccessType: RO 2438 * ResetValue: (uint32_t)0x0 2439 */ 2440 SEDI_RBF_DEFINE(I2C, TXFLR, TXFLR, 0, 7, RO, (uint32_t)0x0); 2441 2442 /* 2443 * Bit Field of Register TXFLR 2444 * RSVD_TXFLR: 2445 * BitOffset : 7 2446 * BitWidth : 25 2447 * AccessType: RO 2448 * ResetValue: (uint32_t)0x0 2449 */ 2450 SEDI_RBF_DEFINE(I2C, TXFLR, RSVD_TXFLR, 7, 25, RO, (uint32_t)0x0); 2451 2452 /* ********* I2C RXFLR *********** 2453 * 2454 * Register of SEDI I2C 2455 * RXFLR: I2C Receive FIFO Level Register 2456 * AddressOffset : 0x78 2457 * AccessType : RO 2458 * WritableBitMask: 0x0 2459 * ResetValue : (uint32_t)0x0 2460 */ 2461 SEDI_REG_DEFINE(I2C, RXFLR, 0x78, RO, (uint32_t)0x0, (uint32_t)0x0); 2462 2463 /* 2464 * Bit Field of Register RXFLR 2465 * RXFLR: 2466 * BitOffset : 0 2467 * BitWidth : 7 2468 * AccessType: RO 2469 * ResetValue: (uint32_t)0x0 2470 */ 2471 SEDI_RBF_DEFINE(I2C, RXFLR, RXFLR, 0, 7, RO, (uint32_t)0x0); 2472 2473 /* 2474 * Bit Field of Register RXFLR 2475 * RSVD_RXFLR: 2476 * BitOffset : 7 2477 * BitWidth : 25 2478 * AccessType: RO 2479 * ResetValue: (uint32_t)0x0 2480 */ 2481 SEDI_RBF_DEFINE(I2C, RXFLR, RSVD_RXFLR, 7, 25, RO, (uint32_t)0x0); 2482 2483 /* ********* I2C SDA_HOLD *********** 2484 * 2485 * Register of SEDI I2C 2486 * SDA_HOLD: I2C SDA Hold Time Length Register 2487 * AddressOffset : 0x7c 2488 * AccessType : RW 2489 * WritableBitMask: 0xffffff 2490 * ResetValue : (uint32_t)0x5 2491 */ 2492 SEDI_REG_DEFINE(I2C, SDA_HOLD, 0x7c, RW, (uint32_t)0xffffff, (uint32_t)0x5); 2493 2494 /* 2495 * Bit Field of Register SDA_HOLD 2496 * IC_SDA_TX_HOLD: 2497 * BitOffset : 0 2498 * BitWidth : 16 2499 * AccessType: RW 2500 * ResetValue: (uint32_t)0x5 2501 */ 2502 SEDI_RBF_DEFINE(I2C, SDA_HOLD, IC_SDA_TX_HOLD, 0, 16, RW, (uint32_t)0x5); 2503 2504 /* 2505 * Bit Field of Register SDA_HOLD 2506 * IC_SDA_RX_HOLD: 2507 * BitOffset : 16 2508 * BitWidth : 8 2509 * AccessType: RW 2510 * ResetValue: (uint32_t)0x0 2511 */ 2512 SEDI_RBF_DEFINE(I2C, SDA_HOLD, IC_SDA_RX_HOLD, 16, 8, RW, (uint32_t)0x0); 2513 2514 /* 2515 * Bit Field of Register SDA_HOLD 2516 * RSVD_IC_SDA_HOLD: 2517 * BitOffset : 24 2518 * BitWidth : 8 2519 * AccessType: RO 2520 * ResetValue: (uint32_t)0x0 2521 */ 2522 SEDI_RBF_DEFINE(I2C, SDA_HOLD, RSVD_IC_SDA_HOLD, 24, 8, RO, (uint32_t)0x0); 2523 2524 /* ********* I2C TX_ABRT_SOURCE *********** 2525 * 2526 * Register of SEDI I2C 2527 * TX_ABRT_SOURCE: I2C Transmit Abort Source Register 2528 * AddressOffset : 0x80 2529 * AccessType : RO 2530 * WritableBitMask: 0x0 2531 * ResetValue : (uint32_t)0x0 2532 */ 2533 SEDI_REG_DEFINE(I2C, TX_ABRT_SOURCE, 0x80, RO, (uint32_t)0x0, (uint32_t)0x0); 2534 2535 /* 2536 * Bit Field of Register TX_ABRT_SOURCE 2537 * ABRT_7B_ADDR_NOACK: 2538 * BitOffset : 0 2539 * BitWidth : 1 2540 * AccessType: RO 2541 * ResetValue: (uint32_t)0x0 2542 */ 2543 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_7B_ADDR_NOACK, 0, 1, RO, (uint32_t)0x0); 2544 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_7B_ADDR_NOACK, ACTIVE, 0x1); 2545 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_7B_ADDR_NOACK, INACTIVE, 0x0); 2546 2547 /* 2548 * Bit Field of Register TX_ABRT_SOURCE 2549 * ABRT_10ADDR1_NOACK: 2550 * BitOffset : 1 2551 * BitWidth : 1 2552 * AccessType: RO 2553 * ResetValue: (uint32_t)0x0 2554 */ 2555 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10ADDR1_NOACK, 1, 1, RO, (uint32_t)0x0); 2556 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10ADDR1_NOACK, ACTIVE, 0x1); 2557 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10ADDR1_NOACK, INACTIVE, 0x0); 2558 2559 /* 2560 * Bit Field of Register TX_ABRT_SOURCE 2561 * ABRT_10ADDR2_NOACK: 2562 * BitOffset : 2 2563 * BitWidth : 1 2564 * AccessType: RO 2565 * ResetValue: (uint32_t)0x0 2566 */ 2567 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10ADDR2_NOACK, 2, 1, RO, (uint32_t)0x0); 2568 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10ADDR2_NOACK, ACTIVE, 0x1); 2569 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10ADDR2_NOACK, INACTIVE, 0x0); 2570 2571 /* 2572 * Bit Field of Register TX_ABRT_SOURCE 2573 * ABRT_TXDATA_NOACK: 2574 * BitOffset : 3 2575 * BitWidth : 1 2576 * AccessType: RO 2577 * ResetValue: (uint32_t)0x0 2578 */ 2579 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_TXDATA_NOACK, 3, 1, RO, (uint32_t)0x0); 2580 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_TXDATA_NOACK, ABRT_TXDATA_NOACK_GENERATED, 0x1); 2581 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_TXDATA_NOACK, ABRT_TXDATA_NOACK_VOID, 0x0); 2582 2583 /* 2584 * Bit Field of Register TX_ABRT_SOURCE 2585 * ABRT_GCALL_NOACK: 2586 * BitOffset : 4 2587 * BitWidth : 1 2588 * AccessType: RO 2589 * ResetValue: (uint32_t)0x0 2590 */ 2591 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_GCALL_NOACK, 4, 1, RO, (uint32_t)0x0); 2592 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_GCALL_NOACK, ABRT_GCALL_NOACK_GENERATED, 0x1); 2593 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_GCALL_NOACK, ABRT_GCALL_NOACK_VOID, 0x0); 2594 2595 /* 2596 * Bit Field of Register TX_ABRT_SOURCE 2597 * ABRT_GCALL_READ: 2598 * BitOffset : 5 2599 * BitWidth : 1 2600 * AccessType: RO 2601 * ResetValue: (uint32_t)0x0 2602 */ 2603 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_GCALL_READ, 5, 1, RO, (uint32_t)0x0); 2604 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_GCALL_READ, ABRT_GCALL_READ_GENERATED, 0x1); 2605 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_GCALL_READ, ABRT_GCALL_READ_VOID, 0x0); 2606 2607 /* 2608 * Bit Field of Register TX_ABRT_SOURCE 2609 * ABRT_HS_ACKDET: 2610 * BitOffset : 6 2611 * BitWidth : 1 2612 * AccessType: RO 2613 * ResetValue: (uint32_t)0x0 2614 */ 2615 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_HS_ACKDET, 6, 1, RO, (uint32_t)0x0); 2616 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_HS_ACKDET, ABRT_HS_ACK_GENERATED, 0x1); 2617 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_HS_ACKDET, ABRT_HS_ACK_VOID, 0x0); 2618 2619 /* 2620 * Bit Field of Register TX_ABRT_SOURCE 2621 * ABRT_SBYTE_ACKDET: 2622 * BitOffset : 7 2623 * BitWidth : 1 2624 * AccessType: RO 2625 * ResetValue: (uint32_t)0x0 2626 */ 2627 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SBYTE_ACKDET, 7, 1, RO, (uint32_t)0x0); 2628 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SBYTE_ACKDET, ABRT_SBYTE_ACKDET_GENERATED, 0x1); 2629 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SBYTE_ACKDET, ABRT_SBYTE_ACKDET_VOID, 0x0); 2630 2631 /* 2632 * Bit Field of Register TX_ABRT_SOURCE 2633 * ABRT_HS_NORSTRT: 2634 * BitOffset : 8 2635 * BitWidth : 1 2636 * AccessType: RO 2637 * ResetValue: (uint32_t)0x0 2638 */ 2639 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_HS_NORSTRT, 8, 1, RO, (uint32_t)0x0); 2640 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_HS_NORSTRT, ABRT_HS_NORSTRT_GENERATED, 0x1); 2641 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_HS_NORSTRT, ABRT_HS_NORSTRT_VOID, 0x0); 2642 2643 /* 2644 * Bit Field of Register TX_ABRT_SOURCE 2645 * ABRT_SBYTE_NORSTRT: 2646 * BitOffset : 9 2647 * BitWidth : 1 2648 * AccessType: RO 2649 * ResetValue: (uint32_t)0x0 2650 */ 2651 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SBYTE_NORSTRT, 9, 1, RO, (uint32_t)0x0); 2652 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SBYTE_NORSTRT, ABRT_SBYTE_NORSTRT_GENERATED, 0x1); 2653 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SBYTE_NORSTRT, ABRT_SBYTE_NORSTRT_VOID, 0x0); 2654 2655 /* 2656 * Bit Field of Register TX_ABRT_SOURCE 2657 * ABRT_10B_RD_NORSTRT: 2658 * BitOffset : 10 2659 * BitWidth : 1 2660 * AccessType: RO 2661 * ResetValue: (uint32_t)0x0 2662 */ 2663 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10B_RD_NORSTRT, 10, 1, RO, (uint32_t)0x0); 2664 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10B_RD_NORSTRT, ABRT_10B_RD_GENERATED, 0x1); 2665 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_10B_RD_NORSTRT, ABRT_10B_RD_VOID, 0x0); 2666 2667 /* 2668 * Bit Field of Register TX_ABRT_SOURCE 2669 * ABRT_MASTER_DIS: 2670 * BitOffset : 11 2671 * BitWidth : 1 2672 * AccessType: RO 2673 * ResetValue: (uint32_t)0x0 2674 */ 2675 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_MASTER_DIS, 11, 1, RO, (uint32_t)0x0); 2676 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_MASTER_DIS, ABRT_MASTER_DIS_GENERATED, 0x1); 2677 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_MASTER_DIS, ABRT_MASTER_DIS_VOID, 0x0); 2678 2679 /* 2680 * Bit Field of Register TX_ABRT_SOURCE 2681 * ARB_LOST: 2682 * BitOffset : 12 2683 * BitWidth : 1 2684 * AccessType: RO 2685 * ResetValue: (uint32_t)0x0 2686 */ 2687 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ARB_LOST, 12, 1, RO, (uint32_t)0x0); 2688 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ARB_LOST, ABRT_LOST_GENERATED, 0x1); 2689 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ARB_LOST, ABRT_LOST_VOID, 0x0); 2690 2691 /* 2692 * Bit Field of Register TX_ABRT_SOURCE 2693 * ABRT_SLVFLUSH_TXFIFO: 2694 * BitOffset : 13 2695 * BitWidth : 1 2696 * AccessType: RO 2697 * ResetValue: (uint32_t)0x0 2698 */ 2699 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLVFLUSH_TXFIFO, 13, 1, RO, (uint32_t)0x0); 2700 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLVFLUSH_TXFIFO, ABRT_SLVFLUSH_TXFIFO_GENERATED, 0x1); 2701 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLVFLUSH_TXFIFO, ABRT_SLVFLUSH_TXFIFO_VOID, 0x0); 2702 2703 /* 2704 * Bit Field of Register TX_ABRT_SOURCE 2705 * ABRT_SLV_ARBLOST: 2706 * BitOffset : 14 2707 * BitWidth : 1 2708 * AccessType: RO 2709 * ResetValue: (uint32_t)0x0 2710 */ 2711 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLV_ARBLOST, 14, 1, RO, (uint32_t)0x0); 2712 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLV_ARBLOST, ABRT_SLV_ARBLOST_GENERATED, 0x1); 2713 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLV_ARBLOST, ABRT_SLV_ARBLOST_VOID, 0x0); 2714 2715 /* 2716 * Bit Field of Register TX_ABRT_SOURCE 2717 * ABRT_SLVRD_INTX: 2718 * BitOffset : 15 2719 * BitWidth : 1 2720 * AccessType: RO 2721 * ResetValue: (uint32_t)0x0 2722 */ 2723 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLVRD_INTX, 15, 1, RO, (uint32_t)0x0); 2724 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLVRD_INTX, ABRT_SLVRD_INTX_GENERATED, 0x1); 2725 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SLVRD_INTX, ABRT_SLVRD_INTX_VOID, 0x0); 2726 2727 /* 2728 * Bit Field of Register TX_ABRT_SOURCE 2729 * ABRT_USER_ABRT: 2730 * BitOffset : 16 2731 * BitWidth : 1 2732 * AccessType: RO 2733 * ResetValue: (uint32_t)0x0 2734 */ 2735 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_USER_ABRT, 16, 1, RO, (uint32_t)0x0); 2736 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_USER_ABRT, ABRT_USER_ABRT_GENERATED, 0x1); 2737 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_USER_ABRT, ABRT_USER_ABRT_VOID, 0x0); 2738 2739 /* 2740 * Bit Field of Register TX_ABRT_SOURCE 2741 * ABRT_SDA_STUCK_AT_LOW: 2742 * BitOffset : 17 2743 * BitWidth : 1 2744 * AccessType: RO 2745 * ResetValue: (uint32_t)0x0 2746 */ 2747 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SDA_STUCK_AT_LOW, 17, 1, RO, (uint32_t)0x0); 2748 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SDA_STUCK_AT_LOW, ACTIVE, 0x1); 2749 SEDI_RBFV_DEFINE(I2C, TX_ABRT_SOURCE, ABRT_SDA_STUCK_AT_LOW, INACTIVE, 0x0); 2750 2751 /* 2752 * Bit Field of Register TX_ABRT_SOURCE 2753 * RSVD_ABRT_DEVICE_WRITE: 2754 * BitOffset : 18 2755 * BitWidth : 3 2756 * AccessType: RO 2757 * ResetValue: (uint32_t)0x0 2758 */ 2759 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, RSVD_ABRT_DEVICE_WRITE, 18, 3, RO, (uint32_t)0x0); 2760 2761 /* 2762 * Bit Field of Register TX_ABRT_SOURCE 2763 * RSVD_IC_TX_ABRT_SOURCE: 2764 * BitOffset : 21 2765 * BitWidth : 2 2766 * AccessType: RO 2767 * ResetValue: (uint32_t)0x0 2768 */ 2769 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, RSVD_IC_TX_ABRT_SOURCE, 21, 2, RO, (uint32_t)0x0); 2770 2771 /* 2772 * Bit Field of Register TX_ABRT_SOURCE 2773 * TX_FLUSH_CNT: 2774 * BitOffset : 23 2775 * BitWidth : 9 2776 * AccessType: RO 2777 * ResetValue: (uint32_t)0x0 2778 */ 2779 SEDI_RBF_DEFINE(I2C, TX_ABRT_SOURCE, TX_FLUSH_CNT, 23, 9, RO, (uint32_t)0x0); 2780 2781 /* ********* I2C DMA_CR *********** 2782 * 2783 * Register of SEDI I2C 2784 * DMA_CR: DMA Control Register 2785 * AddressOffset : 0x88 2786 * AccessType : RW 2787 * WritableBitMask: 0x3 2788 * ResetValue : (uint32_t)0x0 2789 */ 2790 SEDI_REG_DEFINE(I2C, DMA_CR, 0x88, RW, (uint32_t)0x3, (uint32_t)0x0); 2791 2792 /* 2793 * Bit Field of Register DMA_CR 2794 * RDMAE: 2795 * BitOffset : 0 2796 * BitWidth : 1 2797 * AccessType: RW 2798 * ResetValue: (uint32_t)0x0 2799 */ 2800 SEDI_RBF_DEFINE(I2C, DMA_CR, RDMAE, 0, 1, RW, (uint32_t)0x0); 2801 SEDI_RBFV_DEFINE(I2C, DMA_CR, RDMAE, DISABLED, 0x0); 2802 SEDI_RBFV_DEFINE(I2C, DMA_CR, RDMAE, ENABLED, 0x1); 2803 2804 /* 2805 * Bit Field of Register DMA_CR 2806 * TDMAE: 2807 * BitOffset : 1 2808 * BitWidth : 1 2809 * AccessType: RW 2810 * ResetValue: (uint32_t)0x0 2811 */ 2812 SEDI_RBF_DEFINE(I2C, DMA_CR, TDMAE, 1, 1, RW, (uint32_t)0x0); 2813 SEDI_RBFV_DEFINE(I2C, DMA_CR, TDMAE, DISABLED, 0x0); 2814 SEDI_RBFV_DEFINE(I2C, DMA_CR, TDMAE, ENABLED, 0x1); 2815 2816 /* 2817 * Bit Field of Register DMA_CR 2818 * RSVD_IC_DMA_CR_2_31: 2819 * BitOffset : 2 2820 * BitWidth : 30 2821 * AccessType: RO 2822 * ResetValue: (uint32_t)0x0 2823 */ 2824 SEDI_RBF_DEFINE(I2C, DMA_CR, RSVD_IC_DMA_CR_2_31, 2, 30, RO, (uint32_t)0x0); 2825 2826 /* ********* I2C DMA_TDLR *********** 2827 * 2828 * Register of SEDI I2C 2829 * DMA_TDLR: DMA Transmit Data Level Register 2830 * AddressOffset : 0x8c 2831 * AccessType : RW 2832 * WritableBitMask: 0x3f 2833 * ResetValue : (uint32_t)0x0 2834 */ 2835 SEDI_REG_DEFINE(I2C, DMA_TDLR, 0x8c, RW, (uint32_t)0x3f, (uint32_t)0x0); 2836 2837 /* 2838 * Bit Field of Register DMA_TDLR 2839 * DMATDL: 2840 * BitOffset : 0 2841 * BitWidth : 6 2842 * AccessType: RW 2843 * ResetValue: (uint32_t)0x0 2844 */ 2845 SEDI_RBF_DEFINE(I2C, DMA_TDLR, DMATDL, 0, 6, RW, (uint32_t)0x0); 2846 2847 /* 2848 * Bit Field of Register DMA_TDLR 2849 * RSVD_DMA_TDLR: 2850 * BitOffset : 6 2851 * BitWidth : 26 2852 * AccessType: RO 2853 * ResetValue: (uint32_t)0x0 2854 */ 2855 SEDI_RBF_DEFINE(I2C, DMA_TDLR, RSVD_DMA_TDLR, 6, 26, RO, (uint32_t)0x0); 2856 2857 /* ********* I2C DMA_RDLR *********** 2858 * 2859 * Register of SEDI I2C 2860 * DMA_RDLR: DMA Receive Data Level Register 2861 * AddressOffset : 0x90 2862 * AccessType : RW 2863 * WritableBitMask: 0x3f 2864 * ResetValue : (uint32_t)0x0 2865 */ 2866 SEDI_REG_DEFINE(I2C, DMA_RDLR, 0x90, RW, (uint32_t)0x3f, (uint32_t)0x0); 2867 2868 /* 2869 * Bit Field of Register DMA_RDLR 2870 * DMARDL: 2871 * BitOffset : 0 2872 * BitWidth : 6 2873 * AccessType: RW 2874 * ResetValue: (uint32_t)0x0 2875 */ 2876 SEDI_RBF_DEFINE(I2C, DMA_RDLR, DMARDL, 0, 6, RW, (uint32_t)0x0); 2877 2878 /* 2879 * Bit Field of Register DMA_RDLR 2880 * RSVD_DMA_RDLR: 2881 * BitOffset : 6 2882 * BitWidth : 26 2883 * AccessType: RO 2884 * ResetValue: (uint32_t)0x0 2885 */ 2886 SEDI_RBF_DEFINE(I2C, DMA_RDLR, RSVD_DMA_RDLR, 6, 26, RO, (uint32_t)0x0); 2887 2888 /* ********* I2C SDA_SETUP *********** 2889 * 2890 * Register of SEDI I2C 2891 * SDA_SETUP: I2C SDA Setup Register 2892 * AddressOffset : 0x94 2893 * AccessType : RW 2894 * WritableBitMask: 0xff 2895 * ResetValue : (uint32_t)0x2 2896 */ 2897 SEDI_REG_DEFINE(I2C, SDA_SETUP, 0x94, RW, (uint32_t)0xff, (uint32_t)0x2); 2898 2899 /* 2900 * Bit Field of Register SDA_SETUP 2901 * SDA_SETUP: 2902 * BitOffset : 0 2903 * BitWidth : 8 2904 * AccessType: RW 2905 * ResetValue: (uint32_t)0x2 2906 */ 2907 SEDI_RBF_DEFINE(I2C, SDA_SETUP, SDA_SETUP, 0, 8, RW, (uint32_t)0x2); 2908 2909 /* 2910 * Bit Field of Register SDA_SETUP 2911 * RSVD_IC_SDA_SETUP: 2912 * BitOffset : 8 2913 * BitWidth : 24 2914 * AccessType: RO 2915 * ResetValue: (uint32_t)0x0 2916 */ 2917 SEDI_RBF_DEFINE(I2C, SDA_SETUP, RSVD_IC_SDA_SETUP, 8, 24, RO, (uint32_t)0x0); 2918 2919 /* ********* I2C ACK_GENERAL_CALL *********** 2920 * 2921 * Register of SEDI I2C 2922 * ACK_GENERAL_CALL: I2C ACK General Call Register 2923 * AddressOffset : 0x98 2924 * AccessType : RW 2925 * WritableBitMask: 0x1 2926 * ResetValue : (uint32_t)0x0 2927 */ 2928 SEDI_REG_DEFINE(I2C, ACK_GENERAL_CALL, 0x98, RW, (uint32_t)0x1, (uint32_t)0x0); 2929 2930 /* 2931 * Bit Field of Register ACK_GENERAL_CALL 2932 * ACK_GEN_CALL: 2933 * BitOffset : 0 2934 * BitWidth : 1 2935 * AccessType: RW 2936 * ResetValue: (uint32_t)0x0 2937 */ 2938 SEDI_RBF_DEFINE(I2C, ACK_GENERAL_CALL, ACK_GEN_CALL, 0, 1, RW, (uint32_t)0x0); 2939 SEDI_RBFV_DEFINE(I2C, ACK_GENERAL_CALL, ACK_GEN_CALL, DISABLED, 0x0); 2940 SEDI_RBFV_DEFINE(I2C, ACK_GENERAL_CALL, ACK_GEN_CALL, ENABLED, 0x1); 2941 2942 /* 2943 * Bit Field of Register ACK_GENERAL_CALL 2944 * RSVD_IC_ACK_GEN_1_31: 2945 * BitOffset : 1 2946 * BitWidth : 31 2947 * AccessType: RO 2948 * ResetValue: (uint32_t)0x0 2949 */ 2950 SEDI_RBF_DEFINE(I2C, ACK_GENERAL_CALL, RSVD_IC_ACK_GEN_1_31, 1, 31, RO, (uint32_t)0x0); 2951 2952 /* ********* I2C ENABLE_STATUS *********** 2953 * 2954 * Register of SEDI I2C 2955 * ENABLE_STATUS: I2C Enable Status Register 2956 * AddressOffset : 0x9c 2957 * AccessType : RO 2958 * WritableBitMask: 0x0 2959 * ResetValue : (uint32_t)0x0 2960 */ 2961 SEDI_REG_DEFINE(I2C, ENABLE_STATUS, 0x9c, RO, (uint32_t)0x0, (uint32_t)0x0); 2962 2963 /* 2964 * Bit Field of Register ENABLE_STATUS 2965 * IC_EN: 2966 * BitOffset : 0 2967 * BitWidth : 1 2968 * AccessType: RO 2969 * ResetValue: (uint32_t)0x0 2970 */ 2971 SEDI_RBF_DEFINE(I2C, ENABLE_STATUS, IC_EN, 0, 1, RO, (uint32_t)0x0); 2972 SEDI_RBFV_DEFINE(I2C, ENABLE_STATUS, IC_EN, DISABLED, 0x0); 2973 SEDI_RBFV_DEFINE(I2C, ENABLE_STATUS, IC_EN, ENABLED, 0x1); 2974 2975 /* 2976 * Bit Field of Register ENABLE_STATUS 2977 * SLV_DISABLED_WHILE_BUSY: 2978 * BitOffset : 1 2979 * BitWidth : 1 2980 * AccessType: RO 2981 * ResetValue: (uint32_t)0x0 2982 */ 2983 SEDI_RBF_DEFINE(I2C, ENABLE_STATUS, SLV_DISABLED_WHILE_BUSY, 1, 1, RO, (uint32_t)0x0); 2984 SEDI_RBFV_DEFINE(I2C, ENABLE_STATUS, SLV_DISABLED_WHILE_BUSY, ACTIVE, 0x1); 2985 SEDI_RBFV_DEFINE(I2C, ENABLE_STATUS, SLV_DISABLED_WHILE_BUSY, INACTIVE, 0x0); 2986 2987 /* 2988 * Bit Field of Register ENABLE_STATUS 2989 * SLV_RX_DATA_LOST: 2990 * BitOffset : 2 2991 * BitWidth : 1 2992 * AccessType: RO 2993 * ResetValue: (uint32_t)0x0 2994 */ 2995 SEDI_RBF_DEFINE(I2C, ENABLE_STATUS, SLV_RX_DATA_LOST, 2, 1, RO, (uint32_t)0x0); 2996 SEDI_RBFV_DEFINE(I2C, ENABLE_STATUS, SLV_RX_DATA_LOST, ACTIVE, 0x1); 2997 SEDI_RBFV_DEFINE(I2C, ENABLE_STATUS, SLV_RX_DATA_LOST, INACTIVE, 0x0); 2998 2999 /* 3000 * Bit Field of Register ENABLE_STATUS 3001 * RSVD_IC_ENABLE_STATUS: 3002 * BitOffset : 3 3003 * BitWidth : 29 3004 * AccessType: RO 3005 * ResetValue: (uint32_t)0x0 3006 */ 3007 SEDI_RBF_DEFINE(I2C, ENABLE_STATUS, RSVD_IC_ENABLE_STATUS, 3, 29, RO, (uint32_t)0x0); 3008 3009 /* ********* I2C FS_SPKLEN *********** 3010 * 3011 * Register of SEDI I2C 3012 * FS_SPKLEN: I2C SS, FS or FM+ spike suppression limit 3013 * AddressOffset : 0xa0 3014 * AccessType : RW 3015 * WritableBitMask: 0xff 3016 * ResetValue : (uint32_t)0x5 3017 */ 3018 SEDI_REG_DEFINE(I2C, FS_SPKLEN, 0xa0, RW, (uint32_t)0xff, (uint32_t)0x5); 3019 3020 /* 3021 * Bit Field of Register FS_SPKLEN 3022 * IC_FS_SPKLEN: 3023 * BitOffset : 0 3024 * BitWidth : 8 3025 * AccessType: RW 3026 * ResetValue: (uint32_t)0x5 3027 */ 3028 SEDI_RBF_DEFINE(I2C, FS_SPKLEN, IC_FS_SPKLEN, 0, 8, RW, (uint32_t)0x5); 3029 3030 /* 3031 * Bit Field of Register FS_SPKLEN 3032 * RSVD_IC_FS_SPKLEN: 3033 * BitOffset : 8 3034 * BitWidth : 24 3035 * AccessType: RO 3036 * ResetValue: (uint32_t)0x0 3037 */ 3038 SEDI_RBF_DEFINE(I2C, FS_SPKLEN, RSVD_IC_FS_SPKLEN, 8, 24, RO, (uint32_t)0x0); 3039 3040 /* ********* I2C HS_SPKLEN *********** 3041 * 3042 * Register of SEDI I2C 3043 * HS_SPKLEN: I2C HS spike suppression limit register 3044 * AddressOffset : 0xa4 3045 * AccessType : RW 3046 * WritableBitMask: 0xff 3047 * ResetValue : (uint32_t)0x2 3048 */ 3049 SEDI_REG_DEFINE(I2C, HS_SPKLEN, 0xa4, RW, (uint32_t)0xff, (uint32_t)0x2); 3050 3051 /* 3052 * Bit Field of Register HS_SPKLEN 3053 * IC_HS_SPKLEN: 3054 * BitOffset : 0 3055 * BitWidth : 8 3056 * AccessType: RW 3057 * ResetValue: (uint32_t)0x2 3058 */ 3059 SEDI_RBF_DEFINE(I2C, HS_SPKLEN, IC_HS_SPKLEN, 0, 8, RW, (uint32_t)0x2); 3060 3061 /* 3062 * Bit Field of Register HS_SPKLEN 3063 * RSVD_IC_HS_SPKLEN: 3064 * BitOffset : 8 3065 * BitWidth : 24 3066 * AccessType: RO 3067 * ResetValue: (uint32_t)0x0 3068 */ 3069 SEDI_RBF_DEFINE(I2C, HS_SPKLEN, RSVD_IC_HS_SPKLEN, 8, 24, RO, (uint32_t)0x0); 3070 3071 /* ********* I2C CLR_RESTART_DET *********** 3072 * 3073 * Register of SEDI I2C 3074 * CLR_RESTART_DET: Clear RESTART_DET Interrupt Register 3075 * AddressOffset : 0xa8 3076 * AccessType : RO 3077 * WritableBitMask: 0x0 3078 * ResetValue : (uint32_t)0x0 3079 */ 3080 SEDI_REG_DEFINE(I2C, CLR_RESTART_DET, 0xa8, RO, (uint32_t)0x0, (uint32_t)0x0); 3081 3082 /* 3083 * Bit Field of Register CLR_RESTART_DET 3084 * CLR_RESTART_DET: 3085 * BitOffset : 0 3086 * BitWidth : 1 3087 * AccessType: RO 3088 * ResetValue: (uint32_t)0x0 3089 */ 3090 SEDI_RBF_DEFINE(I2C, CLR_RESTART_DET, CLR_RESTART_DET, 0, 1, RO, (uint32_t)0x0); 3091 SEDI_RBFV_DEFINE(I2C, CLR_RESTART_DET, CLR_RESTART_DET, 0, 0); 3092 SEDI_RBFV_DEFINE(I2C, CLR_RESTART_DET, CLR_RESTART_DET, 1, 1); 3093 3094 /* 3095 * Bit Field of Register CLR_RESTART_DET 3096 * RSVD_IC_CLR_RESTART_DET: 3097 * BitOffset : 1 3098 * BitWidth : 31 3099 * AccessType: RO 3100 * ResetValue: (uint32_t)0x0 3101 */ 3102 SEDI_RBF_DEFINE(I2C, CLR_RESTART_DET, RSVD_IC_CLR_RESTART_DET, 1, 31, RO, (uint32_t)0x0); 3103 3104 /* ********* I2C SCL_STUCK_AT_LOW_TIMEOUT *********** 3105 * 3106 * Register of SEDI I2C 3107 * SCL_STUCK_AT_LOW_TIMEOUT: I2C SCL Stuck at Low Timeout register 3108 * AddressOffset : 0xac 3109 * AccessType : RW 3110 * WritableBitMask: 0xffffffff 3111 * ResetValue : (uint32_t)-1 3112 */ 3113 SEDI_REG_DEFINE(I2C, SCL_STUCK_AT_LOW_TIMEOUT, 0xac, RW, (uint32_t)0xffffffff, (uint32_t)-1); 3114 3115 /* 3116 * Bit Field of Register SCL_STUCK_AT_LOW_TIMEOUT 3117 * IC_SCL_STUCK_LOW_TIMEOUT: 3118 * BitOffset : 0 3119 * BitWidth : 32 3120 * AccessType: RW 3121 * ResetValue: (uint32_t)-1 3122 */ 3123 SEDI_RBF_DEFINE(I2C, SCL_STUCK_AT_LOW_TIMEOUT, IC_SCL_STUCK_LOW_TIMEOUT, 0, 32, RW, (uint32_t)-1); 3124 3125 /* ********* I2C SDA_STUCK_AT_LOW_TIMEOUT *********** 3126 * 3127 * Register of SEDI I2C 3128 * SDA_STUCK_AT_LOW_TIMEOUT: I2C SDA Stuck at Low Timeout register 3129 * AddressOffset : 0xb0 3130 * AccessType : RW 3131 * WritableBitMask: 0xffffffff 3132 * ResetValue : (uint32_t)-1 3133 */ 3134 SEDI_REG_DEFINE(I2C, SDA_STUCK_AT_LOW_TIMEOUT, 0xb0, RW, (uint32_t)0xffffffff, (uint32_t)-1); 3135 3136 /* 3137 * Bit Field of Register SDA_STUCK_AT_LOW_TIMEOUT 3138 * IC_SDA_STUCK_LOW_TIMEOUT: 3139 * BitOffset : 0 3140 * BitWidth : 32 3141 * AccessType: RW 3142 * ResetValue: (uint32_t)-1 3143 */ 3144 SEDI_RBF_DEFINE(I2C, SDA_STUCK_AT_LOW_TIMEOUT, IC_SDA_STUCK_LOW_TIMEOUT, 0, 32, RW, (uint32_t)-1); 3145 3146 /* ********* I2C CLR_SCL_STUCK_DET *********** 3147 * 3148 * Register of SEDI I2C 3149 * CLR_SCL_STUCK_DET: Clear SCL Stuck at Low Detect interrupt Register 3150 * AddressOffset : 0xb4 3151 * AccessType : RO 3152 * WritableBitMask: 0x0 3153 * ResetValue : (uint32_t)0x0 3154 */ 3155 SEDI_REG_DEFINE(I2C, CLR_SCL_STUCK_DET, 0xb4, RO, (uint32_t)0x0, (uint32_t)0x0); 3156 3157 /* 3158 * Bit Field of Register CLR_SCL_STUCK_DET 3159 * CLR_SCL_STUCK_DET: 3160 * BitOffset : 0 3161 * BitWidth : 1 3162 * AccessType: RO 3163 * ResetValue: (uint32_t)0x0 3164 */ 3165 SEDI_RBF_DEFINE(I2C, CLR_SCL_STUCK_DET, CLR_SCL_STUCK_DET, 0, 1, RO, (uint32_t)0x0); 3166 SEDI_RBFV_DEFINE(I2C, CLR_SCL_STUCK_DET, CLR_SCL_STUCK_DET, 0, 0); 3167 SEDI_RBFV_DEFINE(I2C, CLR_SCL_STUCK_DET, CLR_SCL_STUCK_DET, 1, 1); 3168 3169 /* 3170 * Bit Field of Register CLR_SCL_STUCK_DET 3171 * RSVD_CLR_SCL_STUCK_DET: 3172 * BitOffset : 1 3173 * BitWidth : 31 3174 * AccessType: RO 3175 * ResetValue: (uint32_t)0x0 3176 */ 3177 SEDI_RBF_DEFINE(I2C, CLR_SCL_STUCK_DET, RSVD_CLR_SCL_STUCK_DET, 1, 31, RO, (uint32_t)0x0); 3178 3179 /* ********* I2C COMP_PARAM_1 *********** 3180 * 3181 * Register of SEDI I2C 3182 * COMP_PARAM_1: Component Parameter Register 1 3183 * AddressOffset : 0xf4 3184 * AccessType : RO 3185 * WritableBitMask: 0x0 3186 * ResetValue : (uint32_t)0x3f3fee 3187 */ 3188 SEDI_REG_DEFINE(I2C, COMP_PARAM_1, 0xf4, RO, (uint32_t)0x0, (uint32_t)0x3f3fee); 3189 3190 /* 3191 * Bit Field of Register COMP_PARAM_1 3192 * APB_DATA_WIDTH: 3193 * BitOffset : 0 3194 * BitWidth : 2 3195 * AccessType: RO 3196 * ResetValue: (uint32_t)0x2 3197 */ 3198 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, APB_DATA_WIDTH, 0, 2, RO, (uint32_t)0x2); 3199 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, APB_DATA_WIDTH, APB_08BITS, 0x0); 3200 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, APB_DATA_WIDTH, APB_16BITS, 0x1); 3201 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, APB_DATA_WIDTH, APB_32BITS, 0x2); 3202 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, APB_DATA_WIDTH, RESERVED, 0x3); 3203 3204 /* 3205 * Bit Field of Register COMP_PARAM_1 3206 * MAX_SPEED_MODE: 3207 * BitOffset : 2 3208 * BitWidth : 2 3209 * AccessType: RO 3210 * ResetValue: (uint32_t)0x3 3211 */ 3212 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, MAX_SPEED_MODE, 2, 2, RO, (uint32_t)0x3); 3213 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, MAX_SPEED_MODE, FAST, 0x2); 3214 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, MAX_SPEED_MODE, HIGH, 0x3); 3215 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, MAX_SPEED_MODE, STANDARD, 0x1); 3216 3217 /* 3218 * Bit Field of Register COMP_PARAM_1 3219 * HC_COUNT_VALUES: 3220 * BitOffset : 4 3221 * BitWidth : 1 3222 * AccessType: RO 3223 * ResetValue: (uint32_t)0x0 3224 */ 3225 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, HC_COUNT_VALUES, 4, 1, RO, (uint32_t)0x0); 3226 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, HC_COUNT_VALUES, DISABLED, 0x0); 3227 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, HC_COUNT_VALUES, ENABLED, 0x1); 3228 3229 /* 3230 * Bit Field of Register COMP_PARAM_1 3231 * INTR_IO: 3232 * BitOffset : 5 3233 * BitWidth : 1 3234 * AccessType: RO 3235 * ResetValue: (uint32_t)0x1 3236 */ 3237 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, INTR_IO, 5, 1, RO, (uint32_t)0x1); 3238 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, INTR_IO, COMBINED, 0x1); 3239 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, INTR_IO, INDIVIDUAL, 0x0); 3240 3241 /* 3242 * Bit Field of Register COMP_PARAM_1 3243 * HAS_DMA: 3244 * BitOffset : 6 3245 * BitWidth : 1 3246 * AccessType: RO 3247 * ResetValue: (uint32_t)0x1 3248 */ 3249 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, HAS_DMA, 6, 1, RO, (uint32_t)0x1); 3250 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, HAS_DMA, DISABLED, 0x0); 3251 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, HAS_DMA, ENABLED, 0x1); 3252 3253 /* 3254 * Bit Field of Register COMP_PARAM_1 3255 * ADD_ENCODED_PARAMS: 3256 * BitOffset : 7 3257 * BitWidth : 1 3258 * AccessType: RO 3259 * ResetValue: (uint32_t)0x1 3260 */ 3261 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, ADD_ENCODED_PARAMS, 7, 1, RO, (uint32_t)0x1); 3262 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, ADD_ENCODED_PARAMS, DISBALED, 0x0); 3263 SEDI_RBFV_DEFINE(I2C, COMP_PARAM_1, ADD_ENCODED_PARAMS, ENABLED, 0x1); 3264 3265 /* 3266 * Bit Field of Register COMP_PARAM_1 3267 * RX_BUFFER_DEPTH: 3268 * BitOffset : 8 3269 * BitWidth : 8 3270 * AccessType: RO 3271 * ResetValue: (uint32_t)0x3f 3272 */ 3273 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, RX_BUFFER_DEPTH, 8, 8, RO, (uint32_t)0x3f); 3274 3275 /* 3276 * Bit Field of Register COMP_PARAM_1 3277 * TX_BUFFER_DEPTH: 3278 * BitOffset : 16 3279 * BitWidth : 8 3280 * AccessType: RO 3281 * ResetValue: (uint32_t)0x3f 3282 */ 3283 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, TX_BUFFER_DEPTH, 16, 8, RO, (uint32_t)0x3f); 3284 3285 /* 3286 * Bit Field of Register COMP_PARAM_1 3287 * RSVD_IC_COMP_PARAM_1: 3288 * BitOffset : 24 3289 * BitWidth : 8 3290 * AccessType: RO 3291 * ResetValue: (uint32_t)0x0 3292 */ 3293 SEDI_RBF_DEFINE(I2C, COMP_PARAM_1, RSVD_IC_COMP_PARAM_1, 24, 8, RO, (uint32_t)0x0); 3294 3295 /* ********* I2C COMP_VERSION *********** 3296 * 3297 * Register of SEDI I2C 3298 * COMP_VERSION: I2C Component Version Register 3299 * AddressOffset : 0xf8 3300 * AccessType : RO 3301 * WritableBitMask: 0x0 3302 * ResetValue : (uint32_t)0x3230332a 3303 */ 3304 SEDI_REG_DEFINE(I2C, COMP_VERSION, 0xf8, RO, (uint32_t)0x0, (uint32_t)0x3230332a); 3305 3306 /* 3307 * Bit Field of Register COMP_VERSION 3308 * IC_COMP_VERSION: 3309 * BitOffset : 0 3310 * BitWidth : 32 3311 * AccessType: RO 3312 * ResetValue: (uint32_t)0x3230332a 3313 */ 3314 SEDI_RBF_DEFINE(I2C, COMP_VERSION, IC_COMP_VERSION, 0, 32, RO, (uint32_t)0x3230332a); 3315 3316 /* ********* I2C COMP_TYPE *********** 3317 * 3318 * Register of SEDI I2C 3319 * COMP_TYPE: I2C Component Type Register 3320 * AddressOffset : 0xfc 3321 * AccessType : RO 3322 * WritableBitMask: 0x0 3323 * ResetValue : (uint32_t)0x44570140 3324 */ 3325 SEDI_REG_DEFINE(I2C, COMP_TYPE, 0xfc, RO, (uint32_t)0x0, (uint32_t)0x44570140); 3326 3327 /* 3328 * Bit Field of Register COMP_TYPE 3329 * IC_COMP_TYPE: 3330 * BitOffset : 0 3331 * BitWidth : 32 3332 * AccessType: RO 3333 * ResetValue: (uint32_t)0x44570140 3334 */ 3335 SEDI_RBF_DEFINE(I2C, COMP_TYPE, IC_COMP_TYPE, 0, 32, RO, (uint32_t)0x44570140); 3336 3337 /* 3338 * Registers' Address Map Structure 3339 */ 3340 3341 typedef struct { 3342 /* I2C Control Register */ 3343 __IO_RW uint32_t con; 3344 3345 /* I2C Target Address Register */ 3346 __IO_RW uint32_t tar; 3347 3348 /* I2C Slave Address Register */ 3349 __IO_RW uint32_t sar; 3350 3351 /* I2C High Speed Master Mode Code Address Register */ 3352 __IO_RW uint32_t hs_maddr; 3353 3354 /* I2C Rx/Tx Data Buffer and Command Register */ 3355 __IO_RW uint32_t data_cmd; 3356 3357 /* Standard Speed I2C Clock SCL High Count Register */ 3358 __IO_RW uint32_t ss_scl_hcnt; 3359 3360 /* Standard Speed I2C Clock SCL Low Count Register */ 3361 __IO_RW uint32_t ss_scl_lcnt; 3362 3363 /* Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register */ 3364 __IO_RW uint32_t fs_scl_hcnt; 3365 3366 /* Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register */ 3367 __IO_RW uint32_t fs_scl_lcnt; 3368 3369 /* High Speed I2C Clock SCL High Count Register */ 3370 __IO_RW uint32_t hs_scl_hcnt; 3371 3372 /* High Speed I2C Clock SCL Low Count Register */ 3373 __IO_RW uint32_t hs_scl_lcnt; 3374 3375 /* I2C Interrupt Status Register */ 3376 __IO_R uint32_t intr_stat; 3377 3378 /* I2C Interrupt Mask Register */ 3379 __IO_RW uint32_t intr_mask; 3380 3381 /* I2C Raw Interrupt Status Register */ 3382 __IO_R uint32_t raw_intr_stat; 3383 3384 /* I2C Receive FIFO Threshold Register */ 3385 __IO_RW uint32_t rx_tl; 3386 3387 /* I2C Transmit FIFO Threshold Register */ 3388 __IO_RW uint32_t tx_tl; 3389 3390 /* Clear Combined and Individual Interrupt Register */ 3391 __IO_R uint32_t clr_intr; 3392 3393 /* Clear RX_UNDER Interrupt Register */ 3394 __IO_R uint32_t clr_rx_under; 3395 3396 /* Clear RX_OVER Interrupt Register */ 3397 __IO_R uint32_t clr_rx_over; 3398 3399 /* Clear TX_OVER Interrupt Register */ 3400 __IO_R uint32_t clr_tx_over; 3401 3402 /* Clear RD_REQ Interrupt Register */ 3403 __IO_R uint32_t clr_rd_req; 3404 3405 /* Clear TX_ABRT Interrupt Register */ 3406 __IO_R uint32_t clr_tx_abrt; 3407 3408 /* Clear RX_DONE Interrupt Register */ 3409 __IO_R uint32_t clr_rx_done; 3410 3411 /* Clear ACTIVITY Interrupt Register */ 3412 __IO_R uint32_t clr_activity; 3413 3414 /* Clear STOP_DET Interrupt Register */ 3415 __IO_R uint32_t clr_stop_det; 3416 3417 /* Clear START_DET Interrupt Register */ 3418 __IO_R uint32_t clr_start_det; 3419 3420 /* Clear GEN_CALL Interrupt Register */ 3421 __IO_R uint32_t clr_gen_call; 3422 3423 /* I2C ENABLE Register */ 3424 __IO_RW uint32_t enable; 3425 3426 /* I2C STATUS Register */ 3427 __IO_R uint32_t status; 3428 3429 /* I2C Transmit FIFO Level Register */ 3430 __IO_R uint32_t txflr; 3431 3432 /* I2C Receive FIFO Level Register */ 3433 __IO_R uint32_t rxflr; 3434 3435 /* I2C SDA Hold Time Length Register */ 3436 __IO_RW uint32_t sda_hold; 3437 3438 /* I2C Transmit Abort Source Register */ 3439 __IO_R uint32_t tx_abrt_source; 3440 3441 /* Reserved */ 3442 __IO_RW uint32_t reserved0[1]; 3443 3444 /* DMA Control Register */ 3445 __IO_RW uint32_t dma_cr; 3446 3447 /* DMA Transmit Data Level Register */ 3448 __IO_RW uint32_t dma_tdlr; 3449 3450 /* DMA Receive Data Level Register */ 3451 __IO_RW uint32_t dma_rdlr; 3452 3453 /* I2C SDA Setup Register */ 3454 __IO_RW uint32_t sda_setup; 3455 3456 /* I2C ACK General Call Register */ 3457 __IO_RW uint32_t ack_general_call; 3458 3459 /* I2C Enable Status Register */ 3460 __IO_R uint32_t enable_status; 3461 3462 /* I2C SS, FS or FM+ spike suppression limit */ 3463 __IO_RW uint32_t fs_spklen; 3464 3465 /* I2C HS spike suppression limit register */ 3466 __IO_RW uint32_t hs_spklen; 3467 3468 /* Clear RESTART_DET Interrupt Register */ 3469 __IO_R uint32_t clr_restart_det; 3470 3471 /* I2C SCL Stuck at Low Timeout register */ 3472 __IO_RW uint32_t scl_stuck_at_low_timeout; 3473 3474 /* I2C SDA Stuck at Low Timeout register */ 3475 __IO_RW uint32_t sda_stuck_at_low_timeout; 3476 3477 /* Clear SCL Stuck at Low Detect interrupt Register */ 3478 __IO_R uint32_t clr_scl_stuck_det; 3479 3480 /* Reserved */ 3481 __IO_RW uint32_t reserved1[15]; 3482 3483 /* Component Parameter Register 1 */ 3484 __IO_R uint32_t comp_param_1; 3485 3486 /* I2C Component Version Register */ 3487 __IO_R uint32_t comp_version; 3488 3489 /* I2C Component Type Register */ 3490 __IO_R uint32_t comp_type; 3491 3492 } sedi_i2c_regs_t; 3493 3494 3495 #endif /* _SEDI_I2C_REGS_H_ */ 3496
