1 /***************************************************************************//**
2 * @file
3 * @brief Inter-integrated Circuit (I2C) Peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #include "em_i2c.h"
32 #if defined(I2C_COUNT) && (I2C_COUNT > 0)
33
34 #include "em_cmu.h"
35 #include "em_bus.h"
36 #include "em_assert.h"
37
38 #include <limits.h>
39
40 /***************************************************************************//**
41 * @addtogroup i2c I2C - Inter-Integrated Circuit
42 * @brief Inter-integrated Circuit (I2C) Peripheral API
43 * @details
44 * This module contains functions to control the I2C peripheral of Silicon
45 * Labs 32-bit MCUs and SoCs. The I2C interface allows communication on I2C
46 * buses with the lowest energy consumption possible.
47 * @{
48 ******************************************************************************/
49
50 /*******************************************************************************
51 ******************************* DEFINES ***********************************
52 ******************************************************************************/
53
54 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
55
56 /** Validation of the I2C register block pointer reference for assert statements. */
57 #if (I2C_COUNT == 1)
58 #define I2C_REF_VALID(ref) ((ref) == I2C0)
59 #elif (I2C_COUNT == 2)
60 #define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1))
61 #elif (I2C_COUNT == 3)
62 #define I2C_REF_VALID(ref) (((ref) == I2C0) || ((ref) == I2C1) || ((ref) == I2C2))
63 #endif
64
65 /** Error flags indicating that the I2C transfer has failed. */
66 /* Notice that I2C_IF_TXOF (transmit overflow) is not really possible with */
67 /* the software-supporting master mode. Likewise, for I2C_IF_RXUF (receive underflow) */
68 /* RXUF is only likely to occur with the software if using a debugger peeking into */
69 /* the RXDATA register. Therefore, those types of faults are ignored. */
70 #define I2C_IF_ERRORS (I2C_IF_BUSERR | I2C_IF_ARBLOST)
71 #define I2C_IEN_ERRORS (I2C_IEN_BUSERR | I2C_IEN_ARBLOST)
72
73 /* Maximum I2C transmission rate constant. */
74 #if defined(_SILICON_LABS_32B_SERIES_0)
75 #define I2C_CR_MAX 4
76 #elif defined(_SILICON_LABS_32B_SERIES_1)
77 #define I2C_CR_MAX 8
78 #elif defined(_SILICON_LABS_32B_SERIES_2)
79 #define I2C_CR_MAX 8
80 #else
81 #warning "Max I2C transmission rate constant is not defined"
82 #endif
83
84 /** @endcond */
85
86 /*******************************************************************************
87 ******************************** ENUMS ************************************
88 ******************************************************************************/
89
90 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
91
92 /** Master mode transfer states. */
93 typedef enum {
94 i2cStateStartAddrSend, /**< Send start + (first part of) address. */
95 i2cStateAddrWFAckNack, /**< Wait for ACK/NACK on (the first part of) address. */
96 i2cStateAddrWF2ndAckNack, /**< Wait for ACK/NACK on the second part of a 10 bit address. */
97 i2cStateRStartAddrSend, /**< Send a repeated start + (first part of) address. */
98 i2cStateRAddrWFAckNack, /**< Wait for ACK/NACK on an address sent after a repeated start. */
99 i2cStateDataSend, /**< Send data. */
100 i2cStateDataWFAckNack, /**< Wait for ACK/NACK on data sent. */
101 i2cStateWFData, /**< Wait for data. */
102 i2cStateWFStopSent, /**< Wait for STOP to have been transmitted. */
103 i2cStateDone /**< Transfer completed successfully. */
104 } I2C_TransferState_TypeDef;
105
106 /** @endcond */
107
108 /*******************************************************************************
109 ******************************* STRUCTS ***********************************
110 ******************************************************************************/
111
112 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
113
114 /** Structure used to store state information on an ongoing master mode transfer. */
115 typedef struct {
116 /** Current state. */
117 I2C_TransferState_TypeDef state;
118
119 /** Result return code. */
120 I2C_TransferReturn_TypeDef result;
121
122 /** Offset in the current sequence buffer. */
123 uint16_t offset;
124
125 /* Index to the current sequence buffer in use. */
126 uint8_t bufIndx;
127
128 /** Reference to the I2C transfer sequence definition provided by the user. */
129 I2C_TransferSeq_TypeDef *seq;
130 } I2C_Transfer_TypeDef;
131
132 /** @endcond */
133
134 /*******************************************************************************
135 ***************************** LOCAL DATA *******^**************************
136 ******************************************************************************/
137
138 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
139
140 /**
141 * Lookup table for Nlow + Nhigh setting defined by CLHR. Set the undefined
142 * index (0x3) to reflect a default setting just in case.
143 */
144 static const uint8_t i2cNSum[] = { 4 + 4, 6 + 3, 11 + 6, 4 + 4 };
145
146 /** A transfer state information for an ongoing master mode transfer. */
147 static I2C_Transfer_TypeDef i2cTransfer[I2C_COUNT];
148
149 /** @endcond */
150
151 /*******************************************************************************
152 ************************** LOCAL FUNCTIONS *******************************
153 ******************************************************************************/
154
155 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
156
157 /***************************************************************************//**
158 * @brief
159 * Empty received data buffer.
160 ******************************************************************************/
flushRx(I2C_TypeDef * i2c)161 static void flushRx(I2C_TypeDef *i2c)
162 {
163 while (i2c->STATUS & I2C_STATUS_RXDATAV) {
164 i2c->RXDATA;
165 }
166
167 #if defined(_SILICON_LABS_32B_SERIES_2)
168 /* SW needs to clear RXDATAV IF on Series 2 devices.
169 Flag is kept high by HW if buffer is not empty. */
170 I2C_IntClear(i2c, I2C_IF_RXDATAV);
171 #endif
172 }
173
174 /** @endcond */
175
176 /*******************************************************************************
177 ************************** GLOBAL FUNCTIONS *******************************
178 ******************************************************************************/
179
180 /***************************************************************************//**
181 * @brief
182 * Get the current configured I2C bus frequency.
183 *
184 * @details
185 * This frequency is only relevant when acting as master.
186 *
187 * @note
188 * The actual frequency is a real number, this function returns a rounded
189 * down (truncated) integer value.
190 *
191 * @param[in] i2c
192 * A pointer to the I2C peripheral register block.
193 *
194 * @return
195 * The current I2C frequency in Hz.
196 ******************************************************************************/
I2C_BusFreqGet(I2C_TypeDef * i2c)197 uint32_t I2C_BusFreqGet(I2C_TypeDef *i2c)
198 {
199 uint32_t freqHfper = 0;
200 uint32_t n;
201
202 /* Maximum frequency is given by freqScl = freqHfper/((Nlow + Nhigh)(DIV + 1) + I2C_CR_MAX)
203 * For more details, see the reference manual
204 * I2C Clock Generation chapter. */
205 if (i2c == I2C0) {
206 freqHfper = CMU_ClockFreqGet(cmuClock_I2C0);
207 #if defined(I2C1)
208 } else if (i2c == I2C1) {
209 freqHfper = CMU_ClockFreqGet(cmuClock_I2C1);
210 #endif
211 #if defined(I2C2)
212 } else if (i2c == I2C2) {
213 freqHfper = CMU_ClockFreqGet(cmuClock_I2C2);
214 #endif
215 } else {
216 EFM_ASSERT(false);
217 }
218
219 /* n = Nlow + Nhigh */
220 n = (uint32_t)i2cNSum[(i2c->CTRL & _I2C_CTRL_CLHR_MASK)
221 >> _I2C_CTRL_CLHR_SHIFT];
222 return freqHfper / ((n * (i2c->CLKDIV + 1)) + I2C_CR_MAX);
223 }
224
225 /***************************************************************************//**
226 * @brief
227 * Set the I2C bus frequency.
228 *
229 * @details
230 * The bus frequency is only relevant when acting as master. The bus
231 * frequency should not be set higher than the maximum frequency accepted by the
232 * slowest device on the bus.
233 *
234 * Notice that, due to asymmetric requirements on low and high I2C clock
235 * cycles in the I2C specification, the maximum frequency allowed
236 * to comply with the specification may be somewhat lower than expected.
237 *
238 * See the reference manual, details on I2C clock generation,
239 * for maximum allowed theoretical frequencies for different modes.
240 *
241 * @param[in] i2c
242 * A pointer to the I2C peripheral register block.
243 *
244 * @param[in] freqRef
245 * An I2C reference clock frequency in Hz that will be used. If set to 0,
246 * HFPERCLK / HFPERCCLK clock is used. Setting it to a higher than actual
247 * configured value has the consequence of reducing the real I2C frequency.
248 *
249 * @param[in] freqScl
250 * A bus frequency to set (bus speed may be lower due to integer
251 * prescaling). Safe (according to the I2C specification) maximum frequencies for
252 * standard fast and fast+ modes are available using I2C_FREQ_ defines.
253 * (Using I2C_FREQ_ defines requires corresponding setting of @p type.)
254 * The slowest slave device on a bus must always be considered.
255 *
256 * @param[in] i2cMode
257 * A clock low-to-high ratio type to use. If not using i2cClockHLRStandard,
258 * make sure all devices on the bus support the specified mode. Using a
259 * non-standard ratio is useful to achieve a higher bus clock in fast and
260 * fast+ modes.
261 ******************************************************************************/
I2C_BusFreqSet(I2C_TypeDef * i2c,uint32_t freqRef,uint32_t freqScl,I2C_ClockHLR_TypeDef i2cMode)262 void I2C_BusFreqSet(I2C_TypeDef *i2c,
263 uint32_t freqRef,
264 uint32_t freqScl,
265 I2C_ClockHLR_TypeDef i2cMode)
266 {
267 uint32_t n, minFreq, denominator;
268 int32_t div;
269
270 /* Avoid dividing by 0. */
271 EFM_ASSERT(freqScl);
272 if (!freqScl) {
273 return;
274 }
275
276 /* Ensure mode is valid */
277 i2cMode &= _I2C_CTRL_CLHR_MASK >> _I2C_CTRL_CLHR_SHIFT;
278
279 /* Set the CLHR (clock low-to-high ratio). */
280 i2c->CTRL &= ~_I2C_CTRL_CLHR_MASK;
281 BUS_RegMaskedWrite(&i2c->CTRL,
282 _I2C_CTRL_CLHR_MASK,
283 i2cMode << _I2C_CTRL_CLHR_SHIFT);
284
285 if (freqRef == 0) {
286 if (i2c == I2C0) {
287 freqRef = CMU_ClockFreqGet(cmuClock_I2C0);
288 #if defined(I2C1)
289 } else if (i2c == I2C1) {
290 freqRef = CMU_ClockFreqGet(cmuClock_I2C1);
291 #endif
292 #if defined(I2C2)
293 } else if (i2c == I2C2) {
294 freqRef = CMU_ClockFreqGet(cmuClock_I2C2);
295 #endif
296 } else {
297 EFM_ASSERT(false);
298 }
299 }
300
301 /* Check the minumum HF peripheral clock. */
302 minFreq = UINT_MAX;
303 if (i2c->CTRL & I2C_CTRL_SLAVE) {
304 switch (i2cMode) {
305 case i2cClockHLRStandard:
306 #if defined(_SILICON_LABS_32B_SERIES_0)
307 minFreq = 4200000; break;
308 #elif defined(_SILICON_LABS_32B_SERIES_1)
309 minFreq = 2000000; break;
310 #elif defined(_SILICON_LABS_32B_SERIES_2)
311 minFreq = 2000000; break;
312 #endif
313 case i2cClockHLRAsymetric:
314 #if defined(_SILICON_LABS_32B_SERIES_0)
315 minFreq = 11000000; break;
316 #elif defined(_SILICON_LABS_32B_SERIES_1)
317 minFreq = 5000000; break;
318 #elif defined(_SILICON_LABS_32B_SERIES_2)
319 minFreq = 5000000; break;
320 #endif
321 case i2cClockHLRFast:
322 #if defined(_SILICON_LABS_32B_SERIES_0)
323 minFreq = 24400000; break;
324 #elif defined(_SILICON_LABS_32B_SERIES_1)
325 minFreq = 14000000; break;
326 #elif defined(_SILICON_LABS_32B_SERIES_2)
327 minFreq = 14000000; break;
328 #endif
329 default:
330 /* MISRA requires the default case. */
331 break;
332 }
333 } else {
334 /* For master mode, platform 1 and 2 share the same
335 minimum frequencies. */
336 switch (i2cMode) {
337 case i2cClockHLRStandard:
338 minFreq = 2000000; break;
339 case i2cClockHLRAsymetric:
340 minFreq = 9000000; break;
341 case i2cClockHLRFast:
342 minFreq = 20000000; break;
343 default:
344 /* MISRA requires default case */
345 break;
346 }
347 }
348
349 /* Frequency most be larger-than. */
350 EFM_ASSERT(freqRef > minFreq);
351
352 /* SCL frequency is given by:
353 * freqScl = freqRef/((Nlow + Nhigh) * (DIV + 1) + I2C_CR_MAX)
354 *
355 * Therefore,
356 * DIV = ((freqRef - (I2C_CR_MAX * freqScl))/((Nlow + Nhigh) * freqScl)) - 1
357 *
358 * For more details, see the reference manual
359 * I2C Clock Generation chapter. */
360
361 /* n = Nlow + Nhigh */
362 n = (uint32_t)i2cNSum[i2cMode];
363 denominator = n * freqScl;
364
365 /* Explicitly ensure denominator is never zero. */
366 if (denominator == 0) {
367 EFM_ASSERT(0);
368 return;
369 }
370 /* Perform integer division so that div is rounded up. */
371 div = ((freqRef - (I2C_CR_MAX * freqScl) + denominator - 1)
372 / denominator) - 1;
373 EFM_ASSERT(div >= 0);
374 EFM_ASSERT((uint32_t)div <= _I2C_CLKDIV_DIV_MASK);
375
376 /* The clock divisor must be at least 1 in slave mode according to the reference */
377 /* manual (in which case there is normally no need to set the bus frequency). */
378 if ((i2c->CTRL & I2C_CTRL_SLAVE) && (div == 0)) {
379 div = 1;
380 }
381 i2c->CLKDIV = (uint32_t)div;
382 }
383
384 /***************************************************************************//**
385 * @brief
386 * Enable/disable I2C.
387 *
388 * @note
389 * After enabling the I2C (from being disabled), the I2C is in BUSY state.
390 *
391 * @param[in] i2c
392 * A pointer to the I2C peripheral register block.
393 *
394 * @param[in] enable
395 * True to enable counting, false to disable.
396 ******************************************************************************/
I2C_Enable(I2C_TypeDef * i2c,bool enable)397 void I2C_Enable(I2C_TypeDef *i2c, bool enable)
398 {
399 EFM_ASSERT(I2C_REF_VALID(i2c));
400
401 #if defined (_I2C_EN_MASK)
402 BUS_RegBitWrite(&(i2c->EN), _I2C_EN_EN_SHIFT, enable);
403 #else
404 BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_EN_SHIFT, enable);
405 #endif
406 }
407
408 /***************************************************************************//**
409 * @brief
410 * Initialize I2C.
411 *
412 * @param[in] i2c
413 * A pointer to the I2C peripheral register block.
414 *
415 * @param[in] init
416 * A pointer to the I2C initialization structure.
417 ******************************************************************************/
I2C_Init(I2C_TypeDef * i2c,const I2C_Init_TypeDef * init)418 void I2C_Init(I2C_TypeDef *i2c, const I2C_Init_TypeDef *init)
419 {
420 EFM_ASSERT(I2C_REF_VALID(i2c));
421
422 i2c->IEN = 0;
423 I2C_IntClear(i2c, _I2C_IF_MASK);
424
425 /* Set SLAVE select mode. */
426 BUS_RegBitWrite(&(i2c->CTRL), _I2C_CTRL_SLAVE_SHIFT, init->master ? 0 : 1);
427
428 I2C_BusFreqSet(i2c, init->refFreq, init->freq, init->clhr);
429
430 I2C_Enable(i2c, init->enable);
431 }
432
433 /***************************************************************************//**
434 * @brief
435 * Reset I2C to the same state that it was in after a hardware reset.
436 *
437 * @note
438 * The ROUTE register is NOT reset by this function to allow for
439 * centralized setup of this feature.
440 *
441 * @param[in] i2c
442 * A pointer to the I2C peripheral register block.
443 ******************************************************************************/
I2C_Reset(I2C_TypeDef * i2c)444 void I2C_Reset(I2C_TypeDef *i2c)
445 {
446 // Cancel ongoing operations and clear TX buffer
447 i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX | I2C_CMD_ABORT;
448 i2c->CTRL = _I2C_CTRL_RESETVALUE;
449 i2c->CLKDIV = _I2C_CLKDIV_RESETVALUE;
450 i2c->SADDR = _I2C_SADDR_RESETVALUE;
451 i2c->SADDRMASK = _I2C_SADDRMASK_RESETVALUE;
452 i2c->IEN = _I2C_IEN_RESETVALUE;
453 #if defined (_I2C_EN_EN_MASK)
454 i2c->EN = _I2C_EN_RESETVALUE;
455 #endif
456
457 // Empty received data buffer
458 flushRx(i2c);
459 I2C_IntClear(i2c, _I2C_IF_MASK);
460 /* Do not reset the route register; setting should be done independently. */
461 }
462
463 // *****************************************************************************
464 /// @brief
465 /// Continue an initiated I2C transfer (single master mode only).
466 ///
467 /// @details
468 /// This function is used repeatedly after a I2C_TransferInit() to
469 /// complete a transfer. It may be used in polled mode as the below example
470 /// shows:
471 /// @code{.c}
472 /// I2C_TransferReturn_TypeDef ret;
473 ///
474 /// // Do a polled transfer
475 /// ret = I2C_TransferInit(I2C0, seq);
476 /// while (ret == i2cTransferInProgress)
477 /// {
478 /// ret = I2C_Transfer(I2C0);
479 /// }
480 /// @endcode
481 /// It may also be used in interrupt driven mode, where this function is invoked
482 /// from the interrupt handler. Notice that, if used in interrupt mode, NVIC
483 /// interrupts must be configured and enabled for the I2C bus used. I2C
484 /// peripheral specific interrupts are managed by this software.
485 ///
486 /// @note
487 /// Only single master mode is supported.
488 ///
489 /// @param[in] i2c
490 /// A pointer to the I2C peripheral register block.
491 ///
492 /// @return
493 /// Returns status for an ongoing transfer.
494 /// @li #i2cTransferInProgress - indicates that transfer not finished.
495 /// @li #i2cTransferDone - transfer completed successfully.
496 /// @li otherwise some sort of error has occurred.
497 ///
498 // *****************************************************************************
I2C_Transfer(I2C_TypeDef * i2c)499 I2C_TransferReturn_TypeDef I2C_Transfer(I2C_TypeDef *i2c)
500 {
501 uint32_t tmp;
502 uint32_t pending;
503 I2C_Transfer_TypeDef *transfer;
504 I2C_TransferSeq_TypeDef *seq;
505
506 EFM_ASSERT(I2C_REF_VALID(i2c));
507
508 /* Support up to 2 I2C buses. */
509 if (i2c == I2C0) {
510 transfer = i2cTransfer;
511 }
512 #if (I2C_COUNT > 1)
513 else if (i2c == I2C1) {
514 transfer = i2cTransfer + 1;
515 }
516 #endif
517 #if (I2C_COUNT > 2)
518 else if (i2c == I2C2) {
519 transfer = i2cTransfer + 2;
520 }
521 #endif
522 else {
523 return i2cTransferUsageFault;
524 }
525
526 seq = transfer->seq;
527 for (;; ) {
528 pending = i2c->IF;
529
530 /* If some sort of fault, abort transfer. */
531 if (pending & I2C_IF_ERRORS) {
532 if (pending & I2C_IF_ARBLOST) {
533 /* If an arbitration fault, indicates either a slave device */
534 /* not responding as expected, or other master which is not */
535 /* supported by this software. */
536 transfer->result = i2cTransferArbLost;
537 } else if (pending & I2C_IF_BUSERR) {
538 /* A bus error indicates a misplaced start or stop, which should */
539 /* not occur in master mode controlled by this software. */
540 transfer->result = i2cTransferBusErr;
541 }
542
543 /* Ifan error occurs, it is difficult to know */
544 /* an exact cause and how to resolve. It will be up to a wrapper */
545 /* to determine how to handle a fault/recovery if possible. */
546 transfer->state = i2cStateDone;
547 goto done;
548 }
549
550 switch (transfer->state) {
551 /***************************************************/
552 /* Send the first start+address (first byte if 10 bit). */
553 /***************************************************/
554 case i2cStateStartAddrSend:
555 if (seq->flags & I2C_FLAG_10BIT_ADDR) {
556 tmp = (((uint32_t)(seq->addr) >> 8) & 0x06) | 0xf0;
557
558 /* In 10 bit address mode, the address following the first */
559 /* start always indicates write. */
560 } else {
561 tmp = (uint32_t)(seq->addr) & 0xfe;
562
563 if (seq->flags & I2C_FLAG_READ) {
564 /* Indicate read request */
565 tmp |= 1;
566 }
567 }
568
569 transfer->state = i2cStateAddrWFAckNack;
570 i2c->TXDATA = tmp;/* Data not transmitted until the START is sent. */
571 i2c->CMD = I2C_CMD_START;
572 goto done;
573
574 /*******************************************************/
575 /* Wait for ACK/NACK on the address (first byte if 10 bit). */
576 /*******************************************************/
577 case i2cStateAddrWFAckNack:
578 if (pending & I2C_IF_NACK) {
579 I2C_IntClear(i2c, I2C_IF_NACK);
580 transfer->result = i2cTransferNack;
581 transfer->state = i2cStateWFStopSent;
582 i2c->CMD = I2C_CMD_STOP;
583 } else if (pending & I2C_IF_ACK) {
584 I2C_IntClear(i2c, I2C_IF_ACK);
585
586 /* If a 10 bit address, send the 2nd byte of the address. */
587 if (seq->flags & I2C_FLAG_10BIT_ADDR) {
588 transfer->state = i2cStateAddrWF2ndAckNack;
589 i2c->TXDATA = (uint32_t)(seq->addr) & 0xff;
590 } else {
591 /* Determine whether receiving or sending data. */
592 if (seq->flags & I2C_FLAG_READ) {
593 transfer->state = i2cStateWFData;
594 if (seq->buf[transfer->bufIndx].len == 1) {
595 i2c->CMD = I2C_CMD_NACK;
596 }
597 } else {
598 transfer->state = i2cStateDataSend;
599 continue;
600 }
601 }
602 }
603 goto done;
604
605 /******************************************************/
606 /* Wait for ACK/NACK on the second byte of a 10 bit address. */
607 /******************************************************/
608 case i2cStateAddrWF2ndAckNack:
609 if (pending & I2C_IF_NACK) {
610 I2C_IntClear(i2c, I2C_IF_NACK);
611 transfer->result = i2cTransferNack;
612 transfer->state = i2cStateWFStopSent;
613 i2c->CMD = I2C_CMD_STOP;
614 } else if (pending & I2C_IF_ACK) {
615 I2C_IntClear(i2c, I2C_IF_ACK);
616
617 /* If using a plain read sequence with a 10 bit address, switch to send */
618 /* a repeated start. */
619 if (seq->flags & I2C_FLAG_READ) {
620 transfer->state = i2cStateRStartAddrSend;
621 }
622 /* Otherwise, expected to write 0 or more bytes. */
623 else {
624 transfer->state = i2cStateDataSend;
625 }
626 continue;
627 }
628 goto done;
629
630 /*******************************/
631 /* Send a repeated start+address */
632 /*******************************/
633 case i2cStateRStartAddrSend:
634 if (seq->flags & I2C_FLAG_10BIT_ADDR) {
635 tmp = ((seq->addr >> 8) & 0x06) | 0xf0;
636 } else {
637 tmp = seq->addr & 0xfe;
638 }
639
640 /* If this is a write+read combined sequence, read is about to start. */
641 if (seq->flags & I2C_FLAG_WRITE_READ) {
642 /* Indicate a read request. */
643 tmp |= 1;
644 /* If reading only one byte, prepare the NACK now before START command. */
645 if (seq->buf[transfer->bufIndx].len == 1) {
646 i2c->CMD = I2C_CMD_NACK;
647 }
648 }
649
650 transfer->state = i2cStateRAddrWFAckNack;
651 /* The START command has to be written first since repeated start. Otherwise, */
652 /* data would be sent first. */
653 i2c->CMD = I2C_CMD_START;
654 i2c->TXDATA = tmp;
655 goto done;
656
657 /**********************************************************************/
658 /* Wait for ACK/NACK on the repeated start+address (first byte if 10 bit) */
659 /**********************************************************************/
660 case i2cStateRAddrWFAckNack:
661 if (pending & I2C_IF_NACK) {
662 I2C_IntClear(i2c, I2C_IF_NACK);
663 transfer->result = i2cTransferNack;
664 transfer->state = i2cStateWFStopSent;
665 i2c->CMD = I2C_CMD_STOP;
666 } else if (pending & I2C_IF_ACK) {
667 I2C_IntClear(i2c, I2C_IF_ACK);
668
669 /* Determine whether receiving or sending data. */
670 if (seq->flags & I2C_FLAG_WRITE_READ) {
671 transfer->state = i2cStateWFData;
672 } else {
673 transfer->state = i2cStateDataSend;
674 continue;
675 }
676 }
677 goto done;
678
679 /*****************************/
680 /* Send a data byte to the slave */
681 /*****************************/
682 case i2cStateDataSend:
683 /* Reached end of data buffer. */
684 if (transfer->offset >= seq->buf[transfer->bufIndx].len) {
685 /* Move to the next message part. */
686 transfer->offset = 0;
687 transfer->bufIndx++;
688
689 /* Send a repeated start when switching to read mode on the 2nd buffer. */
690 if (seq->flags & I2C_FLAG_WRITE_READ) {
691 transfer->state = i2cStateRStartAddrSend;
692 continue;
693 }
694
695 /* Only writing from one buffer or finished both buffers. */
696 if ((seq->flags & I2C_FLAG_WRITE) || (transfer->bufIndx > 1)) {
697 transfer->state = i2cStateWFStopSent;
698 i2c->CMD = I2C_CMD_STOP;
699 goto done;
700 }
701
702 /* Reprocess in case the next buffer is empty. */
703 continue;
704 }
705
706 /* Send byte. */
707 i2c->TXDATA = (uint32_t)(seq->buf[transfer->bufIndx].data[transfer->offset++]);
708 transfer->state = i2cStateDataWFAckNack;
709 goto done;
710
711 /*********************************************************/
712 /* Wait for ACK/NACK from the slave after sending data to it. */
713 /*********************************************************/
714 case i2cStateDataWFAckNack:
715 if (pending & I2C_IF_NACK) {
716 I2C_IntClear(i2c, I2C_IF_NACK);
717 transfer->result = i2cTransferNack;
718 transfer->state = i2cStateWFStopSent;
719 i2c->CMD = I2C_CMD_STOP;
720 } else if (pending & I2C_IF_ACK) {
721 I2C_IntClear(i2c, I2C_IF_ACK);
722 transfer->state = i2cStateDataSend;
723 continue;
724 }
725 goto done;
726
727 /****************************/
728 /* Wait for data from slave */
729 /****************************/
730 case i2cStateWFData:
731 if (pending & I2C_IF_RXDATAV) {
732 uint8_t data;
733 unsigned int rxLen = seq->buf[transfer->bufIndx].len;
734
735 /* Must read out data not to block further progress. */
736 data = (uint8_t)(i2c->RXDATA);
737
738 /* SW needs to clear RXDATAV IF on Series 2 devices.
739 Flag is kept high by HW if buffer is not empty. */
740 #if defined(_SILICON_LABS_32B_SERIES_2)
741 I2C_IntClear(i2c, I2C_IF_RXDATAV);
742 #endif
743
744 /* Make sure that there is no storing beyond the end of the buffer (just in case). */
745 if (transfer->offset < rxLen) {
746 seq->buf[transfer->bufIndx].data[transfer->offset++] = data;
747 }
748
749 /* If all requested data is read, the sequence should end. */
750 if (transfer->offset >= rxLen) {
751 transfer->state = i2cStateWFStopSent;
752 i2c->CMD = I2C_CMD_STOP;
753 } else {
754 /* Send ACK and wait for the next byte. */
755 i2c->CMD = I2C_CMD_ACK;
756
757 if ( (1 < rxLen) && (transfer->offset == (rxLen - 1)) ) {
758 /* If receiving more than one byte and this is the next
759 to last byte, transmit the NACK now before receiving
760 the last byte. */
761 i2c->CMD = I2C_CMD_NACK;
762 }
763 }
764 }
765 goto done;
766
767 /***********************************/
768 /* Wait for STOP to have been sent */
769 /***********************************/
770 case i2cStateWFStopSent:
771 if (pending & I2C_IF_MSTOP) {
772 I2C_IntClear(i2c, I2C_IF_MSTOP);
773 transfer->state = i2cStateDone;
774 }
775 goto done;
776
777 /******************************/
778 /* An unexpected state, software fault */
779 /******************************/
780 default:
781 transfer->result = i2cTransferSwFault;
782 transfer->state = i2cStateDone;
783 goto done;
784 }
785 }
786
787 done:
788
789 if (transfer->state == i2cStateDone) {
790 /* Disable interrupt sources when done. */
791 i2c->IEN = 0;
792
793 /* Update the result unless a fault has already occurred. */
794 if (transfer->result == i2cTransferInProgress) {
795 transfer->result = i2cTransferDone;
796 }
797 }
798 /* Until transfer is done, keep returning i2cTransferInProgress. */
799 else {
800 return i2cTransferInProgress;
801 }
802
803 return transfer->result;
804 }
805
806 /***************************************************************************//**
807 * @brief
808 * Prepare and start an I2C transfer (single master mode only).
809 *
810 * @details
811 * This function must be invoked to start an I2C transfer
812 * sequence. To complete the transfer, I2C_Transfer() must
813 * be used either in polled mode or by adding a small driver wrapper using
814 * interrupts.
815 *
816 * @note
817 * Only single master mode is supported.
818 *
819 * @param[in] i2c
820 * A pointer to the I2C peripheral register block.
821 *
822 * @param[in] seq
823 * A pointer to the sequence structure defining the I2C transfer to take place. The
824 * referenced structure must exist until the transfer has fully completed.
825 *
826 * @return
827 * Returns the status for an ongoing transfer:
828 * @li #i2cTransferInProgress - indicates that the transfer is not finished.
829 * @li Otherwise, an error has occurred.
830 ******************************************************************************/
I2C_TransferInit(I2C_TypeDef * i2c,I2C_TransferSeq_TypeDef * seq)831 I2C_TransferReturn_TypeDef I2C_TransferInit(I2C_TypeDef *i2c,
832 I2C_TransferSeq_TypeDef *seq)
833 {
834 I2C_Transfer_TypeDef *transfer;
835
836 EFM_ASSERT(I2C_REF_VALID(i2c));
837 EFM_ASSERT(seq);
838
839 /* Support up to 2 I2C buses. */
840 if (i2c == I2C0) {
841 transfer = i2cTransfer;
842 }
843 #if (I2C_COUNT > 1)
844 else if (i2c == I2C1) {
845 transfer = i2cTransfer + 1;
846 }
847 #endif
848 #if (I2C_COUNT > 2)
849 else if (i2c == I2C2) {
850 transfer = i2cTransfer + 2;
851 }
852 #endif
853 else {
854 return i2cTransferUsageFault;
855 }
856
857 /* Check if in a busy state. Since this software assumes a single master, */
858 /* issue an abort. The BUSY state is normal after a reset. */
859 if (i2c->STATE & I2C_STATE_BUSY) {
860 i2c->CMD = I2C_CMD_ABORT;
861 }
862
863 /* Do not try to read 0 bytes. It is not */
864 /* possible according to the I2C spec, since the slave will always start */
865 /* sending the first byte ACK on an address. The read operation can */
866 /* only be stopped by NACKing a received byte, i.e., minimum 1 byte. */
867 if (((seq->flags & I2C_FLAG_READ) && !(seq->buf[0].len))
868 || ((seq->flags & I2C_FLAG_WRITE_READ) && !(seq->buf[1].len))
869 ) {
870 return i2cTransferUsageFault;
871 }
872
873 /* Prepare for a transfer. */
874 transfer->state = i2cStateStartAddrSend;
875 transfer->result = i2cTransferInProgress;
876 transfer->offset = 0;
877 transfer->bufIndx = 0;
878 transfer->seq = seq;
879
880 /* Ensure buffers are empty. */
881 i2c->CMD = I2C_CMD_CLEARPC | I2C_CMD_CLEARTX;
882 flushRx(i2c);
883
884 /* Clear all pending interrupts prior to starting a transfer. */
885 I2C_IntClear(i2c, _I2C_IF_MASK);
886
887 /* Enable relevant interrupts. */
888 /* Notice that the I2C interrupt must also be enabled in the NVIC, but */
889 /* that is left for an additional driver wrapper. */
890 i2c->IEN |= I2C_IEN_NACK | I2C_IEN_ACK | I2C_IEN_MSTOP
891 | I2C_IEN_RXDATAV | I2C_IEN_ERRORS;
892
893 /* Start a transfer. */
894 return I2C_Transfer(i2c);
895 }
896
897 /** @} (end addtogroup i2c) */
898 #endif /* defined(I2C_COUNT) && (I2C_COUNT > 0) */
899
