1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2018 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 */ 8 9 /** 10 * \file include/ipc/dai-intel.h 11 * \brief IPC definitions 12 * \author Liam Girdwood <liam.r.girdwood@linux.intel.com> 13 * \author Keyon Jie <yang.jie@linux.intel.com> 14 */ 15 16 #ifndef __IPC_DAI_INTEL_H__ 17 #define __IPC_DAI_INTEL_H__ 18 19 #include <ipc/header.h> 20 #include <stdint.h> 21 22 /* ssc1: TINTE */ 23 #define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) 24 /* ssc1: PINTE */ 25 #define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) 26 /* ssc2: SMTATF */ 27 #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) 28 /* ssc2: MMRATF */ 29 #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) 30 /* ssc2: PSPSTWFDFD */ 31 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) 32 /* ssc2: PSPSRWFDFD */ 33 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) 34 /* ssc1: LBM */ 35 #define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) 36 37 /* here is the possibility to define others aux macros */ 38 39 #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 40 #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 41 42 /* SSP clocks control settings 43 * 44 * Macros for clks_control field in sof_ipc_dai_ssp_params struct. 45 */ 46 47 /* mclk 0 disable */ 48 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) 49 /* mclk 1 disable */ 50 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) 51 /* mclk keep active */ 52 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) 53 /* bclk keep active */ 54 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) 55 /* fs keep active */ 56 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) 57 /* bclk idle */ 58 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) 59 /* mclk early start */ 60 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES BIT(6) 61 /* bclk early start */ 62 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES BIT(7) 63 /* mclk always on */ 64 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_AON BIT(8) 65 66 /* DMIC max. four controllers for eight microphone channels */ 67 #define SOF_DAI_INTEL_DMIC_NUM_CTRL 4 68 69 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ 70 struct sof_ipc_dai_ssp_params { 71 uint32_t reserved0; 72 uint16_t reserved1; 73 uint16_t mclk_id; 74 75 uint32_t mclk_rate; /* mclk frequency in Hz */ 76 uint32_t fsync_rate; /* fsync frequency in Hz */ 77 uint32_t bclk_rate; /* bclk frequency in Hz */ 78 79 /* TDM */ 80 uint32_t tdm_slots; 81 uint32_t rx_slots; 82 uint32_t tx_slots; 83 84 /* data */ 85 uint32_t sample_valid_bits; 86 uint16_t tdm_slot_width; 87 uint16_t reserved2; /* alignment */ 88 89 /* MCLK */ 90 uint32_t mclk_direction; 91 92 uint16_t frame_pulse_width; 93 uint16_t tdm_per_slot_padding_flag; 94 uint32_t clks_control; 95 uint32_t quirks; 96 uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK 97 * will be driven, before sending data 98 */ 99 } __attribute__((packed, aligned(4))); 100 101 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ 102 struct sof_ipc_dai_hda_params { 103 uint32_t reserved0; 104 uint32_t link_dma_ch; 105 uint32_t rate; 106 uint32_t channels; 107 } __attribute__((packed, aligned(4))); 108 109 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ 110 struct sof_ipc_dai_alh_params { 111 uint32_t reserved0; 112 uint32_t stream_id; 113 uint32_t rate; 114 uint32_t channels; 115 116 /* reserved for future use */ 117 uint32_t reserved[13]; 118 } __attribute__((packed, aligned(4))); 119 120 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ 121 122 /* This struct is defined per 2ch PDM controller available in the platform. 123 * Normally it is sufficient to set the used microphone specific enables to 1 124 * and keep other parameters as zero. The customizations are: 125 * 126 * 1. If a device mixes different microphones types with different polarity 127 * and/or the absolute polarity matters the PCM signal from a microphone 128 * can be inverted with the controls. 129 * 130 * 2. If the microphones in a stereo pair do not appear in captured stream 131 * in desired order due to board schematics choises they can be swapped with 132 * the clk_edge parameter. 133 * 134 * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter 135 * that delays the sampling time of data by half cycles of DMIC source clock 136 * can be tried for improvement. However there is no guarantee for this to fix 137 * data integrity problems. 138 */ 139 struct sof_ipc_dai_dmic_pdm_ctrl { 140 uint32_t reserved0; 141 uint16_t id; /**< PDM controller ID */ 142 143 uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ 144 uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ 145 146 uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ 147 uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ 148 149 uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ 150 uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ 151 152 uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ 153 } __attribute__((packed, aligned(4))); 154 155 /* This struct contains the global settings for all 2ch PDM controllers. The 156 * version number used in configuration data is checked vs. version used by 157 * device driver src/drivers/dmic.c need to match. It is incremented from 158 * initial value 1 if updates done for the to driver would alter the operation 159 * of the microphone. 160 * 161 * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) 162 * parameters need to be set as defined in microphone data sheet. E.g. clock 163 * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are 164 * multi-mode capable and there may be denied mic clock frequencies between 165 * the modes. In such case set the clock range limits of the desired mode to 166 * avoid the driver to set clock to an illegal rate. 167 * 168 * The duty cycle could be set to 48-52% if not known. Generally these 169 * parameters can be altered within data sheet specified limits to match 170 * required audio application performance power. 171 * 172 * The microphone clock needs to be usually about 50-80 times the used audio 173 * sample rate. With highest sample rates above 48 kHz this can relaxed 174 * somewhat. 175 * 176 * The parameter wake_up_time describes how long time the microphone needs 177 * for the data line to produce valid output from mic clock start. The driver 178 * will mute the captured audio for the given time. The min_clock_on_time 179 * parameter is used to prevent too short clock bursts to happen. The driver 180 * will keep the clock active after capture stop if this time is not yet 181 * met. The unit for both is microseconds (us). Exceed of 100 ms will be 182 * treated as an error. 183 */ 184 185 struct sof_ipc_dai_dmic_params { 186 uint32_t reserved0; 187 uint32_t driver_ipc_version; /**< Version (1..N) */ 188 189 uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ 190 uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ 191 192 uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ 193 uint32_t reserved_1; /**< Reserved */ 194 uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ 195 uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */ 196 197 uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ 198 uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ 199 200 uint32_t num_pdm_active; /**< Number of active pdm controllers. */ 201 /**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */ 202 203 uint32_t wake_up_time; /**< Time from clock start to data (us) */ 204 uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ 205 uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ 206 207 /* reserved for future use */ 208 uint32_t reserved[5]; 209 210 /**< PDM controllers configuration */ 211 struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL]; 212 } __attribute__((packed, aligned(4))); 213 214 #endif /* __IPC_DAI_INTEL_H__ */ 215
