1 /** 2 * @file flc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup flc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_FLC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_FLC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup flc 67 * @defgroup flc_registers FLC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 69 * @details Flash Memory Control. 70 */ 71 72 /** 73 * @ingroup flc_registers 74 * Structure type to access the FLC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t flsh_addr; /**< <tt>\b 0x00:</tt> FLC FLSH_ADDR Register */ 78 __IO uint32_t flsh_clkdiv; /**< <tt>\b 0x04:</tt> FLC FLSH_CLKDIV Register */ 79 __IO uint32_t flsh_cn; /**< <tt>\b 0x08:</tt> FLC FLSH_CN Register */ 80 __R uint32_t rsv_0xc_0x23[6]; 81 __IO uint32_t flsh_int; /**< <tt>\b 0x24:</tt> FLC FLSH_INT Register */ 82 __R uint32_t rsv_0x28_0x2f[2]; 83 __IO uint32_t flsh_data[4]; /**< <tt>\b 0x30:</tt> FLC FLSH_DATA Register */ 84 __O uint32_t acntl; /**< <tt>\b 0x40:</tt> FLC ACNTL Register */ 85 } mxc_flc_regs_t; 86 87 /* Register offsets for module FLC */ 88 /** 89 * @ingroup flc_registers 90 * @defgroup FLC_Register_Offsets Register Offsets 91 * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_FLC_FLSH_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_FLC_FLSH_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_FLC_FLSH_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_FLC_FLSH_INT ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 98 #define MXC_R_FLC_FLSH_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 99 #define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 100 /**@} end of group flc_registers */ 101 102 /** 103 * @ingroup flc_registers 104 * @defgroup FLC_FLSH_ADDR FLC_FLSH_ADDR 105 * @brief Flash Write Address. 106 * @{ 107 */ 108 #define MXC_F_FLC_FLSH_ADDR_ADDR_POS 0 /**< FLSH_ADDR_ADDR Position */ 109 #define MXC_F_FLC_FLSH_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_FLSH_ADDR_ADDR_POS)) /**< FLSH_ADDR_ADDR Mask */ 110 111 /**@} end of group FLC_FLSH_ADDR_Register */ 112 113 /** 114 * @ingroup flc_registers 115 * @defgroup FLC_FLSH_CLKDIV FLC_FLSH_CLKDIV 116 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 117 * MHz clock for Flash controller. 118 * @{ 119 */ 120 #define MXC_F_FLC_FLSH_CLKDIV_CLKDIV_POS 0 /**< FLSH_CLKDIV_CLKDIV Position */ 121 #define MXC_F_FLC_FLSH_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_FLSH_CLKDIV_CLKDIV_POS)) /**< FLSH_CLKDIV_CLKDIV Mask */ 122 123 /**@} end of group FLC_FLSH_CLKDIV_Register */ 124 125 /** 126 * @ingroup flc_registers 127 * @defgroup FLC_FLSH_CN FLC_FLSH_CN 128 * @brief Flash Control Register. 129 * @{ 130 */ 131 #define MXC_F_FLC_FLSH_CN_WR_POS 0 /**< FLSH_CN_WR Position */ 132 #define MXC_F_FLC_FLSH_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_WR_POS)) /**< FLSH_CN_WR Mask */ 133 134 #define MXC_F_FLC_FLSH_CN_ME_POS 1 /**< FLSH_CN_ME Position */ 135 #define MXC_F_FLC_FLSH_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_ME_POS)) /**< FLSH_CN_ME Mask */ 136 137 #define MXC_F_FLC_FLSH_CN_PGE_POS 2 /**< FLSH_CN_PGE Position */ 138 #define MXC_F_FLC_FLSH_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_PGE_POS)) /**< FLSH_CN_PGE Mask */ 139 140 #define MXC_F_FLC_FLSH_CN_ERASE_CODE_POS 8 /**< FLSH_CN_ERASE_CODE Position */ 141 #define MXC_F_FLC_FLSH_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS)) /**< FLSH_CN_ERASE_CODE Mask */ 142 #define MXC_V_FLC_FLSH_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< FLSH_CN_ERASE_CODE_NOP Value */ 143 #define MXC_S_FLC_FLSH_CN_ERASE_CODE_NOP (MXC_V_FLC_FLSH_CN_ERASE_CODE_NOP << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS) /**< FLSH_CN_ERASE_CODE_NOP Setting */ 144 #define MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< FLSH_CN_ERASE_CODE_ERASEPAGE Value */ 145 #define MXC_S_FLC_FLSH_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS) /**< FLSH_CN_ERASE_CODE_ERASEPAGE Setting */ 146 #define MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< FLSH_CN_ERASE_CODE_ERASEALL Value */ 147 #define MXC_S_FLC_FLSH_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_FLSH_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_FLSH_CN_ERASE_CODE_POS) /**< FLSH_CN_ERASE_CODE_ERASEALL Setting */ 148 149 #define MXC_F_FLC_FLSH_CN_PEND_POS 24 /**< FLSH_CN_PEND Position */ 150 #define MXC_F_FLC_FLSH_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_CN_PEND_POS)) /**< FLSH_CN_PEND Mask */ 151 152 #define MXC_F_FLC_FLSH_CN_UNLOCK_POS 28 /**< FLSH_CN_UNLOCK Position */ 153 #define MXC_F_FLC_FLSH_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_FLSH_CN_UNLOCK_POS)) /**< FLSH_CN_UNLOCK Mask */ 154 #define MXC_V_FLC_FLSH_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< FLSH_CN_UNLOCK_UNLOCKED Value */ 155 #define MXC_S_FLC_FLSH_CN_UNLOCK_UNLOCKED (MXC_V_FLC_FLSH_CN_UNLOCK_UNLOCKED << MXC_F_FLC_FLSH_CN_UNLOCK_POS) /**< FLSH_CN_UNLOCK_UNLOCKED Setting */ 156 #define MXC_V_FLC_FLSH_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< FLSH_CN_UNLOCK_LOCKED Value */ 157 #define MXC_S_FLC_FLSH_CN_UNLOCK_LOCKED (MXC_V_FLC_FLSH_CN_UNLOCK_LOCKED << MXC_F_FLC_FLSH_CN_UNLOCK_POS) /**< FLSH_CN_UNLOCK_LOCKED Setting */ 158 159 /**@} end of group FLC_FLSH_CN_Register */ 160 161 /** 162 * @ingroup flc_registers 163 * @defgroup FLC_FLSH_INT FLC_FLSH_INT 164 * @brief Flash Interrupt Register. 165 * @{ 166 */ 167 #define MXC_F_FLC_FLSH_INT_DONE_POS 0 /**< FLSH_INT_DONE Position */ 168 #define MXC_F_FLC_FLSH_INT_DONE ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_DONE_POS)) /**< FLSH_INT_DONE Mask */ 169 170 #define MXC_F_FLC_FLSH_INT_AF_POS 1 /**< FLSH_INT_AF Position */ 171 #define MXC_F_FLC_FLSH_INT_AF ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_AF_POS)) /**< FLSH_INT_AF Mask */ 172 173 #define MXC_F_FLC_FLSH_INT_DONEIE_POS 8 /**< FLSH_INT_DONEIE Position */ 174 #define MXC_F_FLC_FLSH_INT_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_DONEIE_POS)) /**< FLSH_INT_DONEIE Mask */ 175 176 #define MXC_F_FLC_FLSH_INT_AFIE_POS 9 /**< FLSH_INT_AFIE Position */ 177 #define MXC_F_FLC_FLSH_INT_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_FLSH_INT_AFIE_POS)) /**< FLSH_INT_AFIE Mask */ 178 179 /**@} end of group FLC_FLSH_INT_Register */ 180 181 /** 182 * @ingroup flc_registers 183 * @defgroup FLC_FLSH_DATA FLC_FLSH_DATA 184 * @brief Flash Write Data. 185 * @{ 186 */ 187 #define MXC_F_FLC_FLSH_DATA_DATA_POS 0 /**< FLSH_DATA_DATA Position */ 188 #define MXC_F_FLC_FLSH_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_FLSH_DATA_DATA_POS)) /**< FLSH_DATA_DATA Mask */ 189 190 /**@} end of group FLC_FLSH_DATA_Register */ 191 192 /** 193 * @ingroup flc_registers 194 * @defgroup FLC_ACNTL FLC_ACNTL 195 * @brief Access Control Register. Writing the ACTRL register with the following values in 196 * the order shown, allows read and write access to the system and user Information 197 * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 198 * 0xa1e34f20; pflc-actrl = 0x9608b2c1. When unlocked, a write of 199 * any word will disable access to system and user information block. Readback of 200 * this register is always zero. 201 * @{ 202 */ 203 #define MXC_F_FLC_ACNTL_ADATA_POS 0 /**< ACNTL_ADATA Position */ 204 #define MXC_F_FLC_ACNTL_ADATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ADATA_POS)) /**< ACNTL_ADATA Mask */ 205 206 /**@} end of group FLC_ACNTL_Register */ 207 208 #ifdef __cplusplus 209 } 210 #endif 211 212 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32520_INCLUDE_FLC_REGS_H_ 213
