1 /** 2 * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: PGM Data Registers */ 14 /** Type of pgm_data0 register 15 * Register 0 that stores data to be programmed. 16 */ 17 typedef union { 18 struct { 19 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 20 * The content of the 0th 32-bit data to be programmed. 21 */ 22 uint32_t pgm_data_0:32; 23 }; 24 uint32_t val; 25 } efuse_pgm_data0_reg_t; 26 27 /** Type of pgm_data1 register 28 * Register 1 that stores data to be programmed. 29 */ 30 typedef union { 31 struct { 32 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 33 * The content of the 1th 32-bit data to be programmed. 34 */ 35 uint32_t pgm_data_0:32; 36 }; 37 uint32_t val; 38 } efuse_pgm_data1_reg_t; 39 40 /** Type of pgm_data2 register 41 * Register 2 that stores data to be programmed. 42 */ 43 typedef union { 44 struct { 45 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 46 * The content of the 2th 32-bit data to be programmed. 47 */ 48 uint32_t pgm_data_0:32; 49 }; 50 uint32_t val; 51 } efuse_pgm_data2_reg_t; 52 53 /** Type of pgm_data3 register 54 * Register 3 that stores data to be programmed. 55 */ 56 typedef union { 57 struct { 58 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 59 * The content of the 3th 32-bit data to be programmed. 60 */ 61 uint32_t pgm_data_0:32; 62 }; 63 uint32_t val; 64 } efuse_pgm_data3_reg_t; 65 66 /** Type of pgm_data4 register 67 * Register 4 that stores data to be programmed. 68 */ 69 typedef union { 70 struct { 71 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 72 * The content of the 4th 32-bit data to be programmed. 73 */ 74 uint32_t pgm_data_0:32; 75 }; 76 uint32_t val; 77 } efuse_pgm_data4_reg_t; 78 79 /** Type of pgm_data5 register 80 * Register 5 that stores data to be programmed. 81 */ 82 typedef union { 83 struct { 84 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 85 * The content of the 5th 32-bit data to be programmed. 86 */ 87 uint32_t pgm_data_0:32; 88 }; 89 uint32_t val; 90 } efuse_pgm_data5_reg_t; 91 92 /** Type of pgm_data6 register 93 * Register 6 that stores data to be programmed. 94 */ 95 typedef union { 96 struct { 97 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 98 * The content of the 6th 32-bit data to be programmed. 99 */ 100 uint32_t pgm_data_0:32; 101 }; 102 uint32_t val; 103 } efuse_pgm_data6_reg_t; 104 105 /** Type of pgm_data7 register 106 * Register 7 that stores data to be programmed. 107 */ 108 typedef union { 109 struct { 110 /** pgm_data_0 : R/W; bitpos: [31:0]; default: 0; 111 * The content of the 7th 32-bit data to be programmed. 112 */ 113 uint32_t pgm_data_0:32; 114 }; 115 uint32_t val; 116 } efuse_pgm_data7_reg_t; 117 118 /** Type of pgm_check_value0 register 119 * Register 0 that stores the RS code to be programmed. 120 */ 121 typedef union { 122 struct { 123 /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; 124 * The content of the 0th 32-bit RS code to be programmed. 125 */ 126 uint32_t pgm_rs_data_0:32; 127 }; 128 uint32_t val; 129 } efuse_pgm_check_value0_reg_t; 130 131 /** Type of pgm_check_value1 register 132 * Register 1 that stores the RS code to be programmed. 133 */ 134 typedef union { 135 struct { 136 /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; 137 * The content of the 1th 32-bit RS code to be programmed. 138 */ 139 uint32_t pgm_rs_data_0:32; 140 }; 141 uint32_t val; 142 } efuse_pgm_check_value1_reg_t; 143 144 /** Type of pgm_check_value2 register 145 * Register 2 that stores the RS code to be programmed. 146 */ 147 typedef union { 148 struct { 149 /** pgm_rs_data_0 : R/W; bitpos: [31:0]; default: 0; 150 * The content of the 2th 32-bit RS code to be programmed. 151 */ 152 uint32_t pgm_rs_data_0:32; 153 }; 154 uint32_t val; 155 } efuse_pgm_check_value2_reg_t; 156 157 158 /** Group: Read Data Registers */ 159 /** Type of rd_wr_dis register 160 * Register 0 of BLOCK0. 161 */ 162 typedef union { 163 struct { 164 /** wr_dis : RO; bitpos: [31:0]; default: 0; 165 * Disables programming of individual eFuses. 166 */ 167 uint32_t wr_dis:32; 168 }; 169 uint32_t val; 170 } efuse_rd_wr_dis_reg_t; 171 172 /** Type of rd_repeat_data0 register 173 * Register 1 of BLOCK0. 174 */ 175 typedef union { 176 struct { 177 /** rd_dis : RO; bitpos: [6:0]; default: 0; 178 * Disables software reading from individual eFuse blocks (BLOCK4-10). 179 */ 180 uint32_t rd_dis:7; 181 /** dis_rtc_ram_boot : RO; bitpos: [7]; default: 0; 182 * Reserved. 183 */ 184 uint32_t dis_rtc_ram_boot:1; 185 /** dis_icache : RO; bitpos: [8]; default: 0; 186 * Set this bit to disable Icache. 187 */ 188 uint32_t dis_icache:1; 189 /** dis_dcache : RO; bitpos: [9]; default: 0; 190 * Set this bit to disable Dcache. 191 */ 192 uint32_t dis_dcache:1; 193 /** dis_download_icache : RO; bitpos: [10]; default: 0; 194 * Disables Icache when SoC is in Download mode. 195 */ 196 uint32_t dis_download_icache:1; 197 /** dis_download_dcache : RO; bitpos: [11]; default: 0; 198 * Disables Dcache when SoC is in Download mode. 199 */ 200 uint32_t dis_download_dcache:1; 201 /** dis_force_download : RO; bitpos: [12]; default: 0; 202 * Set this bit to disable the function that forces chip into download mode. 203 */ 204 uint32_t dis_force_download:1; 205 /** dis_usb : RO; bitpos: [13]; default: 0; 206 * Set this bit to disable USB OTG function. 207 */ 208 uint32_t dis_usb:1; 209 /** dis_twai : RO; bitpos: [14]; default: 0; 210 * Set this bit to disable the TWAI Controller function. 211 */ 212 uint32_t dis_twai:1; 213 /** dis_boot_remap : RO; bitpos: [15]; default: 0; 214 * Disables capability to Remap RAM to ROM address space. 215 */ 216 uint32_t dis_boot_remap:1; 217 /** rpt4_reserved5 : RO; bitpos: [16]; default: 0; 218 * Reserved (used for four backups method). 219 */ 220 uint32_t rpt4_reserved5:1; 221 /** soft_dis_jtag : RO; bitpos: [17]; default: 0; 222 * Software disables JTAG. When software disabled, JTAG can be activated temporarily 223 * by HMAC peripheral. 224 */ 225 uint32_t soft_dis_jtag:1; 226 /** hard_dis_jtag : RO; bitpos: [18]; default: 0; 227 * Hardware disables JTAG permanently. 228 */ 229 uint32_t hard_dis_jtag:1; 230 /** dis_download_manual_encrypt : RO; bitpos: [19]; default: 0; 231 * Disables flash encryption when in download boot modes. 232 */ 233 uint32_t dis_download_manual_encrypt:1; 234 /** usb_drefh : RO; bitpos: [21:20]; default: 0; 235 * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored 236 * in eFuse. 237 */ 238 uint32_t usb_drefh:2; 239 /** usb_drefl : RO; bitpos: [23:22]; default: 0; 240 * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, 241 * stored in eFuse. 242 */ 243 uint32_t usb_drefl:2; 244 /** usb_exchg_pins : RO; bitpos: [24]; default: 0; 245 * Set this bit to exchange USB D+ and D- pins. 246 */ 247 uint32_t usb_exchg_pins:1; 248 /** usb_ext_phy_enable : RO; bitpos: [25]; default: 0; 249 * Set this bit to enable external USB PHY. 250 */ 251 uint32_t usb_ext_phy_enable:1; 252 /** usb_force_nopersist : RO; bitpos: [26]; default: 0; 253 * If set, forces USB BVALID to 1. 254 */ 255 uint32_t usb_force_nopersist:1; 256 /** block0_version : R; bitpos: [28:27]; default: 0; 257 * BLOCK0 efuse version 258 */ 259 uint32_t block0_version:2; 260 /** vdd_spi_modecurlim : RO; bitpos: [29]; default: 0; 261 * SPI regulator switches current limit mode. 262 */ 263 uint32_t vdd_spi_modecurlim:1; 264 /** vdd_spi_drefh : RO; bitpos: [31:30]; default: 0; 265 * SPI regulator high voltage reference. 266 */ 267 uint32_t vdd_spi_drefh:2; 268 }; 269 uint32_t val; 270 } efuse_rd_repeat_data0_reg_t; 271 272 /** Type of rd_repeat_data1 register 273 * Register 2 of BLOCK0. 274 */ 275 typedef union { 276 struct { 277 /** vdd_spi_drefm : RO; bitpos: [1:0]; default: 0; 278 * SPI regulator medium voltage reference. 279 */ 280 uint32_t vdd_spi_drefm:2; 281 /** vdd_spi_drefl : RO; bitpos: [3:2]; default: 0; 282 * SPI regulator low voltage reference. 283 */ 284 uint32_t vdd_spi_drefl:2; 285 /** vdd_spi_xpd : RO; bitpos: [4]; default: 0; 286 * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is powered on. 287 */ 288 uint32_t vdd_spi_xpd:1; 289 /** vdd_spi_tieh : RO; bitpos: [5]; default: 0; 290 * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to 1.8 V 291 * LDO. 1: VDD_SPI connects to VDD_RTC_IO. 292 */ 293 uint32_t vdd_spi_tieh:1; 294 /** vdd_spi_force : RO; bitpos: [6]; default: 0; 295 * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO. 296 */ 297 uint32_t vdd_spi_force:1; 298 /** vdd_spi_en_init : RO; bitpos: [7]; default: 0; 299 * Set SPI regulator to 0 to configure init[1:0]=0. 300 */ 301 uint32_t vdd_spi_en_init:1; 302 /** vdd_spi_encurlim : RO; bitpos: [8]; default: 0; 303 * Set SPI regulator to 1 to enable output current limit. 304 */ 305 uint32_t vdd_spi_encurlim:1; 306 /** vdd_spi_dcurlim : RO; bitpos: [11:9]; default: 0; 307 * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d). 308 */ 309 uint32_t vdd_spi_dcurlim:3; 310 /** vdd_spi_init : RO; bitpos: [13:12]; default: 0; 311 * Adds resistor from LDO output to ground. 0: no resistance. 1: 6 K. 2: 4 K. 3: 2 K. 312 */ 313 uint32_t vdd_spi_init:2; 314 /** vdd_spi_dcap : RO; bitpos: [15:14]; default: 0; 315 * Prevents SPI regulator from overshoot. 316 */ 317 uint32_t vdd_spi_dcap:2; 318 /** wdt_delay_sel : RO; bitpos: [17:16]; default: 0; 319 * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock cycles. 1: 320 * 80,000 slow clock cycles. 2: 160,000 slow clock cycles. 3: 320,000 slow clock 321 * cycles. 322 */ 323 uint32_t wdt_delay_sel:2; 324 /** spi_boot_crypt_cnt : RO; bitpos: [20:18]; default: 0; 325 * Enables encryption and decryption, when an SPI boot mode is set. Feature is enabled 326 * 1 or 3 bits are set in the eFuse, disabled otherwise. 327 */ 328 uint32_t spi_boot_crypt_cnt:3; 329 /** secure_boot_key_revoke0 : RO; bitpos: [21]; default: 0; 330 * If set, revokes use of secure boot key digest 0. 331 */ 332 uint32_t secure_boot_key_revoke0:1; 333 /** secure_boot_key_revoke1 : RO; bitpos: [22]; default: 0; 334 * If set, revokes use of secure boot key digest 1. 335 */ 336 uint32_t secure_boot_key_revoke1:1; 337 /** secure_boot_key_revoke2 : RO; bitpos: [23]; default: 0; 338 * If set, revokes use of secure boot key digest 2. 339 */ 340 uint32_t secure_boot_key_revoke2:1; 341 /** key_purpose_0 : RO; bitpos: [27:24]; default: 0; 342 * Purpose of KEY0. Refer to Table Key Purpose Values. 343 */ 344 uint32_t key_purpose_0:4; 345 /** key_purpose_1 : RO; bitpos: [31:28]; default: 0; 346 * Purpose of KEY1. Refer to Table Key Purpose Values. 347 */ 348 uint32_t key_purpose_1:4; 349 }; 350 uint32_t val; 351 } efuse_rd_repeat_data1_reg_t; 352 353 /** Type of rd_repeat_data2 register 354 * Register 3 of BLOCK0. 355 */ 356 typedef union { 357 struct { 358 /** key_purpose_2 : RO; bitpos: [3:0]; default: 0; 359 * Purpose of KEY2. Refer to Table Key Purpose Values. 360 */ 361 uint32_t key_purpose_2:4; 362 /** key_purpose_3 : RO; bitpos: [7:4]; default: 0; 363 * Purpose of KEY3. Refer to Table Key Purpose Values. 364 */ 365 uint32_t key_purpose_3:4; 366 /** key_purpose_4 : RO; bitpos: [11:8]; default: 0; 367 * Purpose of KEY4. Refer to Table Key Purpose Values. 368 */ 369 uint32_t key_purpose_4:4; 370 /** key_purpose_5 : RO; bitpos: [15:12]; default: 0; 371 * Purpose of KEY5. Refer to Table Key Purpose Values. 372 */ 373 uint32_t key_purpose_5:4; 374 /** key_purpose_6 : RO; bitpos: [19:16]; default: 0; 375 * Purpose of KEY6. Refer to Table Key Purpose Values. 376 */ 377 uint32_t key_purpose_6:4; 378 /** secure_boot_en : RO; bitpos: [20]; default: 0; 379 * Set this bit to enable secure boot. 380 */ 381 uint32_t secure_boot_en:1; 382 /** secure_boot_aggressive_revoke : RO; bitpos: [21]; default: 0; 383 * Set this bit to enable aggressive secure boot key revocation mode. 384 */ 385 uint32_t secure_boot_aggressive_revoke:1; 386 /** rpt4_reserved1 : RO; bitpos: [27:22]; default: 0; 387 * Reserved (used for four backups method). 388 */ 389 uint32_t rpt4_reserved1:6; 390 /** flash_tpuw : RO; bitpos: [31:28]; default: 0; 391 * Configures flash startup delay after SoC power-up, in unit of (ms/2). When the 392 * value is 15, delay is 7.5 ms. 393 */ 394 uint32_t flash_tpuw:4; 395 }; 396 uint32_t val; 397 } efuse_rd_repeat_data2_reg_t; 398 399 /** Type of rd_repeat_data3 register 400 * Register 4 of BLOCK0. 401 */ 402 typedef union { 403 struct { 404 /** dis_download_mode : RO; bitpos: [0]; default: 0; 405 * Set this bit to disable all download boot modes. 406 */ 407 uint32_t dis_download_mode:1; 408 /** dis_legacy_spi_boot : RO; bitpos: [1]; default: 0; 409 * Set this bit to disable Legacy SPI boot mode. 410 */ 411 uint32_t dis_legacy_spi_boot:1; 412 /** uart_print_channel : RO; bitpos: [2]; default: 0; 413 * Selects the default UART for printing boot messages. 0: UART0. 1: UART1. 414 */ 415 uint32_t uart_print_channel:1; 416 /** rpt4_reserved3 : RO; bitpos: [3]; default: 0; 417 * Reserved (used for four backups method). 418 */ 419 uint32_t rpt4_reserved3:1; 420 /** dis_usb_download_mode : RO; bitpos: [4]; default: 0; 421 * Set this bit to disable use of USB OTG in UART download boot mode. 422 */ 423 uint32_t dis_usb_download_mode:1; 424 /** enable_security_download : RO; bitpos: [5]; default: 0; 425 * Set this bit to enable secure UART download mode (read/write flash only). 426 */ 427 uint32_t enable_security_download:1; 428 /** uart_print_control : RO; bitpos: [7:6]; default: 0; 429 * Set the default UART boot message output mode. 00: Enabled. 01: Enable when GPIO46 430 * is low at reset. 10: Enable when GPIO46 is high at reset. 11: Disabled. 431 */ 432 uint32_t uart_print_control:2; 433 /** pin_power_selection : RO; bitpos: [8]; default: 0; 434 * Set default power supply for GPIO33-GPIO37, set when SPI flash is initialized. 0: 435 * VDD3P3_CPU. 1: VDD_SPI. 436 */ 437 uint32_t pin_power_selection:1; 438 /** flash_type : RO; bitpos: [9]; default: 0; 439 * SPI flash type. 0: maximum four data lines, 1: eight data lines. 440 */ 441 uint32_t flash_type:1; 442 /** force_send_resume : RO; bitpos: [10]; default: 0; 443 * If set, forces ROM code to send an SPI flash resume command during SPI boot. 444 */ 445 uint32_t force_send_resume:1; 446 /** secure_version : RO; bitpos: [26:11]; default: 0; 447 * Secure version (used by ESP-IDF anti-rollback feature). 448 */ 449 uint32_t secure_version:16; 450 /** rpt4_reserved2 : RO; bitpos: [31:27]; default: 0; 451 * Reserved (used for four backups method). 452 */ 453 uint32_t rpt4_reserved2:5; 454 }; 455 uint32_t val; 456 } efuse_rd_repeat_data3_reg_t; 457 458 /** Type of rd_repeat_data4 register 459 * Register 5 of BLOCK0. 460 */ 461 typedef union { 462 struct { 463 /** disable_wafer_version_major : R; bitpos: [0]; default: 0; 464 * Disables check of wafer version major 465 */ 466 uint32_t disable_wafer_version_major:1; 467 /** disable_blk_version_major : R; bitpos: [1]; default: 0; 468 * Disables check of blk version major 469 */ 470 uint32_t disable_blk_version_major:1; 471 /** reserved_0_162 : R; bitpos: [23:2]; default: 0; 472 * reserved 473 */ 474 uint32_t reserved_0_162:22; 475 uint32_t reserved_24:8; 476 }; 477 uint32_t val; 478 } efuse_rd_repeat_data4_reg_t; 479 480 /** Type of rd_mac_spi_sys_0 register 481 * Register 0 of BLOCK1. 482 */ 483 typedef union { 484 struct { 485 /** mac_0 : RO; bitpos: [31:0]; default: 0; 486 * Stores the low 32 bits of MAC address. 487 */ 488 uint32_t mac_0:32; 489 }; 490 uint32_t val; 491 } efuse_rd_mac_spi_sys_0_reg_t; 492 493 /** Type of rd_mac_spi_sys_1 register 494 * Register 1 of BLOCK1. 495 */ 496 typedef union { 497 struct { 498 /** mac_1 : RO; bitpos: [15:0]; default: 0; 499 * Stores the high 16 bits of MAC address. 500 */ 501 uint32_t mac_1:16; 502 /** spi_pad_config_clk : R; bitpos: [21:16]; default: 0; 503 * SPI_PAD_configure CLK 504 */ 505 uint32_t spi_pad_config_clk:6; 506 /** spi_pad_config_q : R; bitpos: [27:22]; default: 0; 507 * SPI_PAD_configure Q(D1) 508 */ 509 uint32_t spi_pad_config_q:6; 510 /** spi_pad_config_d : R; bitpos: [31:28]; default: 0; 511 * SPI_PAD_configure D(D0) 512 */ 513 uint32_t spi_pad_config_d:4; 514 }; 515 uint32_t val; 516 } efuse_rd_mac_spi_sys_1_reg_t; 517 518 /** Type of rd_mac_spi_sys_2 register 519 * Register 2 of BLOCK1. 520 */ 521 typedef union { 522 struct { 523 /** spi_pad_config_d_1 : R; bitpos: [1:0]; default: 0; 524 * SPI_PAD_configure D(D0) 525 */ 526 uint32_t spi_pad_config_d_1:2; 527 /** spi_pad_config_cs : R; bitpos: [7:2]; default: 0; 528 * SPI_PAD_configure CS 529 */ 530 uint32_t spi_pad_config_cs:6; 531 /** spi_pad_config_hd : R; bitpos: [13:8]; default: 0; 532 * SPI_PAD_configure HD(D3) 533 */ 534 uint32_t spi_pad_config_hd:6; 535 /** spi_pad_config_wp : R; bitpos: [19:14]; default: 0; 536 * SPI_PAD_configure WP(D2) 537 */ 538 uint32_t spi_pad_config_wp:6; 539 /** spi_pad_config_dqs : R; bitpos: [25:20]; default: 0; 540 * SPI_PAD_configure DQS 541 */ 542 uint32_t spi_pad_config_dqs:6; 543 /** spi_pad_config_d4 : R; bitpos: [31:26]; default: 0; 544 * SPI_PAD_configure D4 545 */ 546 uint32_t spi_pad_config_d4:6; 547 }; 548 uint32_t val; 549 } efuse_rd_mac_spi_sys_2_reg_t; 550 551 /** Type of rd_mac_spi_sys_3 register 552 * Register 3 of BLOCK1. 553 */ 554 typedef union { 555 struct { 556 /** spi_pad_config_d5 : R; bitpos: [5:0]; default: 0; 557 * SPI_PAD_configure D5 558 */ 559 uint32_t spi_pad_config_d5:6; 560 /** spi_pad_config_d6 : R; bitpos: [11:6]; default: 0; 561 * SPI_PAD_configure D6 562 */ 563 uint32_t spi_pad_config_d6:6; 564 /** spi_pad_config_d7 : R; bitpos: [17:12]; default: 0; 565 * SPI_PAD_configure D7 566 */ 567 uint32_t spi_pad_config_d7:6; 568 /** wafer_version_major : R; bitpos: [19:18]; default: 0; 569 * WAFER_VERSION_MAJOR 570 */ 571 uint32_t wafer_version_major:2; 572 /** wafer_version_minor_hi : R; bitpos: [20]; default: 0; 573 * WAFER_VERSION_MINOR most significant bit 574 */ 575 uint32_t wafer_version_minor_hi:1; 576 /** flash_version : R; bitpos: [24:21]; default: 0; 577 * Flash version 578 */ 579 uint32_t flash_version:4; 580 /** blk_version_major : R; bitpos: [26:25]; default: 0; 581 * BLK_VERSION_MAJOR 582 */ 583 uint32_t blk_version_major:2; 584 /** reserved_1_123 : R; bitpos: [27]; default: 0; 585 * reserved 586 */ 587 uint32_t reserved_1_123:1; 588 /** psram_version : R; bitpos: [31:28]; default: 0; 589 * PSRAM version 590 */ 591 uint32_t psram_version:4; 592 }; 593 uint32_t val; 594 } efuse_rd_mac_spi_sys_3_reg_t; 595 596 /** Type of rd_mac_spi_sys_4 register 597 * Register 4 of BLOCK1. 598 */ 599 typedef union { 600 struct { 601 /** pkg_version : R; bitpos: [3:0]; default: 0; 602 * Package version 603 */ 604 uint32_t pkg_version:4; 605 /** wafer_version_minor_lo : R; bitpos: [6:4]; default: 0; 606 * WAFER_VERSION_MINOR least significant bits 607 */ 608 uint32_t wafer_version_minor_lo:3; 609 /** reserved_1_135 : R; bitpos: [31:7]; default: 0; 610 * reserved 611 */ 612 uint32_t reserved_1_135:25; 613 }; 614 uint32_t val; 615 } efuse_rd_mac_spi_sys_4_reg_t; 616 617 /** Type of rd_mac_spi_sys_5 register 618 * Register 5 of BLOCK1. 619 */ 620 typedef union { 621 struct { 622 /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; 623 * Stores the second part of the zeroth part of system data. 624 */ 625 uint32_t sys_data_part0_2:32; 626 }; 627 uint32_t val; 628 } efuse_rd_mac_spi_sys_5_reg_t; 629 630 /** Type of rd_sys_part1_data0 register 631 * Register 0 of BLOCK2 (system). 632 */ 633 typedef union { 634 struct { 635 /** optional_unique_id : R; bitpos: [31:0]; default: 0; 636 * Optional unique 128-bit ID 637 */ 638 uint32_t optional_unique_id:32; 639 }; 640 uint32_t val; 641 } efuse_rd_sys_part1_data0_reg_t; 642 643 /** Type of rd_sys_part1_data1 register 644 * Register 1 of BLOCK2 (system). 645 */ 646 typedef union { 647 struct { 648 /** optional_unique_id_1 : R; bitpos: [31:0]; default: 0; 649 * Optional unique 128-bit ID 650 */ 651 uint32_t optional_unique_id_1:32; 652 }; 653 uint32_t val; 654 } efuse_rd_sys_part1_data1_reg_t; 655 656 /** Type of rd_sys_part1_data2 register 657 * Register 2 of BLOCK2 (system). 658 */ 659 typedef union { 660 struct { 661 /** optional_unique_id_2 : R; bitpos: [31:0]; default: 0; 662 * Optional unique 128-bit ID 663 */ 664 uint32_t optional_unique_id_2:32; 665 }; 666 uint32_t val; 667 } efuse_rd_sys_part1_data2_reg_t; 668 669 /** Type of rd_sys_part1_data3 register 670 * Register 3 of BLOCK2 (system). 671 */ 672 typedef union { 673 struct { 674 /** optional_unique_id_3 : R; bitpos: [31:0]; default: 0; 675 * Optional unique 128-bit ID 676 */ 677 uint32_t optional_unique_id_3:32; 678 }; 679 uint32_t val; 680 } efuse_rd_sys_part1_data3_reg_t; 681 682 /** Type of rd_sys_part1_data4 register 683 * Register 4 of BLOCK2 (system). 684 */ 685 typedef union { 686 struct { 687 /** adc_calib : R; bitpos: [3:0]; default: 0; 688 * 4 bit of ADC calibration 689 */ 690 uint32_t adc_calib:4; 691 /** blk_version_minor : R; bitpos: [6:4]; default: 0; 692 * BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2 693 */ 694 uint32_t blk_version_minor:3; 695 /** temp_calib : R; bitpos: [15:7]; default: 0; 696 * Temperature calibration data 697 */ 698 uint32_t temp_calib:9; 699 /** rtccalib_v1idx_a10h : R; bitpos: [23:16]; default: 0; */ 700 uint32_t rtccalib_v1idx_a10h:8; 701 /** rtccalib_v1idx_a11h : R; bitpos: [31:24]; default: 0; */ 702 uint32_t rtccalib_v1idx_a11h:8; 703 }; 704 uint32_t val; 705 } efuse_rd_sys_part1_data4_reg_t; 706 707 /** Type of rd_sys_part1_data5 register 708 * Register 5 of BLOCK2 (system). 709 */ 710 typedef union { 711 struct { 712 /** rtccalib_v1idx_a12h : R; bitpos: [7:0]; default: 0; */ 713 uint32_t rtccalib_v1idx_a12h:8; 714 /** rtccalib_v1idx_a13h : R; bitpos: [15:8]; default: 0; */ 715 uint32_t rtccalib_v1idx_a13h:8; 716 /** rtccalib_v1idx_a20h : R; bitpos: [23:16]; default: 0; */ 717 uint32_t rtccalib_v1idx_a20h:8; 718 /** rtccalib_v1idx_a21h : R; bitpos: [31:24]; default: 0; */ 719 uint32_t rtccalib_v1idx_a21h:8; 720 }; 721 uint32_t val; 722 } efuse_rd_sys_part1_data5_reg_t; 723 724 /** Type of rd_sys_part1_data6 register 725 * Register 6 of BLOCK2 (system). 726 */ 727 typedef union { 728 struct { 729 /** rtccalib_v1idx_a22h : R; bitpos: [7:0]; default: 0; */ 730 uint32_t rtccalib_v1idx_a22h:8; 731 /** rtccalib_v1idx_a23h : R; bitpos: [15:8]; default: 0; */ 732 uint32_t rtccalib_v1idx_a23h:8; 733 /** rtccalib_v1idx_a10l : R; bitpos: [21:16]; default: 0; */ 734 uint32_t rtccalib_v1idx_a10l:6; 735 /** rtccalib_v1idx_a11l : R; bitpos: [27:22]; default: 0; */ 736 uint32_t rtccalib_v1idx_a11l:6; 737 /** rtccalib_v1idx_a12l : R; bitpos: [31:28]; default: 0; */ 738 uint32_t rtccalib_v1idx_a12l:4; 739 }; 740 uint32_t val; 741 } efuse_rd_sys_part1_data6_reg_t; 742 743 /** Type of rd_sys_part1_data7 register 744 * Register 7 of BLOCK2 (system). 745 */ 746 typedef union { 747 struct { 748 /** rtccalib_v1idx_a12l_1 : R; bitpos: [1:0]; default: 0; */ 749 uint32_t rtccalib_v1idx_a12l_1:2; 750 /** rtccalib_v1idx_a13l : R; bitpos: [7:2]; default: 0; */ 751 uint32_t rtccalib_v1idx_a13l:6; 752 /** rtccalib_v1idx_a20l : R; bitpos: [13:8]; default: 0; */ 753 uint32_t rtccalib_v1idx_a20l:6; 754 /** rtccalib_v1idx_a21l : R; bitpos: [19:14]; default: 0; */ 755 uint32_t rtccalib_v1idx_a21l:6; 756 /** rtccalib_v1idx_a22l : R; bitpos: [25:20]; default: 0; */ 757 uint32_t rtccalib_v1idx_a22l:6; 758 /** rtccalib_v1idx_a23l : R; bitpos: [31:26]; default: 0; */ 759 uint32_t rtccalib_v1idx_a23l:6; 760 }; 761 uint32_t val; 762 } efuse_rd_sys_part1_data7_reg_t; 763 764 /** Type of rd_usr_data0 register 765 * Register 0 of BLOCK3 (user). 766 */ 767 typedef union { 768 struct { 769 /** usr_data0 : RO; bitpos: [31:0]; default: 0; 770 * Stores the 0th 32 bits of BLOCK3 (user). 771 */ 772 uint32_t usr_data0:32; 773 }; 774 uint32_t val; 775 } efuse_rd_usr_data0_reg_t; 776 777 /** Type of rd_usr_data1 register 778 * Register 1 of BLOCK3 (user). 779 */ 780 typedef union { 781 struct { 782 /** usr_data1 : RO; bitpos: [31:0]; default: 0; 783 * Stores the 1th 32 bits of BLOCK3 (user). 784 */ 785 uint32_t usr_data1:32; 786 }; 787 uint32_t val; 788 } efuse_rd_usr_data1_reg_t; 789 790 /** Type of rd_usr_data2 register 791 * Register 2 of BLOCK3 (user). 792 */ 793 typedef union { 794 struct { 795 /** usr_data2 : RO; bitpos: [31:0]; default: 0; 796 * Stores the 2th 32 bits of BLOCK3 (user). 797 */ 798 uint32_t usr_data2:32; 799 }; 800 uint32_t val; 801 } efuse_rd_usr_data2_reg_t; 802 803 /** Type of rd_usr_data3 register 804 * Register 3 of BLOCK3 (user). 805 */ 806 typedef union { 807 struct { 808 /** usr_data3 : RO; bitpos: [31:0]; default: 0; 809 * Stores the 3th 32 bits of BLOCK3 (user). 810 */ 811 uint32_t usr_data3:32; 812 }; 813 uint32_t val; 814 } efuse_rd_usr_data3_reg_t; 815 816 /** Type of rd_usr_data4 register 817 * Register 4 of BLOCK3 (user). 818 */ 819 typedef union { 820 struct { 821 /** usr_data4 : RO; bitpos: [31:0]; default: 0; 822 * Stores the 4th 32 bits of BLOCK3 (user). 823 */ 824 uint32_t usr_data4:32; 825 }; 826 uint32_t val; 827 } efuse_rd_usr_data4_reg_t; 828 829 /** Type of rd_usr_data5 register 830 * Register 5 of BLOCK3 (user). 831 */ 832 typedef union { 833 struct { 834 /** usr_data5 : RO; bitpos: [31:0]; default: 0; 835 * Stores the 5th 32 bits of BLOCK3 (user). 836 */ 837 uint32_t usr_data5:32; 838 }; 839 uint32_t val; 840 } efuse_rd_usr_data5_reg_t; 841 842 /** Type of rd_usr_data6 register 843 * Register 6 of BLOCK3 (user). 844 */ 845 typedef union { 846 struct { 847 /** reserved_3_192 : R; bitpos: [7:0]; default: 0; 848 * reserved 849 */ 850 uint32_t reserved_3_192:8; 851 /** custom_mac : R; bitpos: [31:8]; default: 0; 852 * Custom MAC 853 */ 854 uint32_t custom_mac:24; 855 }; 856 uint32_t val; 857 } efuse_rd_usr_data6_reg_t; 858 859 /** Type of rd_usr_data7 register 860 * Register 7 of BLOCK3 (user). 861 */ 862 typedef union { 863 struct { 864 /** custom_mac_1 : R; bitpos: [23:0]; default: 0; 865 * Custom MAC 866 */ 867 uint32_t custom_mac_1:24; 868 /** reserved_3_248 : R; bitpos: [31:24]; default: 0; 869 * reserved 870 */ 871 uint32_t reserved_3_248:8; 872 }; 873 uint32_t val; 874 } efuse_rd_usr_data7_reg_t; 875 876 /** Type of rd_key0_data0 register 877 * Register 0 of BLOCK4 (KEY0). 878 */ 879 typedef union { 880 struct { 881 /** key0_data0 : RO; bitpos: [31:0]; default: 0; 882 * Stores the 0th 32 bits of KEY0. 883 */ 884 uint32_t key0_data0:32; 885 }; 886 uint32_t val; 887 } efuse_rd_key0_data0_reg_t; 888 889 /** Type of rd_key0_data1 register 890 * Register 1 of BLOCK4 (KEY0). 891 */ 892 typedef union { 893 struct { 894 /** key0_data1 : RO; bitpos: [31:0]; default: 0; 895 * Stores the 1th 32 bits of KEY0. 896 */ 897 uint32_t key0_data1:32; 898 }; 899 uint32_t val; 900 } efuse_rd_key0_data1_reg_t; 901 902 /** Type of rd_key0_data2 register 903 * Register 2 of BLOCK4 (KEY0). 904 */ 905 typedef union { 906 struct { 907 /** key0_data2 : RO; bitpos: [31:0]; default: 0; 908 * Stores the 2th 32 bits of KEY0. 909 */ 910 uint32_t key0_data2:32; 911 }; 912 uint32_t val; 913 } efuse_rd_key0_data2_reg_t; 914 915 /** Type of rd_key0_data3 register 916 * Register 3 of BLOCK4 (KEY0). 917 */ 918 typedef union { 919 struct { 920 /** key0_data3 : RO; bitpos: [31:0]; default: 0; 921 * Stores the 3th 32 bits of KEY0. 922 */ 923 uint32_t key0_data3:32; 924 }; 925 uint32_t val; 926 } efuse_rd_key0_data3_reg_t; 927 928 /** Type of rd_key0_data4 register 929 * Register 4 of BLOCK4 (KEY0). 930 */ 931 typedef union { 932 struct { 933 /** key0_data4 : RO; bitpos: [31:0]; default: 0; 934 * Stores the 4th 32 bits of KEY0. 935 */ 936 uint32_t key0_data4:32; 937 }; 938 uint32_t val; 939 } efuse_rd_key0_data4_reg_t; 940 941 /** Type of rd_key0_data5 register 942 * Register 5 of BLOCK4 (KEY0). 943 */ 944 typedef union { 945 struct { 946 /** key0_data5 : RO; bitpos: [31:0]; default: 0; 947 * Stores the 5th 32 bits of KEY0. 948 */ 949 uint32_t key0_data5:32; 950 }; 951 uint32_t val; 952 } efuse_rd_key0_data5_reg_t; 953 954 /** Type of rd_key0_data6 register 955 * Register 6 of BLOCK4 (KEY0). 956 */ 957 typedef union { 958 struct { 959 /** key0_data6 : RO; bitpos: [31:0]; default: 0; 960 * Stores the 6th 32 bits of KEY0. 961 */ 962 uint32_t key0_data6:32; 963 }; 964 uint32_t val; 965 } efuse_rd_key0_data6_reg_t; 966 967 /** Type of rd_key0_data7 register 968 * Register 7 of BLOCK4 (KEY0). 969 */ 970 typedef union { 971 struct { 972 /** key0_data7 : RO; bitpos: [31:0]; default: 0; 973 * Stores the 7th 32 bits of KEY0. 974 */ 975 uint32_t key0_data7:32; 976 }; 977 uint32_t val; 978 } efuse_rd_key0_data7_reg_t; 979 980 /** Type of rd_key1_data0 register 981 * Register 0 of BLOCK5 (KEY1). 982 */ 983 typedef union { 984 struct { 985 /** key1_data0 : RO; bitpos: [31:0]; default: 0; 986 * Stores the 0th 32 bits of KEY1. 987 */ 988 uint32_t key1_data0:32; 989 }; 990 uint32_t val; 991 } efuse_rd_key1_data0_reg_t; 992 993 /** Type of rd_key1_data1 register 994 * Register 1 of BLOCK5 (KEY1). 995 */ 996 typedef union { 997 struct { 998 /** key1_data1 : RO; bitpos: [31:0]; default: 0; 999 * Stores the 1th 32 bits of KEY1. 1000 */ 1001 uint32_t key1_data1:32; 1002 }; 1003 uint32_t val; 1004 } efuse_rd_key1_data1_reg_t; 1005 1006 /** Type of rd_key1_data2 register 1007 * Register 2 of BLOCK5 (KEY1). 1008 */ 1009 typedef union { 1010 struct { 1011 /** key1_data2 : RO; bitpos: [31:0]; default: 0; 1012 * Stores the 2th 32 bits of KEY1. 1013 */ 1014 uint32_t key1_data2:32; 1015 }; 1016 uint32_t val; 1017 } efuse_rd_key1_data2_reg_t; 1018 1019 /** Type of rd_key1_data3 register 1020 * Register 3 of BLOCK5 (KEY1). 1021 */ 1022 typedef union { 1023 struct { 1024 /** key1_data3 : RO; bitpos: [31:0]; default: 0; 1025 * Stores the 3th 32 bits of KEY1. 1026 */ 1027 uint32_t key1_data3:32; 1028 }; 1029 uint32_t val; 1030 } efuse_rd_key1_data3_reg_t; 1031 1032 /** Type of rd_key1_data4 register 1033 * Register 4 of BLOCK5 (KEY1). 1034 */ 1035 typedef union { 1036 struct { 1037 /** key1_data4 : RO; bitpos: [31:0]; default: 0; 1038 * Stores the 4th 32 bits of KEY1. 1039 */ 1040 uint32_t key1_data4:32; 1041 }; 1042 uint32_t val; 1043 } efuse_rd_key1_data4_reg_t; 1044 1045 /** Type of rd_key1_data5 register 1046 * Register 5 of BLOCK5 (KEY1). 1047 */ 1048 typedef union { 1049 struct { 1050 /** key1_data5 : RO; bitpos: [31:0]; default: 0; 1051 * Stores the 5th 32 bits of KEY1. 1052 */ 1053 uint32_t key1_data5:32; 1054 }; 1055 uint32_t val; 1056 } efuse_rd_key1_data5_reg_t; 1057 1058 /** Type of rd_key1_data6 register 1059 * Register 6 of BLOCK5 (KEY1). 1060 */ 1061 typedef union { 1062 struct { 1063 /** key1_data6 : RO; bitpos: [31:0]; default: 0; 1064 * Stores the 6th 32 bits of KEY1. 1065 */ 1066 uint32_t key1_data6:32; 1067 }; 1068 uint32_t val; 1069 } efuse_rd_key1_data6_reg_t; 1070 1071 /** Type of rd_key1_data7 register 1072 * Register 7 of BLOCK5 (KEY1). 1073 */ 1074 typedef union { 1075 struct { 1076 /** key1_data7 : RO; bitpos: [31:0]; default: 0; 1077 * Stores the 7th 32 bits of KEY1. 1078 */ 1079 uint32_t key1_data7:32; 1080 }; 1081 uint32_t val; 1082 } efuse_rd_key1_data7_reg_t; 1083 1084 /** Type of rd_key2_data0 register 1085 * Register 0 of BLOCK6 (KEY2). 1086 */ 1087 typedef union { 1088 struct { 1089 /** key2_data0 : RO; bitpos: [31:0]; default: 0; 1090 * Stores the 0th 32 bits of KEY2. 1091 */ 1092 uint32_t key2_data0:32; 1093 }; 1094 uint32_t val; 1095 } efuse_rd_key2_data0_reg_t; 1096 1097 /** Type of rd_key2_data1 register 1098 * Register 1 of BLOCK6 (KEY2). 1099 */ 1100 typedef union { 1101 struct { 1102 /** key2_data1 : RO; bitpos: [31:0]; default: 0; 1103 * Stores the 1th 32 bits of KEY2. 1104 */ 1105 uint32_t key2_data1:32; 1106 }; 1107 uint32_t val; 1108 } efuse_rd_key2_data1_reg_t; 1109 1110 /** Type of rd_key2_data2 register 1111 * Register 2 of BLOCK6 (KEY2). 1112 */ 1113 typedef union { 1114 struct { 1115 /** key2_data2 : RO; bitpos: [31:0]; default: 0; 1116 * Stores the 2th 32 bits of KEY2. 1117 */ 1118 uint32_t key2_data2:32; 1119 }; 1120 uint32_t val; 1121 } efuse_rd_key2_data2_reg_t; 1122 1123 /** Type of rd_key2_data3 register 1124 * Register 3 of BLOCK6 (KEY2). 1125 */ 1126 typedef union { 1127 struct { 1128 /** key2_data3 : RO; bitpos: [31:0]; default: 0; 1129 * Stores the 3th 32 bits of KEY2. 1130 */ 1131 uint32_t key2_data3:32; 1132 }; 1133 uint32_t val; 1134 } efuse_rd_key2_data3_reg_t; 1135 1136 /** Type of rd_key2_data4 register 1137 * Register 4 of BLOCK6 (KEY2). 1138 */ 1139 typedef union { 1140 struct { 1141 /** key2_data4 : RO; bitpos: [31:0]; default: 0; 1142 * Stores the 4th 32 bits of KEY2. 1143 */ 1144 uint32_t key2_data4:32; 1145 }; 1146 uint32_t val; 1147 } efuse_rd_key2_data4_reg_t; 1148 1149 /** Type of rd_key2_data5 register 1150 * Register 5 of BLOCK6 (KEY2). 1151 */ 1152 typedef union { 1153 struct { 1154 /** key2_data5 : RO; bitpos: [31:0]; default: 0; 1155 * Stores the 5th 32 bits of KEY2. 1156 */ 1157 uint32_t key2_data5:32; 1158 }; 1159 uint32_t val; 1160 } efuse_rd_key2_data5_reg_t; 1161 1162 /** Type of rd_key2_data6 register 1163 * Register 6 of BLOCK6 (KEY2). 1164 */ 1165 typedef union { 1166 struct { 1167 /** key2_data6 : RO; bitpos: [31:0]; default: 0; 1168 * Stores the 6th 32 bits of KEY2. 1169 */ 1170 uint32_t key2_data6:32; 1171 }; 1172 uint32_t val; 1173 } efuse_rd_key2_data6_reg_t; 1174 1175 /** Type of rd_key2_data7 register 1176 * Register 7 of BLOCK6 (KEY2). 1177 */ 1178 typedef union { 1179 struct { 1180 /** key2_data7 : RO; bitpos: [31:0]; default: 0; 1181 * Stores the 7th 32 bits of KEY2. 1182 */ 1183 uint32_t key2_data7:32; 1184 }; 1185 uint32_t val; 1186 } efuse_rd_key2_data7_reg_t; 1187 1188 /** Type of rd_key3_data0 register 1189 * Register 0 of BLOCK7 (KEY3). 1190 */ 1191 typedef union { 1192 struct { 1193 /** key3_data0 : RO; bitpos: [31:0]; default: 0; 1194 * Stores the 0th 32 bits of KEY3. 1195 */ 1196 uint32_t key3_data0:32; 1197 }; 1198 uint32_t val; 1199 } efuse_rd_key3_data0_reg_t; 1200 1201 /** Type of rd_key3_data1 register 1202 * Register 1 of BLOCK7 (KEY3). 1203 */ 1204 typedef union { 1205 struct { 1206 /** key3_data1 : RO; bitpos: [31:0]; default: 0; 1207 * Stores the 1th 32 bits of KEY3. 1208 */ 1209 uint32_t key3_data1:32; 1210 }; 1211 uint32_t val; 1212 } efuse_rd_key3_data1_reg_t; 1213 1214 /** Type of rd_key3_data2 register 1215 * Register 2 of BLOCK7 (KEY3). 1216 */ 1217 typedef union { 1218 struct { 1219 /** key3_data2 : RO; bitpos: [31:0]; default: 0; 1220 * Stores the 2th 32 bits of KEY3. 1221 */ 1222 uint32_t key3_data2:32; 1223 }; 1224 uint32_t val; 1225 } efuse_rd_key3_data2_reg_t; 1226 1227 /** Type of rd_key3_data3 register 1228 * Register 3 of BLOCK7 (KEY3). 1229 */ 1230 typedef union { 1231 struct { 1232 /** key3_data3 : RO; bitpos: [31:0]; default: 0; 1233 * Stores the 3th 32 bits of KEY3. 1234 */ 1235 uint32_t key3_data3:32; 1236 }; 1237 uint32_t val; 1238 } efuse_rd_key3_data3_reg_t; 1239 1240 /** Type of rd_key3_data4 register 1241 * Register 4 of BLOCK7 (KEY3). 1242 */ 1243 typedef union { 1244 struct { 1245 /** key3_data4 : RO; bitpos: [31:0]; default: 0; 1246 * Stores the 4th 32 bits of KEY3. 1247 */ 1248 uint32_t key3_data4:32; 1249 }; 1250 uint32_t val; 1251 } efuse_rd_key3_data4_reg_t; 1252 1253 /** Type of rd_key3_data5 register 1254 * Register 5 of BLOCK7 (KEY3). 1255 */ 1256 typedef union { 1257 struct { 1258 /** key3_data5 : RO; bitpos: [31:0]; default: 0; 1259 * Stores the 5th 32 bits of KEY3. 1260 */ 1261 uint32_t key3_data5:32; 1262 }; 1263 uint32_t val; 1264 } efuse_rd_key3_data5_reg_t; 1265 1266 /** Type of rd_key3_data6 register 1267 * Register 6 of BLOCK7 (KEY3). 1268 */ 1269 typedef union { 1270 struct { 1271 /** key3_data6 : RO; bitpos: [31:0]; default: 0; 1272 * Stores the 6th 32 bits of KEY3. 1273 */ 1274 uint32_t key3_data6:32; 1275 }; 1276 uint32_t val; 1277 } efuse_rd_key3_data6_reg_t; 1278 1279 /** Type of rd_key3_data7 register 1280 * Register 7 of BLOCK7 (KEY3). 1281 */ 1282 typedef union { 1283 struct { 1284 /** key3_data7 : RO; bitpos: [31:0]; default: 0; 1285 * Stores the 7th 32 bits of KEY3. 1286 */ 1287 uint32_t key3_data7:32; 1288 }; 1289 uint32_t val; 1290 } efuse_rd_key3_data7_reg_t; 1291 1292 /** Type of rd_key4_data0 register 1293 * Register 0 of BLOCK8 (KEY4). 1294 */ 1295 typedef union { 1296 struct { 1297 /** key4_data0 : RO; bitpos: [31:0]; default: 0; 1298 * Stores the 0th 32 bits of KEY4. 1299 */ 1300 uint32_t key4_data0:32; 1301 }; 1302 uint32_t val; 1303 } efuse_rd_key4_data0_reg_t; 1304 1305 /** Type of rd_key4_data1 register 1306 * Register 1 of BLOCK8 (KEY4). 1307 */ 1308 typedef union { 1309 struct { 1310 /** key4_data1 : RO; bitpos: [31:0]; default: 0; 1311 * Stores the 1th 32 bits of KEY4. 1312 */ 1313 uint32_t key4_data1:32; 1314 }; 1315 uint32_t val; 1316 } efuse_rd_key4_data1_reg_t; 1317 1318 /** Type of rd_key4_data2 register 1319 * Register 2 of BLOCK8 (KEY4). 1320 */ 1321 typedef union { 1322 struct { 1323 /** key4_data2 : RO; bitpos: [31:0]; default: 0; 1324 * Stores the 2th 32 bits of KEY4. 1325 */ 1326 uint32_t key4_data2:32; 1327 }; 1328 uint32_t val; 1329 } efuse_rd_key4_data2_reg_t; 1330 1331 /** Type of rd_key4_data3 register 1332 * Register 3 of BLOCK8 (KEY4). 1333 */ 1334 typedef union { 1335 struct { 1336 /** key4_data3 : RO; bitpos: [31:0]; default: 0; 1337 * Stores the 3th 32 bits of KEY4. 1338 */ 1339 uint32_t key4_data3:32; 1340 }; 1341 uint32_t val; 1342 } efuse_rd_key4_data3_reg_t; 1343 1344 /** Type of rd_key4_data4 register 1345 * Register 4 of BLOCK8 (KEY4). 1346 */ 1347 typedef union { 1348 struct { 1349 /** key4_data4 : RO; bitpos: [31:0]; default: 0; 1350 * Stores the 4th 32 bits of KEY4. 1351 */ 1352 uint32_t key4_data4:32; 1353 }; 1354 uint32_t val; 1355 } efuse_rd_key4_data4_reg_t; 1356 1357 /** Type of rd_key4_data5 register 1358 * Register 5 of BLOCK8 (KEY4). 1359 */ 1360 typedef union { 1361 struct { 1362 /** key4_data5 : RO; bitpos: [31:0]; default: 0; 1363 * Stores the 5th 32 bits of KEY4. 1364 */ 1365 uint32_t key4_data5:32; 1366 }; 1367 uint32_t val; 1368 } efuse_rd_key4_data5_reg_t; 1369 1370 /** Type of rd_key4_data6 register 1371 * Register 6 of BLOCK8 (KEY4). 1372 */ 1373 typedef union { 1374 struct { 1375 /** key4_data6 : RO; bitpos: [31:0]; default: 0; 1376 * Stores the 6th 32 bits of KEY4. 1377 */ 1378 uint32_t key4_data6:32; 1379 }; 1380 uint32_t val; 1381 } efuse_rd_key4_data6_reg_t; 1382 1383 /** Type of rd_key4_data7 register 1384 * Register 7 of BLOCK8 (KEY4). 1385 */ 1386 typedef union { 1387 struct { 1388 /** key4_data7 : RO; bitpos: [31:0]; default: 0; 1389 * Stores the 7th 32 bits of KEY4. 1390 */ 1391 uint32_t key4_data7:32; 1392 }; 1393 uint32_t val; 1394 } efuse_rd_key4_data7_reg_t; 1395 1396 /** Type of rd_key5_data0 register 1397 * Register 0 of BLOCK9 (KEY5). 1398 */ 1399 typedef union { 1400 struct { 1401 /** key5_data0 : RO; bitpos: [31:0]; default: 0; 1402 * Stores the 0th 32 bits of KEY5. 1403 */ 1404 uint32_t key5_data0:32; 1405 }; 1406 uint32_t val; 1407 } efuse_rd_key5_data0_reg_t; 1408 1409 /** Type of rd_key5_data1 register 1410 * Register 1 of BLOCK9 (KEY5). 1411 */ 1412 typedef union { 1413 struct { 1414 /** key5_data1 : RO; bitpos: [31:0]; default: 0; 1415 * Stores the 1th 32 bits of KEY5. 1416 */ 1417 uint32_t key5_data1:32; 1418 }; 1419 uint32_t val; 1420 } efuse_rd_key5_data1_reg_t; 1421 1422 /** Type of rd_key5_data2 register 1423 * Register 2 of BLOCK9 (KEY5). 1424 */ 1425 typedef union { 1426 struct { 1427 /** key5_data2 : RO; bitpos: [31:0]; default: 0; 1428 * Stores the 2th 32 bits of KEY5. 1429 */ 1430 uint32_t key5_data2:32; 1431 }; 1432 uint32_t val; 1433 } efuse_rd_key5_data2_reg_t; 1434 1435 /** Type of rd_key5_data3 register 1436 * Register 3 of BLOCK9 (KEY5). 1437 */ 1438 typedef union { 1439 struct { 1440 /** key5_data3 : RO; bitpos: [31:0]; default: 0; 1441 * Stores the 3th 32 bits of KEY5. 1442 */ 1443 uint32_t key5_data3:32; 1444 }; 1445 uint32_t val; 1446 } efuse_rd_key5_data3_reg_t; 1447 1448 /** Type of rd_key5_data4 register 1449 * Register 4 of BLOCK9 (KEY5). 1450 */ 1451 typedef union { 1452 struct { 1453 /** key5_data4 : RO; bitpos: [31:0]; default: 0; 1454 * Stores the 4th 32 bits of KEY5. 1455 */ 1456 uint32_t key5_data4:32; 1457 }; 1458 uint32_t val; 1459 } efuse_rd_key5_data4_reg_t; 1460 1461 /** Type of rd_key5_data5 register 1462 * Register 5 of BLOCK9 (KEY5). 1463 */ 1464 typedef union { 1465 struct { 1466 /** key5_data5 : RO; bitpos: [31:0]; default: 0; 1467 * Stores the 5th 32 bits of KEY5. 1468 */ 1469 uint32_t key5_data5:32; 1470 }; 1471 uint32_t val; 1472 } efuse_rd_key5_data5_reg_t; 1473 1474 /** Type of rd_key5_data6 register 1475 * Register 6 of BLOCK9 (KEY5). 1476 */ 1477 typedef union { 1478 struct { 1479 /** key5_data6 : RO; bitpos: [31:0]; default: 0; 1480 * Stores the 6th 32 bits of KEY5. 1481 */ 1482 uint32_t key5_data6:32; 1483 }; 1484 uint32_t val; 1485 } efuse_rd_key5_data6_reg_t; 1486 1487 /** Type of rd_key5_data7 register 1488 * Register 7 of BLOCK9 (KEY5). 1489 */ 1490 typedef union { 1491 struct { 1492 /** key5_data7 : RO; bitpos: [31:0]; default: 0; 1493 * Stores the 7th 32 bits of KEY5. 1494 */ 1495 uint32_t key5_data7:32; 1496 }; 1497 uint32_t val; 1498 } efuse_rd_key5_data7_reg_t; 1499 1500 /** Type of rd_sys_part2_data0 register 1501 * Register 0 of BLOCK10 (system). 1502 */ 1503 typedef union { 1504 struct { 1505 /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; 1506 * Stores the 0th 32 bits of the 2nd part of system data. 1507 */ 1508 uint32_t sys_data_part2_0:32; 1509 }; 1510 uint32_t val; 1511 } efuse_rd_sys_part2_data0_reg_t; 1512 1513 /** Type of rd_sys_part2_data1 register 1514 * Register 1 of BLOCK10 (system). 1515 */ 1516 typedef union { 1517 struct { 1518 /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; 1519 * Stores the 1th 32 bits of the 2nd part of system data. 1520 */ 1521 uint32_t sys_data_part2_1:32; 1522 }; 1523 uint32_t val; 1524 } efuse_rd_sys_part2_data1_reg_t; 1525 1526 /** Type of rd_sys_part2_data2 register 1527 * Register 2 of BLOCK10 (system). 1528 */ 1529 typedef union { 1530 struct { 1531 /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; 1532 * Stores the 2th 32 bits of the 2nd part of system data. 1533 */ 1534 uint32_t sys_data_part2_2:32; 1535 }; 1536 uint32_t val; 1537 } efuse_rd_sys_part2_data2_reg_t; 1538 1539 /** Type of rd_sys_part2_data3 register 1540 * Register 3 of BLOCK10 (system). 1541 */ 1542 typedef union { 1543 struct { 1544 /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; 1545 * Stores the 3th 32 bits of the 2nd part of system data. 1546 */ 1547 uint32_t sys_data_part2_3:32; 1548 }; 1549 uint32_t val; 1550 } efuse_rd_sys_part2_data3_reg_t; 1551 1552 /** Type of rd_sys_part2_data4 register 1553 * Register 4 of BLOCK10 (system). 1554 */ 1555 typedef union { 1556 struct { 1557 /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; 1558 * Stores the 4th 32 bits of the 2nd part of system data. 1559 */ 1560 uint32_t sys_data_part2_4:32; 1561 }; 1562 uint32_t val; 1563 } efuse_rd_sys_part2_data4_reg_t; 1564 1565 /** Type of rd_sys_part2_data5 register 1566 * Register 5 of BLOCK10 (system). 1567 */ 1568 typedef union { 1569 struct { 1570 /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; 1571 * Stores the 5th 32 bits of the 2nd part of system data. 1572 */ 1573 uint32_t sys_data_part2_5:32; 1574 }; 1575 uint32_t val; 1576 } efuse_rd_sys_part2_data5_reg_t; 1577 1578 /** Type of rd_sys_part2_data6 register 1579 * Register 6 of BLOCK10 (system). 1580 */ 1581 typedef union { 1582 struct { 1583 /** sys_data_part2_6 : RO; bitpos: [31:0]; default: 0; 1584 * Stores the 6th 32 bits of the 2nd part of system data. 1585 */ 1586 uint32_t sys_data_part2_6:32; 1587 }; 1588 uint32_t val; 1589 } efuse_rd_sys_part2_data6_reg_t; 1590 1591 /** Type of rd_sys_part2_data7 register 1592 * Register 7 of BLOCK10 (system). 1593 */ 1594 typedef union { 1595 struct { 1596 /** sys_data_part2_7 : RO; bitpos: [31:0]; default: 0; 1597 * Stores the 7th 32 bits of the 2nd part of system data. 1598 */ 1599 uint32_t sys_data_part2_7:32; 1600 }; 1601 uint32_t val; 1602 } efuse_rd_sys_part2_data7_reg_t; 1603 1604 1605 /** Group: Error Status Registers */ 1606 /** Type of rd_repeat_err0 register 1607 * Programming error record register 0 of BLOCK0. 1608 */ 1609 typedef union { 1610 struct { 1611 /** rd_dis_err : RO; bitpos: [6:0]; default: 0; 1612 * Any bit equal to 1 denotes a programming error in EFUSE_RD_DIS. 1613 */ 1614 uint32_t rd_dis_err:7; 1615 /** dis_rtc_ram_boot_err : RO; bitpos: [7]; default: 0; 1616 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_RTC_RAM_BOOT. 1617 */ 1618 uint32_t dis_rtc_ram_boot_err:1; 1619 /** dis_icache_err : RO; bitpos: [8]; default: 0; 1620 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_ICACHE. 1621 */ 1622 uint32_t dis_icache_err:1; 1623 /** dis_dcache_err : RO; bitpos: [9]; default: 0; 1624 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DCACHE. 1625 */ 1626 uint32_t dis_dcache_err:1; 1627 /** dis_download_icache_err : RO; bitpos: [10]; default: 0; 1628 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_ICACHE. 1629 */ 1630 uint32_t dis_download_icache_err:1; 1631 /** dis_download_dcache_err : RO; bitpos: [11]; default: 0; 1632 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_DCACHE. 1633 */ 1634 uint32_t dis_download_dcache_err:1; 1635 /** dis_force_download_err : RO; bitpos: [12]; default: 0; 1636 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_FORCE_DOWNLOAD. 1637 */ 1638 uint32_t dis_force_download_err:1; 1639 /** dis_usb_err : RO; bitpos: [13]; default: 0; 1640 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB. 1641 */ 1642 uint32_t dis_usb_err:1; 1643 /** dis_can_err : RO; bitpos: [14]; default: 0; 1644 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_CAN. 1645 */ 1646 uint32_t dis_can_err:1; 1647 /** dis_boot_remap_err : RO; bitpos: [15]; default: 0; 1648 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_BOOT_REMAP. 1649 */ 1650 uint32_t dis_boot_remap_err:1; 1651 /** rpt4_reserved5_err : RO; bitpos: [16]; default: 0; 1652 * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED5. 1653 */ 1654 uint32_t rpt4_reserved5_err:1; 1655 /** soft_dis_jtag_err : RO; bitpos: [17]; default: 0; 1656 * Any bit equal to 1 denotes a programming error in EFUSE_SOFT_DIS_JTAG. 1657 */ 1658 uint32_t soft_dis_jtag_err:1; 1659 /** hard_dis_jtag_err : RO; bitpos: [18]; default: 0; 1660 * Any bit equal to 1 denotes a programming error in EFUSE_HARD_DIS_JTAG. 1661 */ 1662 uint32_t hard_dis_jtag_err:1; 1663 /** dis_download_manual_encrypt_err : RO; bitpos: [19]; default: 0; 1664 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. 1665 */ 1666 uint32_t dis_download_manual_encrypt_err:1; 1667 /** usb_drefh_err : RO; bitpos: [21:20]; default: 0; 1668 * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFH. 1669 */ 1670 uint32_t usb_drefh_err:2; 1671 /** usb_drefl_err : RO; bitpos: [23:22]; default: 0; 1672 * Any bit equal to 1 denotes a programming error in EFUSE_USB_DREFL. 1673 */ 1674 uint32_t usb_drefl_err:2; 1675 /** usb_exchg_pins_err : RO; bitpos: [24]; default: 0; 1676 * Any bit equal to 1 denotes a programming error in EFUSE_USB_EXCHG_PINS. 1677 */ 1678 uint32_t usb_exchg_pins_err:1; 1679 /** ext_phy_enable_err : RO; bitpos: [25]; default: 0; 1680 * Any bit equal to 1 denotes a programming error in EFUSE_EXT_PHY_ENABLE. 1681 */ 1682 uint32_t ext_phy_enable_err:1; 1683 /** usb_force_nopersist_err : RO; bitpos: [26]; default: 0; 1684 * Any bit equal to 1 denotes a programming error in EFUSE_USB_FORCE_NOPERSIST. 1685 */ 1686 uint32_t usb_force_nopersist_err:1; 1687 /** rpt4_reserved0_err : RO; bitpos: [28:27]; default: 0; 1688 * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED0. 1689 */ 1690 uint32_t rpt4_reserved0_err:2; 1691 /** vdd_spi_modecurlim_err : RO; bitpos: [29]; default: 0; 1692 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_MODECURLIM. 1693 */ 1694 uint32_t vdd_spi_modecurlim_err:1; 1695 /** vdd_spi_drefh_err : RO; bitpos: [31:30]; default: 0; 1696 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFH. 1697 */ 1698 uint32_t vdd_spi_drefh_err:2; 1699 }; 1700 uint32_t val; 1701 } efuse_rd_repeat_err0_reg_t; 1702 1703 /** Type of rd_repeat_err1 register 1704 * Programming error record register 1 of BLOCK0. 1705 */ 1706 typedef union { 1707 struct { 1708 /** vdd_spi_drefm_err : RO; bitpos: [1:0]; default: 0; 1709 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFM. 1710 */ 1711 uint32_t vdd_spi_drefm_err:2; 1712 /** vdd_spi_drefl_err : RO; bitpos: [3:2]; default: 0; 1713 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DREFL. 1714 */ 1715 uint32_t vdd_spi_drefl_err:2; 1716 /** vdd_spi_xpd_err : RO; bitpos: [4]; default: 0; 1717 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_XPD. 1718 */ 1719 uint32_t vdd_spi_xpd_err:1; 1720 /** vdd_spi_tieh_err : RO; bitpos: [5]; default: 0; 1721 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_TIEH. 1722 */ 1723 uint32_t vdd_spi_tieh_err:1; 1724 /** vdd_spi_force_err : RO; bitpos: [6]; default: 0; 1725 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_FORCE. 1726 */ 1727 uint32_t vdd_spi_force_err:1; 1728 /** vdd_spi_en_init_err : RO; bitpos: [7]; default: 0; 1729 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_EN_INIT. 1730 */ 1731 uint32_t vdd_spi_en_init_err:1; 1732 /** vdd_spi_encurlim_err : RO; bitpos: [8]; default: 0; 1733 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_ENCURLIM. 1734 */ 1735 uint32_t vdd_spi_encurlim_err:1; 1736 /** vdd_spi_dcurlim_err : RO; bitpos: [11:9]; default: 0; 1737 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCURLIM. 1738 */ 1739 uint32_t vdd_spi_dcurlim_err:3; 1740 /** vdd_spi_init_err : RO; bitpos: [13:12]; default: 0; 1741 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_INIT. 1742 */ 1743 uint32_t vdd_spi_init_err:2; 1744 /** vdd_spi_dcap_err : RO; bitpos: [15:14]; default: 0; 1745 * Any bit equal to 1 denotes a programming error in EFUSE_VDD_SPI_DCAP. 1746 */ 1747 uint32_t vdd_spi_dcap_err:2; 1748 /** wdt_delay_sel_err : RO; bitpos: [17:16]; default: 0; 1749 * Any bit equal to 1 denotes a programming error in EFUSE_WDT_DELAY_SEL. 1750 */ 1751 uint32_t wdt_delay_sel_err:2; 1752 /** spi_boot_crypt_cnt_err : RO; bitpos: [20:18]; default: 0; 1753 * Any bit equal to 1 denotes a programming error in EFUSE_SPI_BOOT_CRYPT_CNT. 1754 */ 1755 uint32_t spi_boot_crypt_cnt_err:3; 1756 /** secure_boot_key_revoke0_err : RO; bitpos: [21]; default: 0; 1757 * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE0. 1758 */ 1759 uint32_t secure_boot_key_revoke0_err:1; 1760 /** secure_boot_key_revoke1_err : RO; bitpos: [22]; default: 0; 1761 * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE1. 1762 */ 1763 uint32_t secure_boot_key_revoke1_err:1; 1764 /** secure_boot_key_revoke2_err : RO; bitpos: [23]; default: 0; 1765 * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_KEY_REVOKE2. 1766 */ 1767 uint32_t secure_boot_key_revoke2_err:1; 1768 /** key_purpose_0_err : RO; bitpos: [27:24]; default: 0; 1769 * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_0. 1770 */ 1771 uint32_t key_purpose_0_err:4; 1772 /** key_purpose_1_err : RO; bitpos: [31:28]; default: 0; 1773 * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_1. 1774 */ 1775 uint32_t key_purpose_1_err:4; 1776 }; 1777 uint32_t val; 1778 } efuse_rd_repeat_err1_reg_t; 1779 1780 /** Type of rd_repeat_err2 register 1781 * Programming error record register 2 of BLOCK0. 1782 */ 1783 typedef union { 1784 struct { 1785 /** key_purpose_2_err : RO; bitpos: [3:0]; default: 0; 1786 * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_2. 1787 */ 1788 uint32_t key_purpose_2_err:4; 1789 /** key_purpose_3_err : RO; bitpos: [7:4]; default: 0; 1790 * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_3. 1791 */ 1792 uint32_t key_purpose_3_err:4; 1793 /** key_purpose_4_err : RO; bitpos: [11:8]; default: 0; 1794 * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_4. 1795 */ 1796 uint32_t key_purpose_4_err:4; 1797 /** key_purpose_5_err : RO; bitpos: [15:12]; default: 0; 1798 * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_5. 1799 */ 1800 uint32_t key_purpose_5_err:4; 1801 /** key_purpose_6_err : RO; bitpos: [19:16]; default: 0; 1802 * Any bit equal to 1 denotes a programming error in EFUSE_KEY_PURPOSE_6. 1803 */ 1804 uint32_t key_purpose_6_err:4; 1805 /** secure_boot_en_err : RO; bitpos: [20]; default: 0; 1806 * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_BOOT_EN. 1807 */ 1808 uint32_t secure_boot_en_err:1; 1809 /** secure_boot_aggressive_revoke_err : RO; bitpos: [21]; default: 0; 1810 * Any bit equal to 1 denotes a programming error in 1811 * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. 1812 */ 1813 uint32_t secure_boot_aggressive_revoke_err:1; 1814 /** rpt4_reserved1_err : RO; bitpos: [27:22]; default: 0; 1815 * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED1. 1816 */ 1817 uint32_t rpt4_reserved1_err:6; 1818 /** flash_tpuw_err : RO; bitpos: [31:28]; default: 0; 1819 * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TPUW. 1820 */ 1821 uint32_t flash_tpuw_err:4; 1822 }; 1823 uint32_t val; 1824 } efuse_rd_repeat_err2_reg_t; 1825 1826 /** Type of rd_repeat_err3 register 1827 * Programming error record register 3 of BLOCK0. 1828 */ 1829 typedef union { 1830 struct { 1831 /** dis_download_mode_err : RO; bitpos: [0]; default: 0; 1832 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_DOWNLOAD_MODE. 1833 */ 1834 uint32_t dis_download_mode_err:1; 1835 /** dis_legacy_spi_boot_err : RO; bitpos: [1]; default: 0; 1836 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_LEGACY_SPI_BOOT. 1837 */ 1838 uint32_t dis_legacy_spi_boot_err:1; 1839 /** uart_print_channel_err : RO; bitpos: [2]; default: 0; 1840 * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CHANNEL. 1841 */ 1842 uint32_t uart_print_channel_err:1; 1843 /** rpt4_reserved3_err : RO; bitpos: [3]; default: 0; 1844 * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED3. 1845 */ 1846 uint32_t rpt4_reserved3_err:1; 1847 /** dis_usb_download_mode_err : RO; bitpos: [4]; default: 0; 1848 * Any bit equal to 1 denotes a programming error in EFUSE_DIS_USB_DOWNLOAD_MODE. 1849 */ 1850 uint32_t dis_usb_download_mode_err:1; 1851 /** enable_security_download_err : RO; bitpos: [5]; default: 0; 1852 * Any bit equal to 1 denotes a programming error in EFUSE_ENABLE_SECURITY_DOWNLOAD. 1853 */ 1854 uint32_t enable_security_download_err:1; 1855 /** uart_print_control_err : RO; bitpos: [7:6]; default: 0; 1856 * Any bit equal to 1 denotes a programming error in EFUSE_UART_PRINT_CONTROL. 1857 */ 1858 uint32_t uart_print_control_err:2; 1859 /** pin_power_selection_err : RO; bitpos: [8]; default: 0; 1860 * Any bit equal to 1 denotes a programming error in EFUSE_PIN_POWER_SELECTION. 1861 */ 1862 uint32_t pin_power_selection_err:1; 1863 /** flash_type_err : RO; bitpos: [9]; default: 0; 1864 * Any bit equal to 1 denotes a programming error in EFUSE_FLASH_TYPE. 1865 */ 1866 uint32_t flash_type_err:1; 1867 /** force_send_resume_err : RO; bitpos: [10]; default: 0; 1868 * Any bit equal to 1 denotes a programming error in EFUSE_FORCE_SEND_RESUME. 1869 */ 1870 uint32_t force_send_resume_err:1; 1871 /** secure_version_err : RO; bitpos: [26:11]; default: 0; 1872 * Any bit equal to 1 denotes a programming error in EFUSE_SECURE_VERSION. 1873 */ 1874 uint32_t secure_version_err:16; 1875 /** rpt4_reserved2_err : RO; bitpos: [31:27]; default: 0; 1876 * Any bit equal to 1 denotes a programming error in EFUSE_RPT4_RESERVED2. 1877 */ 1878 uint32_t rpt4_reserved2_err:5; 1879 }; 1880 uint32_t val; 1881 } efuse_rd_repeat_err3_reg_t; 1882 1883 /** Type of rd_repeat_err4 register 1884 * Programming error record register 4 of BLOCK0. 1885 */ 1886 typedef union { 1887 struct { 1888 /** rpt4_reserved4_err : RO; bitpos: [23:0]; default: 0; 1889 * If any bit in RPT4_RESERVED4 is 1, there is a programming error in 1890 * EFUSE_RPT4_RESERVED4. 1891 */ 1892 uint32_t rpt4_reserved4_err:24; 1893 uint32_t reserved_24:8; 1894 }; 1895 uint32_t val; 1896 } efuse_rd_repeat_err4_reg_t; 1897 1898 /** Type of rd_rs_err0 register 1899 * Programming error record register 0 of BLOCK1-10. 1900 */ 1901 typedef union { 1902 struct { 1903 /** mac_spi_8m_err_num : RO; bitpos: [2:0]; default: 0; 1904 * The value of this signal means the number of error bytes in BLOCK1. 1905 */ 1906 uint32_t mac_spi_8m_err_num:3; 1907 /** mac_spi_8m_fail : RO; bitpos: [3]; default: 0; 1908 * 0: Means no failure and that the data of BLOCK1 is reliable. 1: Means that 1909 * programming BLOCK1 data failed and the number of error bytes is over 5. 1910 */ 1911 uint32_t mac_spi_8m_fail:1; 1912 /** sys_part1_num : RO; bitpos: [6:4]; default: 0; 1913 * The value of this signal means the number of error bytes in BLOCK2. 1914 */ 1915 uint32_t sys_part1_num:3; 1916 /** sys_part1_fail : RO; bitpos: [7]; default: 0; 1917 * 0: Means no failure and that the data of BLOCK2 is reliable. 1: Means that 1918 * programming BLOCK2 data failed and the number of error bytes is over 5. 1919 */ 1920 uint32_t sys_part1_fail:1; 1921 /** usr_data_err_num : RO; bitpos: [10:8]; default: 0; 1922 * The value of this signal means the number of error bytes in BLOCK3. 1923 */ 1924 uint32_t usr_data_err_num:3; 1925 /** usr_data_fail : RO; bitpos: [11]; default: 0; 1926 * 0: Means no failure and that the data of BLOCK3 is reliable. 1: Means that 1927 * programming BLOCK3 data failed and the number of error bytes is over 5. 1928 */ 1929 uint32_t usr_data_fail:1; 1930 /** key0_err_num : RO; bitpos: [14:12]; default: 0; 1931 * The value of this signal means the number of error bytes in KEY0. 1932 */ 1933 uint32_t key0_err_num:3; 1934 /** key0_fail : RO; bitpos: [15]; default: 0; 1935 * 0: Means no failure and that the data of KEY0 is reliable. 1: Means that 1936 * programming KEY0 failed and the number of error bytes is over 5. 1937 */ 1938 uint32_t key0_fail:1; 1939 /** key1_err_num : RO; bitpos: [18:16]; default: 0; 1940 * The value of this signal means the number of error bytes in KEY1. 1941 */ 1942 uint32_t key1_err_num:3; 1943 /** key1_fail : RO; bitpos: [19]; default: 0; 1944 * 0: Means no failure and that the data of KEY1 is reliable. 1: Means that 1945 * programming KEY1 failed and the number of error bytes is over 5. 1946 */ 1947 uint32_t key1_fail:1; 1948 /** key2_err_num : RO; bitpos: [22:20]; default: 0; 1949 * The value of this signal means the number of error bytes in KEY2. 1950 */ 1951 uint32_t key2_err_num:3; 1952 /** key2_fail : RO; bitpos: [23]; default: 0; 1953 * 0: Means no failure and that the data of KEY2 is reliable. 1: Means that 1954 * programming KEY2 failed and the number of error bytes is over 5. 1955 */ 1956 uint32_t key2_fail:1; 1957 /** key3_err_num : RO; bitpos: [26:24]; default: 0; 1958 * The value of this signal means the number of error bytes in KEY3. 1959 */ 1960 uint32_t key3_err_num:3; 1961 /** key3_fail : RO; bitpos: [27]; default: 0; 1962 * 0: Means no failure and that the data of KEY3 is reliable. 1: Means that 1963 * programming KEY3 failed and the number of error bytes is over 5. 1964 */ 1965 uint32_t key3_fail:1; 1966 /** key4_err_num : RO; bitpos: [30:28]; default: 0; 1967 * The value of this signal means the number of error bytes in KEY4. 1968 */ 1969 uint32_t key4_err_num:3; 1970 /** key4_fail : RO; bitpos: [31]; default: 0; 1971 * 0: Means no failure and that the data of KEY4 is reliable. 1: Means that 1972 * programming KEY4 failed and the number of error bytes is over 5. 1973 */ 1974 uint32_t key4_fail:1; 1975 }; 1976 uint32_t val; 1977 } efuse_rd_rs_err0_reg_t; 1978 1979 /** Type of rd_rs_err1 register 1980 * Programming error record register 1 of BLOCK1-10. 1981 */ 1982 typedef union { 1983 struct { 1984 /** key5_err_num : RO; bitpos: [2:0]; default: 0; 1985 * The value of this signal means the number of error bytes in KEY5. 1986 */ 1987 uint32_t key5_err_num:3; 1988 /** key5_fail : RO; bitpos: [3]; default: 0; 1989 * 0: Means no failure and that the data of KEY5 is reliable. 1: Means that 1990 * programming user data failed and the number of error bytes is over 5. 1991 */ 1992 uint32_t key5_fail:1; 1993 /** sys_part2_err_num : RO; bitpos: [6:4]; default: 0; 1994 * The value of this signal means the number of error bytes in BLOCK10. 1995 */ 1996 uint32_t sys_part2_err_num:3; 1997 /** sys_part2_fail : RO; bitpos: [7]; default: 0; 1998 * 0: Means no failure and that the data of BLOCK10 is reliable. 1: Means that 1999 * programming BLOCK10 data failed and the number of error bytes is over 5. 2000 */ 2001 uint32_t sys_part2_fail:1; 2002 uint32_t reserved_8:24; 2003 }; 2004 uint32_t val; 2005 } efuse_rd_rs_err1_reg_t; 2006 2007 2008 /** Group: Control/Status Registers */ 2009 /** Type of clk register 2010 * eFuse clock configuration register. 2011 */ 2012 typedef union { 2013 struct { 2014 /** efuse_mem_force_pd : R/W; bitpos: [0]; default: 0; 2015 * If set, forces eFuse SRAM into power-saving mode. 2016 */ 2017 uint32_t efuse_mem_force_pd:1; 2018 /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; 2019 * If set, forces to activate clock signal of eFuse SRAM. 2020 */ 2021 uint32_t mem_clk_force_on:1; 2022 /** efuse_mem_force_pu : R/W; bitpos: [2]; default: 0; 2023 * If set, forces eFuse SRAM into working mode. 2024 */ 2025 uint32_t efuse_mem_force_pu:1; 2026 uint32_t reserved_3:13; 2027 /** clk_en : R/W; bitpos: [16]; default: 0; 2028 * If set, forces to enable clock signal of eFuse memory. 2029 */ 2030 uint32_t clk_en:1; 2031 uint32_t reserved_17:15; 2032 }; 2033 uint32_t val; 2034 } efuse_clk_reg_t; 2035 2036 /** Type of conf register 2037 * eFuse operation mode configuration register. 2038 */ 2039 typedef union { 2040 struct { 2041 /** op_code : R/W; bitpos: [15:0]; default: 0; 2042 * 0x5A5A: Operate programming command. 0x5AA5: Operate read command. 2043 */ 2044 uint32_t op_code:16; 2045 uint32_t reserved_16:16; 2046 }; 2047 uint32_t val; 2048 } efuse_conf_reg_t; 2049 2050 /** Type of status register 2051 * eFuse status register. 2052 */ 2053 typedef union { 2054 struct { 2055 /** state : RO; bitpos: [3:0]; default: 0; 2056 * Indicates the state of the eFuse state machine. 2057 */ 2058 uint32_t state:4; 2059 /** otp_load_sw : RO; bitpos: [4]; default: 0; 2060 * The value of OTP_LOAD_SW. 2061 */ 2062 uint32_t otp_load_sw:1; 2063 /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; 2064 * The value of OTP_VDDQ_C_SYNC2. 2065 */ 2066 uint32_t otp_vddq_c_sync2:1; 2067 /** otp_strobe_sw : RO; bitpos: [6]; default: 0; 2068 * The value of OTP_STROBE_SW. 2069 */ 2070 uint32_t otp_strobe_sw:1; 2071 /** otp_csb_sw : RO; bitpos: [7]; default: 0; 2072 * The value of OTP_CSB_SW. 2073 */ 2074 uint32_t otp_csb_sw:1; 2075 /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; 2076 * The value of OTP_PGENB_SW. 2077 */ 2078 uint32_t otp_pgenb_sw:1; 2079 /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; 2080 * The value of OTP_VDDQ_IS_SW. 2081 */ 2082 uint32_t otp_vddq_is_sw:1; 2083 /** repeat_err_cnt : RO; bitpos: [17:10]; default: 0; 2084 * Indicates the number of error bits during programming BLOCK0. 2085 */ 2086 uint32_t repeat_err_cnt:8; 2087 uint32_t reserved_18:14; 2088 }; 2089 uint32_t val; 2090 } efuse_status_reg_t; 2091 2092 /** Type of cmd register 2093 * eFuse command register. 2094 */ 2095 typedef union { 2096 struct { 2097 /** read_cmd : R/W; bitpos: [0]; default: 0; 2098 * Set this bit to send read command. 2099 */ 2100 uint32_t read_cmd:1; 2101 /** pgm_cmd : R/W; bitpos: [1]; default: 0; 2102 * Set this bit to send programming command. 2103 */ 2104 uint32_t pgm_cmd:1; 2105 /** blk_num : R/W; bitpos: [5:2]; default: 0; 2106 * The serial number of the block to be programmed. Value 0-10 corresponds to block 2107 * number 0-10, respectively. 2108 */ 2109 uint32_t blk_num:4; 2110 uint32_t reserved_6:26; 2111 }; 2112 uint32_t val; 2113 } efuse_cmd_reg_t; 2114 2115 /** Type of dac_conf register 2116 * Controls the eFuse programming voltage. 2117 */ 2118 typedef union { 2119 struct { 2120 /** dac_clk_div : R/W; bitpos: [7:0]; default: 28; 2121 * Controls the division factor of the rising clock of the programming voltage. 2122 */ 2123 uint32_t dac_clk_div:8; 2124 /** dac_clk_pad_sel : R/W; bitpos: [8]; default: 0; 2125 * Don't care. 2126 */ 2127 uint32_t dac_clk_pad_sel:1; 2128 /** dac_num : R/W; bitpos: [16:9]; default: 255; 2129 * Controls the rising period of the programming voltage. 2130 */ 2131 uint32_t dac_num:8; 2132 /** oe_clr : R/W; bitpos: [17]; default: 0; 2133 * Reduces the power supply of the programming voltage. 2134 */ 2135 uint32_t oe_clr:1; 2136 uint32_t reserved_18:14; 2137 }; 2138 uint32_t val; 2139 } efuse_dac_conf_reg_t; 2140 2141 2142 /** Group: Interrupt Registers */ 2143 /** Type of int_raw register 2144 * eFuse raw interrupt register. 2145 */ 2146 typedef union { 2147 struct { 2148 /** read_done_int_raw : RO; bitpos: [0]; default: 0; 2149 * The raw bit signal for read_done interrupt. 2150 */ 2151 uint32_t read_done_int_raw:1; 2152 /** pgm_done_int_raw : RO; bitpos: [1]; default: 0; 2153 * The raw bit signal for pgm_done interrupt. 2154 */ 2155 uint32_t pgm_done_int_raw:1; 2156 uint32_t reserved_2:30; 2157 }; 2158 uint32_t val; 2159 } efuse_int_raw_reg_t; 2160 2161 /** Type of int_st register 2162 * eFuse interrupt status register. 2163 */ 2164 typedef union { 2165 struct { 2166 /** read_done_int_st : RO; bitpos: [0]; default: 0; 2167 * The status signal for read_done interrupt. 2168 */ 2169 uint32_t read_done_int_st:1; 2170 /** pgm_done_int_st : RO; bitpos: [1]; default: 0; 2171 * The status signal for pgm_done interrupt. 2172 */ 2173 uint32_t pgm_done_int_st:1; 2174 uint32_t reserved_2:30; 2175 }; 2176 uint32_t val; 2177 } efuse_int_st_reg_t; 2178 2179 /** Type of int_ena register 2180 * eFuse interrupt enable register. 2181 */ 2182 typedef union { 2183 struct { 2184 /** read_done_int_ena : R/W; bitpos: [0]; default: 0; 2185 * The enable signal for read_done interrupt. 2186 */ 2187 uint32_t read_done_int_ena:1; 2188 /** pgm_done_int_ena : R/W; bitpos: [1]; default: 0; 2189 * The enable signal for pgm_done interrupt. 2190 */ 2191 uint32_t pgm_done_int_ena:1; 2192 uint32_t reserved_2:30; 2193 }; 2194 uint32_t val; 2195 } efuse_int_ena_reg_t; 2196 2197 /** Type of int_clr register 2198 * eFuse interrupt clear register. 2199 */ 2200 typedef union { 2201 struct { 2202 /** read_done_int_clr : WO; bitpos: [0]; default: 0; 2203 * The clear signal for read_done interrupt. 2204 */ 2205 uint32_t read_done_int_clr:1; 2206 /** pgm_done_int_clr : WO; bitpos: [1]; default: 0; 2207 * The clear signal for pgm_done interrupt. 2208 */ 2209 uint32_t pgm_done_int_clr:1; 2210 uint32_t reserved_2:30; 2211 }; 2212 uint32_t val; 2213 } efuse_int_clr_reg_t; 2214 2215 2216 /** Group: Configuration Registers */ 2217 /** Type of rd_tim_conf register 2218 * Configures read timing parameters. 2219 */ 2220 typedef union { 2221 struct { 2222 /** thr_a : R/W; bitpos: [7:0]; default: 1; 2223 * Configures the hold time of read operation. 2224 */ 2225 uint32_t thr_a:8; 2226 /** trd : R/W; bitpos: [15:8]; default: 1; 2227 * Configures the length of pulse of read operation. 2228 */ 2229 uint32_t trd:8; 2230 /** tsur_a : R/W; bitpos: [23:16]; default: 1; 2231 * Configures the setup time of read operation. 2232 */ 2233 uint32_t tsur_a:8; 2234 /** read_init_num : R/W; bitpos: [31:24]; default: 18; 2235 * Configures the initial read time of eFuse. 2236 */ 2237 uint32_t read_init_num:8; 2238 }; 2239 uint32_t val; 2240 } efuse_rd_tim_conf_reg_t; 2241 2242 /** Type of wr_tim_conf0 register 2243 * Configuration register 0 of eFuse programming timing parameters. 2244 */ 2245 typedef union { 2246 struct { 2247 /** thp_a : R/W; bitpos: [7:0]; default: 1; 2248 * Configures the hold time of programming operation. 2249 */ 2250 uint32_t thp_a:8; 2251 /** tpgm_inactive : R/W; bitpos: [15:8]; default: 1; 2252 * Configures the length of pulse during programming 0 to eFuse. 2253 */ 2254 uint32_t tpgm_inactive:8; 2255 /** tpgm : R/W; bitpos: [31:16]; default: 200; 2256 * Configures the length of pulse during programming 1 to eFuse. 2257 */ 2258 uint32_t tpgm:16; 2259 }; 2260 uint32_t val; 2261 } efuse_wr_tim_conf0_reg_t; 2262 2263 /** Type of wr_tim_conf1 register 2264 * Configuration register 1 of eFuse programming timing parameters. 2265 */ 2266 typedef union { 2267 struct { 2268 /** tsup_a : R/W; bitpos: [7:0]; default: 1; 2269 * Configures the setup time of programming operation. 2270 */ 2271 uint32_t tsup_a:8; 2272 /** pwr_on_num : R/W; bitpos: [23:8]; default: 10368; 2273 * Configures the power up time for VDDQ. 2274 */ 2275 uint32_t pwr_on_num:16; 2276 uint32_t reserved_24:8; 2277 }; 2278 uint32_t val; 2279 } efuse_wr_tim_conf1_reg_t; 2280 2281 /** Type of wr_tim_conf2 register 2282 * Configuration register 2 of eFuse programming timing parameters. 2283 */ 2284 typedef union { 2285 struct { 2286 /** pwr_off_num : R/W; bitpos: [15:0]; default: 400; 2287 * Configures the power outage time for VDDQ. 2288 */ 2289 uint32_t pwr_off_num:16; 2290 uint32_t reserved_16:16; 2291 }; 2292 uint32_t val; 2293 } efuse_wr_tim_conf2_reg_t; 2294 2295 2296 /** Group: Version Register */ 2297 /** Type of date register 2298 * Version control register. 2299 */ 2300 typedef union { 2301 struct { 2302 /** date : R/W; bitpos: [31:0]; default: 419959040; 2303 * Version control register. 2304 */ 2305 uint32_t date:32; 2306 }; 2307 uint32_t val; 2308 } efuse_date_reg_t; 2309 2310 2311 typedef struct { 2312 volatile efuse_pgm_data0_reg_t pgm_data0; 2313 volatile efuse_pgm_data1_reg_t pgm_data1; 2314 volatile efuse_pgm_data2_reg_t pgm_data2; 2315 volatile efuse_pgm_data3_reg_t pgm_data3; 2316 volatile efuse_pgm_data4_reg_t pgm_data4; 2317 volatile efuse_pgm_data5_reg_t pgm_data5; 2318 volatile efuse_pgm_data6_reg_t pgm_data6; 2319 volatile efuse_pgm_data7_reg_t pgm_data7; 2320 volatile efuse_pgm_check_value0_reg_t pgm_check_value0; 2321 volatile efuse_pgm_check_value1_reg_t pgm_check_value1; 2322 volatile efuse_pgm_check_value2_reg_t pgm_check_value2; 2323 volatile efuse_rd_wr_dis_reg_t rd_wr_dis; 2324 volatile efuse_rd_repeat_data0_reg_t rd_repeat_data0; 2325 volatile efuse_rd_repeat_data1_reg_t rd_repeat_data1; 2326 volatile efuse_rd_repeat_data2_reg_t rd_repeat_data2; 2327 volatile efuse_rd_repeat_data3_reg_t rd_repeat_data3; 2328 volatile efuse_rd_repeat_data4_reg_t rd_repeat_data4; 2329 volatile efuse_rd_mac_spi_sys_0_reg_t rd_mac_spi_sys_0; 2330 volatile efuse_rd_mac_spi_sys_1_reg_t rd_mac_spi_sys_1; 2331 volatile efuse_rd_mac_spi_sys_2_reg_t rd_mac_spi_sys_2; 2332 volatile efuse_rd_mac_spi_sys_3_reg_t rd_mac_spi_sys_3; 2333 volatile efuse_rd_mac_spi_sys_4_reg_t rd_mac_spi_sys_4; 2334 volatile efuse_rd_mac_spi_sys_5_reg_t rd_mac_spi_sys_5; 2335 volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0; 2336 volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1; 2337 volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2; 2338 volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3; 2339 volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4; 2340 volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5; 2341 volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6; 2342 volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7; 2343 volatile efuse_rd_usr_data0_reg_t rd_usr_data0; 2344 volatile efuse_rd_usr_data1_reg_t rd_usr_data1; 2345 volatile efuse_rd_usr_data2_reg_t rd_usr_data2; 2346 volatile efuse_rd_usr_data3_reg_t rd_usr_data3; 2347 volatile efuse_rd_usr_data4_reg_t rd_usr_data4; 2348 volatile efuse_rd_usr_data5_reg_t rd_usr_data5; 2349 volatile efuse_rd_usr_data6_reg_t rd_usr_data6; 2350 volatile efuse_rd_usr_data7_reg_t rd_usr_data7; 2351 volatile efuse_rd_key0_data0_reg_t rd_key0_data0; 2352 volatile efuse_rd_key0_data1_reg_t rd_key0_data1; 2353 volatile efuse_rd_key0_data2_reg_t rd_key0_data2; 2354 volatile efuse_rd_key0_data3_reg_t rd_key0_data3; 2355 volatile efuse_rd_key0_data4_reg_t rd_key0_data4; 2356 volatile efuse_rd_key0_data5_reg_t rd_key0_data5; 2357 volatile efuse_rd_key0_data6_reg_t rd_key0_data6; 2358 volatile efuse_rd_key0_data7_reg_t rd_key0_data7; 2359 volatile efuse_rd_key1_data0_reg_t rd_key1_data0; 2360 volatile efuse_rd_key1_data1_reg_t rd_key1_data1; 2361 volatile efuse_rd_key1_data2_reg_t rd_key1_data2; 2362 volatile efuse_rd_key1_data3_reg_t rd_key1_data3; 2363 volatile efuse_rd_key1_data4_reg_t rd_key1_data4; 2364 volatile efuse_rd_key1_data5_reg_t rd_key1_data5; 2365 volatile efuse_rd_key1_data6_reg_t rd_key1_data6; 2366 volatile efuse_rd_key1_data7_reg_t rd_key1_data7; 2367 volatile efuse_rd_key2_data0_reg_t rd_key2_data0; 2368 volatile efuse_rd_key2_data1_reg_t rd_key2_data1; 2369 volatile efuse_rd_key2_data2_reg_t rd_key2_data2; 2370 volatile efuse_rd_key2_data3_reg_t rd_key2_data3; 2371 volatile efuse_rd_key2_data4_reg_t rd_key2_data4; 2372 volatile efuse_rd_key2_data5_reg_t rd_key2_data5; 2373 volatile efuse_rd_key2_data6_reg_t rd_key2_data6; 2374 volatile efuse_rd_key2_data7_reg_t rd_key2_data7; 2375 volatile efuse_rd_key3_data0_reg_t rd_key3_data0; 2376 volatile efuse_rd_key3_data1_reg_t rd_key3_data1; 2377 volatile efuse_rd_key3_data2_reg_t rd_key3_data2; 2378 volatile efuse_rd_key3_data3_reg_t rd_key3_data3; 2379 volatile efuse_rd_key3_data4_reg_t rd_key3_data4; 2380 volatile efuse_rd_key3_data5_reg_t rd_key3_data5; 2381 volatile efuse_rd_key3_data6_reg_t rd_key3_data6; 2382 volatile efuse_rd_key3_data7_reg_t rd_key3_data7; 2383 volatile efuse_rd_key4_data0_reg_t rd_key4_data0; 2384 volatile efuse_rd_key4_data1_reg_t rd_key4_data1; 2385 volatile efuse_rd_key4_data2_reg_t rd_key4_data2; 2386 volatile efuse_rd_key4_data3_reg_t rd_key4_data3; 2387 volatile efuse_rd_key4_data4_reg_t rd_key4_data4; 2388 volatile efuse_rd_key4_data5_reg_t rd_key4_data5; 2389 volatile efuse_rd_key4_data6_reg_t rd_key4_data6; 2390 volatile efuse_rd_key4_data7_reg_t rd_key4_data7; 2391 volatile efuse_rd_key5_data0_reg_t rd_key5_data0; 2392 volatile efuse_rd_key5_data1_reg_t rd_key5_data1; 2393 volatile efuse_rd_key5_data2_reg_t rd_key5_data2; 2394 volatile efuse_rd_key5_data3_reg_t rd_key5_data3; 2395 volatile efuse_rd_key5_data4_reg_t rd_key5_data4; 2396 volatile efuse_rd_key5_data5_reg_t rd_key5_data5; 2397 volatile efuse_rd_key5_data6_reg_t rd_key5_data6; 2398 volatile efuse_rd_key5_data7_reg_t rd_key5_data7; 2399 volatile efuse_rd_sys_part2_data0_reg_t rd_sys_part2_data0; 2400 volatile efuse_rd_sys_part2_data1_reg_t rd_sys_part2_data1; 2401 volatile efuse_rd_sys_part2_data2_reg_t rd_sys_part2_data2; 2402 volatile efuse_rd_sys_part2_data3_reg_t rd_sys_part2_data3; 2403 volatile efuse_rd_sys_part2_data4_reg_t rd_sys_part2_data4; 2404 volatile efuse_rd_sys_part2_data5_reg_t rd_sys_part2_data5; 2405 volatile efuse_rd_sys_part2_data6_reg_t rd_sys_part2_data6; 2406 volatile efuse_rd_sys_part2_data7_reg_t rd_sys_part2_data7; 2407 volatile efuse_rd_repeat_err0_reg_t rd_repeat_err0; 2408 volatile efuse_rd_repeat_err1_reg_t rd_repeat_err1; 2409 volatile efuse_rd_repeat_err2_reg_t rd_repeat_err2; 2410 volatile efuse_rd_repeat_err3_reg_t rd_repeat_err3; 2411 uint32_t reserved_18c; 2412 volatile efuse_rd_repeat_err4_reg_t rd_repeat_err4; 2413 uint32_t reserved_194[11]; 2414 volatile efuse_rd_rs_err0_reg_t rd_rs_err0; 2415 volatile efuse_rd_rs_err1_reg_t rd_rs_err1; 2416 volatile efuse_clk_reg_t clk; 2417 volatile efuse_conf_reg_t conf; 2418 volatile efuse_status_reg_t status; 2419 volatile efuse_cmd_reg_t cmd; 2420 volatile efuse_int_raw_reg_t int_raw; 2421 volatile efuse_int_st_reg_t int_st; 2422 volatile efuse_int_ena_reg_t int_ena; 2423 volatile efuse_int_clr_reg_t int_clr; 2424 volatile efuse_dac_conf_reg_t dac_conf; 2425 volatile efuse_rd_tim_conf_reg_t rd_tim_conf; 2426 volatile efuse_wr_tim_conf0_reg_t wr_tim_conf0; 2427 volatile efuse_wr_tim_conf1_reg_t wr_tim_conf1; 2428 volatile efuse_wr_tim_conf2_reg_t wr_tim_conf2; 2429 volatile efuse_date_reg_t date; 2430 } efuse_dev_t; 2431 2432 extern efuse_dev_t EFUSE; 2433 2434 #ifndef __cplusplus 2435 _Static_assert(sizeof(efuse_dev_t) == 0x200, "Invalid size of efuse_dev_t structure"); 2436 #endif 2437 2438 #ifdef __cplusplus 2439 } 2440 #endif 2441
