1 /*
2 * Copyright (c) 2025 Analog Devices, Inc.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT adi_ad7124_adc
8
9 #include <zephyr/device.h>
10 #include <zephyr/devicetree.h>
11 #include <zephyr/drivers/adc.h>
12 #include <zephyr/drivers/spi.h>
13 #include <zephyr/logging/log.h>
14 #include <zephyr/kernel.h>
15 #include <zephyr/sys/byteorder.h>
16 #include <zephyr/sys/util.h>
17 #include <zephyr/sys/crc.h>
18
19 LOG_MODULE_REGISTER(adc_ad7124, CONFIG_ADC_LOG_LEVEL);
20
21 #define ADC_CONTEXT_USES_KERNEL_TIMER
22 #include "adc_context.h"
23
24 #define AD7124_MAX_RETURNED_DATA_SIZE 6
25 #define AD7124_ADC_VREF_MV 2500U
26 #define AD7124_RESOLUTION 24
27 #define AD7124_SPI_RDY_POLL_CNT 10000
28
29 /* Maximum number of channels */
30 #define AD7124_MAX_CHANNELS 16
31 /* Total Number of Setups */
32 #define AD7124_MAX_SETUPS 8
33
34 /* AD7124-4 Standard Device ID */
35 #define AD7124_4_STD_ID 0x04
36 /* AD7124-4 B Grade Device ID */
37 #define AD7124_4_B_GRADE_ID 0x06
38 /* Device ID for the re-designed die in the AD7124-4 standard part and B-grade */
39 #define AD7124_4_NEW_ID 0x07
40
41 /* AD7124-8 Standard Device ID */
42 #define AD7124_8_STD_ID 0x14
43 /* AD7124-8 B and W Grade Device ID */
44 #define AD7124_8_B_W_GRADE_ID 0x16
45 /* Device ID for the re-designed die in the AD7124-8 standard part, B-grade and W-grade */
46 #define AD7124_8_NEW_ID 0x17
47
48 /* ODR */
49 #define ADC_ODR_DEFAULT_VALUE 0xA /* 10SPS */
50 #define ADC_ODR_MIN_VALUE 0xA /* 10SPS */
51 #define ADC_ODR_LOW_POWER_MAX 0x960 /* 2400SPS */
52 #define ADC_ODR_MID_POWER_MAX 0x12C0 /* 4800SPS */
53 #define ADC_ODR_HIGH_POWER_MAX 0x4B00 /* 19200SPS */
54
55 #define ADC_ODR_SEL_BITS_MAX 0x7FF
56 #define ADC_ODR_SEL_BITS_MIN 0x1
57
58 /* AD7124 registers */
59 #define AD7124_STATUS 0x00
60 #define AD7124_ADC_CONTROL 0x01
61 #define AD7124_DATA 0x02
62 #define AD7124_ID 0x05
63 #define AD7124_ERROR 0x06
64 #define AD7124_ERROR_EN 0x07
65 #define AD7124_CHANNEL(x) (0x09 + (x))
66 #define AD7124_CONFIG(x) (0x19 + (x))
67 #define AD7124_FILTER(x) (0x21 + (x))
68
69 /* Configuration Registers 0-7 bits */
70 #define AD7124_CFG_REG_BIPOLAR BIT(11)
71 #define AD7124_CFG_REG_REF_BUFP BIT(8)
72 #define AD7124_CFG_REG_REF_BUFM BIT(7)
73 #define AD7124_CFG_REG_AIN_BUFP BIT(6)
74 #define AD7124_CFG_REG_AINN_BUFM BIT(5)
75
76 #define AD7124_REF_BUF_MSK GENMASK(8, 7)
77 #define AD7124_AIN_BUF_MSK GENMASK(6, 5)
78 #define AD7124_SETUP_CONF_REG_REF_SEL_MSK GENMASK(4, 3)
79 #define AD7124_SETUP_CONF_PGA_MSK GENMASK(2, 0)
80 #define AD7124_ALL_BUF_MSK GENMASK(8, 0)
81
82 #define AD7124_SETUP_CONFIGURATION_MASK (AD7124_CFG_REG_BIPOLAR | AD7124_ALL_BUF_MSK)
83
84 /* ADC_Control Register bits */
85 #define AD7124_ADC_CTRL_REG_DATA_STATUS BIT(10)
86 #define AD7124_ADC_CTRL_REG_REF_EN BIT(8)
87
88 /* CRC */
89 #define AD7124_CRC8_POLYNOMIAL_REPRESENTATION 0x07 /* x8 + x2 + x + 1 */
90
91 /* Communication Register bits */
92 #define AD7124_COMM_REG_WEN (0 << 7)
93 #define AD7124_COMM_REG_WR (0 << 6)
94 #define AD7124_COMM_REG_RD BIT(6)
95 #define AD7124_COMM_REG_RA(x) ((x) & 0x3F)
96
97 /* Filter register bits */
98 #define AD7124_FILTER_CONF_REG_FILTER_MSK GENMASK(23, 21)
99 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
100
101 /* Channel register bits */
102 #define AD7124_CH_MAP_REG_CH_ENABLE BIT(15)
103 #define AD7124_CHMAP_REG_SETUP_SEL_MSK GENMASK(14, 12)
104 #define AD7124_CHMAP_REG_AINPOS_MSK GENMASK(9, 5)
105 #define AD7124_CHMAP_REG_AINNEG_MSK GENMASK(4, 0)
106
107 /* Status register bits */
108 #define AD7124_STATUS_REG_RDY BIT(7)
109 #define AD7124_STATUS_REG_POR_FLAG BIT(4)
110 #define AD7124_STATUS_REG_CH_ACTIVE(x) ((x) & 0xF)
111
112 /* Error_En register bits */
113 #define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN BIT(6)
114 #define AD7124_ERREN_REG_SPI_CRC_ERR_EN BIT(2)
115
116 /* ADC control register bits */
117 #define AD7124_POWER_MODE_MSK GENMASK(7, 6)
118 #define AD7124_ADC_CTRL_REG_MODE_MSK GENMASK(5, 2)
119
120 /* Error register bits */
121 #define AD7124_ERR_REG_SPI_IGNORE_ERR BIT(6)
122
123 enum ad7124_register_lengths {
124 AD7124_STATUS_REG_LEN = 1,
125 AD7124_ADC_CONTROL_REG_LEN = 2,
126 AD7124_DATA_REG_LEN = 3,
127 AD7124_ID_REG_LEN = 1,
128 AD7124_ERROR_REG_LEN = 3,
129 AD7124_ERROR_EN_REG_LEN = 3,
130 AD7124_CHANNEL_REG_LEN = 2,
131 AD7124_CONFIG_REG_LEN = 2,
132 AD7124_FILTER_REG_LEN = 3,
133 };
134
135 enum ad7124_mode {
136 AD7124_CONTINUOUS,
137 AD7124_SINGLE,
138 AD7124_STANDBY,
139 AD7124_POWER_DOWN,
140 AD7124_IDLE,
141 AD7124_IN_ZERO_SCALE_OFF,
142 AD7124_IN_FULL_SCALE_GAIN,
143 AD7124_SYS_ZERO_SCALE_OFF,
144 AD7124_SYS_ZERO_SCALE_GAIN,
145 };
146
147 enum ad7124_power_mode {
148 AD7124_LOW_POWER_MODE,
149 AD7124_MID_POWER_MODE,
150 AD7124_HIGH_POWER_MODE
151 };
152
153 enum adc_ad7124_master_clk_freq_hz {
154 AD7124_LOW_POWER_CLK = 76800,
155 AD7124_MID_POWER_CLK = 153600,
156 AD7124_HIGH_POWER_CLK = 614400,
157 };
158
159 enum ad7124_device_type {
160 ID_AD7124_4,
161 ID_AD7124_8
162 };
163
164 struct ad7124_control_status {
165 uint16_t value;
166 bool is_read;
167 };
168
169 enum ad7124_reference_source {
170 /* External Reference REFIN1+/-*/
171 EXTERNAL_REFIN1,
172 /* External Reference REFIN2+/-*/
173 EXTERNAL_REFIN2,
174 /* Internal 2.5V Reference */
175 INTERNAL_REF,
176 /* AVDD - AVSS */
177 AVDD_AVSS,
178 };
179
180 enum ad7124_gain {
181 AD7124_GAIN_1,
182 AD7124_GAIN_2,
183 AD7124_GAIN_4,
184 AD7124_GAIN_8,
185 AD7124_GAIN_16,
186 AD7124_GAIN_32,
187 AD7124_GAIN_64,
188 AD7124_GAIN_128
189 };
190
191 enum ad7124_filter_type {
192 AD7124_FILTER_SINC4,
193 AD7124_FILTER_SINC3 = 2U,
194 };
195
196 struct ad7124_config_props {
197 enum ad7124_reference_source refsel;
198 enum ad7124_gain pga_bits;
199 enum ad7124_filter_type filter_type;
200 uint16_t odr_sel_bits;
201 bool bipolar;
202 bool inbuf_enable;
203 bool refbuf_enable;
204 };
205
206 struct ad7124_channel_config {
207 struct ad7124_config_props props;
208 uint8_t cfg_slot;
209 bool live_cfg;
210 };
211
212 struct adc_ad7124_config {
213 struct spi_dt_spec bus;
214 uint16_t filter_type_mask;
215 uint16_t bipolar_mask;
216 uint16_t inbuf_enable_mask;
217 uint16_t refbuf_enable_mask;
218 enum ad7124_mode adc_mode;
219 enum ad7124_power_mode power_mode;
220 enum ad7124_device_type active_device;
221 uint8_t resolution;
222 bool ref_en;
223 };
224
225 struct adc_ad7124_data {
226 const struct device *dev;
227 struct adc_context ctx;
228 struct ad7124_control_status adc_control_status;
229 struct ad7124_channel_config channel_setup_cfg[AD7124_MAX_CHANNELS];
230 uint8_t setup_cfg_slots;
231 struct k_sem acquire_signal;
232 uint16_t channels;
233 uint32_t *buffer;
234 uint32_t *repeat_buffer;
235 bool crc_enable;
236 bool spi_ready;
237 #if CONFIG_ADC_ASYNC
238 struct k_thread thread;
239
240 K_KERNEL_STACK_MEMBER(stack, CONFIG_ADI_AD7124_ADC_ACQUISITION_THREAD_STACK_SIZE);
241 #endif /* CONFIG_ADC_ASYNC */
242 };
243
244 static int adc_ad7124_read_reg(const struct device *dev, uint32_t reg,
245 enum ad7124_register_lengths len, uint32_t *val);
246
adc_context_update_buffer_pointer(struct adc_context * ctx,bool repeat_sampling)247 static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
248 {
249 struct adc_ad7124_data *data = CONTAINER_OF(ctx, struct adc_ad7124_data, ctx);
250
251 if (repeat_sampling) {
252 data->buffer = data->repeat_buffer;
253 }
254 }
255
adc_context_start_sampling(struct adc_context * ctx)256 static void adc_context_start_sampling(struct adc_context *ctx)
257 {
258 struct adc_ad7124_data *data = CONTAINER_OF(ctx, struct adc_ad7124_data, ctx);
259
260 data->repeat_buffer = data->buffer;
261 k_sem_give(&data->acquire_signal);
262 }
263
adc_ad7124_acq_time_to_odr(const struct device * dev,uint16_t acq_time,uint16_t * odr)264 static int adc_ad7124_acq_time_to_odr(const struct device *dev, uint16_t acq_time, uint16_t *odr)
265 {
266 const struct adc_ad7124_config *config = dev->config;
267 uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(acq_time);
268 uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(acq_time);
269
270 /* The AD7124 uses samples per seconds units with the lowest being 10SPS
271 * regardless of the selected power mode and with acquisition_time only
272 * having 14b for time, this will not fit within here for microsecond units.
273 * Use Tick units and allow the user to specify the ODR directly.
274 */
275
276 if (acq_time == ADC_ACQ_TIME_DEFAULT) {
277 *odr = ADC_ODR_DEFAULT_VALUE;
278 return 0;
279 }
280
281 if (acquisition_time_unit != ADC_ACQ_TIME_TICKS) {
282 LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
283 return -EINVAL;
284 }
285
286 if (acquisition_time_value < ADC_ODR_MIN_VALUE) {
287 LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
288 return -EINVAL;
289 } else if (config->power_mode == AD7124_HIGH_POWER_MODE &&
290 acquisition_time_value > ADC_ODR_HIGH_POWER_MAX) {
291 LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
292 return -EINVAL;
293 } else if (config->power_mode == AD7124_MID_POWER_MODE &&
294 acquisition_time_value > ADC_ODR_MID_POWER_MAX) {
295 LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
296 return -EINVAL;
297 } else if (config->power_mode == AD7124_LOW_POWER_MODE &&
298 acquisition_time_value > ADC_ODR_LOW_POWER_MAX) {
299 LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
300 return -EINVAL;
301 }
302
303 *odr = acquisition_time_value;
304
305 return 0;
306 }
307
adc_ad7124_odr_to_fs(const struct device * dev,int16_t odr)308 static uint16_t adc_ad7124_odr_to_fs(const struct device *dev, int16_t odr)
309 {
310 const struct adc_ad7124_config *config = dev->config;
311 uint16_t odr_sel_bits;
312 uint32_t master_clk_freq;
313
314 switch (config->power_mode) {
315 case AD7124_HIGH_POWER_MODE:
316 master_clk_freq = AD7124_HIGH_POWER_CLK;
317 break;
318 case AD7124_MID_POWER_MODE:
319 master_clk_freq = AD7124_MID_POWER_CLK;
320 break;
321 case AD7124_LOW_POWER_MODE:
322 master_clk_freq = AD7124_LOW_POWER_CLK;
323 break;
324 default:
325 LOG_ERR("Invalid power mode (%u)", config->power_mode);
326 return -EINVAL;
327 }
328
329 odr_sel_bits = DIV_ROUND_CLOSEST(master_clk_freq, odr * 32);
330
331 if (odr_sel_bits < ADC_ODR_SEL_BITS_MIN) {
332 odr_sel_bits = ADC_ODR_SEL_BITS_MIN;
333 } else if (odr_sel_bits > ADC_ODR_SEL_BITS_MAX) {
334 odr_sel_bits = ADC_ODR_SEL_BITS_MAX;
335 }
336
337 return odr_sel_bits;
338 }
339
adc_ad7124_create_new_cfg(const struct device * dev,const struct adc_channel_cfg * cfg,struct ad7124_channel_config * new_cfg)340 static int adc_ad7124_create_new_cfg(const struct device *dev, const struct adc_channel_cfg *cfg,
341 struct ad7124_channel_config *new_cfg)
342 {
343 const struct adc_ad7124_config *config = dev->config;
344 uint16_t odr;
345 enum ad7124_reference_source ref_source;
346 enum ad7124_gain gain;
347 int ret;
348
349 if (cfg->channel_id >= AD7124_MAX_CHANNELS) {
350 LOG_ERR("Invalid channel (%u)", cfg->channel_id);
351 return -EINVAL;
352 }
353
354 switch (cfg->reference) {
355 case ADC_REF_INTERNAL:
356 ref_source = INTERNAL_REF;
357 break;
358 case ADC_REF_EXTERNAL0:
359 ref_source = EXTERNAL_REFIN1;
360 break;
361 case ADC_REF_EXTERNAL1:
362 ref_source = EXTERNAL_REFIN2;
363 break;
364 case ADC_REF_VDD_1:
365 ref_source = AVDD_AVSS;
366 break;
367 default:
368 LOG_ERR("Invalid reference source (%u)", cfg->reference);
369 return -EINVAL;
370 }
371
372 new_cfg->props.refsel = ref_source;
373
374 switch (cfg->gain) {
375 case ADC_GAIN_1:
376 gain = AD7124_GAIN_1;
377 break;
378 case ADC_GAIN_2:
379 gain = AD7124_GAIN_2;
380 break;
381 case ADC_GAIN_4:
382 gain = AD7124_GAIN_4;
383 break;
384 case ADC_GAIN_8:
385 gain = AD7124_GAIN_8;
386 break;
387 case ADC_GAIN_16:
388 gain = AD7124_GAIN_16;
389 break;
390 case ADC_GAIN_32:
391 gain = AD7124_GAIN_32;
392 break;
393 case ADC_GAIN_64:
394 gain = AD7124_GAIN_64;
395 break;
396 case ADC_GAIN_128:
397 gain = AD7124_GAIN_128;
398 break;
399 default:
400 LOG_ERR("Invalid gain value (%u)", cfg->gain);
401 return -EINVAL;
402 }
403
404 new_cfg->props.pga_bits = gain;
405
406 ret = adc_ad7124_acq_time_to_odr(dev, cfg->acquisition_time, &odr);
407 if (ret) {
408 return ret;
409 }
410
411 if (config->filter_type_mask & BIT(cfg->channel_id)) {
412 new_cfg->props.filter_type = AD7124_FILTER_SINC3;
413 } else {
414 new_cfg->props.filter_type = AD7124_FILTER_SINC4;
415 }
416
417 new_cfg->props.odr_sel_bits = adc_ad7124_odr_to_fs(dev, odr);
418 new_cfg->props.bipolar = config->bipolar_mask & BIT(cfg->channel_id);
419 new_cfg->props.inbuf_enable = config->inbuf_enable_mask & BIT(cfg->channel_id);
420 new_cfg->props.refbuf_enable = config->refbuf_enable_mask & BIT(cfg->channel_id);
421
422 return 0;
423 }
424
adc_ad7124_find_new_slot(const struct device * dev)425 static int adc_ad7124_find_new_slot(const struct device *dev)
426 {
427 struct adc_ad7124_data *data = dev->data;
428 uint8_t slot = data->setup_cfg_slots;
429
430 int cnt = 0;
431
432 while (slot) {
433 if ((slot & 0x1) == 0) {
434 return cnt;
435 }
436 slot >>= 1;
437 cnt++;
438 }
439
440 if (cnt == AD7124_MAX_SETUPS) {
441 return -1;
442 }
443
444 return cnt;
445 }
446
adc_ad7124_find_similar_configuration(const struct device * dev,const struct ad7124_channel_config * cfg,int channel_id)447 static int adc_ad7124_find_similar_configuration(const struct device *dev,
448 const struct ad7124_channel_config *cfg,
449 int channel_id)
450 {
451 struct adc_ad7124_data *data = dev->data;
452 int similar_channel_index = -1;
453
454 for (int i = 0; i < AD7124_MAX_CHANNELS; i++) {
455 if (!data->channel_setup_cfg[i].live_cfg && i == channel_id) {
456 continue;
457 }
458
459 if (memcmp(&cfg->props, &data->channel_setup_cfg[i].props,
460 sizeof(struct ad7124_config_props)) == 0) {
461 similar_channel_index = i;
462 break;
463 }
464 }
465
466 return similar_channel_index;
467 }
468
adc_ad7124_wait_for_spi_ready(const struct device * dev)469 static int adc_ad7124_wait_for_spi_ready(const struct device *dev)
470 {
471 int ret = 0;
472 uint32_t read_val = 0;
473 bool ready = false;
474 uint16_t spi_ready_try_count = AD7124_SPI_RDY_POLL_CNT;
475
476 while (!ready && --spi_ready_try_count) {
477 ret = adc_ad7124_read_reg(dev, AD7124_ERROR, AD7124_ERROR_REG_LEN, &read_val);
478 if (ret) {
479 return ret;
480 }
481
482 ready = (read_val & AD7124_ERR_REG_SPI_IGNORE_ERR) == 0;
483 }
484
485 if (!spi_ready_try_count) {
486 return -ETIMEDOUT;
487 }
488
489 return 0;
490 }
491
adc_ad7124_read_reg(const struct device * dev,uint32_t reg,enum ad7124_register_lengths len,uint32_t * val)492 static int adc_ad7124_read_reg(const struct device *dev, uint32_t reg,
493 enum ad7124_register_lengths len, uint32_t *val)
494 {
495 const struct adc_ad7124_config *config = dev->config;
496 struct adc_ad7124_data *data = dev->data;
497 const struct spi_dt_spec *spec = &config->bus;
498
499 int ret;
500 uint32_t cntrl_value = 0;
501 uint8_t add_status_length = 0;
502 uint8_t buffer_tx[AD7124_MAX_RETURNED_DATA_SIZE] = {0};
503 uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
504 uint8_t crc_check;
505
506 if (reg != AD7124_ERROR && data->spi_ready) {
507 ret = adc_ad7124_wait_for_spi_ready(dev);
508 if (ret) {
509 return ret;
510 }
511 }
512
513 if (reg == AD7124_DATA) {
514
515 if (data->adc_control_status.is_read) {
516 cntrl_value = data->adc_control_status.value;
517 } else {
518 ret = adc_ad7124_read_reg(dev, AD7124_ADC_CONTROL,
519 AD7124_ADC_CONTROL_REG_LEN, &cntrl_value);
520 if (ret) {
521 return ret;
522 }
523 }
524
525 if (cntrl_value & AD7124_ADC_CTRL_REG_DATA_STATUS) {
526 add_status_length = 1;
527 }
528 }
529
530 struct spi_buf tx_buf[] = {{
531 .buf = buffer_tx,
532 .len = 1,
533 }};
534 struct spi_buf rx_buf[] = {{
535 .buf = buffer_rx,
536 .len = ((data->crc_enable) ? len + 1 : len) + 1 + add_status_length,
537 }};
538 const struct spi_buf_set tx = {.buffers = tx_buf, .count = ARRAY_SIZE(tx_buf)};
539 const struct spi_buf_set rx = {.buffers = rx_buf, .count = ARRAY_SIZE(rx_buf)};
540
541 buffer_tx[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_RD | AD7124_COMM_REG_RA(reg);
542
543 ret = spi_transceive_dt(spec, &tx, &rx);
544 if (ret) {
545 return ret;
546 }
547
548 if (data->crc_enable) {
549 buffer_rx[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_RD | AD7124_COMM_REG_RA(reg);
550
551 crc_check = crc8(buffer_rx, len + 2 + add_status_length,
552 AD7124_CRC8_POLYNOMIAL_REPRESENTATION, 0, false);
553 if (crc_check) {
554 return -EBADMSG;
555 }
556 }
557
558 switch (len) {
559 case 1:
560 *val = buffer_rx[1];
561 break;
562 case 2:
563 *val = sys_get_be16(&buffer_rx[1]);
564 break;
565 case 3:
566 *val = sys_get_be24(&buffer_rx[1]);
567 break;
568 default:
569 return -EINVAL;
570 }
571
572 if (reg == AD7124_ADC_CONTROL) {
573 data->adc_control_status.value = *val;
574 data->adc_control_status.is_read = true;
575 }
576
577 return 0;
578 }
579
adc_ad7124_write_reg(const struct device * dev,uint32_t reg,enum ad7124_register_lengths len,uint32_t val)580 static int adc_ad7124_write_reg(const struct device *dev, uint32_t reg,
581 enum ad7124_register_lengths len, uint32_t val)
582 {
583 const struct adc_ad7124_config *config = dev->config;
584 struct adc_ad7124_data *data = dev->data;
585 const struct spi_dt_spec *spec = &config->bus;
586
587 int ret;
588 uint8_t buffer_tx[AD7124_MAX_RETURNED_DATA_SIZE] = {0};
589 uint8_t crc;
590
591 if (data->spi_ready) {
592 ret = adc_ad7124_wait_for_spi_ready(dev);
593 if (ret) {
594 return ret;
595 }
596 }
597
598 buffer_tx[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_WR | AD7124_COMM_REG_RA(reg);
599
600 switch (len) {
601 case 1:
602 buffer_tx[1] = val;
603 break;
604 case 2:
605 sys_put_be16(val, &buffer_tx[1]);
606 break;
607 case 3:
608 sys_put_be24(val, &buffer_tx[1]);
609 break;
610 default:
611 return -EINVAL;
612 }
613
614 if (data->crc_enable) {
615 crc = crc8(buffer_tx, len + 1, AD7124_CRC8_POLYNOMIAL_REPRESENTATION, 0, false);
616 buffer_tx[len + 1] = crc;
617 }
618
619 struct spi_buf tx_buf[] = {{
620 .buf = buffer_tx,
621 .len = ((data->crc_enable) ? len + 1 : len) + 1,
622 }};
623
624 const struct spi_buf_set tx = {.buffers = tx_buf, .count = ARRAY_SIZE(tx_buf)};
625
626 ret = spi_transceive_dt(spec, &tx, NULL);
627 if (ret) {
628 return ret;
629 }
630
631 return 0;
632 }
633
adc_ad7124_reg_write_msk(const struct device * dev,uint32_t reg,enum ad7124_register_lengths len,uint32_t data,uint32_t mask)634 static int adc_ad7124_reg_write_msk(const struct device *dev, uint32_t reg,
635 enum ad7124_register_lengths len, uint32_t data, uint32_t mask)
636 {
637 int ret;
638 uint32_t reg_data;
639
640 ret = adc_ad7124_read_reg(dev, reg, len, ®_data);
641 if (ret) {
642 return ret;
643 }
644
645 reg_data &= ~mask;
646 reg_data |= data;
647
648 ret = adc_ad7124_write_reg(dev, reg, len, reg_data);
649 if (ret) {
650 return ret;
651 }
652
653 return 0;
654 }
655
adc_ad7124_setup_cfg(const struct device * dev,const struct ad7124_channel_config * cfg)656 static int adc_ad7124_setup_cfg(const struct device *dev, const struct ad7124_channel_config *cfg)
657 {
658 const struct adc_ad7124_config *config = dev->config;
659 int ret;
660 int configuration_setup = 0;
661 int configuration_mask = 0;
662 int ref_internal = 0;
663
664 if (cfg->props.bipolar) {
665 configuration_setup |= AD7124_CFG_REG_BIPOLAR;
666 }
667
668 if (cfg->props.inbuf_enable) {
669 configuration_setup |= AD7124_CFG_REG_AIN_BUFP | AD7124_CFG_REG_AINN_BUFM;
670 }
671
672 if (cfg->props.refbuf_enable) {
673 configuration_setup |= AD7124_CFG_REG_REF_BUFP | AD7124_CFG_REG_REF_BUFM;
674 }
675
676 configuration_setup |= FIELD_PREP(AD7124_SETUP_CONF_REG_REF_SEL_MSK, cfg->props.refsel);
677 configuration_setup |= FIELD_PREP(AD7124_SETUP_CONF_PGA_MSK, cfg->props.pga_bits);
678 configuration_mask |= AD7124_SETUP_CONFIGURATION_MASK;
679
680 ret = adc_ad7124_reg_write_msk(dev, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_REG_LEN,
681 configuration_setup, configuration_mask);
682 if (ret) {
683 return ret;
684 }
685
686 if (config->ref_en) {
687 ref_internal = AD7124_ADC_CTRL_REG_REF_EN;
688 }
689
690 if (cfg->props.refsel == INTERNAL_REF) {
691 ret = adc_ad7124_reg_write_msk(dev, AD7124_ADC_CONTROL, AD7124_ADC_CONTROL_REG_LEN,
692 ref_internal, AD7124_ADC_CTRL_REG_REF_EN);
693 if (ret) {
694 return ret;
695 }
696 }
697
698 return 0;
699 }
700
adc_ad7124_filter_cfg(const struct device * dev,const struct ad7124_channel_config * cfg)701 static int adc_ad7124_filter_cfg(const struct device *dev, const struct ad7124_channel_config *cfg)
702 {
703 int filter_setup = 0;
704 int filter_mask = 0;
705 int ret;
706
707 filter_setup = FIELD_PREP(AD7124_FILTER_CONF_REG_FILTER_MSK, cfg->props.filter_type) |
708 FIELD_PREP(AD7124_FILTER_FS_MSK, cfg->props.odr_sel_bits);
709 filter_mask = AD7124_FILTER_CONF_REG_FILTER_MSK | AD7124_FILTER_FS_MSK;
710
711 /* Set filter type and odr*/
712 ret = adc_ad7124_reg_write_msk(dev, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_REG_LEN,
713 filter_setup, filter_mask);
714 if (ret) {
715 return ret;
716 }
717
718 return 0;
719 }
720
adc_ad7124_connect_analog_input(const struct device * dev,uint8_t chn_num,uint8_t ainp,uint8_t ainm)721 static int adc_ad7124_connect_analog_input(const struct device *dev, uint8_t chn_num, uint8_t ainp,
722 uint8_t ainm)
723 {
724 int ret;
725
726 ret = adc_ad7124_reg_write_msk(dev, AD7124_CHANNEL(chn_num), AD7124_CHANNEL_REG_LEN,
727 FIELD_PREP(AD7124_CHMAP_REG_AINPOS_MSK, ainp),
728 AD7124_CHMAP_REG_AINPOS_MSK);
729 if (ret) {
730 return ret;
731 }
732
733 ret = adc_ad7124_reg_write_msk(dev, AD7124_CHANNEL(chn_num), AD7124_CHANNEL_REG_LEN,
734 FIELD_PREP(AD7124_CHMAP_REG_AINNEG_MSK, ainm),
735 AD7124_CHMAP_REG_AINNEG_MSK);
736 if (ret) {
737 return ret;
738 }
739
740 return 0;
741 }
742
adc_ad7124_set_channel_status(const struct device * dev,uint8_t chn_num,bool channel_status)743 static int adc_ad7124_set_channel_status(const struct device *dev, uint8_t chn_num,
744 bool channel_status)
745 {
746 int ret;
747 uint16_t status;
748
749 if (channel_status) {
750 status = AD7124_CH_MAP_REG_CH_ENABLE;
751 } else {
752 status = 0x0U;
753 }
754
755 ret = adc_ad7124_reg_write_msk(dev, AD7124_CHANNEL(chn_num), AD7124_CHANNEL_REG_LEN, status,
756 AD7124_CH_MAP_REG_CH_ENABLE);
757 if (ret) {
758 return ret;
759 }
760
761 return 0;
762 }
763
adc_ad7124_channel_cfg(const struct device * dev,const struct adc_channel_cfg * cfg)764 static int adc_ad7124_channel_cfg(const struct device *dev, const struct adc_channel_cfg *cfg)
765 {
766 struct adc_ad7124_data *data = dev->data;
767 int ret;
768
769 ret = adc_ad7124_connect_analog_input(dev, cfg->channel_id, cfg->input_positive,
770 cfg->input_negative);
771 if (ret) {
772 return ret;
773 }
774
775 /* Assign setup */
776 ret = adc_ad7124_reg_write_msk(
777 dev, AD7124_CHANNEL(cfg->channel_id), AD7124_CHANNEL_REG_LEN,
778 FIELD_PREP(AD7124_CHMAP_REG_SETUP_SEL_MSK,
779 data->channel_setup_cfg[cfg->channel_id].cfg_slot),
780 AD7124_CHMAP_REG_SETUP_SEL_MSK);
781 if (ret) {
782 return ret;
783 }
784
785 ret = adc_ad7124_set_channel_status(dev, cfg->channel_id, true);
786 if (ret) {
787 return ret;
788 }
789
790 return 0;
791 }
792
adc_ad7124_channel_setup(const struct device * dev,const struct adc_channel_cfg * cfg)793 static int adc_ad7124_channel_setup(const struct device *dev, const struct adc_channel_cfg *cfg)
794 {
795 struct adc_ad7124_data *data = dev->data;
796 struct ad7124_channel_config new_cfg;
797 int new_slot;
798 int ret;
799 int similar_channel_index;
800
801 data->channel_setup_cfg[cfg->channel_id].live_cfg = false;
802
803 ret = adc_ad7124_create_new_cfg(dev, cfg, &new_cfg);
804 if (ret) {
805 return ret;
806 }
807
808 /* AD7124 supports only 8 different configurations for 16 channels*/
809 new_slot = adc_ad7124_find_new_slot(dev);
810
811 if (new_slot == -1) {
812 similar_channel_index =
813 adc_ad7124_find_similar_configuration(dev, &new_cfg, cfg->channel_id);
814 if (similar_channel_index == -1) {
815 return -EINVAL;
816 }
817 new_cfg.cfg_slot = data->channel_setup_cfg[similar_channel_index].cfg_slot;
818 } else {
819 new_cfg.cfg_slot = new_slot;
820 WRITE_BIT(data->setup_cfg_slots, new_slot, true);
821 }
822
823 new_cfg.live_cfg = true;
824
825 memcpy(&data->channel_setup_cfg[cfg->channel_id], &new_cfg,
826 sizeof(struct ad7124_channel_config));
827
828 /* Setup the channel configuration */
829 ret = adc_ad7124_setup_cfg(dev, &data->channel_setup_cfg[cfg->channel_id]);
830 if (ret) {
831 LOG_ERR("Error setting up configuration");
832 return ret;
833 }
834
835 /* Setup the filter configuration */
836 ret = adc_ad7124_filter_cfg(dev, &data->channel_setup_cfg[cfg->channel_id]);
837 if (ret) {
838 LOG_ERR("Error setting up filter");
839 return ret;
840 }
841
842 /* Setup the channel */
843 ret = adc_ad7124_channel_cfg(dev, cfg);
844 if (ret) {
845 LOG_ERR("Error setting up channel");
846 return ret;
847 }
848
849 WRITE_BIT(data->channels, cfg->channel_id, true);
850
851 return 0;
852 }
853
adc_ad7124_wait_to_power_up(const struct device * dev)854 int adc_ad7124_wait_to_power_up(const struct device *dev)
855 {
856 int ret = 0;
857 uint32_t read_val = 0;
858 bool powered_on = false;
859 uint16_t spi_ready_try_count = AD7124_SPI_RDY_POLL_CNT;
860
861 while (!powered_on && --spi_ready_try_count) {
862
863 ret = adc_ad7124_read_reg(dev, AD7124_STATUS, AD7124_STATUS_REG_LEN, &read_val);
864 if (ret) {
865 return ret;
866 }
867
868 powered_on = (read_val & AD7124_STATUS_REG_POR_FLAG) == 0;
869 }
870
871 if (!spi_ready_try_count) {
872 return -ETIMEDOUT;
873 }
874
875 return 0;
876 }
877
adc_ad7124_reset(const struct device * dev)878 int adc_ad7124_reset(const struct device *dev)
879 {
880 const struct adc_ad7124_config *config = dev->config;
881 const struct spi_dt_spec *spec = &config->bus;
882
883 int ret;
884 uint8_t buffer_tx[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
885
886 struct spi_buf tx_buf[] = {{
887 .buf = buffer_tx,
888 .len = ARRAY_SIZE(buffer_tx),
889 }};
890
891 const struct spi_buf_set tx = {.buffers = tx_buf, .count = ARRAY_SIZE(tx_buf)};
892
893 ret = spi_transceive_dt(spec, &tx, NULL);
894 if (ret) {
895 return ret;
896 }
897
898 ret = adc_ad7124_wait_to_power_up(dev);
899 if (ret) {
900 return ret;
901 }
902
903 return ret;
904 }
905
adc_ad7124_update_crc(const struct device * dev)906 static int adc_ad7124_update_crc(const struct device *dev)
907 {
908 struct adc_ad7124_data *data = dev->data;
909
910 int ret = 0;
911 uint32_t reg_temp = 0;
912
913 ret = adc_ad7124_read_reg(dev, AD7124_ERROR_EN, AD7124_ERROR_EN_REG_LEN, ®_temp);
914 if (ret) {
915 return ret;
916 }
917
918 if (reg_temp & AD7124_ERREN_REG_SPI_CRC_ERR_EN) {
919 data->crc_enable = true;
920 } else {
921 data->crc_enable = false;
922 }
923
924 return 0;
925 }
926
adc_ad7124_update_spi_check_ready(const struct device * dev)927 static int adc_ad7124_update_spi_check_ready(const struct device *dev)
928 {
929 struct adc_ad7124_data *data = dev->data;
930
931 int ret = 0;
932 uint32_t reg_temp = 0;
933
934 ret = adc_ad7124_read_reg(dev, AD7124_ERROR_EN, AD7124_ERROR_EN_REG_LEN, ®_temp);
935 if (ret) {
936 return ret;
937 }
938
939 if (reg_temp & AD7124_ERREN_REG_SPI_IGNORE_ERR_EN) {
940 data->spi_ready = true;
941 } else {
942 data->spi_ready = false;
943 }
944
945 return 0;
946 }
947
adc_ad7124_check_chip_id(const struct device * dev)948 static int adc_ad7124_check_chip_id(const struct device *dev)
949 {
950 const struct adc_ad7124_config *config = dev->config;
951 uint32_t reg_temp = 0;
952 int ret;
953
954 ret = adc_ad7124_read_reg(dev, AD7124_ID, AD7124_ID_REG_LEN, ®_temp);
955 if (ret) {
956 return ret;
957 }
958
959 if (config->active_device == ID_AD7124_4) {
960 switch (reg_temp) {
961 case AD7124_4_STD_ID:
962 case AD7124_4_B_GRADE_ID:
963 case AD7124_4_NEW_ID:
964 break;
965
966 default:
967 return -ENODEV;
968 }
969 } else if (config->active_device == ID_AD7124_8) {
970 switch (reg_temp) {
971 case AD7124_8_STD_ID:
972 case AD7124_8_B_W_GRADE_ID:
973 case AD7124_8_NEW_ID:
974 break;
975
976 default:
977 return -ENODEV;
978 }
979 } else {
980 return -ENODEV;
981 }
982
983 return 0;
984 }
985
adc_ad7124_set_adc_mode(const struct device * dev,enum ad7124_mode adc_mode)986 static int adc_ad7124_set_adc_mode(const struct device *dev, enum ad7124_mode adc_mode)
987 {
988 int ret;
989
990 ret = adc_ad7124_reg_write_msk(dev, AD7124_ADC_CONTROL, AD7124_ADC_CONTROL_REG_LEN,
991 FIELD_PREP(AD7124_ADC_CTRL_REG_MODE_MSK, adc_mode),
992 AD7124_ADC_CTRL_REG_MODE_MSK);
993 if (ret) {
994 return ret;
995 }
996
997 return 0;
998 }
999
adc_ad7124_set_power_mode(const struct device * dev,enum ad7124_power_mode power_mode)1000 static int adc_ad7124_set_power_mode(const struct device *dev, enum ad7124_power_mode power_mode)
1001 {
1002 int ret;
1003
1004 ret = adc_ad7124_reg_write_msk(dev, AD7124_ADC_CONTROL, AD7124_ADC_CONTROL_REG_LEN,
1005 FIELD_PREP(AD7124_POWER_MODE_MSK, power_mode),
1006 AD7124_POWER_MODE_MSK);
1007 if (ret) {
1008 return ret;
1009 }
1010
1011 return 0;
1012 }
1013
adc_ad7124_setup(const struct device * dev)1014 static int adc_ad7124_setup(const struct device *dev)
1015 {
1016 const struct adc_ad7124_config *config = dev->config;
1017 int ret;
1018
1019 /* Reset the device interface */
1020 ret = adc_ad7124_reset(dev);
1021 if (ret) {
1022 return ret;
1023 }
1024
1025 /* Get CRC State */
1026 ret = adc_ad7124_update_crc(dev);
1027 if (ret) {
1028 return ret;
1029 }
1030
1031 ret = adc_ad7124_update_spi_check_ready(dev);
1032 if (ret) {
1033 return ret;
1034 }
1035
1036 /* Check the device ID */
1037 ret = adc_ad7124_check_chip_id(dev);
1038 if (ret) {
1039 return ret;
1040 }
1041
1042 /* Disable channel 0 */
1043 ret = adc_ad7124_set_channel_status(dev, 0, false);
1044 if (ret) {
1045 return ret;
1046 }
1047
1048 ret = adc_ad7124_set_adc_mode(dev, config->adc_mode);
1049 if (ret) {
1050 return ret;
1051 }
1052
1053 ret = adc_ad7124_set_power_mode(dev, config->power_mode);
1054 if (ret) {
1055 return ret;
1056 }
1057
1058 return 0;
1059 }
1060
adc_ad7124_wait_for_conv_ready(const struct device * dev)1061 static int adc_ad7124_wait_for_conv_ready(const struct device *dev)
1062 {
1063 int ret = 0;
1064 uint32_t read_val = 0;
1065 bool ready = false;
1066 uint16_t spi_ready_try_count = AD7124_SPI_RDY_POLL_CNT;
1067
1068 while (!ready && --spi_ready_try_count) {
1069
1070 ret = adc_ad7124_read_reg(dev, AD7124_STATUS, AD7124_STATUS_REG_LEN, &read_val);
1071 if (ret) {
1072 return ret;
1073 }
1074
1075 ready = (read_val & AD7124_STATUS_REG_RDY) == 0;
1076 }
1077
1078 if (!spi_ready_try_count) {
1079 return -ETIMEDOUT;
1080 }
1081
1082 return 0;
1083 }
1084
get_next_ch_idx(uint16_t ch_mask,uint16_t last_idx,uint16_t * new_idx)1085 static bool get_next_ch_idx(uint16_t ch_mask, uint16_t last_idx, uint16_t *new_idx)
1086 {
1087 last_idx++;
1088 if (last_idx >= AD7124_MAX_CHANNELS) {
1089 return 0;
1090 }
1091 ch_mask >>= last_idx;
1092 if (!ch_mask) {
1093 *new_idx = -1;
1094 return 0;
1095 }
1096 while (!(ch_mask & 1)) {
1097 last_idx++;
1098 ch_mask >>= 1;
1099 }
1100 *new_idx = last_idx;
1101
1102 return 1;
1103 }
1104
adc_ad7124_get_read_chan_id(const struct device * dev,uint16_t * chan_id)1105 static int adc_ad7124_get_read_chan_id(const struct device *dev, uint16_t *chan_id)
1106 {
1107 int ret;
1108 uint32_t reg_temp;
1109
1110 ret = adc_ad7124_read_reg(dev, AD7124_STATUS, AD7124_STATUS_REG_LEN, ®_temp);
1111 if (ret) {
1112 return ret;
1113 }
1114
1115 *chan_id = reg_temp & AD7124_STATUS_REG_CH_ACTIVE(0xF);
1116
1117 return 0;
1118 }
1119
adc_ad7124_perform_read(const struct device * dev)1120 static int adc_ad7124_perform_read(const struct device *dev)
1121 {
1122 int ret;
1123 struct adc_ad7124_data *data = dev->data;
1124 uint16_t ch_idx = -1;
1125 uint16_t prev_ch_idx = -1;
1126 uint16_t adc_ch_id = 0;
1127 bool status;
1128
1129 k_sem_take(&data->acquire_signal, K_FOREVER);
1130
1131 do {
1132 prev_ch_idx = ch_idx;
1133
1134 status = get_next_ch_idx(data->ctx.sequence.channels, ch_idx, &ch_idx);
1135 if (!status) {
1136 break;
1137 }
1138
1139 ret = adc_ad7124_wait_for_conv_ready(dev);
1140 if (ret) {
1141 LOG_ERR("waiting for conversion ready failed");
1142 adc_context_complete(&data->ctx, ret);
1143 return ret;
1144 }
1145
1146 ret = adc_ad7124_read_reg(dev, AD7124_DATA, AD7124_DATA_REG_LEN, data->buffer);
1147 if (ret) {
1148 LOG_ERR("reading sample failed");
1149 adc_context_complete(&data->ctx, ret);
1150 return ret;
1151 }
1152
1153 ret = adc_ad7124_get_read_chan_id(dev, &adc_ch_id);
1154 if (ret) {
1155 LOG_ERR("reading channel id failed");
1156 adc_context_complete(&data->ctx, ret);
1157 return ret;
1158 }
1159
1160 if (ch_idx == adc_ch_id) {
1161 data->buffer++;
1162 } else {
1163 ch_idx = prev_ch_idx;
1164 }
1165
1166 } while (true);
1167
1168 adc_context_on_sampling_done(&data->ctx, dev);
1169
1170 return ret;
1171 }
1172
adc_ad7124_validate_sequence(const struct device * dev,const struct adc_sequence * sequence)1173 static int adc_ad7124_validate_sequence(const struct device *dev,
1174 const struct adc_sequence *sequence)
1175 {
1176 const struct adc_ad7124_config *config = dev->config;
1177 struct adc_ad7124_data *data = dev->data;
1178 const size_t channel_maximum = 8 * sizeof(sequence->channels);
1179 uint32_t num_requested_channels;
1180 size_t necessary;
1181
1182 if (sequence->resolution != config->resolution) {
1183 LOG_ERR("invalid resolution");
1184 return -EINVAL;
1185 }
1186
1187 if (!sequence->channels) {
1188 LOG_ERR("no channel selected");
1189 return -EINVAL;
1190 }
1191
1192 if (sequence->oversampling) {
1193 LOG_ERR("oversampling is not supported");
1194 return -EINVAL;
1195 }
1196
1197 num_requested_channels = POPCOUNT(sequence->channels);
1198 necessary = num_requested_channels * sizeof(int32_t);
1199
1200 if (sequence->options) {
1201 necessary *= (1 + sequence->options->extra_samplings);
1202 }
1203
1204 if (sequence->buffer_size < necessary) {
1205 LOG_ERR("buffer size %u is too small, need %u", sequence->buffer_size, necessary);
1206 return -ENOMEM;
1207 }
1208
1209 for (size_t i = 0; i < channel_maximum; ++i) {
1210 if ((BIT(i) & sequence->channels) == 0) {
1211 continue;
1212 }
1213
1214 if ((BIT(i) & sequence->channels) && !(BIT(i) & data->channels)) {
1215 LOG_ERR("Channel-%d not enabled", i);
1216 return -EINVAL;
1217 }
1218
1219 if (i >= AD7124_MAX_CHANNELS) {
1220 LOG_ERR("invalid channel selection");
1221 return -EINVAL;
1222 }
1223 }
1224
1225 return 0;
1226 }
1227
adc_ad7124_start_read(const struct device * dev,const struct adc_sequence * sequence,bool wait)1228 static int adc_ad7124_start_read(const struct device *dev, const struct adc_sequence *sequence,
1229 bool wait)
1230 {
1231 int result;
1232 struct adc_ad7124_data *data = dev->data;
1233
1234 result = adc_ad7124_validate_sequence(dev, sequence);
1235 if (result != 0) {
1236 LOG_ERR("sequence validation failed");
1237 return result;
1238 }
1239
1240 data->buffer = sequence->buffer;
1241
1242 adc_context_start_read(&data->ctx, sequence);
1243
1244 if (wait) {
1245 result = adc_context_wait_for_completion(&data->ctx);
1246 }
1247
1248 return result;
1249 }
1250
1251 #if CONFIG_ADC_ASYNC
adc_ad7124_read_async(const struct device * dev,const struct adc_sequence * sequence,struct k_poll_signal * async)1252 static int adc_ad7124_read_async(const struct device *dev, const struct adc_sequence *sequence,
1253 struct k_poll_signal *async)
1254 {
1255 int status;
1256 struct adc_ad7124_data *data = dev->data;
1257
1258 adc_context_lock(&data->ctx, true, async);
1259 status = adc_ad7124_start_read(dev, sequence, true);
1260 adc_context_release(&data->ctx, status);
1261
1262 return status;
1263 }
1264
adc_ad7124_read(const struct device * dev,const struct adc_sequence * sequence)1265 static int adc_ad7124_read(const struct device *dev, const struct adc_sequence *sequence)
1266 {
1267 int status;
1268 struct adc_ad7124_data *data = dev->data;
1269
1270 adc_context_lock(&data->ctx, false, NULL);
1271 status = adc_ad7124_start_read(dev, sequence, true);
1272 adc_context_release(&data->ctx, status);
1273
1274 return status;
1275 }
1276
1277 #else
adc_ad7124_read(const struct device * dev,const struct adc_sequence * sequence)1278 static int adc_ad7124_read(const struct device *dev, const struct adc_sequence *sequence)
1279 {
1280 int status;
1281 struct adc_ad7124_data *data = dev->data;
1282
1283 adc_context_lock(&data->ctx, false, NULL);
1284
1285 status = adc_ad7124_start_read(dev, sequence, false);
1286
1287 while (status == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
1288 status = adc_ad7124_perform_read(dev);
1289 }
1290
1291 adc_context_release(&data->ctx, status);
1292
1293 return status;
1294 }
1295 #endif
1296
1297 #if CONFIG_ADC_ASYNC
adc_ad7124_acquisition_thread(void * p1,void * p2,void * p3)1298 static void adc_ad7124_acquisition_thread(void *p1, void *p2, void *p3)
1299 {
1300 ARG_UNUSED(p2);
1301 ARG_UNUSED(p3);
1302
1303 const struct device *dev = p1;
1304
1305 while (true) {
1306 adc_ad7124_perform_read(dev);
1307 }
1308 }
1309 #endif /* CONFIG_ADC_ASYNC */
1310
adc_ad7124_init(const struct device * dev)1311 static int adc_ad7124_init(const struct device *dev)
1312 {
1313 const struct adc_ad7124_config *config = dev->config;
1314 struct adc_ad7124_data *data = dev->data;
1315 int ret;
1316
1317 data->dev = dev;
1318
1319 k_sem_init(&data->acquire_signal, 0, 1);
1320
1321 if (!spi_is_ready_dt(&config->bus)) {
1322 LOG_ERR("spi bus %s not ready", config->bus.bus->name);
1323 return -ENODEV;
1324 }
1325
1326 ret = adc_ad7124_setup(dev);
1327 if (ret) {
1328 return ret;
1329 }
1330
1331 #if CONFIG_ADC_ASYNC
1332 k_tid_t tid = k_thread_create(
1333 &data->thread, data->stack, CONFIG_ADI_AD7124_ADC_ACQUISITION_THREAD_STACK_SIZE,
1334 adc_ad7124_acquisition_thread, (void *)dev, NULL, NULL,
1335 CONFIG_ADI_AD7124_ADC_ACQUISITION_THREAD_INIT_PRIO, 0, K_NO_WAIT);
1336 k_thread_name_set(tid, "adc_ad7124");
1337 #endif /* CONFIG_ADC_ASYNC */
1338
1339 adc_context_unlock_unconditionally(&data->ctx);
1340
1341 return 0;
1342 }
1343
1344 static DEVICE_API(adc, adc_ad7124_api) = {
1345 .channel_setup = adc_ad7124_channel_setup,
1346 .read = adc_ad7124_read,
1347 #ifdef CONFIG_ADC_ASYNC
1348 .read_async = adc_ad7124_read_async,
1349 #endif
1350 .ref_internal = AD7124_ADC_VREF_MV,
1351 };
1352
1353 #define ADC_AD7124_INST_DEFINE(inst) \
1354 static const struct adc_ad7124_config adc_ad7124_config##inst = { \
1355 .bus = SPI_DT_SPEC_INST_GET( \
1356 inst, \
1357 SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8), 0), \
1358 .resolution = AD7124_RESOLUTION, \
1359 .filter_type_mask = DT_INST_PROP(inst, filter_type_mask), \
1360 .bipolar_mask = DT_INST_PROP(inst, bipolar_mask), \
1361 .inbuf_enable_mask = DT_INST_PROP(inst, inbuf_enable_mask), \
1362 .refbuf_enable_mask = DT_INST_PROP(inst, refbuf_enable_mask), \
1363 .adc_mode = DT_INST_PROP(inst, adc_mode), \
1364 .power_mode = DT_INST_PROP(inst, power_mode), \
1365 .active_device = DT_INST_PROP(inst, active_device), \
1366 .ref_en = DT_INST_PROP(inst, reference_enable), \
1367 }; \
1368 static struct adc_ad7124_data adc_ad7124_data##inst = { \
1369 ADC_CONTEXT_INIT_LOCK(adc_ad7124_data##inst, ctx), \
1370 ADC_CONTEXT_INIT_TIMER(adc_ad7124_data##inst, ctx), \
1371 ADC_CONTEXT_INIT_SYNC(adc_ad7124_data##inst, ctx), \
1372 }; \
1373 DEVICE_DT_INST_DEFINE(inst, adc_ad7124_init, NULL, &adc_ad7124_data##inst, \
1374 &adc_ad7124_config##inst, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, \
1375 &adc_ad7124_api);
1376
1377 DT_INST_FOREACH_STATUS_OKAY(ADC_AD7124_INST_DEFINE)
1378
