1 /* 2 * Copyright 2023 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 */ 8 #ifndef FLASH_CONFIG_H_ 9 #define FLASH_CONFIG_H_ 10 #include <stdint.h> 11 #include "fsl_common.h" 12 13 /*! @name Driver version */ 14 /*@{*/ 15 /*! @brief FLASH_CONFIG driver version 2.0.0. */ 16 #define FSL_FLASH_CONFIG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) 17 /*@}*/ 18 19 /******************************************************************************* 20 * Definition 21 ******************************************************************************/ 22 23 /* XSPI memory config block related defintions */ 24 #define FC_XSPI_CFG_BLK_TAG (0x42464346UL) /* ascii "FCFB" Big Endian */ 25 #define FC_XSPI_CFG_BLK_VERSION (0x56010400UL) /* V1.4.0 */ 26 27 /* !@brief XSPI clock configuration - When clock source is PLL */ 28 enum 29 { 30 Fc_XspiSerialClk_30MHz = 1, 31 Fc_XspiSerialClk_50MHz = 2, 32 Fc_XspiSerialClk_60MHz = 3, 33 Fc_XspiSerialClk_80MHz = 4, 34 Fc_XspiSerialClk_100MHz = 5, 35 Fc_XspiSerialClk_120MHz = 6, 36 Fc_XspiSerialClk_133MHz = 7, 37 Fc_XspiSerialClk_166MHz = 8, 38 Fc_XspiSerialClk_200MHz = 9, 39 }; 40 41 /* !@brief LUT instructions supported by XSPI */ 42 #define FC_CMD_STOP 0x00U /*!< Stop execution, deassert CS. */ 43 #define FC_CMD_SDR 0x01U /*!< Transmit Command code to Flash, using SDR mode. */ 44 #define FC_CMD_RADDR_SDR 0x02U /*!< Transmit Row Address to Flash, using SDR mode. */ 45 #define FC_CMD_DUMMY_SDR 0x03U /*!< Leave data lines undriven by xSPI controller, using SDR mode. */ 46 #define FC_CMD_MODE_SDR 0x04U /*!< Transmit 8-bit Mode bits to Flash, using SDR mode. */ 47 #define FC_CMD_MODE2_SDR 0x05U /*!< Transmit 2-bit Mode bits to Flash, using SDR mode. */ 48 #define FC_CMD_MODE4_SDR 0x06U /*!< Transmit 4-bit Mode bits to Flash, using SDR mode. */ 49 #define FC_CMD_READ_SDR 0x07U /*!< Receive Read Data from Flash, using SDR mode. */ 50 #define FC_CMD_WRITE_SDR 0x08U /*!< Transmit Programming Data to Flash, using SDR mode. */ 51 #define FC_CMD_JMP_ON_CS 0x09U /*!< Stop execution, deassert CS and save operand[7:0] as the 52 instruction start pointer for next sequence*/ 53 #define FC_CMD_RADDR_DDR 0x0AU /*!< Transmit Row Address to Flash, using DDR mode. */ 54 #define FC_CMD_MODE_DDR 0x0BU /*!< Transmit 8-bit Mode bits to Flash, using DDR mode. */ 55 #define FC_CMD_MODE2_DDR 0x0CU /*!< Transmit 2-bit Mode bits to Flash, using DDR mode. */ 56 #define FC_CMD_MODE4_DDR 0x0DU /*!< Transmit 4-bit Mode bits to Flash, using DDR mode. */ 57 #define FC_CMD_READ_DDR 0x0EU /*!< Receive Read Data from Flash, using DDR mode. */ 58 #define FC_CMD_WRITE_DDR 0x0FU /*!< Transmit Programming Data to Flash, using DDR mode. */ 59 #define FC_CMD_LEARN_DDR 0x10U /*!< Receive Read Data or Preamble bit from Flash, DDR mode. */ 60 #define FC_CMD_DDR 0x11U /*!< Transmit Command code to Flash, using DDR mode. */ 61 #define FC_CMD_CADDR_SDR 0x12U /*!< Transmit Column Address to Flash, using SDR mode. */ 62 #define FC_CMD_CADDR_DDR 0x13U /*!< Transmit Column Address to Flash, using DDR mode. */ 63 #define FC_CMD_JUMP_TO_SEQ 0x14U 64 65 #define FC_XSPI_1PAD 0 66 #define FC_XSPI_2PAD 1 67 #define FC_XSPI_4PAD 2 68 #define FC_XSPI_8PAD 3 69 70 #define FC_XSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 71 (XSPI_LUT_INSTR0(cmd0) | XSPI_LUT_PAD0(pad0) | XSPI_LUT_OPRND0(op0) | XSPI_LUT_INSTR1(cmd1) | \ 72 XSPI_LUT_PAD1(pad1) | XSPI_LUT_OPRND1(op1)) 73 74 /* !@brief XSPI Read Sample Clock Source definition */ 75 typedef enum _FlashReadSampleClkSource 76 { 77 kXSPIReadSampleClk_LoopbackInternally = 0, 78 kXSPIReadSampleClk_LoopbackFromDqsPad = 2, 79 kXSPIReadSampleClk_ExternalInputFromDqsPad = 3, 80 } fc_xspi_read_sample_clk_t; 81 82 /* !@brief Misc feature bit definitions */ 83 enum 84 { 85 Fc_XspiMiscOffset_DiffClkEnable = 0, /* !< Bit for Differential clock enable */ 86 Fc_XspiMiscOffset_WordAddressableEnable = 3, /* !< Bit for Word Addressable enable */ 87 Fc_XspiMiscOffset_SafeConfigFreqEnable = 4, /* !< Bit for Safe Configuration Frequency enable */ 88 Fc_XspiMiscOffset_DdrModeEnable = 6, /* !< Bit for DDR clock confiuration indication. */ 89 }; 90 91 typedef struct 92 { 93 uint8_t time_100ps; /* !< Data valid time, in terms of 100ps */ 94 uint8_t delay_cells; /* !< Data valid time, in terms of delay cells */ 95 } fc_xspi_dll_time_t; 96 97 /* !@brief XSPI LUT Sequence structure */ 98 typedef struct _lut_sequence 99 { 100 uint8_t seqNum; /* !< Sequence Number, valid number: 1-16 */ 101 uint8_t seqId; /* !< Sequence Index, valid number: 0-15 */ 102 uint16_t reserved; 103 } fc_xspi_lut_seq_t; 104 105 /* !@brief XSPI Memory Configuration Block */ 106 typedef struct _XSPIConfig 107 { 108 uint32_t tag; /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */ 109 uint32_t version; /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ 110 uint32_t reserved0; /* !< [0x008-0x00b] Reserved for future use */ 111 uint8_t readSampleClkSrc; /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 112 0: internal sampling 113 2: DQS pad loopback 114 3: External DQS signal */ 115 uint8_t csHoldTime; /* !< [0x00d-0x00d] CS hold time, default value: 3 */ 116 uint8_t csSetupTime; /* !< [0x00e-0x00e] CS setup time, default value: 3 */ 117 uint8_t columnAddressWidth; /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, others to 0. */ 118 uint8_t deviceModeCfgEnable; /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ 119 uint8_t deviceModeType; /* !< [0x011-0x011] Specify the configuration command type. 120 0: No mode change 121 1: Quad enable (switch from SPI to Quad mode) 122 2: Spi2Xpi (switch from SPI to DPI, QPI, or OPI mode) 123 3: Xpi2Spi (switch from DPI, QPI, or OPI to SPI mode) */ 124 uint16_t waitTimeCfgCommands; /* !< [0x012-0x013] Wait time for Device mode configuration command, unit: 100us */ 125 fc_xspi_lut_seq_t deviceModeSeq; /* !< [0x014-0x017] Device mode sequence info 126 [ 7:0] - Number of required sequences 127 [15:8] - Sequence index */ 128 uint32_t deviceModeArg; /* !< [0x018-0x01b] Argument/Parameter for device configuration */ 129 uint8_t configCmdEnable; /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ 130 uint8_t configModeType[3]; /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ 131 fc_xspi_lut_seq_t configCmdSeqs[3]; /* !< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ 132 uint32_t reserved1; /* !< [0x02c-0x02f] Reserved for future use */ 133 uint32_t configCmdArgs[3]; /* !< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ 134 uint32_t reserved2; /* !< [0x03c-0x03f] Reserved for future use */ 135 uint32_t controllerMiscOption; /* !< [0x040-0x043] Controller Misc Options. 136 Bit 0: Differential clock enable: 1 for HyperFlash NOR flash memory 1V8 device and 0 for other devices 137 Bit 3: WordAddressableEnable: 1 for HyperFlash NOR flash memory and 0 for other devices 138 Bit 4: SafeConfigFreqEnable: set to 1 if expecting to configure the chip with a safe frequency 139 Bit 6: DDR mode enable: set to 1 if DDR read is expected 140 Other bits Reserved; set to 0 */ 141 uint8_t deviceType; /* !< [0x044-0x044] Device Type: 1 for Serial NOR flash memory */ 142 uint8_t sflashPadType; /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ 143 uint8_t serialClkFreq; /* !< [0x046-0x046] Serial Flash Frequencey 144 1: 30 MHz 145 2: 50 MHz 146 3: 60 MHz 147 4: 80 MHz 148 5: 100 MHz 149 6: 120 MHz 150 7: 133 MHz 151 8: 166 MHz 152 9: 200 MHz */ 153 uint8_t lutCustomSeqEnable; /* !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot 154 be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ 155 uint32_t reserved3[2]; /* !< [0x048-0x04f] Reserved for future use */ 156 uint32_t sflashA1Size; /* !< [0x050-0x053] Size of Flash connected to A1 */ 157 uint32_t sflashA2Size; /* !< [0x054-0x057] Size of Flash connected to A2 */ 158 uint32_t sflashB1Size; /* !< [0x058-0x05b] Size of Flash connected to B1 */ 159 uint32_t sflashB2Size; /* !< [0x05c-0x05f] Size of Flash connected to B2 */ 160 uint32_t csPadSettingOverride; /* !< [0x060-0x063] CS pad setting override value */ 161 uint32_t sclkPadSettingOverride; /* !< [0x064-0x067] SCK pad setting override value */ 162 uint32_t dataPadSettingOverride; /* !< [0x068-0x06b] data pad setting override value */ 163 uint32_t dqsPadSettingOverride; /* !< [0x06c-0x06f] DQS pad setting override value */ 164 uint32_t timeoutInMs; /* !< [0x070-0x073] Timeout threshold for read status command */ 165 uint32_t commandInterval; /* !< [0x074-0x077] CS deselect interval between two commands */ 166 fc_xspi_dll_time_t dataValidTime[2]; /* !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ 167 uint16_t busyOffset; /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */ 168 uint16_t busyBitPolarity; /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - 169 busy flag is 0 when flash device is busy */ 170 uint32_t lookupTable[80]; /* !< [0x080-0x1bf] Lookup table holds Flash command sequences */ 171 fc_xspi_lut_seq_t lutCustomSeq[12]; /* !< [0x1c0-0x1ef] Customizable LUT Sequences */ 172 uint32_t dllCraSdrVal; /* !< [0x1f0-0x1f3] Customizable DLLCRA for SDR setting */ 173 uint32_t smprSdrVal; /* !< [0x1f4-0x1f7] Customizable SMPR SDR setting */ 174 uint32_t dllCraDdrVal; /* !< [0x1f8-0x1fb] Customizable DLLCRA for DDR setting */ 175 uint32_t smprDdrVal; /* !< [0x1fc-0x1ff] Customizable SMPR DDR setting */ 176 } fc_xspi_mem_config_t; 177 /* 178 * Serial NOR configuration block 179 */ 180 typedef struct _fc_xspi_nor_config 181 { 182 fc_xspi_mem_config_t memConfig; /* !< Common memory configuration info via XSPI */ 183 uint32_t pageSize; /* !< Page size of Serial NOR */ 184 uint32_t sectorSize; /* !< Sector size of Serial NOR */ 185 uint8_t ipcmdSerialClkFreq; /* !< Clock frequency for IP command */ 186 uint8_t isUniformBlockSize; /* !< Sector/Block size is the same */ 187 uint8_t isDataOrderSwapped; /* !< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ 188 uint8_t reserved0[1]; /* !< Reserved for future use */ 189 uint8_t serialNorType; /* !< Serial NOR Flash type: 0/1/2/3 */ 190 uint8_t needExitNoCmdMode; /* !< Need to exit NoCmd mode before other IP command */ 191 uint8_t halfClkForNonReadCmd; /* !< Half the Serial Clock for non-read command: true/false */ 192 uint8_t needRestoreNoCmdMode; /* !< Need to Restore NoCmd mode after IP commmand execution */ 193 uint32_t blockSize; /* !< Block size */ 194 uint32_t flashStateCtx; /* !< Flash State Context */ 195 uint32_t reserved2[58]; /* !< Reserved for future use */ 196 } fc_xspi_nor_config_t; 197 198 /* 199 * Serial PSRAM configuration block 200 */ 201 typedef struct _fc_xspi_psram_config 202 { 203 uint32_t xmcdHeader; /* !< XMCD header */ 204 uint32_t xmcdOpt0; /* !< Simplified XSPI RAM Configuration Option 0 */ 205 uint32_t xmcdOpt1; /* !< Simplified XSPI RAM Configuration Option 1 */ 206 uint32_t reserved2[189]; /* !< Reserved for future use */ 207 } fc_xspi_psram_config_t; 208 209 typedef struct { 210 fc_xspi_nor_config_t xspi_fcb_block; /* !< Configure structure for boot device connected to XSPI0/XSPI1 interface. */ 211 fc_xspi_psram_config_t psram_config_block; /* !< Configure structure for PSRAM device connected to XSPI0/XSPI1 interface. */ 212 uint8_t xspi2_fcb_block[768]; /* !< Configure structure for PSRAM device connected to XSPI2 interface. Only for 213 users' usage, Boot ROM doesn't use this part */ 214 uint8_t reserved[1792]; /* !< Reserved for future usage */ 215 } fc_static_platform_config_t; 216 #endif 217
