1/*
2 * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <xtensa/coreasm.h>
8#include <xtensa/corebits.h>
9#include <xtensa/config/system.h>
10#include <xtensa/hal.h>
11
12/* esp_test_ipc_isr_asm(void *arg)
13 *
14 * It should be called by the CALLX0 command from the handler of High-priority interrupt.
15 * Only these registers [a2, a3, a4] can be used here.
16 */
17    .section    .iram1, "ax"
18    .align      4
19    .global     esp_test_ipc_isr_asm
20    .type       esp_test_ipc_isr_asm, @function
21// Args:
22// a2 - void* arg
23esp_test_ipc_isr_asm:
24    movi    a3, 0xa5a5
25    s32i    a3, a2, 0
26    ret
27
28
29/* esp_test_ipc_isr_get_other_core_id(void *arg)
30 *
31 * this function puts the core_id of the other CPU in the arg.
32 * use only a2, a3 and a4 regs here.
33*/
34    .section    .iram1, "ax"
35    .align      4
36    .global     esp_test_ipc_isr_get_other_core_id
37    .type       esp_test_ipc_isr_get_other_core_id, @function
38    // Args:
39    // a2 - void* arg
40    esp_test_ipc_isr_get_other_core_id:
41    rsr.prid a3
42    extui   a3, a3, 13, 1
43    s32i    a3, a2, 0
44    ret
45
46
47/* esp_test_ipc_isr_get_cycle_count_other_cpu(void *arg)
48 *
49 * this function puts CCOUNT of the other CPU in the arg.
50 * use only a2, a3 and a4 regs here.
51*/
52    .section    .iram1, "ax"
53    .align      4
54    .global     esp_test_ipc_isr_get_cycle_count_other_cpu
55    .type       esp_test_ipc_isr_get_cycle_count_other_cpu, @function
56    // Args:
57    // a2 - void* arg
58    esp_test_ipc_isr_get_cycle_count_other_cpu:
59    rsr.ccount a3
60    s32i    a3, a2, 0
61    ret
62