1 // Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stddef.h>
16 #include <string.h>
17 #include <sys/lock.h>
18 #include <sys/param.h>
19
20 #include "esp_attr.h"
21 #include "esp_sleep.h"
22 #include "esp_private/esp_timer_private.h"
23 #include "esp_private/system_internal.h"
24 #include "esp_log.h"
25 #include "esp_newlib.h"
26 #include "esp_timer.h"
27 #include "freertos/FreeRTOS.h"
28 #include "freertos/task.h"
29 #include "soc/soc_caps.h"
30 #include "driver/rtc_io.h"
31 #include "hal/rtc_io_hal.h"
32
33 #include "driver/uart.h"
34
35 #include "soc/cpu.h"
36 #include "soc/rtc.h"
37 #include "soc/soc_caps.h"
38
39 #include "hal/wdt_hal.h"
40 #include "hal/rtc_hal.h"
41 #include "hal/uart_hal.h"
42 #if SOC_TOUCH_SENSOR_NUM > 0
43 #include "hal/touch_sensor_hal.h"
44 #include "driver/touch_sensor.h"
45 #include "driver/touch_sensor_common.h"
46 #endif
47 #include "hal/clk_gate_ll.h"
48
49 #include "sdkconfig.h"
50 #include "esp_rom_uart.h"
51
52 #ifdef CONFIG_IDF_TARGET_ESP32
53 #include "esp32/rom/cache.h"
54 #include "esp32/clk.h"
55 #include "esp32/rom/rtc.h"
56 #include "esp_private/gpio.h"
57 #elif CONFIG_IDF_TARGET_ESP32S2
58 #include "esp32s2/clk.h"
59 #include "esp32s2/rom/cache.h"
60 #include "esp32s2/rom/rtc.h"
61 #include "esp32s2/brownout.h"
62 #include "soc/extmem_reg.h"
63 #include "esp_private/gpio.h"
64 #elif CONFIG_IDF_TARGET_ESP32S3
65 #include "esp32s3/clk.h"
66 #include "esp32s3/rom/cache.h"
67 #include "esp32s3/rom/rtc.h"
68 #include "soc/extmem_reg.h"
69 #elif CONFIG_IDF_TARGET_ESP32C3
70 #include "esp32c3/clk.h"
71 #include "esp32c3/rom/cache.h"
72 #include "esp32c3/rom/rtc.h"
73 #include "soc/extmem_reg.h"
74 #include "esp_heap_caps.h"
75 #endif
76
77 // If light sleep time is less than that, don't power down flash
78 #define FLASH_PD_MIN_SLEEP_TIME_US 2000
79
80 // Time from VDD_SDIO power up to first flash read in ROM code
81 #define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700
82
83 // Cycles for RTC Timer clock source (internal oscillator) calibrate
84 #define RTC_CLK_SRC_CAL_CYCLES (10)
85
86 #ifdef CONFIG_IDF_TARGET_ESP32
87 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
88 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (212)
89 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (60)
90 #elif CONFIG_IDF_TARGET_ESP32S2
91 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ
92 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (147)
93 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (28)
94 #elif CONFIG_IDF_TARGET_ESP32S3
95 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ
96 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (0)
97 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (0)
98 #elif CONFIG_IDF_TARGET_ESP32C3
99 #define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32C3_DEFAULT_CPU_FREQ_MHZ
100 #define DEFAULT_SLEEP_OUT_OVERHEAD_US (105)
101 #define DEFAULT_HARDWARE_OUT_OVERHEAD_US (37)
102 #endif
103
104 #define LIGHT_SLEEP_TIME_OVERHEAD_US DEFAULT_HARDWARE_OUT_OVERHEAD_US
105 #if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) || \
106 defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS) || \
107 defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS) || \
108 defined(CONFIG_ESP32S3_RTC_CLK_SRC_EXT_CRYS)
109 #define DEEP_SLEEP_TIME_OVERHEAD_US (650 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
110 #else
111 #define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ)
112 #endif
113
114 #if defined(CONFIG_IDF_TARGET_ESP32) && defined(CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY)
115 #define DEEP_SLEEP_WAKEUP_DELAY CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY
116 #else
117 #define DEEP_SLEEP_WAKEUP_DELAY 0
118 #endif
119
120 extern void periph_inform_out_light_sleep_overhead(uint32_t out_light_sleep_time);
121
122 // Minimal amount of time we can sleep for
123 #define LIGHT_SLEEP_MIN_TIME_US 200
124
125 #define RTC_MODULE_SLEEP_PREPARE_CYCLES (6)
126
127 #define CHECK_SOURCE(source, value, mask) ((s_config.wakeup_triggers & mask) && \
128 (source == value))
129
130 /**
131 * Internal structure which holds all requested deep sleep parameters
132 */
133 typedef struct {
134 esp_sleep_pd_option_t pd_options[ESP_PD_DOMAIN_MAX];
135 uint64_t sleep_duration;
136 uint32_t wakeup_triggers : 15;
137 uint32_t ext1_trigger_mode : 1;
138 uint32_t ext1_rtc_gpio_mask : 18;
139 uint32_t ext0_trigger_level : 1;
140 uint32_t ext0_rtc_gpio_num : 5;
141 uint32_t gpio_wakeup_mask : 6;
142 uint32_t gpio_trigger_mode : 6;
143 uint32_t sleep_time_adjustment;
144 uint32_t ccount_ticks_record;
145 uint32_t sleep_time_overhead_out;
146 uint32_t rtc_clk_cal_period;
147 uint64_t rtc_ticks_at_sleep_start;
148 #if SOC_PM_SUPPORT_CPU_PD
149 void *cpu_pd_mem;
150 #endif
151 } sleep_config_t;
152
153 static sleep_config_t s_config = {
154 .pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO },
155 .ccount_ticks_record = 0,
156 .sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US,
157 .wakeup_triggers = 0
158 };
159
160 /* Internal variable used to track if light sleep wakeup sources are to be
161 expected when determining wakeup cause. */
162 static bool s_light_sleep_wakeup = false;
163
164 /* Updating RTC_MEMORY_CRC_REG register via set_rtc_memory_crc()
165 is not thread-safe, so we need to disable interrupts before going to deep sleep. */
166 static portMUX_TYPE spinlock_rtc_deep_sleep = portMUX_INITIALIZER_UNLOCKED;
167
168 static const char *TAG = "sleep";
169
170 static uint32_t get_power_down_flags(void);
171 #if SOC_PM_SUPPORT_EXT_WAKEUP
172 static void ext0_wakeup_prepare(void);
173 static void ext1_wakeup_prepare(void);
174 #endif
175 static void timer_wakeup_prepare(void);
176 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
177 static void touch_wakeup_prepare(void);
178 #endif
179 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
180 static void esp_deep_sleep_wakeup_prepare(void);
181 #endif
182
183 #if CONFIG_MAC_BB_PD
184 #define MAC_BB_POWER_DOWN_CB_NO 2
185 #define MAC_BB_POWER_UP_CB_NO 2
186 static DRAM_ATTR mac_bb_power_down_cb_t s_mac_bb_power_down_cb[MAC_BB_POWER_DOWN_CB_NO];
187 static DRAM_ATTR mac_bb_power_up_cb_t s_mac_bb_power_up_cb[MAC_BB_POWER_UP_CB_NO];
188
esp_register_mac_bb_pd_callback(mac_bb_power_down_cb_t cb)189 esp_err_t esp_register_mac_bb_pd_callback(mac_bb_power_down_cb_t cb)
190 {
191 int index = MAC_BB_POWER_DOWN_CB_NO;
192 for (int i = MAC_BB_POWER_DOWN_CB_NO - 1; i >= 0; i--) {
193 if (s_mac_bb_power_down_cb[i] == cb) {
194 return ESP_ERR_INVALID_STATE;
195 }
196
197 if (s_mac_bb_power_down_cb[i] == NULL) {
198 index = i;
199 }
200 }
201
202 if (index < MAC_BB_POWER_DOWN_CB_NO) {
203 s_mac_bb_power_down_cb[index] = cb;
204 return ESP_OK;
205 }
206
207 return ESP_ERR_NO_MEM;
208 }
209
esp_unregister_mac_bb_pd_callback(mac_bb_power_down_cb_t cb)210 esp_err_t esp_unregister_mac_bb_pd_callback(mac_bb_power_down_cb_t cb)
211 {
212 for (int i = MAC_BB_POWER_DOWN_CB_NO - 1; i >= 0; i--) {
213 if (s_mac_bb_power_down_cb[i] == cb) {
214 s_mac_bb_power_down_cb[i] = NULL;
215 return ESP_OK;
216 }
217 }
218 return ESP_ERR_INVALID_STATE;
219 }
220
mac_bb_power_down_cb_execute(void)221 static IRAM_ATTR void mac_bb_power_down_cb_execute(void)
222 {
223 for (int i = 0; i < MAC_BB_POWER_DOWN_CB_NO; i++) {
224 if (s_mac_bb_power_down_cb[i]) {
225 s_mac_bb_power_down_cb[i]();
226 }
227 }
228 }
229
esp_register_mac_bb_pu_callback(mac_bb_power_up_cb_t cb)230 esp_err_t esp_register_mac_bb_pu_callback(mac_bb_power_up_cb_t cb)
231 {
232 int index = MAC_BB_POWER_UP_CB_NO;
233 for (int i = MAC_BB_POWER_UP_CB_NO - 1; i >= 0; i--) {
234 if (s_mac_bb_power_up_cb[i] == cb) {
235 return ESP_ERR_INVALID_STATE;
236 }
237
238 if (s_mac_bb_power_up_cb[i] == NULL) {
239 index = i;
240 }
241 }
242
243 if (index < MAC_BB_POWER_UP_CB_NO) {
244 s_mac_bb_power_up_cb[index] = cb;
245 return ESP_OK;
246 }
247
248 return ESP_ERR_NO_MEM;
249 }
250
esp_unregister_mac_bb_pu_callback(mac_bb_power_up_cb_t cb)251 esp_err_t esp_unregister_mac_bb_pu_callback(mac_bb_power_up_cb_t cb)
252 {
253 for (int i = MAC_BB_POWER_UP_CB_NO - 1; i >= 0; i--) {
254 if (s_mac_bb_power_up_cb[i] == cb) {
255 s_mac_bb_power_up_cb[i] = NULL;
256 return ESP_OK;
257 }
258 }
259 return ESP_ERR_INVALID_STATE;
260 }
261
mac_bb_power_up_cb_execute(void)262 static IRAM_ATTR void mac_bb_power_up_cb_execute(void)
263 {
264 for (int i = 0; i < MAC_BB_POWER_UP_CB_NO; i++) {
265 if (s_mac_bb_power_up_cb[i]) {
266 s_mac_bb_power_up_cb[i]();
267 }
268 }
269 }
270 #endif ///CONFIG_MAC_BB_PD
271
272 /* Wake from deep sleep stub
273 See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
274 */
esp_get_deep_sleep_wake_stub(void)275 esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
276 {
277 esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG);
278 if (!esp_ptr_executable(stub_ptr)) {
279 return NULL;
280 }
281 return stub_ptr;
282 }
283
esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)284 void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
285 {
286 REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
287 }
288
esp_default_wake_deep_sleep(void)289 void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void)
290 {
291 /* Clear MMU for CPU 0 */
292 #if CONFIG_IDF_TARGET_ESP32
293 _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
294 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR);
295 _DPORT_REG_WRITE(DPORT_PRO_CACHE_CTRL1_REG,
296 _DPORT_REG_READ(DPORT_PRO_CACHE_CTRL1_REG) & (~DPORT_PRO_CACHE_MMU_IA_CLR));
297 #if DEEP_SLEEP_WAKEUP_DELAY > 0
298 // ROM code has not started yet, so we need to set delay factor
299 // used by esp_rom_delay_us first.
300 ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000);
301 // This delay is configured in menuconfig, it can be used to give
302 // the flash chip some time to become ready.
303 esp_rom_delay_us(DEEP_SLEEP_WAKEUP_DELAY);
304 #endif
305 #elif CONFIG_IDF_TARGET_ESP32S2
306 REG_SET_BIT(EXTMEM_CACHE_DBG_INT_ENA_REG, EXTMEM_CACHE_DBG_EN);
307 #endif
308 }
309
310 void __attribute__((weak, alias("esp_default_wake_deep_sleep"))) esp_wake_deep_sleep(void);
311
esp_deep_sleep(uint64_t time_in_us)312 void esp_deep_sleep(uint64_t time_in_us)
313 {
314 esp_sleep_enable_timer_wakeup(time_in_us);
315 esp_deep_sleep_start();
316 }
317
318 // [refactor-todo] provide target logic for body of uart functions below
flush_uarts(void)319 static void IRAM_ATTR flush_uarts(void)
320 {
321 for (int i = 0; i < SOC_UART_NUM; ++i) {
322 #ifdef CONFIG_IDF_TARGET_ESP32
323 esp_rom_uart_tx_wait_idle(i);
324 #else
325 if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
326 esp_rom_uart_tx_wait_idle(i);
327 }
328 #endif
329 }
330 }
331
suspend_uarts(void)332 static void IRAM_ATTR suspend_uarts(void)
333 {
334 for (int i = 0; i < SOC_UART_NUM; ++i) {
335 #ifndef CONFIG_IDF_TARGET_ESP32
336 if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
337 continue;
338 }
339 #endif
340 uart_ll_force_xoff(i);
341 #if SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
342 uint32_t uart_fsm = 0;
343 do {
344 uart_fsm = uart_ll_get_fsm_status(i);
345 } while (!(uart_fsm == UART_FSM_IDLE || uart_fsm == UART_FSM_TX_WAIT_SEND));
346 #else
347 while (uart_ll_get_fsm_status(i) != 0) {}
348 #endif
349 }
350 }
351
resume_uarts(void)352 static void IRAM_ATTR resume_uarts(void)
353 {
354 for (int i = 0; i < SOC_UART_NUM; ++i) {
355 #ifndef CONFIG_IDF_TARGET_ESP32
356 if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) {
357 continue;
358 }
359 #endif
360 uart_ll_force_xon(i);
361 }
362 }
363
364 inline static uint32_t IRAM_ATTR call_rtc_sleep_start(uint32_t reject_triggers);
365
366 #if SOC_PM_SUPPORT_CPU_PD
esp_sleep_cpu_pd_low_init(bool enable)367 esp_err_t esp_sleep_cpu_pd_low_init(bool enable)
368 {
369 if (enable) {
370 if (s_config.cpu_pd_mem == NULL) {
371 void *buf = heap_caps_aligned_alloc(RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN,
372 RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE,
373 MALLOC_CAP_RETENTION | MALLOC_CAP_DEFAULT);
374 if (buf) {
375 memset(buf, 0, RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE + RTC_HAL_DMA_LINK_NODE_SIZE);
376 s_config.cpu_pd_mem = rtc_cntl_hal_dma_link_init(buf,
377 buf + RTC_HAL_DMA_LINK_NODE_SIZE, RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE, NULL);
378 } else {
379 return ESP_ERR_NO_MEM;
380 }
381 }
382 } else {
383 if (s_config.cpu_pd_mem) {
384 heap_caps_free(s_config.cpu_pd_mem);
385 s_config.cpu_pd_mem = NULL;
386 }
387 }
388 return ESP_OK;
389 }
390 #endif // SOC_PM_SUPPORT_CPU_PD
391
392 #if SOC_GPIO_SUPPORT_SLP_SWITCH
393 #if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
gpio_sleep_mode_config_apply(void)394 static inline void gpio_sleep_mode_config_apply(void)
395 {
396 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
397 if (GPIO_IS_VALID_GPIO(gpio_num)) {
398 gpio_sleep_pupd_config_apply(gpio_num);
399 }
400 }
401 }
402
gpio_sleep_mode_config_unapply(void)403 static inline void gpio_sleep_mode_config_unapply(void)
404 {
405 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
406 if (GPIO_IS_VALID_GPIO(gpio_num)) {
407 gpio_sleep_pupd_config_unapply(gpio_num);
408 }
409 }
410 }
411 #endif
412
esp_sleep_config_gpio_isolate(void)413 void esp_sleep_config_gpio_isolate(void)
414 {
415 ESP_LOGI(TAG, "Configure to isolate all GPIO pins in sleep state");
416 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
417 if (GPIO_IS_VALID_GPIO(gpio_num)) {
418 gpio_sleep_set_direction(gpio_num, GPIO_MODE_DISABLE);
419 gpio_sleep_set_pull_mode(gpio_num, GPIO_FLOATING);
420 }
421 }
422 }
423
esp_sleep_enable_gpio_switch(bool enable)424 void esp_sleep_enable_gpio_switch(bool enable)
425 {
426 ESP_LOGI(TAG, "%s automatic switching of GPIO sleep configuration", enable ? "Enable" : "Disable");
427 for (gpio_num_t gpio_num = GPIO_NUM_0; gpio_num < GPIO_NUM_MAX; gpio_num++) {
428 if (GPIO_IS_VALID_GPIO(gpio_num)) {
429 if (enable) {
430 gpio_sleep_sel_en(gpio_num);
431 } else {
432 gpio_sleep_sel_dis(gpio_num);
433 }
434 }
435 }
436 }
437 #endif // SOC_GPIO_SUPPORT_SLP_SWITCH
438
439
esp_sleep_start(uint32_t pd_flags)440 static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
441 {
442 // Stop UART output so that output is not lost due to APB frequency change.
443 // For light sleep, suspend UART output — it will resume after wakeup.
444 // For deep sleep, wait for the contents of UART FIFO to be sent.
445 bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;
446
447 #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
448 /* Currently only safe to use deep sleep wake stub & RTC memory as heap in single core mode.
449
450 For ESP32-S3, either disable ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP in config or find a way to set the
451 deep sleep wake stub to NULL.
452 */
453 assert(!deep_sleep || esp_get_deep_sleep_wake_stub() == NULL);
454 #endif
455
456 if (deep_sleep) {
457 flush_uarts();
458 } else {
459 suspend_uarts();
460 }
461
462 // Save current frequency and switch to XTAL
463 rtc_cpu_freq_config_t cpu_freq_config;
464 rtc_clk_cpu_freq_get_config(&cpu_freq_config);
465 rtc_clk_cpu_freq_set_xtal();
466
467 #if CONFIG_MAC_BB_PD
468 mac_bb_power_down_cb_execute();
469 #endif
470
471 #if SOC_PM_SUPPORT_EXT_WAKEUP
472 // Configure pins for external wakeup
473 if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
474 ext0_wakeup_prepare();
475 }
476 if (s_config.wakeup_triggers & RTC_EXT1_TRIG_EN) {
477 ext1_wakeup_prepare();
478 }
479 #endif
480
481 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
482 if (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN) {
483 esp_deep_sleep_wakeup_prepare();
484 }
485 #endif
486
487 #ifdef CONFIG_IDF_TARGET_ESP32
488 // Enable ULP wakeup
489 if (s_config.wakeup_triggers & RTC_ULP_TRIG_EN) {
490 rtc_hal_ulp_wakeup_enable();
491 }
492 #if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
493 gpio_sleep_mode_config_apply();
494 #endif
495 #endif
496
497 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
498 if (deep_sleep) {
499 if (s_config.wakeup_triggers & RTC_TOUCH_TRIG_EN) {
500 touch_wakeup_prepare();
501 /* Workaround: In deep sleep, for ESP32S2, Power down the RTC_PERIPH will change the slope configuration of Touch sensor sleep pad.
502 * The configuration change will change the reading of the sleep pad, which will cause the touch wake-up sensor to trigger falsely.
503 */
504 pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
505 }
506 } else {
507 /* In light sleep, the RTC_PERIPH power domain should be in the power-on state (Power on the touch circuit in light sleep),
508 * otherwise the touch sensor FSM will be cleared, causing touch sensor false triggering.
509 */
510 if (touch_ll_get_fsm_state()) { // Check if the touch sensor is working properly.
511 pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
512 }
513 }
514 #endif
515 uint32_t reject_triggers = 0;
516 if ((pd_flags & RTC_SLEEP_PD_DIG) == 0 && (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN)) {
517 /* Light sleep, enable sleep reject for faster return from this function,
518 * in case the wakeup is already triggerred.
519 */
520 #if CONFIG_IDF_TARGET_ESP32
521 reject_triggers = RTC_CNTL_LIGHT_SLP_REJECT_EN_M | RTC_CNTL_GPIO_REJECT_EN_M;
522 #else
523 reject_triggers = s_config.wakeup_triggers;
524 #endif
525 }
526
527 // Enter sleep
528 rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags);
529 rtc_sleep_init(config);
530 rtc_sleep_low_init(s_config.rtc_clk_cal_period);
531
532 // Set state machine time for light sleep
533 if (!deep_sleep) {
534 rtc_sleep_low_init(s_config.rtc_clk_cal_period);
535 }
536
537 // Configure timer wakeup
538 if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) &&
539 s_config.sleep_duration > 0) {
540 timer_wakeup_prepare();
541 }
542
543 uint32_t result;
544 if (deep_sleep) {
545 /* Disable interrupts in case another task writes to RTC memory while we
546 * calculate RTC memory CRC
547 *
548 * Note: for ESP32-S3 running in dual core mode this is currently not enough,
549 * see the assert at top of this function.
550 */
551 portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
552
553 #if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
554 /* If not possible stack is in RTC FAST memory, use the ROM function to calculate the CRC and save ~140 bytes IRAM */
555 set_rtc_memory_crc();
556 result = call_rtc_sleep_start(reject_triggers);
557 #else
558 /* Otherwise, need to call the dedicated soc function for this */
559 result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
560 #endif
561
562 portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
563 } else {
564 result = call_rtc_sleep_start(reject_triggers);
565 }
566
567 // Restore CPU frequency
568 rtc_clk_cpu_freq_set_config(&cpu_freq_config);
569
570 if (!deep_sleep) {
571 s_config.ccount_ticks_record = cpu_ll_get_cycle_count();
572 }
573
574 #if SOC_PM_SUPPORT_CPU_PD
575 rtc_cntl_hal_disable_cpu_retention();
576 #endif
577
578 #if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
579 gpio_sleep_mode_config_unapply();
580 #endif
581
582 #if CONFIG_MAC_BB_PD
583 mac_bb_power_up_cb_execute();
584 #endif
585 // re-enable UART output
586 resume_uarts();
587
588 return result;
589 }
590
call_rtc_sleep_start(uint32_t reject_triggers)591 inline static uint32_t IRAM_ATTR call_rtc_sleep_start(uint32_t reject_triggers)
592 {
593 #ifdef CONFIG_IDF_TARGET_ESP32
594 return rtc_sleep_start(s_config.wakeup_triggers, reject_triggers);
595 #else
596 return rtc_sleep_start(s_config.wakeup_triggers, reject_triggers, 1);
597 #endif
598 }
599
esp_deep_sleep_start(void)600 void IRAM_ATTR esp_deep_sleep_start(void)
601 {
602 #if CONFIG_IDF_TARGET_ESP32S2
603 /* Due to hardware limitations, on S2 the brownout detector sometimes trigger during deep sleep
604 to circumvent this we disable the brownout detector before sleeping */
605 esp_brownout_disable();
606 #endif //CONFIG_IDF_TARGET_ESP32S2
607
608 // record current RTC time
609 s_config.rtc_ticks_at_sleep_start = rtc_time_get();
610
611 // record current RTC time
612 esp_sync_counters_rtc_and_frc();
613 // Configure wake stub
614 if (esp_get_deep_sleep_wake_stub() == NULL) {
615 esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
616 }
617
618 // Decide which power domains can be powered down
619 uint32_t pd_flags = get_power_down_flags();
620
621 s_config.rtc_clk_cal_period = esp_clk_slowclk_cal_get();
622
623 // Correct the sleep time
624 s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US;
625
626 uint32_t force_pd_flags = RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO;
627
628 #if SOC_PM_SUPPORT_WIFI_PD
629 force_pd_flags |= RTC_SLEEP_PD_WIFI;
630 #endif
631
632 #if SOC_PM_SUPPORT_BT_PD
633 force_pd_flags |= RTC_SLEEP_PD_BT;
634 #endif
635
636 // Enter sleep
637 esp_sleep_start(force_pd_flags | pd_flags);
638
639 // Because RTC is in a slower clock domain than the CPU, it
640 // can take several CPU cycles for the sleep mode to start.
641 while (1) {
642 ;
643 }
644 }
645
646 /**
647 * Helper function which handles entry to and exit from light sleep
648 * Placed into IRAM as flash may need some time to be powered on.
649 */
650 static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
651 uint32_t flash_enable_time_us,
652 rtc_vddsdio_config_t vddsdio_config) IRAM_ATTR __attribute__((noinline));
653
esp_light_sleep_inner(uint32_t pd_flags,uint32_t flash_enable_time_us,rtc_vddsdio_config_t vddsdio_config)654 static esp_err_t esp_light_sleep_inner(uint32_t pd_flags,
655 uint32_t flash_enable_time_us,
656 rtc_vddsdio_config_t vddsdio_config)
657 {
658 // Enter sleep
659 esp_err_t err = esp_sleep_start(pd_flags);
660
661 // If VDDSDIO regulator was controlled by RTC registers before sleep,
662 // restore the configuration.
663 if (vddsdio_config.force) {
664 rtc_vddsdio_set_config(vddsdio_config);
665 }
666
667 // If SPI flash was powered down, wait for it to become ready
668 if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
669 // Wait for the flash chip to start up
670 esp_rom_delay_us(flash_enable_time_us);
671 }
672 return err;
673 }
674
esp_light_sleep_start(void)675 esp_err_t esp_light_sleep_start(void)
676 {
677 s_config.ccount_ticks_record = cpu_ll_get_cycle_count();
678 static portMUX_TYPE light_sleep_lock = portMUX_INITIALIZER_UNLOCKED;
679 portENTER_CRITICAL(&light_sleep_lock);
680 /* We will be calling esp_timer_private_advance inside DPORT access critical
681 * section. Make sure the code on the other CPU is not holding esp_timer
682 * lock, otherwise there will be deadlock.
683 */
684 esp_timer_private_lock();
685
686 s_config.rtc_ticks_at_sleep_start = rtc_time_get();
687 uint32_t ccount_at_sleep_start = cpu_ll_get_cycle_count();
688 uint64_t frc_time_at_start = esp_system_get_time();
689 uint32_t sleep_time_overhead_in = (ccount_at_sleep_start - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
690
691 DPORT_STALL_OTHER_CPU_START();
692
693 // Decide which power domains can be powered down
694 uint32_t pd_flags = get_power_down_flags();
695
696 // Re-calibrate the RTC Timer clock
697 #if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) || defined(CONFIG_ESP32S2_RTC_CLK_SRC_EXT_CRYS) || defined(CONFIG_ESP32C3_RTC_CLK_SRC_EXT_CRYS)
698 uint64_t time_per_us = 1000000ULL;
699 s_config.rtc_clk_cal_period = (time_per_us << RTC_CLK_CAL_FRACT) / rtc_clk_slow_freq_get_hz();
700 #elif defined(CONFIG_ESP32S2_RTC_CLK_SRC_INT_RC)
701 s_config.rtc_clk_cal_period = rtc_clk_cal_cycling(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES);
702 esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
703 #else
704 s_config.rtc_clk_cal_period = rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES);
705 esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
706 #endif
707
708 /*
709 * Adjustment time consists of parts below:
710 * 1. Hardware time waiting for internal 8M oscilate clock and XTAL;
711 * 2. Hardware state swithing time of the rtc main state machine;
712 * 3. Code execution time when clock is not stable;
713 * 4. Code execution time which can be measured;
714 */
715
716 uint32_t rtc_cntl_xtl_buf_wait_slp_cycles = rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period);
717 s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out
718 + rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_slp_cycles + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, s_config.rtc_clk_cal_period);
719
720 // Decide if VDD_SDIO needs to be powered down;
721 // If it needs to be powered down, adjust sleep time.
722 const uint32_t flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US + DEEP_SLEEP_WAKEUP_DELAY;
723
724 /**
725 * If VDD_SDIO power domain is requested to be turned off, bit `RTC_SLEEP_PD_VDDSDIO`
726 * will be set in `pd_flags`.
727 */
728 if (pd_flags & RTC_SLEEP_PD_VDDSDIO) {
729 /*
730 * When VDD_SDIO power domain has to be turned off, the minimum sleep time of the
731 * system needs to meet the sum below:
732 * 1. Wait time for the flash power-on after waking up;
733 * 2. The execution time of codes between RTC Timer get start time
734 * with hardware starts to switch state to sleep;
735 * 3. The hardware state switching time of the rtc state machine during
736 * sleep and wake-up. This process requires 6 cycles to complete.
737 * The specific hardware state switching process and the cycles
738 * consumed are rtc_cpu_run_stall(1), cut_pll_rtl(2), cut_8m(1),
739 * min_protect(2);
740 * 4. All the adjustment time which is s_config.sleep_time_adjustment below.
741 */
742 const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
743 flash_enable_time_us + LIGHT_SLEEP_MIN_TIME_US + s_config.sleep_time_adjustment
744 + rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES, s_config.rtc_clk_cal_period));
745
746 if (s_config.sleep_duration > vddsdio_pd_sleep_duration) {
747 if (s_config.sleep_time_overhead_out < flash_enable_time_us) {
748 s_config.sleep_time_adjustment += flash_enable_time_us;
749 }
750 } else {
751 /**
752 * Minimum sleep time is not enough, then keep the VDD_SDIO power
753 * domain on.
754 */
755 pd_flags &= ~RTC_SLEEP_PD_VDDSDIO;
756 if (s_config.sleep_time_overhead_out > flash_enable_time_us) {
757 s_config.sleep_time_adjustment -= flash_enable_time_us;
758 }
759 }
760 }
761
762 periph_inform_out_light_sleep_overhead(s_config.sleep_time_adjustment - sleep_time_overhead_in);
763
764 #if SOC_PM_SUPPORT_CPU_PD
765 rtc_cntl_hal_enable_cpu_retention(s_config.cpu_pd_mem);
766 #endif
767
768 rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
769
770 // Safety net: enable WDT in case exit from light sleep fails
771 wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
772 bool wdt_was_enabled = wdt_hal_is_enabled(&rtc_wdt_ctx); // If WDT was enabled in the user code, then do not change it here.
773 if (!wdt_was_enabled) {
774 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
775 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
776 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
777 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
778 wdt_hal_enable(&rtc_wdt_ctx);
779 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
780 }
781
782 // Enter sleep, then wait for flash to be ready on wakeup
783 esp_err_t err = esp_light_sleep_inner(pd_flags,
784 flash_enable_time_us, vddsdio_config);
785
786 s_light_sleep_wakeup = true;
787
788 // FRC1 has been clock gated for the duration of the sleep, correct for that.
789 #ifdef CONFIG_IDF_TARGET_ESP32C3
790 /**
791 * On esp32c3, rtc_time_get() is non-blocking, esp_system_get_time() is
792 * blocking, and the measurement data shows that this order is better.
793 */
794 uint64_t frc_time_at_end = esp_system_get_time();
795 uint64_t rtc_ticks_at_end = rtc_time_get();
796 #else
797 uint64_t rtc_ticks_at_end = rtc_time_get();
798 uint64_t frc_time_at_end = esp_system_get_time();
799 #endif
800
801 uint64_t rtc_time_diff = rtc_time_slowclk_to_us(rtc_ticks_at_end - s_config.rtc_ticks_at_sleep_start, s_config.rtc_clk_cal_period);
802 uint64_t frc_time_diff = frc_time_at_end - frc_time_at_start;
803
804 int64_t time_diff = rtc_time_diff - frc_time_diff;
805 /* Small negative values (up to 1 RTC_SLOW clock period) are possible,
806 * for very small values of sleep_duration. Ignore those to keep esp_timer
807 * monotonic.
808 */
809 if (time_diff > 0) {
810 esp_timer_private_advance(time_diff);
811 }
812 esp_set_time_from_rtc();
813
814 esp_timer_private_unlock();
815 DPORT_STALL_OTHER_CPU_END();
816 if (!wdt_was_enabled) {
817 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
818 wdt_hal_disable(&rtc_wdt_ctx);
819 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
820 }
821 portEXIT_CRITICAL(&light_sleep_lock);
822 s_config.sleep_time_overhead_out = (cpu_ll_get_cycle_count() - s_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL);
823 return err;
824 }
825
esp_sleep_disable_wakeup_source(esp_sleep_source_t source)826 esp_err_t esp_sleep_disable_wakeup_source(esp_sleep_source_t source)
827 {
828 // For most of sources it is enough to set trigger mask in local
829 // configuration structure. The actual RTC wake up options
830 // will be updated by esp_sleep_start().
831 if (source == ESP_SLEEP_WAKEUP_ALL) {
832 s_config.wakeup_triggers = 0;
833 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TIMER, RTC_TIMER_TRIG_EN)) {
834 s_config.wakeup_triggers &= ~RTC_TIMER_TRIG_EN;
835 s_config.sleep_duration = 0;
836 #if SOC_PM_SUPPORT_EXT_WAKEUP
837 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT0, RTC_EXT0_TRIG_EN)) {
838 s_config.ext0_rtc_gpio_num = 0;
839 s_config.ext0_trigger_level = 0;
840 s_config.wakeup_triggers &= ~RTC_EXT0_TRIG_EN;
841 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_EXT1, RTC_EXT1_TRIG_EN)) {
842 s_config.ext1_rtc_gpio_mask = 0;
843 s_config.ext1_trigger_mode = 0;
844 s_config.wakeup_triggers &= ~RTC_EXT1_TRIG_EN;
845 #endif
846 #if SOC_TOUCH_PAD_WAKE_SUPPORTED
847 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_TOUCHPAD, RTC_TOUCH_TRIG_EN)) {
848 s_config.wakeup_triggers &= ~RTC_TOUCH_TRIG_EN;
849 #endif
850 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_GPIO, RTC_GPIO_TRIG_EN)) {
851 s_config.wakeup_triggers &= ~RTC_GPIO_TRIG_EN;
852 } else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_UART, (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN))) {
853 s_config.wakeup_triggers &= ~(RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN);
854 }
855 #if defined(CONFIG_ESP32_ULP_COPROC_ENABLED) || defined(CONFIG_ESP32S2_ULP_COPROC_ENABLED)
856 else if (CHECK_SOURCE(source, ESP_SLEEP_WAKEUP_ULP, RTC_ULP_TRIG_EN)) {
857 s_config.wakeup_triggers &= ~RTC_ULP_TRIG_EN;
858 }
859 #endif
860 else {
861 ESP_LOGE(TAG, "Incorrect wakeup source (%d) to disable.", (int) source);
862 return ESP_ERR_INVALID_STATE;
863 }
864 return ESP_OK;
865 }
866
esp_sleep_enable_ulp_wakeup(void)867 esp_err_t esp_sleep_enable_ulp_wakeup(void)
868 {
869 #if CONFIG_IDF_TARGET_ESP32
870 #if ((defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2))
871 ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal");
872 return ESP_ERR_NOT_SUPPORTED;
873 #endif
874 #ifdef CONFIG_ESP32_ULP_COPROC_ENABLED
875 if (s_config.wakeup_triggers & RTC_EXT0_TRIG_EN) {
876 ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
877 return ESP_ERR_INVALID_STATE;
878 }
879 s_config.wakeup_triggers |= RTC_ULP_TRIG_EN;
880 return ESP_OK;
881 #else // CONFIG_ESP32_ULP_COPROC_ENABLED
882 return ESP_ERR_INVALID_STATE;
883 #endif // CONFIG_ESP32_ULP_COPROC_ENABLED
884 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
885 s_config.wakeup_triggers |= (RTC_ULP_TRIG_EN | RTC_COCPU_TRIG_EN | RTC_COCPU_TRAP_TRIG_EN);
886 return ESP_OK;
887 #else
888 return ESP_ERR_NOT_SUPPORTED;
889 #endif
890 }
891
esp_sleep_enable_timer_wakeup(uint64_t time_in_us)892 esp_err_t esp_sleep_enable_timer_wakeup(uint64_t time_in_us)
893 {
894 s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN;
895 s_config.sleep_duration = time_in_us;
896 return ESP_OK;
897 }
898
timer_wakeup_prepare(void)899 static void timer_wakeup_prepare(void)
900 {
901 int64_t sleep_duration = (int64_t) s_config.sleep_duration - (int64_t) s_config.sleep_time_adjustment;
902 if (sleep_duration < 0) {
903 sleep_duration = 0;
904 }
905
906 int64_t ticks = rtc_time_us_to_slowclk(sleep_duration, s_config.rtc_clk_cal_period);
907 rtc_hal_set_wakeup_timer(s_config.rtc_ticks_at_sleep_start + ticks);
908 }
909
910 #if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
911 /* In deep sleep mode, only the sleep channel is supported, and other touch channels should be turned off. */
touch_wakeup_prepare(void)912 static void touch_wakeup_prepare(void)
913 {
914 uint16_t sleep_cycle = 0;
915 uint16_t meas_times = 0;
916 touch_pad_t touch_num = TOUCH_PAD_NUM0;
917 touch_ll_sleep_get_channel_num(&touch_num); // Check if the sleep pad is enabled.
918 if ((touch_num > TOUCH_PAD_NUM0) && (touch_num < TOUCH_PAD_MAX) && touch_ll_get_fsm_state()) {
919 touch_ll_stop_fsm();
920 touch_ll_clear_channel_mask(TOUCH_PAD_BIT_MASK_ALL);
921 touch_ll_intr_clear(TOUCH_PAD_INTR_MASK_ALL); // Clear state from previous wakeup
922 touch_hal_sleep_channel_get_work_time(&sleep_cycle, &meas_times);
923 touch_ll_set_meas_times(meas_times);
924 touch_ll_set_sleep_time(sleep_cycle);
925 touch_ll_set_channel_mask(BIT(touch_num));
926 touch_ll_start_fsm();
927 }
928 }
929 #endif
930
931 #if SOC_TOUCH_SENSOR_NUM > 0
932
esp_sleep_enable_touchpad_wakeup(void)933 esp_err_t esp_sleep_enable_touchpad_wakeup(void)
934 {
935 #if ((defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT) || (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT_V2))
936 ESP_LOGE(TAG, "Failed to enable wakeup when provide current to external 32kHz crystal");
937 return ESP_ERR_NOT_SUPPORTED;
938 #endif
939 if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN)) {
940 ESP_LOGE(TAG, "Conflicting wake-up trigger: ext0");
941 return ESP_ERR_INVALID_STATE;
942 }
943 s_config.wakeup_triggers |= RTC_TOUCH_TRIG_EN;
944 return ESP_OK;
945 }
946
esp_sleep_get_touchpad_wakeup_status(void)947 touch_pad_t esp_sleep_get_touchpad_wakeup_status(void)
948 {
949 if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_TOUCHPAD) {
950 return TOUCH_PAD_MAX;
951 }
952 touch_pad_t pad_num;
953 esp_err_t ret = touch_pad_get_wakeup_status(&pad_num); //TODO 723diff commit id:fda9ada1b
954 assert(ret == ESP_OK && "wakeup reason is RTC_TOUCH_TRIG_EN but SENS_TOUCH_MEAS_EN is zero");
955 return pad_num;
956 }
957
958 #endif // SOC_TOUCH_SENSOR_NUM > 0
959
esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)960 bool esp_sleep_is_valid_wakeup_gpio(gpio_num_t gpio_num)
961 {
962 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
963 return RTC_GPIO_IS_VALID_GPIO(gpio_num);
964 #else
965 return GPIO_IS_DEEP_SLEEP_WAKEUP_VALID_GPIO(gpio_num);
966 #endif // SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
967 }
968
969 #if SOC_PM_SUPPORT_EXT_WAKEUP
970
esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num,int level)971 esp_err_t esp_sleep_enable_ext0_wakeup(gpio_num_t gpio_num, int level)
972 {
973 if (level < 0 || level > 1) {
974 return ESP_ERR_INVALID_ARG;
975 }
976 if (!esp_sleep_is_valid_wakeup_gpio(gpio_num)) {
977 return ESP_ERR_INVALID_ARG;
978 }
979 if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
980 ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
981 return ESP_ERR_INVALID_STATE;
982 }
983 s_config.ext0_rtc_gpio_num = rtc_io_number_get(gpio_num);
984 s_config.ext0_trigger_level = level;
985 s_config.wakeup_triggers |= RTC_EXT0_TRIG_EN;
986 return ESP_OK;
987 }
988
ext0_wakeup_prepare(void)989 static void ext0_wakeup_prepare(void)
990 {
991 int rtc_gpio_num = s_config.ext0_rtc_gpio_num;
992 rtcio_hal_ext0_set_wakeup_pin(rtc_gpio_num, s_config.ext0_trigger_level);
993 rtcio_hal_function_select(rtc_gpio_num, RTCIO_FUNC_RTC);
994 rtcio_hal_input_enable(rtc_gpio_num);
995 }
996
esp_sleep_enable_ext1_wakeup(uint64_t mask,esp_sleep_ext1_wakeup_mode_t mode)997 esp_err_t esp_sleep_enable_ext1_wakeup(uint64_t mask, esp_sleep_ext1_wakeup_mode_t mode)
998 {
999 if (mode > ESP_EXT1_WAKEUP_ANY_HIGH) {
1000 return ESP_ERR_INVALID_ARG;
1001 }
1002 // Translate bit map of GPIO numbers into the bit map of RTC IO numbers
1003 uint32_t rtc_gpio_mask = 0;
1004 for (int gpio = 0; mask; ++gpio, mask >>= 1) {
1005 if ((mask & 1) == 0) {
1006 continue;
1007 }
1008 if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
1009 ESP_LOGE(TAG, "Not an RTC IO: GPIO%d", gpio);
1010 return ESP_ERR_INVALID_ARG;
1011 }
1012 rtc_gpio_mask |= BIT(rtc_io_number_get(gpio));
1013 }
1014 s_config.ext1_rtc_gpio_mask = rtc_gpio_mask;
1015 s_config.ext1_trigger_mode = mode;
1016 s_config.wakeup_triggers |= RTC_EXT1_TRIG_EN;
1017 return ESP_OK;
1018 }
1019
ext1_wakeup_prepare(void)1020 static void ext1_wakeup_prepare(void)
1021 {
1022 // Configure all RTC IOs selected as ext1 wakeup inputs
1023 uint32_t rtc_gpio_mask = s_config.ext1_rtc_gpio_mask;
1024 for (int gpio = 0; gpio < GPIO_PIN_COUNT && rtc_gpio_mask != 0; ++gpio) {
1025 int rtc_pin = rtc_io_number_get(gpio);
1026 if ((rtc_gpio_mask & BIT(rtc_pin)) == 0) {
1027 continue;
1028 }
1029 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
1030 // Route pad to RTC
1031 rtcio_hal_function_select(rtc_pin, RTCIO_FUNC_RTC);
1032 // set input enable in sleep mode
1033 rtcio_hal_input_enable(rtc_pin);
1034 #endif
1035
1036 // Pad configuration depends on RTC_PERIPH state in sleep mode
1037 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
1038 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
1039 // RTC_PERIPH will be powered down, so RTC_IO_ registers will
1040 // loose their state. Lock pad configuration.
1041 // Pullups/pulldowns also need to be disabled.
1042 rtcio_hal_pullup_disable(rtc_pin);
1043 rtcio_hal_pulldown_disable(rtc_pin);
1044 #endif
1045 rtcio_hal_hold_enable(rtc_pin);
1046 }
1047 // Keep track of pins which are processed to bail out early
1048 rtc_gpio_mask &= ~BIT(rtc_pin);
1049 }
1050
1051 // Clear state from previous wakeup
1052 rtc_hal_ext1_clear_wakeup_pins();
1053 // Set RTC IO pins and mode (any high, all low) to be used for wakeup
1054 rtc_hal_ext1_set_wakeup_pins(s_config.ext1_rtc_gpio_mask, s_config.ext1_trigger_mode);
1055 }
1056
esp_sleep_get_ext1_wakeup_status(void)1057 uint64_t esp_sleep_get_ext1_wakeup_status(void)
1058 {
1059 if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_EXT1) {
1060 return 0;
1061 }
1062 uint32_t status = rtc_hal_ext1_get_wakeup_pins();
1063 // Translate bit map of RTC IO numbers into the bit map of GPIO numbers
1064 uint64_t gpio_mask = 0;
1065 for (int gpio = 0; gpio < GPIO_PIN_COUNT; ++gpio) {
1066 if (!esp_sleep_is_valid_wakeup_gpio(gpio)) {
1067 continue;
1068 }
1069 int rtc_pin = rtc_io_number_get(gpio);
1070 if ((status & BIT(rtc_pin)) == 0) {
1071 continue;
1072 }
1073 gpio_mask |= 1ULL << gpio;
1074 }
1075 return gpio_mask;
1076 }
1077
1078 #endif // SOC_PM_SUPPORT_EXT_WAKEUP
1079
1080 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
esp_sleep_get_gpio_wakeup_status(void)1081 uint64_t esp_sleep_get_gpio_wakeup_status(void)
1082 {
1083 if (esp_sleep_get_wakeup_cause() != ESP_SLEEP_WAKEUP_GPIO) {
1084 return 0;
1085 }
1086
1087 return rtc_hal_gpio_get_wakeup_pins();
1088 }
1089
esp_deep_sleep_wakeup_prepare(void)1090 static void esp_deep_sleep_wakeup_prepare(void)
1091 {
1092 for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++) {
1093 if (((1ULL << gpio_idx) & s_config.gpio_wakeup_mask) == 0) {
1094 continue;
1095 }
1096 if (s_config.gpio_trigger_mode & BIT(gpio_idx)) {
1097 ESP_ERROR_CHECK(gpio_pullup_dis(gpio_idx));
1098 ESP_ERROR_CHECK(gpio_pulldown_en(gpio_idx));
1099 } else {
1100 ESP_ERROR_CHECK(gpio_pullup_en(gpio_idx));
1101 ESP_ERROR_CHECK(gpio_pulldown_dis(gpio_idx));
1102 }
1103 rtc_hal_gpio_set_wakeup_pins();
1104 ESP_ERROR_CHECK(gpio_hold_en(gpio_idx));
1105 }
1106 }
1107
esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask,esp_deepsleep_gpio_wake_up_mode_t mode)1108 esp_err_t esp_deep_sleep_enable_gpio_wakeup(uint64_t gpio_pin_mask, esp_deepsleep_gpio_wake_up_mode_t mode)
1109 {
1110 if (mode > ESP_GPIO_WAKEUP_GPIO_HIGH) {
1111 ESP_LOGE(TAG, "invalid mode");
1112 return ESP_ERR_INVALID_ARG;
1113 }
1114 gpio_int_type_t intr_type = ((mode == ESP_GPIO_WAKEUP_GPIO_LOW) ? GPIO_INTR_LOW_LEVEL : GPIO_INTR_HIGH_LEVEL);
1115 esp_err_t err = ESP_OK;
1116 for (gpio_num_t gpio_idx = GPIO_NUM_0; gpio_idx < GPIO_NUM_MAX; gpio_idx++, gpio_pin_mask >>= 1) {
1117 if ((gpio_pin_mask & 1) == 0) {
1118 continue;
1119 }
1120 if (!esp_sleep_is_valid_wakeup_gpio(gpio_idx)) {
1121 ESP_LOGE(TAG, "invalid mask, please ensure gpio number is no more than 5");
1122 return ESP_ERR_INVALID_ARG;
1123 }
1124 err = gpio_deep_sleep_wakeup_enable(gpio_idx, intr_type);
1125
1126 s_config.gpio_wakeup_mask |= BIT(gpio_idx);
1127 if (mode == ESP_GPIO_WAKEUP_GPIO_HIGH) {
1128 s_config.gpio_trigger_mode |= (mode << gpio_idx);
1129 } else {
1130 s_config.gpio_trigger_mode &= ~(mode << gpio_idx);
1131 }
1132 }
1133 s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
1134 rtc_hal_gpio_clear_wakeup_pins();
1135 return err;
1136 }
1137
1138 #endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
1139
esp_sleep_enable_gpio_wakeup(void)1140 esp_err_t esp_sleep_enable_gpio_wakeup(void)
1141 {
1142 #if CONFIG_IDF_TARGET_ESP32
1143 if (s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) {
1144 ESP_LOGE(TAG, "Conflicting wake-up triggers: touch / ULP");
1145 return ESP_ERR_INVALID_STATE;
1146 }
1147 #endif
1148 s_config.wakeup_triggers |= RTC_GPIO_TRIG_EN;
1149 return ESP_OK;
1150 }
1151
esp_sleep_enable_uart_wakeup(int uart_num)1152 esp_err_t esp_sleep_enable_uart_wakeup(int uart_num)
1153 {
1154 if (uart_num == UART_NUM_0) {
1155 s_config.wakeup_triggers |= RTC_UART0_TRIG_EN;
1156 } else if (uart_num == UART_NUM_1) {
1157 s_config.wakeup_triggers |= RTC_UART1_TRIG_EN;
1158 } else {
1159 return ESP_ERR_INVALID_ARG;
1160 }
1161
1162 return ESP_OK;
1163 }
1164
esp_sleep_enable_wifi_wakeup(void)1165 esp_err_t esp_sleep_enable_wifi_wakeup(void)
1166 {
1167 #if SOC_PM_SUPPORT_WIFI_WAKEUP
1168 s_config.wakeup_triggers |= RTC_WIFI_TRIG_EN;
1169 return ESP_OK;
1170 #else
1171 return ESP_ERR_NOT_SUPPORTED;
1172 #endif
1173 }
1174
esp_sleep_disable_wifi_wakeup(void)1175 esp_err_t esp_sleep_disable_wifi_wakeup(void)
1176 {
1177 #if SOC_PM_SUPPORT_WIFI_WAKEUP
1178 s_config.wakeup_triggers &= (~RTC_WIFI_TRIG_EN);
1179 return ESP_OK;
1180 #else
1181 return ESP_ERR_NOT_SUPPORTED;
1182 #endif
1183 }
1184
esp_sleep_get_wakeup_cause(void)1185 esp_sleep_wakeup_cause_t esp_sleep_get_wakeup_cause(void)
1186 {
1187 if (rtc_get_reset_reason(0) != DEEPSLEEP_RESET && !s_light_sleep_wakeup) {
1188 return ESP_SLEEP_WAKEUP_UNDEFINED;
1189 }
1190
1191 #ifdef CONFIG_IDF_TARGET_ESP32
1192 uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
1193 #else
1194 uint32_t wakeup_cause = REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
1195 #endif
1196
1197 if (wakeup_cause & RTC_TIMER_TRIG_EN) {
1198 return ESP_SLEEP_WAKEUP_TIMER;
1199 } else if (wakeup_cause & RTC_GPIO_TRIG_EN) {
1200 return ESP_SLEEP_WAKEUP_GPIO;
1201 } else if (wakeup_cause & (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN)) {
1202 return ESP_SLEEP_WAKEUP_UART;
1203 #if SOC_PM_SUPPORT_EXT_WAKEUP
1204 } else if (wakeup_cause & RTC_EXT0_TRIG_EN) {
1205 return ESP_SLEEP_WAKEUP_EXT0;
1206 } else if (wakeup_cause & RTC_EXT1_TRIG_EN) {
1207 return ESP_SLEEP_WAKEUP_EXT1;
1208 #endif
1209 #if SOC_TOUCH_PAD_WAKE_SUPPORTED
1210 } else if (wakeup_cause & RTC_TOUCH_TRIG_EN) {
1211 return ESP_SLEEP_WAKEUP_TOUCHPAD;
1212 #endif
1213 #if SOC_ULP_SUPPORTED
1214 } else if (wakeup_cause & RTC_ULP_TRIG_EN) {
1215 return ESP_SLEEP_WAKEUP_ULP;
1216 #endif
1217 #if SOC_PM_SUPPORT_WIFI_WAKEUP
1218 } else if (wakeup_cause & RTC_WIFI_TRIG_EN) {
1219 return ESP_SLEEP_WAKEUP_WIFI;
1220 #endif
1221 #if SOC_PM_SUPPORT_BT_WAKEUP
1222 } else if (wakeup_cause & RTC_BT_TRIG_EN) {
1223 return ESP_SLEEP_WAKEUP_BT;
1224 #endif
1225 #if CONFIG_IDF_TARGET_ESP32S2
1226 } else if (wakeup_cause & RTC_COCPU_TRIG_EN) {
1227 return ESP_SLEEP_WAKEUP_ULP;
1228 } else if (wakeup_cause & RTC_COCPU_TRAP_TRIG_EN) {
1229 return ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG;
1230 #endif
1231 } else {
1232 return ESP_SLEEP_WAKEUP_UNDEFINED;
1233 }
1234 }
1235
esp_sleep_pd_config(esp_sleep_pd_domain_t domain,esp_sleep_pd_option_t option)1236 esp_err_t esp_sleep_pd_config(esp_sleep_pd_domain_t domain,
1237 esp_sleep_pd_option_t option)
1238 {
1239 if (domain >= ESP_PD_DOMAIN_MAX || option > ESP_PD_OPTION_AUTO) {
1240 return ESP_ERR_INVALID_ARG;
1241 }
1242 s_config.pd_options[domain] = option;
1243 return ESP_OK;
1244 }
1245
get_power_down_flags(void)1246 static uint32_t get_power_down_flags(void)
1247 {
1248 // Where needed, convert AUTO options to ON. Later interpret AUTO as OFF.
1249
1250 // RTC_SLOW_MEM is needed for the ULP, so keep RTC_SLOW_MEM powered up if ULP
1251 // is used and RTC_SLOW_MEM is Auto.
1252 // If there is any data placed into .rtc.data or .rtc.bss segments, and
1253 // RTC_SLOW_MEM is Auto, keep it powered up as well.
1254
1255 #if SOC_RTC_SLOW_MEM_SUPPORTED && SOC_ULP_SUPPORTED
1256 // Labels are defined in the linker script
1257 extern int _rtc_slow_length;
1258
1259 if ((s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] == ESP_PD_OPTION_AUTO) &&
1260 ((size_t) &_rtc_slow_length > 0 ||
1261 (s_config.wakeup_triggers & RTC_ULP_TRIG_EN))) {
1262 s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] = ESP_PD_OPTION_ON;
1263 }
1264 #endif
1265
1266 #if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
1267 /* RTC_FAST_MEM is needed for deep sleep stub.
1268 If RTC_FAST_MEM is Auto, keep it powered on, so that deep sleep stub can run.
1269 In the new chip revision, deep sleep stub will be optional, and this can be changed. */
1270 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) {
1271 s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
1272 }
1273 #else
1274 /* If RTC_FAST_MEM is used for heap, force RTC_FAST_MEM to be powered on. */
1275 s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON;
1276 #endif
1277
1278 // RTC_PERIPH is needed for EXT0 wakeup and GPIO wakeup.
1279 // If RTC_PERIPH is auto, and EXT0/GPIO aren't enabled, power down RTC_PERIPH.
1280 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) {
1281 #if SOC_TOUCH_PAD_WAKE_SUPPORTED
1282 uint32_t wakeup_source = RTC_TOUCH_TRIG_EN;
1283 #if SOC_ULP_SUPPORTED
1284 wakeup_source |= RTC_ULP_TRIG_EN;
1285 #endif
1286 if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) {
1287 s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
1288 } else if (s_config.wakeup_triggers & wakeup_source) {
1289 // In both rev. 0 and rev. 1 of ESP32, forcing power up of RTC_PERIPH
1290 // prevents ULP timer and touch FSMs from working correctly.
1291 s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
1292 }
1293 #else
1294 if (s_config.wakeup_triggers & RTC_GPIO_TRIG_EN) {
1295 s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON;
1296 } else {
1297 s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF;
1298 }
1299 #endif // SOC_TOUCH_PAD_WAKE_SUPPORTED
1300 }
1301
1302 #if SOC_PM_SUPPORT_CPU_PD
1303 if (s_config.cpu_pd_mem == NULL) {
1304 s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON;
1305 }
1306 #else
1307 if (s_config.pd_options[ESP_PD_DOMAIN_CPU] != ESP_PD_OPTION_ON) {
1308 s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON;
1309 }
1310 #endif
1311
1312 if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) {
1313 s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF;
1314 }
1315
1316 const char *option_str[] = {"OFF", "ON", "AUTO(OFF)" /* Auto works as OFF */};
1317 ESP_LOGD(TAG, "RTC_PERIPH: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH]]);
1318 #if SOC_RTC_SLOW_MEM_SUPPORTED
1319 ESP_LOGD(TAG, "RTC_SLOW_MEM: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM]]);
1320 #endif
1321 ESP_LOGD(TAG, "RTC_FAST_MEM: %s", option_str[s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM]]);
1322
1323 // Prepare flags based on the selected options
1324 uint32_t pd_flags = 0;
1325 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) {
1326 pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM;
1327 }
1328 #if SOC_RTC_SLOW_MEM_SUPPORTED
1329 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) {
1330 pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM;
1331 }
1332 #endif
1333 if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) {
1334 pd_flags |= RTC_SLEEP_PD_RTC_PERIPH;
1335 }
1336
1337 #if SOC_PM_SUPPORT_CPU_PD
1338 if (s_config.pd_options[ESP_PD_DOMAIN_CPU] != ESP_PD_OPTION_ON) {
1339 pd_flags |= RTC_SLEEP_PD_CPU;
1340 }
1341 #endif
1342
1343 #ifdef CONFIG_IDF_TARGET_ESP32
1344 pd_flags |= RTC_SLEEP_PD_XTAL;
1345 #endif
1346
1347 /**
1348 * VDD_SDIO power domain shall be kept on during the light sleep
1349 * when CONFIG_ESP_SYSTEM_PD_FLASH is not set and off when it is set.
1350 * The application can still force the power domain to remain on by calling
1351 * `esp_sleep_pd_config` before getting into light sleep mode.
1352 *
1353 * In deep sleep mode, the power domain will be turned off, regardless the
1354 * value of this field.
1355 */
1356 if (s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] == ESP_PD_OPTION_AUTO) {
1357 #ifdef CONFIG_ESP_SYSTEM_PD_FLASH
1358 s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] = ESP_PD_OPTION_OFF;
1359 #else
1360 s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] = ESP_PD_OPTION_ON;
1361 #endif
1362 }
1363
1364 if (s_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] != ESP_PD_OPTION_ON) {
1365 pd_flags |= RTC_SLEEP_PD_VDDSDIO;
1366 }
1367
1368 #if ((defined CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS) && (defined CONFIG_ESP32_RTC_EXT_CRYST_ADDIT_CURRENT))
1369 if ((s_config.wakeup_triggers & (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) == 0) {
1370 // If enabled EXT1 only and enable the additional current by touch, should be keep RTC_PERIPH power on.
1371 pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
1372 }
1373 #endif
1374
1375 return pd_flags;
1376 }
1377
esp_deep_sleep_disable_rom_logging(void)1378 void esp_deep_sleep_disable_rom_logging(void)
1379 {
1380 esp_rom_disable_logging();
1381 }
1382
