1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdint.h>
16 #include <stdio.h>
17 #include <stdlib.h>
18 #include <stdbool.h>
19 #include "sdkconfig.h"
20 #include "freertos/FreeRTOS.h"
21 #include "freertos/task.h"
22 #include "esp_types.h"
23 #include "esp_err.h"
24 #include "esp_intr_alloc.h"
25 #include "esp_attr.h"
26 #include "esp_freertos_hooks.h"
27 #include "soc/timer_periph.h"
28 #include "driver/timer.h"
29 #include "driver/periph_ctrl.h"
30 #include "esp_int_wdt.h"
31 #include "esp_private/system_internal.h"
32 #include "hal/cpu_hal.h"
33 #include "hal/timer_types.h"
34 #include "hal/wdt_hal.h"
35 #include "hal/interrupt_controller_hal.h"
36
37 #if CONFIG_ESP_INT_WDT
38
39 #define WDT_INT_NUM ETS_T1_WDT_INUM
40
41 #define IWDT_INSTANCE WDT_MWDT1
42 #define IWDT_PRESCALER MWDT1_TICK_PRESCALER //Tick period of 500us if WDT source clock is 80MHz
43 #define IWDT_TICKS_PER_US MWDT1_TICKS_PER_US
44 #define IWDT_INITIAL_TIMEOUT_S 5
45 static wdt_hal_context_t iwdt_context;
46
47 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
48 /*
49 * This parameter is used to indicate the response time of Interrupt watchdog to
50 * identify the live lock.
51 */
52 #define IWDT_LIVELOCK_TIMEOUT_MS (20)
53
54 extern uint32_t _lx_intr_livelock_counter, _lx_intr_livelock_max;
55 #endif
56
57 //Take care: the tick hook can also be called before esp_int_wdt_init() is called.
58 #if CONFIG_ESP_INT_WDT_CHECK_CPU1
59 //Not static; the ISR assembly checks this.
60 bool int_wdt_app_cpu_ticked = false;
61
tick_hook(void)62 static void IRAM_ATTR tick_hook(void)
63 {
64 if (cpu_hal_get_core_id() != 0) {
65 int_wdt_app_cpu_ticked = true;
66 } else {
67 //Only feed wdt if app cpu also ticked.
68 if (int_wdt_app_cpu_ticked) {
69 //Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
70 wdt_hal_write_protect_disable(&iwdt_context);
71 //Reconfigure stage timeouts
72 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
73 _lx_intr_livelock_counter = 0;
74 wdt_hal_config_stage(&iwdt_context, WDT_STAGE0,
75 CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US / (_lx_intr_livelock_max + 1), WDT_STAGE_ACTION_INT); //Set timeout before interrupt
76 #else
77 wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
78 #endif
79 wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
80 wdt_hal_feed(&iwdt_context);
81 wdt_hal_write_protect_enable(&iwdt_context);
82 int_wdt_app_cpu_ticked = false;
83 }
84 }
85 }
86 #else
tick_hook(void)87 static void IRAM_ATTR tick_hook(void)
88 {
89 #if !CONFIG_FREERTOS_UNICORE
90 if (cpu_hal_get_core_id() != 0) {
91 return;
92 }
93 #endif
94 //Todo: Check if there's a way to avoid reconfiguring the stages on each feed.
95 wdt_hal_write_protect_disable(&iwdt_context);
96 //Reconfigure stage timeouts
97 wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT); //Set timeout before interrupt
98 wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, 2 * CONFIG_ESP_INT_WDT_TIMEOUT_MS * 1000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM); //Set timeout before reset
99 wdt_hal_feed(&iwdt_context);
100 wdt_hal_write_protect_enable(&iwdt_context);
101 }
102 #endif
103
104
esp_int_wdt_init(void)105 void esp_int_wdt_init(void)
106 {
107 periph_module_enable(PERIPH_TIMG1_MODULE);
108 //The timer configs initially are set to 5 seconds, to make sure the CPU can start up. The tick hook sets
109 //it to their actual value.
110 wdt_hal_init(&iwdt_context, IWDT_INSTANCE, IWDT_PRESCALER, true);
111 wdt_hal_write_protect_disable(&iwdt_context);
112 //1st stage timeout: interrupt
113 wdt_hal_config_stage(&iwdt_context, WDT_STAGE0, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
114 //2nd stage timeout: reset system
115 wdt_hal_config_stage(&iwdt_context, WDT_STAGE1, IWDT_INITIAL_TIMEOUT_S * 1000000 / IWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);
116 //Enable WDT
117 wdt_hal_enable(&iwdt_context);
118 wdt_hal_write_protect_enable(&iwdt_context);
119
120
121 #if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
122
123 #define APB_DCRSET (0x200c)
124 #define APB_ITCTRL (0x3f00)
125
126 #define ERI_ADDR(APB) (0x100000 + (APB))
127
128 #define _SYM2STR(x) # x
129 #define SYM2STR(x) _SYM2STR(x)
130 uint32_t eriadrs, scratch = 0, immediate = 0;
131 if (soc_has_cache_lock_bug()) {
132 if (xPortGetCoreID() != CONFIG_BTDM_CTRL_PINNED_TO_CORE) {
133 __asm__ __volatile__ (
134 /* Enable Xtensa Debug Module Integration Mode */
135 "movi %[ERI], " SYM2STR(ERI_ADDR(APB_ITCTRL)) "\n"
136 "rer %[REG], %[ERI]\n"
137 "movi %[IMM], 1\n"
138 "or %[REG], %[IMM], %[REG]\n"
139 "wer %[REG], %[ERI]\n"
140 /* Enable Xtensa Debug Module BreakIn signal */
141 "movi %[ERI], " SYM2STR(ERI_ADDR(APB_DCRSET)) "\n"
142 "rer %[REG], %[ERI]\n"
143 "movi %[IMM], 0x10000\n"
144 "or %[REG], %[IMM], %[REG]\n"
145 "wer %[REG], %[ERI]\n"
146 : [ERI] "=r" (eriadrs), [REG] "+r" (scratch), [IMM] "+r" (immediate)
147 );
148 }
149 }
150 #endif
151 }
152
esp_int_wdt_cpu_init(void)153 void esp_int_wdt_cpu_init(void)
154 {
155 assert((CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (portTICK_PERIOD_MS << 1)) && "Interrupt watchdog timeout needs to meet twice the RTOS tick period!");
156 esp_register_freertos_tick_hook_for_cpu(tick_hook, cpu_hal_get_core_id());
157 ESP_INTR_DISABLE(WDT_INT_NUM);
158 intr_matrix_set(cpu_hal_get_core_id(), ETS_TG1_WDT_LEVEL_INTR_SOURCE, WDT_INT_NUM);
159
160 /* Set the type and priority to watch dog interrupts */
161 #if SOC_CPU_HAS_FLEXIBLE_INTC
162 interrupt_controller_hal_set_int_type(WDT_INT_NUM, INTR_TYPE_LEVEL);
163 interrupt_controller_hal_set_int_level(WDT_INT_NUM, SOC_INTERRUPT_LEVEL_MEDIUM);
164 #endif
165
166 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
167 /*
168 * This is a workaround for issue 3.15 in "ESP32 ECO and workarounds for
169 * Bugs" document.
170 */
171 _lx_intr_livelock_counter = 0;
172 if (soc_has_cache_lock_bug()) {
173 assert((portTICK_PERIOD_MS << 1) <= IWDT_LIVELOCK_TIMEOUT_MS);
174 assert(CONFIG_ESP_INT_WDT_TIMEOUT_MS >= (IWDT_LIVELOCK_TIMEOUT_MS * 3));
175 _lx_intr_livelock_max = CONFIG_ESP_INT_WDT_TIMEOUT_MS / IWDT_LIVELOCK_TIMEOUT_MS - 1;
176 }
177 #endif
178
179 // We do not register a handler for the watchdog interrupt because:
180 // 1. Interrupt level 4 on Xtensa architecture is not servicable from C
181 // 2. Instead, we set the entry of watchdog interrupt to the panic handler, see riscv/vector.S and xtensa_vectors.S
182 ESP_INTR_ENABLE(WDT_INT_NUM);
183 }
184
185 #endif
186
