1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <stdlib.h>
8 #include <string.h>
9 #include <sys/param.h> // For MIN/MAX
10 #include "esp_log.h"
11 #include "spi_flash_chip_generic.h"
12 #include "spi_flash_chip_gd.h"
13 #include "spi_flash_defs.h"
14
15 #define ADDR_32BIT(addr) (addr >= (1<<24))
16
17 #define REGION_32BIT(start, len) ((start) + (len) > (1<<24))
18
19 extern esp_err_t spi_flash_chip_winbond_read(esp_flash_t *chip, void *buffer, uint32_t address, uint32_t length);
20 extern esp_err_t spi_flash_chip_winbond_page_program(esp_flash_t *chip, const void *buffer, uint32_t address, uint32_t length);
21 extern esp_err_t spi_flash_chip_winbond_erase_sector(esp_flash_t *chip, uint32_t start_address);
22 extern esp_err_t spi_flash_chip_winbond_erase_block(esp_flash_t *chip, uint32_t start_address);
23
24 #define spi_flash_chip_gd_read spi_flash_chip_winbond_read
25 #define spi_flash_chip_gd_page_program spi_flash_chip_winbond_page_program
26 #define spi_flash_chip_gd_erase_sector spi_flash_chip_winbond_erase_sector
27 #define spi_flash_chip_gd_erase_block spi_flash_chip_winbond_erase_block
28
spi_flash_chip_gd_get_caps(esp_flash_t * chip)29 spi_flash_caps_t spi_flash_chip_gd_get_caps(esp_flash_t *chip)
30 {
31 spi_flash_caps_t caps_flags = 0;
32 // 32M-bits address support
33 if ((chip->chip_id & 0xFF) >= 0x19) {
34 caps_flags |= SPI_FLASH_CHIP_CAP_32MB_SUPPORT;
35 }
36 // flash-suspend is not supported
37 // flash read unique id.
38 caps_flags |= SPI_FLASH_CHIP_CAP_UNIQUE_ID;
39 return caps_flags;
40 }
41
spi_flash_chip_gd_detect_size(esp_flash_t * chip,uint32_t * size)42 esp_err_t spi_flash_chip_gd_detect_size(esp_flash_t *chip, uint32_t *size)
43 {
44 uint32_t id = chip->chip_id;
45 *size = 0;
46
47 /* Can't detect size unless the high byte of the product ID matches the same convention, which is usually 0x40 or
48 * 0xC0 or similar. */
49 if (((id & 0xFFFF) == 0x0000) || ((id & 0xFFFF) == 0xFFFF)) {
50 return ESP_ERR_FLASH_UNSUPPORTED_CHIP;
51 }
52
53 *size = 1 << (id & 0xFF);
54 return ESP_OK;
55 }
56
57 #ifndef CONFIG_SPI_FLASH_ROM_IMPL
58
59 #define FLASH_ID_MASK 0xFF00
60 #define FLASH_SIZE_MASK 0xFF
61 #define GD25Q_PRODUCT_ID 0x4000
62 #define GD25LQ_PRODUCT_ID 0x6000
63
64 #define WRSR_16B_REQUIRED(chip_id) (((chip_id) & FLASH_ID_MASK) == GD25LQ_PRODUCT_ID || \
65 ((chip_id) & FLASH_SIZE_MASK) <= 0x15)
66
67 /* Driver for GD flash chip */
68
spi_flash_chip_gd_probe(esp_flash_t * chip,uint32_t flash_id)69 esp_err_t spi_flash_chip_gd_probe(esp_flash_t *chip, uint32_t flash_id)
70 {
71 /* Check manufacturer and product IDs match our desired masks */
72 const uint8_t MFG_ID = 0xC8;
73 if (flash_id >> 16 != MFG_ID) {
74 return ESP_ERR_NOT_FOUND;
75 }
76
77 uint32_t product_id = flash_id & FLASH_ID_MASK;
78 if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID) {
79 return ESP_ERR_NOT_FOUND;
80 }
81
82 return ESP_OK;
83 }
84
spi_flash_chip_gd_set_io_mode(esp_flash_t * chip)85 esp_err_t spi_flash_chip_gd_set_io_mode(esp_flash_t *chip)
86 {
87 if (WRSR_16B_REQUIRED(chip->chip_id)) {
88 const uint32_t qe = 1<<9;
89 return spi_flash_common_set_io_mode(chip,
90 spi_flash_common_write_status_16b_wrsr,
91 spi_flash_common_read_status_16b_rdsr_rdsr2,
92 qe);
93 } else {
94 const uint32_t qe = 1<<1;
95 return spi_flash_common_set_io_mode(chip,
96 spi_flash_common_write_status_8b_wrsr2,
97 spi_flash_common_read_status_8b_rdsr2,
98 qe);
99 }
100 }
101
spi_flash_chip_gd_get_io_mode(esp_flash_t * chip,esp_flash_io_mode_t * out_io_mode)102 esp_err_t spi_flash_chip_gd_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
103 {
104 /* GD uses bit 1 of SR2 as Quad Enable */
105 const uint8_t BIT_QE = 1 << 1;
106 uint32_t sr;
107 esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
108 if (ret == ESP_OK) {
109 *out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
110 }
111 return ret;
112 }
113 #endif //CONFIG_SPI_FLASH_ROM_IMPL
114
115 static const char chip_name[] = "gd";
116
117 // The issi chip can use the functions for generic chips except from set read mode and probe,
118 // So we only replace these two functions.
119 const spi_flash_chip_t esp_flash_chip_gd = {
120 .name = chip_name,
121 .timeout = &spi_flash_chip_generic_timeout,
122 .probe = spi_flash_chip_gd_probe,
123 .reset = spi_flash_chip_generic_reset,
124 .detect_size = spi_flash_chip_gd_detect_size,
125 .erase_chip = spi_flash_chip_generic_erase_chip,
126 .erase_sector = spi_flash_chip_gd_erase_sector,
127 .erase_block = spi_flash_chip_gd_erase_block,
128 .sector_size = 4 * 1024,
129 .block_erase_size = 64 * 1024,
130
131 .get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
132 .set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
133
134 .num_protectable_regions = 0,
135 .protectable_regions = NULL,
136 .get_protected_regions = NULL,
137 .set_protected_regions = NULL,
138
139 .read = spi_flash_chip_gd_read,
140 .write = spi_flash_chip_generic_write,
141 .program_page = spi_flash_chip_gd_page_program,
142 .page_size = 256,
143 .write_encrypted = spi_flash_chip_generic_write_encrypted,
144
145 .wait_idle = spi_flash_chip_generic_wait_idle,
146 .set_io_mode = spi_flash_chip_gd_set_io_mode,
147 .get_io_mode = spi_flash_chip_gd_get_io_mode,
148
149 .read_reg = spi_flash_chip_generic_read_reg,
150 .yield = spi_flash_chip_generic_yield,
151 .sus_setup = spi_flash_chip_generic_suspend_cmd_conf,
152 .read_unique_id = spi_flash_chip_generic_read_unique_id,
153 .get_chip_caps = spi_flash_chip_gd_get_caps,
154 .config_host_io_mode = spi_flash_chip_generic_config_host_io_mode,
155 };
156
