1 // Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include <stdlib.h>
16 #include "spi_flash_chip_generic.h"
17 #include "spi_flash_chip_gd.h"
18 #include "spi_flash_defs.h"
19
20 #ifndef CONFIG_SPI_FLASH_ROM_IMPL
21
22 #define FLASH_ID_MASK 0xFF00
23 #define FLASH_SIZE_MASK 0xFF
24 #define GD25Q_PRODUCT_ID 0x4000
25 #define GD25LQ_PRODUCT_ID 0x6000
26
27 #define WRSR_16B_REQUIRED(chip_id) (((chip_id) & FLASH_ID_MASK) == GD25LQ_PRODUCT_ID || \
28 ((chip_id) & FLASH_SIZE_MASK) <= 0x15)
29
30 /* Driver for GD flash chip */
31
spi_flash_chip_gd_probe(esp_flash_t * chip,uint32_t flash_id)32 esp_err_t spi_flash_chip_gd_probe(esp_flash_t *chip, uint32_t flash_id)
33 {
34 /* Check manufacturer and product IDs match our desired masks */
35 const uint8_t MFG_ID = 0xC8;
36 if (flash_id >> 16 != MFG_ID) {
37 return ESP_ERR_NOT_FOUND;
38 }
39
40 uint32_t product_id = flash_id & FLASH_ID_MASK;
41 if (product_id != GD25Q_PRODUCT_ID && product_id != GD25LQ_PRODUCT_ID) {
42 return ESP_ERR_NOT_FOUND;
43 }
44
45 return ESP_OK;
46 }
47
spi_flash_chip_gd_set_io_mode(esp_flash_t * chip)48 esp_err_t spi_flash_chip_gd_set_io_mode(esp_flash_t *chip)
49 {
50 if (WRSR_16B_REQUIRED(chip->chip_id)) {
51 const uint32_t qe = 1<<9;
52 return spi_flash_common_set_io_mode(chip,
53 spi_flash_common_write_status_16b_wrsr,
54 spi_flash_common_read_status_16b_rdsr_rdsr2,
55 qe);
56 } else {
57 const uint32_t qe = 1<<1;
58 return spi_flash_common_set_io_mode(chip,
59 spi_flash_common_write_status_8b_wrsr2,
60 spi_flash_common_read_status_8b_rdsr2,
61 qe);
62 }
63 }
64
spi_flash_chip_gd_get_io_mode(esp_flash_t * chip,esp_flash_io_mode_t * out_io_mode)65 esp_err_t spi_flash_chip_gd_get_io_mode(esp_flash_t *chip, esp_flash_io_mode_t* out_io_mode)
66 {
67 /* GD uses bit 1 of SR2 as Quad Enable */
68 const uint8_t BIT_QE = 1 << 1;
69 uint32_t sr;
70 esp_err_t ret = spi_flash_common_read_status_8b_rdsr2(chip, &sr);
71 if (ret == ESP_OK) {
72 *out_io_mode = ((sr & BIT_QE)? SPI_FLASH_QOUT: 0);
73 }
74 return ret;
75 }
76 #endif //CONFIG_SPI_FLASH_ROM_IMPL
77
78 static const char chip_name[] = "gd";
79
80 // The issi chip can use the functions for generic chips except from set read mode and probe,
81 // So we only replace these two functions.
82 const spi_flash_chip_t esp_flash_chip_gd = {
83 .name = chip_name,
84 .timeout = &spi_flash_chip_generic_timeout,
85 .probe = spi_flash_chip_gd_probe,
86 .reset = spi_flash_chip_generic_reset,
87 .detect_size = spi_flash_chip_generic_detect_size,
88 .erase_chip = spi_flash_chip_generic_erase_chip,
89 .erase_sector = spi_flash_chip_generic_erase_sector,
90 .erase_block = spi_flash_chip_generic_erase_block,
91 .sector_size = 4 * 1024,
92 .block_erase_size = 64 * 1024,
93
94 .get_chip_write_protect = spi_flash_chip_generic_get_write_protect,
95 .set_chip_write_protect = spi_flash_chip_generic_set_write_protect,
96
97 .num_protectable_regions = 0,
98 .protectable_regions = NULL,
99 .get_protected_regions = NULL,
100 .set_protected_regions = NULL,
101
102 .read = spi_flash_chip_generic_read,
103 .write = spi_flash_chip_generic_write,
104 .program_page = spi_flash_chip_generic_page_program,
105 .page_size = 256,
106 .write_encrypted = spi_flash_chip_generic_write_encrypted,
107
108 .wait_idle = spi_flash_chip_generic_wait_idle,
109 .set_io_mode = spi_flash_chip_gd_set_io_mode,
110 .get_io_mode = spi_flash_chip_gd_get_io_mode,
111
112 .read_reg = spi_flash_chip_generic_read_reg,
113 .yield = spi_flash_chip_generic_yield,
114 .sus_setup = spi_flash_chip_generic_suspend_cmd_conf,
115 };
116
