1 // Copyright 2019 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #include <string.h>
15 #include <stdlib.h>
16 #include <sys/cdefs.h>
17 #include "esp_log.h"
18 #include "esp_check.h"
19 #include "esp_eth.h"
20 #include "eth_phy_regs_struct.h"
21 #include "freertos/FreeRTOS.h"
22 #include "freertos/task.h"
23 #include "driver/gpio.h"
24 #include "esp_rom_gpio.h"
25 #include "esp_rom_sys.h"
26
27 static const char *TAG = "ip101";
28
29 /***************Vendor Specific Register***************/
30
31 /**
32 * @brief PCR(Page Control Register)
33 *
34 */
35 typedef union {
36 struct {
37 uint32_t register_page_select : 5; /* Select register page, default is 16 */
38 uint32_t reserved : 11; /* Reserved */
39 };
40 uint32_t val;
41 } pcr_reg_t;
42 #define ETH_PHY_PCR_REG_ADDR (0x14)
43
44 /**
45 * @brief ISR(Interrupt Status Register), Page 16
46 *
47 */
48 typedef union {
49 struct {
50 uint32_t link_changed : 1; /* Flag to indicate link status change interrupt */
51 uint32_t duplex_changed : 1; /* Flag to indicate duplex change interrupt */
52 uint32_t speed_changed : 1; /* Flag to indicate speed change interrupt */
53 uint32_t intr_status : 1; /* Flag to indicate interrupt status */
54 uint32_t reserved1 : 4; /* Reserved */
55 uint32_t link_mask : 1; /* Mask link change interrupt */
56 uint32_t duplex_mask : 1; /* Mask duplex change interrupt */
57 uint32_t speed_mask : 1; /* Mask speed change interrupt */
58 uint32_t all_mask : 1; /* Mask all interrupt */
59 uint32_t reserved2 : 3; /* Reserved */
60 uint32_t use_intr_pin : 1; /* Set high to use INTR and INTR_32 as an interrupt pin */
61 };
62 uint32_t val;
63 } isr_reg_t;
64 #define ETH_PHY_ISR_REG_ADDR (0x11)
65
66 /**
67 * @brief PHY MDI/MDIX Control and Specific Status Register, Page 16
68 *
69 */
70 typedef union {
71 struct {
72 uint32_t op_mode : 3; /* Operation Mode Idicator */
73 uint32_t force_mdix : 1; /* Force the MDIX channel to be selected */
74 uint32_t reserved1 : 4; /* Reserved */
75 uint32_t link_up : 1; /* Indicate the link status is OK or FAIL */
76 uint32_t reserved2 : 7; /* Reserved */
77 };
78 uint32_t val;
79 } cssr_reg_t;
80 #define ETH_PHY_CSSR_REG_ADDR (0x1E)
81
82 /**
83 * @brief PSCR(PHY Specific Control Register), Page 1
84 *
85 */
86 typedef union {
87 struct {
88 uint32_t reserved1 : 7; /* Reserved */
89 uint32_t force_link_100 : 1; /* Force Link 100 */
90 uint32_t force_link_10 : 1; /* Force Link 10 */
91 uint32_t reserved2 : 7; /* Reserved */
92 };
93 uint32_t val;
94 } pscr_reg_t;
95 #define ETH_PHY_PSCR_REG_ADDR (0x11)
96
97 typedef struct {
98 esp_eth_phy_t parent;
99 esp_eth_mediator_t *eth;
100 int addr;
101 uint32_t reset_timeout_ms;
102 uint32_t autonego_timeout_ms;
103 eth_link_t link_status;
104 int reset_gpio_num;
105 } phy_ip101_t;
106
ip101_page_select(phy_ip101_t * ip101,uint32_t page)107 static esp_err_t ip101_page_select(phy_ip101_t *ip101, uint32_t page)
108 {
109 esp_err_t ret = ESP_OK;
110 esp_eth_mediator_t *eth = ip101->eth;
111 pcr_reg_t pcr = {
112 .register_page_select = page
113 };
114 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, ip101->addr, ETH_PHY_PCR_REG_ADDR, pcr.val), err, TAG, "write PCR failed");
115 return ESP_OK;
116 err:
117 return ret;
118 }
119
ip101_update_link_duplex_speed(phy_ip101_t * ip101)120 static esp_err_t ip101_update_link_duplex_speed(phy_ip101_t *ip101)
121 {
122 esp_err_t ret = ESP_OK;
123 esp_eth_mediator_t *eth = ip101->eth;
124 eth_speed_t speed = ETH_SPEED_10M;
125 eth_duplex_t duplex = ETH_DUPLEX_HALF;
126 uint32_t peer_pause_ability = false;
127 cssr_reg_t cssr;
128 anlpar_reg_t anlpar;
129 ESP_GOTO_ON_ERROR(ip101_page_select(ip101, 16), err, TAG, "select page 16 failed");
130 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_CSSR_REG_ADDR, &(cssr.val)), err, TAG, "read CSSR failed");
131 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_ANLPAR_REG_ADDR, &(anlpar.val)), err, TAG, "read ANLPAR failed");
132 eth_link_t link = cssr.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
133 /* check if link status changed */
134 if (ip101->link_status != link) {
135 /* when link up, read negotiation result */
136 if (link == ETH_LINK_UP) {
137 switch (cssr.op_mode) {
138 case 1: //10M Half
139 speed = ETH_SPEED_10M;
140 duplex = ETH_DUPLEX_HALF;
141 break;
142 case 2: //100M Half
143 speed = ETH_SPEED_100M;
144 duplex = ETH_DUPLEX_HALF;
145 break;
146 case 5: //10M Full
147 speed = ETH_SPEED_10M;
148 duplex = ETH_DUPLEX_FULL;
149 break;
150 case 6: //100M Full
151 speed = ETH_SPEED_100M;
152 duplex = ETH_DUPLEX_FULL;
153 break;
154 default:
155 break;
156 }
157 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_SPEED, (void *)speed), err, TAG, "change speed failed");
158 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_DUPLEX, (void *)duplex), err, TAG, "change duplex failed");
159 /* if we're in duplex mode, and peer has the flow control ability */
160 if (duplex == ETH_DUPLEX_FULL && anlpar.symmetric_pause) {
161 peer_pause_ability = 1;
162 } else {
163 peer_pause_ability = 0;
164 }
165 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_PAUSE, (void *)peer_pause_ability), err, TAG, "change pause ability failed");
166 }
167 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LINK, (void *)link), err, TAG, "chagne link failed");
168 ip101->link_status = link;
169 }
170 return ESP_OK;
171 err:
172 return ret;
173 }
174
ip101_set_mediator(esp_eth_phy_t * phy,esp_eth_mediator_t * eth)175 static esp_err_t ip101_set_mediator(esp_eth_phy_t *phy, esp_eth_mediator_t *eth)
176 {
177 esp_err_t ret = ESP_OK;
178 ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mediator to null");
179 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
180 ip101->eth = eth;
181 return ESP_OK;
182 err:
183 return ret;
184 }
185
ip101_get_link(esp_eth_phy_t * phy)186 static esp_err_t ip101_get_link(esp_eth_phy_t *phy)
187 {
188 esp_err_t ret = ESP_OK;
189 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
190 /* Updata information about link, speed, duplex */
191 ESP_GOTO_ON_ERROR(ip101_update_link_duplex_speed(ip101), err, TAG, "update link duplex speed failed");
192 return ESP_OK;
193 err:
194 return ret;
195 }
196
ip101_reset(esp_eth_phy_t * phy)197 static esp_err_t ip101_reset(esp_eth_phy_t *phy)
198 {
199 esp_err_t ret = ESP_OK;
200 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
201 ip101->link_status = ETH_LINK_DOWN;
202 esp_eth_mediator_t *eth = ip101->eth;
203 bmcr_reg_t bmcr = {.reset = 1};
204 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
205 /* wait for reset complete */
206 uint32_t to = 0;
207 for (to = 0; to < ip101->reset_timeout_ms / 10; to++) {
208 vTaskDelay(pdMS_TO_TICKS(10));
209 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
210 if (!bmcr.reset) {
211 break;
212 }
213 }
214 ESP_GOTO_ON_FALSE(to < ip101->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "reset timeout");
215 return ESP_OK;
216 err:
217 return ret;
218 }
219
ip101_reset_hw(esp_eth_phy_t * phy)220 static esp_err_t ip101_reset_hw(esp_eth_phy_t *phy)
221 {
222 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
223 if (ip101->reset_gpio_num >= 0) {
224 esp_rom_gpio_pad_select_gpio(ip101->reset_gpio_num);
225 gpio_set_direction(ip101->reset_gpio_num, GPIO_MODE_OUTPUT);
226 gpio_set_level(ip101->reset_gpio_num, 0);
227 esp_rom_delay_us(100); // insert min input assert time
228 gpio_set_level(ip101->reset_gpio_num, 1);
229 }
230 return ESP_OK;
231 }
232
233 /**
234 * @note This function is responsible for restarting a new auto-negotiation,
235 * the result of negotiation won't be relected to uppler layers.
236 * Instead, the negotiation result is fetched by linker timer, see `ip101_get_link()`
237 */
ip101_negotiate(esp_eth_phy_t * phy)238 static esp_err_t ip101_negotiate(esp_eth_phy_t *phy)
239 {
240 esp_err_t ret = ESP_OK;
241 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
242 esp_eth_mediator_t *eth = ip101->eth;
243 /* in case any link status has changed, let's assume we're in link down status */
244 ip101->link_status = ETH_LINK_DOWN;
245 /* Restart auto negotiation */
246 bmcr_reg_t bmcr = {
247 .speed_select = 1, /* 100Mbps */
248 .duplex_mode = 1, /* Full Duplex */
249 .en_auto_nego = 1, /* Auto Negotiation */
250 .restart_auto_nego = 1 /* Restart Auto Negotiation */
251 };
252 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
253 /* Wait for auto negotiation complete */
254 bmsr_reg_t bmsr;
255 uint32_t to = 0;
256 for (to = 0; to < ip101->autonego_timeout_ms / 100; to++) {
257 vTaskDelay(pdMS_TO_TICKS(100));
258 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_BMSR_REG_ADDR, &(bmsr.val)), err, TAG, "read BMSR failed");
259 if (bmsr.auto_nego_complete) {
260 break;
261 }
262 }
263 if ((to >= ip101->autonego_timeout_ms / 100) && (ip101->link_status == ETH_LINK_UP)) {
264 ESP_LOGW(TAG, "auto negotiation timeout");
265 }
266 return ESP_OK;
267 err:
268 return ret;
269 }
270
ip101_pwrctl(esp_eth_phy_t * phy,bool enable)271 static esp_err_t ip101_pwrctl(esp_eth_phy_t *phy, bool enable)
272 {
273 esp_err_t ret = ESP_OK;
274 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
275 esp_eth_mediator_t *eth = ip101->eth;
276 bmcr_reg_t bmcr;
277 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
278 if (!enable) {
279 /* Enable IEEE Power Down Mode */
280 bmcr.power_down = 1;
281 } else {
282 /* Disable IEEE Power Down Mode */
283 bmcr.power_down = 0;
284 }
285 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
286 if (!enable) {
287 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
288 ESP_GOTO_ON_FALSE(bmcr.power_down == 1, ESP_FAIL, err, TAG, "power down failed");
289 } else {
290 /* wait for power up complete */
291 uint32_t to = 0;
292 for (to = 0; to < ip101->reset_timeout_ms / 10; to++) {
293 vTaskDelay(pdMS_TO_TICKS(10));
294 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
295 if (bmcr.power_down == 0) {
296 break;
297 }
298 }
299 ESP_GOTO_ON_FALSE(to < ip101->reset_timeout_ms / 10, ESP_FAIL, err, TAG, "power up timeout");
300 }
301 return ESP_OK;
302 err:
303 return ret;
304 }
305
ip101_set_addr(esp_eth_phy_t * phy,uint32_t addr)306 static esp_err_t ip101_set_addr(esp_eth_phy_t *phy, uint32_t addr)
307 {
308 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
309 ip101->addr = addr;
310 return ESP_OK;
311 }
312
ip101_get_addr(esp_eth_phy_t * phy,uint32_t * addr)313 static esp_err_t ip101_get_addr(esp_eth_phy_t *phy, uint32_t *addr)
314 {
315 esp_err_t ret = ESP_OK;
316 ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "addr can't be null");
317 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
318 *addr = ip101->addr;
319 return ESP_OK;
320 err:
321 return ret;
322 }
323
ip101_del(esp_eth_phy_t * phy)324 static esp_err_t ip101_del(esp_eth_phy_t *phy)
325 {
326 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
327 free(ip101);
328 return ESP_OK;
329 }
330
ip101_advertise_pause_ability(esp_eth_phy_t * phy,uint32_t ability)331 static esp_err_t ip101_advertise_pause_ability(esp_eth_phy_t *phy, uint32_t ability)
332 {
333 esp_err_t ret = ESP_OK;
334 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
335 esp_eth_mediator_t *eth = ip101->eth;
336 /* Set PAUSE function ability */
337 anar_reg_t anar;
338 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_ANAR_REG_ADDR, &(anar.val)), err, TAG, "read ANAR failed");
339 if (ability) {
340 anar.asymmetric_pause = 1;
341 anar.symmetric_pause = 1;
342 } else {
343 anar.asymmetric_pause = 0;
344 anar.symmetric_pause = 0;
345 }
346 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, ip101->addr, ETH_PHY_ANAR_REG_ADDR, anar.val), err, TAG, "write ANAR failed");
347 return ESP_OK;
348 err:
349 return ret;
350 }
351
ip101_loopback(esp_eth_phy_t * phy,bool enable)352 static esp_err_t ip101_loopback(esp_eth_phy_t *phy, bool enable)
353 {
354 esp_err_t ret = ESP_OK;
355 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
356 esp_eth_mediator_t *eth = ip101->eth;
357 /* Set Loopback function */
358 bmcr_reg_t bmcr;
359 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, &(bmcr.val)), err, TAG, "read BMCR failed");
360 if (enable) {
361 bmcr.en_loopback = 1;
362 } else {
363 bmcr.en_loopback = 0;
364 }
365 ESP_GOTO_ON_ERROR(eth->phy_reg_write(eth, ip101->addr, ETH_PHY_BMCR_REG_ADDR, bmcr.val), err, TAG, "write BMCR failed");
366 return ESP_OK;
367 err:
368 return ret;
369 }
370
ip101_init(esp_eth_phy_t * phy)371 static esp_err_t ip101_init(esp_eth_phy_t *phy)
372 {
373 esp_err_t ret = ESP_OK;
374 phy_ip101_t *ip101 = __containerof(phy, phy_ip101_t, parent);
375 esp_eth_mediator_t *eth = ip101->eth;
376 // Detect PHY address
377 if (ip101->addr == ESP_ETH_PHY_ADDR_AUTO) {
378 ESP_GOTO_ON_ERROR(esp_eth_detect_phy_addr(eth, &ip101->addr), err, TAG, "Detect PHY address failed");
379 }
380 /* Power on Ethernet PHY */
381 ESP_GOTO_ON_ERROR(ip101_pwrctl(phy, true), err, TAG, "power control failed");
382 /* Reset Ethernet PHY */
383 ESP_GOTO_ON_ERROR(ip101_reset(phy), err, TAG, "reset failed");
384 /* Check PHY ID */
385 phyidr1_reg_t id1;
386 phyidr2_reg_t id2;
387 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_IDR1_REG_ADDR, &(id1.val)), err, TAG, "read ID1 failed");
388 ESP_GOTO_ON_ERROR(eth->phy_reg_read(eth, ip101->addr, ETH_PHY_IDR2_REG_ADDR, &(id2.val)), err, TAG, "read ID2 failed");
389 ESP_GOTO_ON_FALSE(id1.oui_msb == 0x243 && id2.oui_lsb == 0x3 && id2.vendor_model == 0x5, ESP_FAIL, err, TAG, "wrong chip ID");
390 return ESP_OK;
391 err:
392 return ret;
393 }
394
ip101_deinit(esp_eth_phy_t * phy)395 static esp_err_t ip101_deinit(esp_eth_phy_t *phy)
396 {
397 esp_err_t ret = ESP_OK;
398 /* Power off Ethernet PHY */
399 ESP_GOTO_ON_ERROR(ip101_pwrctl(phy, false), err, TAG, "power control failed");
400 return ESP_OK;
401 err:
402 return ret;
403 }
404
esp_eth_phy_new_ip101(const eth_phy_config_t * config)405 esp_eth_phy_t *esp_eth_phy_new_ip101(const eth_phy_config_t *config)
406 {
407 esp_eth_phy_t *ret = NULL;
408 ESP_GOTO_ON_FALSE(config, NULL, err, TAG, "can't set phy config to null");
409 phy_ip101_t *ip101 = calloc(1, sizeof(phy_ip101_t));
410 ESP_GOTO_ON_FALSE(ip101, NULL, err, TAG, "calloc ip101 failed");
411 ip101->addr = config->phy_addr;
412 ip101->reset_timeout_ms = config->reset_timeout_ms;
413 ip101->reset_gpio_num = config->reset_gpio_num;
414 ip101->link_status = ETH_LINK_DOWN;
415 ip101->autonego_timeout_ms = config->autonego_timeout_ms;
416 ip101->parent.reset = ip101_reset;
417 ip101->parent.reset_hw = ip101_reset_hw;
418 ip101->parent.init = ip101_init;
419 ip101->parent.deinit = ip101_deinit;
420 ip101->parent.set_mediator = ip101_set_mediator;
421 ip101->parent.negotiate = ip101_negotiate;
422 ip101->parent.get_link = ip101_get_link;
423 ip101->parent.pwrctl = ip101_pwrctl;
424 ip101->parent.get_addr = ip101_get_addr;
425 ip101->parent.set_addr = ip101_set_addr;
426 ip101->parent.advertise_pause_ability = ip101_advertise_pause_ability;
427 ip101->parent.loopback = ip101_loopback;
428 ip101->parent.del = ip101_del;
429
430 return &(ip101->parent);
431 err:
432 return ret;
433 }
434
