1 /*
2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <string.h>
8 #include <stdlib.h>
9 #include <sys/cdefs.h>
10 #include "driver/gpio.h"
11 #include "driver/spi_master.h"
12 #include "esp_attr.h"
13 #include "esp_log.h"
14 #include "esp_check.h"
15 #include "esp_eth.h"
16 #include "esp_timer.h"
17 #include "esp_system.h"
18 #include "esp_intr_alloc.h"
19 #include "esp_heap_caps.h"
20 #include "freertos/FreeRTOS.h"
21 #include "freertos/task.h"
22 #include "freertos/semphr.h"
23 #include "hal/cpu_hal.h"
24 #include "dm9051.h"
25 #include "sdkconfig.h"
26 #include "esp_rom_gpio.h"
27 #include "esp_rom_sys.h"
28
29 static const char *TAG = "dm9051.mac";
30
31 #define DM9051_SPI_LOCK_TIMEOUT_MS (50)
32 #define DM9051_PHY_OPERATION_TIMEOUT_US (1000)
33
34 typedef struct {
35 uint8_t flag;
36 uint8_t status;
37 uint8_t length_low;
38 uint8_t length_high;
39 } dm9051_rx_header_t;
40
41 typedef struct {
42 esp_eth_mac_t parent;
43 esp_eth_mediator_t *eth;
44 spi_device_handle_t spi_hdl;
45 SemaphoreHandle_t spi_lock;
46 TaskHandle_t rx_task_hdl;
47 uint32_t sw_reset_timeout_ms;
48 int int_gpio_num;
49 uint8_t addr[6];
50 bool packets_remain;
51 bool flow_ctrl_enabled;
52 } emac_dm9051_t;
53
dm9051_lock(emac_dm9051_t * emac)54 static inline bool dm9051_lock(emac_dm9051_t *emac)
55 {
56 return xSemaphoreTake(emac->spi_lock, pdMS_TO_TICKS(DM9051_SPI_LOCK_TIMEOUT_MS)) == pdTRUE;
57 }
58
dm9051_unlock(emac_dm9051_t * emac)59 static inline bool dm9051_unlock(emac_dm9051_t *emac)
60 {
61 return xSemaphoreGive(emac->spi_lock) == pdTRUE;
62 }
63
64 /**
65 * @brief write value to dm9051 internal register
66 */
dm9051_register_write(emac_dm9051_t * emac,uint8_t reg_addr,uint8_t value)67 static esp_err_t dm9051_register_write(emac_dm9051_t *emac, uint8_t reg_addr, uint8_t value)
68 {
69 esp_err_t ret = ESP_OK;
70 spi_transaction_t trans = {
71 .cmd = DM9051_SPI_WR,
72 .addr = reg_addr,
73 .length = 8,
74 .flags = SPI_TRANS_USE_TXDATA
75 };
76 trans.tx_data[0] = value;
77 if (dm9051_lock(emac)) {
78 if (spi_device_polling_transmit(emac->spi_hdl, &trans) != ESP_OK) {
79 ESP_LOGE(TAG, "%s(%d): spi transmit failed", __FUNCTION__, __LINE__);
80 ret = ESP_FAIL;
81 }
82 dm9051_unlock(emac);
83 } else {
84 ret = ESP_ERR_TIMEOUT;
85 }
86 return ret;
87 }
88
89 /**
90 * @brief read value from dm9051 internal register
91 */
dm9051_register_read(emac_dm9051_t * emac,uint8_t reg_addr,uint8_t * value)92 static esp_err_t dm9051_register_read(emac_dm9051_t *emac, uint8_t reg_addr, uint8_t *value)
93 {
94 esp_err_t ret = ESP_OK;
95 spi_transaction_t trans = {
96 .cmd = DM9051_SPI_RD,
97 .addr = reg_addr,
98 .length = 8,
99 .flags = SPI_TRANS_USE_TXDATA | SPI_TRANS_USE_RXDATA
100 };
101 if (dm9051_lock(emac)) {
102 if (spi_device_polling_transmit(emac->spi_hdl, &trans) != ESP_OK) {
103 ESP_LOGE(TAG, "%s(%d): spi transmit failed", __FUNCTION__, __LINE__);
104 ret = ESP_FAIL;
105 } else {
106 *value = trans.rx_data[0];
107 }
108 dm9051_unlock(emac);
109 } else {
110 ret = ESP_ERR_TIMEOUT;
111 }
112 return ret;
113 }
114
115 /**
116 * @brief write buffer to dm9051 internal memory
117 */
dm9051_memory_write(emac_dm9051_t * emac,uint8_t * buffer,uint32_t len)118 static esp_err_t dm9051_memory_write(emac_dm9051_t *emac, uint8_t *buffer, uint32_t len)
119 {
120 esp_err_t ret = ESP_OK;
121 spi_transaction_t trans = {
122 .cmd = DM9051_SPI_WR,
123 .addr = DM9051_MWCMD,
124 .length = len * 8,
125 .tx_buffer = buffer
126 };
127 if (dm9051_lock(emac)) {
128 if (spi_device_polling_transmit(emac->spi_hdl, &trans) != ESP_OK) {
129 ESP_LOGE(TAG, "%s(%d): spi transmit failed", __FUNCTION__, __LINE__);
130 ret = ESP_FAIL;
131 }
132 dm9051_unlock(emac);
133 } else {
134 ret = ESP_ERR_TIMEOUT;
135 }
136 return ret;
137 }
138
139 /**
140 * @brief read buffer from dm9051 internal memory
141 */
dm9051_memory_read(emac_dm9051_t * emac,uint8_t * buffer,uint32_t len)142 static esp_err_t dm9051_memory_read(emac_dm9051_t *emac, uint8_t *buffer, uint32_t len)
143 {
144 esp_err_t ret = ESP_OK;
145 spi_transaction_t trans = {
146 .cmd = DM9051_SPI_RD,
147 .addr = DM9051_MRCMD,
148 .length = len * 8,
149 .rx_buffer = buffer
150 };
151 if (dm9051_lock(emac)) {
152 if (spi_device_polling_transmit(emac->spi_hdl, &trans) != ESP_OK) {
153 ESP_LOGE(TAG, "%s(%d): spi transmit failed", __FUNCTION__, __LINE__);
154 ret = ESP_FAIL;
155 }
156 dm9051_unlock(emac);
157 } else {
158 ret = ESP_ERR_TIMEOUT;
159 }
160 return ret;
161 }
162
163 /**
164 * @brief peek buffer from dm9051 internal memory (without internal cursor moved)
165 */
dm9051_memory_peek(emac_dm9051_t * emac,uint8_t * buffer,uint32_t len)166 static esp_err_t dm9051_memory_peek(emac_dm9051_t *emac, uint8_t *buffer, uint32_t len)
167 {
168 esp_err_t ret = ESP_OK;
169 spi_transaction_t trans = {
170 .cmd = DM9051_SPI_RD,
171 .addr = DM9051_MRCMDX1,
172 .length = len * 8,
173 .rx_buffer = buffer
174 };
175 if (dm9051_lock(emac)) {
176 if (spi_device_polling_transmit(emac->spi_hdl, &trans) != ESP_OK) {
177 ESP_LOGE(TAG, "%s(%d): spi transmit failed", __FUNCTION__, __LINE__);
178 ret = ESP_FAIL;
179 }
180 dm9051_unlock(emac);
181 } else {
182 ret = ESP_ERR_TIMEOUT;
183 }
184 return ret;
185 }
186
187 /**
188 * @brief read mac address from internal registers
189 */
dm9051_get_mac_addr(emac_dm9051_t * emac)190 static esp_err_t dm9051_get_mac_addr(emac_dm9051_t *emac)
191 {
192 esp_err_t ret = ESP_OK;
193 for (int i = 0; i < 6; i++) {
194 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_PAR + i, &emac->addr[i]), err, TAG, "read PAR failed");
195 }
196 return ESP_OK;
197 err:
198 return ret;
199 }
200
201 /**
202 * @brief set new mac address to internal registers
203 */
dm9051_set_mac_addr(emac_dm9051_t * emac)204 static esp_err_t dm9051_set_mac_addr(emac_dm9051_t *emac)
205 {
206 esp_err_t ret = ESP_OK;
207 for (int i = 0; i < 6; i++) {
208 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_PAR + i, emac->addr[i]), err, TAG, "write PAR failed");
209 }
210 return ESP_OK;
211 err:
212 return ret;
213 }
214
215 /**
216 * @brief clear multicast hash table
217 */
dm9051_clear_multicast_table(emac_dm9051_t * emac)218 static esp_err_t dm9051_clear_multicast_table(emac_dm9051_t *emac)
219 {
220 esp_err_t ret = ESP_OK;
221 /* rx broadcast packet control by bit7 of MAC register 1DH */
222 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_BCASTCR, 0x00), err, TAG, "write BCASTCR failed");
223 for (int i = 0; i < 7; i++) {
224 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_MAR + i, 0x00), err, TAG, "write MAR failed");
225 }
226 /* enable receive broadcast paclets */
227 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_MAR + 7, 0x80), err, TAG, "write MAR failed");
228 return ESP_OK;
229 err:
230 return ret;
231 }
232
233 /**
234 * @brief software reset dm9051 internal register
235 */
dm9051_reset(emac_dm9051_t * emac)236 static esp_err_t dm9051_reset(emac_dm9051_t *emac)
237 {
238 esp_err_t ret = ESP_OK;
239 /* power on phy */
240 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_GPR, 0x00), err, TAG, "write GPR failed");
241 /* mac and phy register won't be accesable within at least 1ms */
242 vTaskDelay(pdMS_TO_TICKS(10));
243 /* software reset */
244 uint8_t ncr = NCR_RST;
245 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_NCR, ncr), err, TAG, "write NCR failed");
246 uint32_t to = 0;
247 for (to = 0; to < emac->sw_reset_timeout_ms / 10; to++) {
248 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_NCR, &ncr), err, TAG, "read NCR failed");
249 if (!(ncr & NCR_RST)) {
250 break;
251 }
252 vTaskDelay(pdMS_TO_TICKS(10));
253 }
254 ESP_GOTO_ON_FALSE(to < emac->sw_reset_timeout_ms / 10, ESP_ERR_TIMEOUT, err, TAG, "reset timeout");
255 return ESP_OK;
256 err:
257 return ret;
258 }
259
260 /**
261 * @brief verify dm9051 chip ID
262 */
dm9051_verify_id(emac_dm9051_t * emac)263 static esp_err_t dm9051_verify_id(emac_dm9051_t *emac)
264 {
265 esp_err_t ret = ESP_OK;
266 uint8_t id[2];
267 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_VIDL, &id[0]), err, TAG, "read VIDL failed");
268 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_VIDH, &id[1]), err, TAG, "read VIDH failed");
269 ESP_GOTO_ON_FALSE(0x0A == id[1] && 0x46 == id[0], ESP_ERR_INVALID_VERSION, err, TAG, "wrong Vendor ID");
270 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_PIDL, &id[0]), err, TAG, "read PIDL failed");
271 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_PIDH, &id[1]), err, TAG, "read PIDH failed");
272 ESP_GOTO_ON_FALSE(0x90 == id[1] && 0x51 == id[0], ESP_ERR_INVALID_VERSION, err, TAG, "wrong Product ID");
273 return ESP_OK;
274 err:
275 return ret;
276 }
277
278 /**
279 * @brief default setup for dm9051 internal registers
280 */
dm9051_setup_default(emac_dm9051_t * emac)281 static esp_err_t dm9051_setup_default(emac_dm9051_t *emac)
282 {
283 esp_err_t ret = ESP_OK;
284 /* disable wakeup */
285 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_NCR, 0x00), err, TAG, "write NCR failed");
286 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_WCR, 0x00), err, TAG, "write WCR failed");
287 /* stop transmitting, enable appending pad, crc for packets */
288 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TCR, 0x00), err, TAG, "write TCR failed");
289 /* stop receiving, no promiscuous mode, no runt packet(size < 64bytes), not all multicast packets*/
290 /* discard long packet(size > 1522bytes) and crc error packet, enable watchdog */
291 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RCR, RCR_DIS_LONG | RCR_DIS_CRC), err, TAG, "write RCR failed");
292 /* retry late collision packet, at most two transmit command can be issued before transmit complete */
293 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TCR2, TCR2_RLCP), err, TAG, "write TCR2 failed");
294 /* enable auto transmit */
295 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_ATCR, ATCR_AUTO_TX), err, TAG, "write ATCR failed");
296 /* generate checksum for UDP, TCP and IPv4 packets */
297 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TCSCR, TCSCR_IPCSE | TCSCR_TCPCSE | TCSCR_UDPCSE), err, TAG, "write TCSCR failed");
298 /* disable check sum for receive packets */
299 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RCSCSR, 0x00), err, TAG, "write RCSCSR failed");
300 /* interrupt pin config: push-pull output, active high */
301 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_INTCR, 0x00), err, TAG, "write INTCR failed");
302 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_INTCKCR, 0x00), err, TAG, "write INTCKCR failed");
303 /* no length limitation for rx packets */
304 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RLENCR, 0x00), err, TAG, "write RLENCR failed");
305 /* 3K-byte for TX and 13K-byte for RX */
306 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_MEMSCR, 0x00), err, TAG, "write MEMSCR failed");
307 /* reset tx and rx memory pointer */
308 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_MPTRCR, MPTRCR_RST_RX | MPTRCR_RST_TX), err, TAG, "write MPTRCR failed");
309 /* clear network status: wakeup event, tx complete */
310 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END), err, TAG, "write NSR failed");
311 /* clear interrupt status */
312 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_ISR, ISR_CLR_STATUS), err, TAG, "write ISR failed");
313 return ESP_OK;
314 err:
315 return ret;
316 }
317
dm9051_enable_flow_ctrl(emac_dm9051_t * emac,bool enable)318 static esp_err_t dm9051_enable_flow_ctrl(emac_dm9051_t *emac, bool enable)
319 {
320 esp_err_t ret = ESP_OK;
321 if (enable) {
322 /* send jam pattern (duration time = 1.15ms) when rx free space < 3k bytes */
323 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_BPTR, 0x3F), err, TAG, "write BPTR failed");
324 /* flow control: high water threshold = 3k bytes, low water threshold = 8k bytes */
325 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_FCTR, 0x38), err, TAG, "write FCTR failed");
326 /* enable flow control */
327 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_FCR, FCR_FLOW_ENABLE), err, TAG, "write FCR failed");
328 } else {
329 /* disable flow control */
330 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_FCR, 0), err, TAG, "write FCR failed");
331 }
332 return ESP_OK;
333 err:
334 return ret;
335 }
336
337 /**
338 * @brief start dm9051: enable interrupt and start receive
339 */
emac_dm9051_start(esp_eth_mac_t * mac)340 static esp_err_t emac_dm9051_start(esp_eth_mac_t *mac)
341 {
342 esp_err_t ret = ESP_OK;
343 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
344 /* enable only Rx related interrupts as others are processed synchronously */
345 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_IMR, IMR_PAR | IMR_PRI), err, TAG, "write IMR failed");
346 /* enable rx */
347 uint8_t rcr = 0;
348 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_RCR, &rcr), err, TAG, "read RCR failed");
349 rcr |= RCR_RXEN;
350 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RCR, rcr), err, TAG, "write RCR failed");
351 return ESP_OK;
352 err:
353 return ret;
354 }
355
356 /**
357 * @brief stop dm9051: disable interrupt and stop receive
358 */
emac_dm9051_stop(esp_eth_mac_t * mac)359 static esp_err_t emac_dm9051_stop(esp_eth_mac_t *mac)
360 {
361 esp_err_t ret = ESP_OK;
362 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
363 /* disable interrupt */
364 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_IMR, 0x00), err, TAG, "write IMR failed");
365 /* disable rx */
366 uint8_t rcr = 0;
367 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_RCR, &rcr), err, TAG, "read RCR failed");
368 rcr &= ~RCR_RXEN;
369 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RCR, rcr), err, TAG, "write RCR failed");
370 return ESP_OK;
371 err:
372 return ret;
373 }
374
dm9051_isr_handler(void * arg)375 IRAM_ATTR static void dm9051_isr_handler(void *arg)
376 {
377 emac_dm9051_t *emac = (emac_dm9051_t *)arg;
378 BaseType_t high_task_wakeup = pdFALSE;
379 /* notify dm9051 task */
380 vTaskNotifyGiveFromISR(emac->rx_task_hdl, &high_task_wakeup);
381 if (high_task_wakeup != pdFALSE) {
382 portYIELD_FROM_ISR();
383 }
384 }
385
emac_dm9051_task(void * arg)386 static void emac_dm9051_task(void *arg)
387 {
388 emac_dm9051_t *emac = (emac_dm9051_t *)arg;
389 uint8_t status = 0;
390 uint8_t *buffer = NULL;
391 uint32_t length = 0;
392 while (1) {
393 // check if the task receives any notification
394 if (ulTaskNotifyTake(pdTRUE, pdMS_TO_TICKS(1000)) == 0 && // if no notification ...
395 gpio_get_level(emac->int_gpio_num) == 0) { // ...and no interrupt asserted
396 continue; // -> just continue to check again
397 }
398 /* clear interrupt status */
399 dm9051_register_read(emac, DM9051_ISR, &status);
400 dm9051_register_write(emac, DM9051_ISR, status);
401 /* packet received */
402 if (status & ISR_PR) {
403 do {
404 length = ETH_MAX_PACKET_SIZE;
405 buffer = heap_caps_malloc(length, MALLOC_CAP_DMA);
406 if (!buffer) {
407 ESP_LOGE(TAG, "no mem for receive buffer");
408 } else if (emac->parent.receive(&emac->parent, buffer, &length) == ESP_OK) {
409 /* pass the buffer to stack (e.g. TCP/IP layer) */
410 if (length) {
411 emac->eth->stack_input(emac->eth, buffer, length);
412 } else {
413 free(buffer);
414 }
415 } else {
416 free(buffer);
417 }
418 } while (emac->packets_remain);
419 }
420 }
421 vTaskDelete(NULL);
422 }
423
emac_dm9051_set_mediator(esp_eth_mac_t * mac,esp_eth_mediator_t * eth)424 static esp_err_t emac_dm9051_set_mediator(esp_eth_mac_t *mac, esp_eth_mediator_t *eth)
425 {
426 esp_err_t ret = ESP_OK;
427 ESP_GOTO_ON_FALSE(eth, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac's mediator to null");
428 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
429 emac->eth = eth;
430 return ESP_OK;
431 err:
432 return ret;
433 }
434
emac_dm9051_write_phy_reg(esp_eth_mac_t * mac,uint32_t phy_addr,uint32_t phy_reg,uint32_t reg_value)435 static esp_err_t emac_dm9051_write_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t reg_value)
436 {
437 esp_err_t ret = ESP_OK;
438 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
439 /* check if phy access is in progress */
440 uint8_t epcr = 0;
441 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_EPCR, &epcr), err, TAG, "read EPCR failed");
442 ESP_GOTO_ON_FALSE(!(epcr & EPCR_ERRE), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
443 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_EPAR, (uint8_t)(((phy_addr << 6) & 0xFF) | phy_reg)), err, TAG, "write EPAR failed");
444 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_EPDRL, (uint8_t)(reg_value & 0xFF)), err, TAG, "write EPDRL failed");
445 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_EPDRH, (uint8_t)((reg_value >> 8) & 0xFF)), err, TAG, "write EPDRH failed");
446 /* select PHY and select write operation */
447 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_EPCR, EPCR_EPOS | EPCR_ERPRW), err, TAG, "write EPCR failed");
448 /* polling the busy flag */
449 uint32_t to = 0;
450 do {
451 esp_rom_delay_us(100);
452 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_EPCR, &epcr), err, TAG, "read EPCR failed");
453 to += 100;
454 } while ((epcr & EPCR_ERRE) && to < DM9051_PHY_OPERATION_TIMEOUT_US);
455 ESP_GOTO_ON_FALSE(!(epcr & EPCR_ERRE), ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
456 return ESP_OK;
457 err:
458 return ret;
459 }
460
emac_dm9051_read_phy_reg(esp_eth_mac_t * mac,uint32_t phy_addr,uint32_t phy_reg,uint32_t * reg_value)461 static esp_err_t emac_dm9051_read_phy_reg(esp_eth_mac_t *mac, uint32_t phy_addr, uint32_t phy_reg, uint32_t *reg_value)
462 {
463 esp_err_t ret = ESP_OK;
464 ESP_GOTO_ON_FALSE(reg_value, ESP_ERR_INVALID_ARG, err, TAG, "can't set reg_value to null");
465 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
466 /* check if phy access is in progress */
467 uint8_t epcr = 0;
468 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_EPCR, &epcr), err, TAG, "read EPCR failed");
469 ESP_GOTO_ON_FALSE(!(epcr & 0x01), ESP_ERR_INVALID_STATE, err, TAG, "phy is busy");
470 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_EPAR, (uint8_t)(((phy_addr << 6) & 0xFF) | phy_reg)), err, TAG, "write EPAR failed");
471 /* Select PHY and select read operation */
472 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_EPCR, 0x0C), err, TAG, "write EPCR failed");
473 /* polling the busy flag */
474 uint32_t to = 0;
475 do {
476 esp_rom_delay_us(100);
477 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_EPCR, &epcr), err, TAG, "read EPCR failed");
478 to += 100;
479 } while ((epcr & EPCR_ERRE) && to < DM9051_PHY_OPERATION_TIMEOUT_US);
480 ESP_GOTO_ON_FALSE(!(epcr & EPCR_ERRE), ESP_ERR_TIMEOUT, err, TAG, "phy is busy");
481 uint8_t value_h = 0;
482 uint8_t value_l = 0;
483 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_EPDRH, &value_h), err, TAG, "read EPDRH failed");
484 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_EPDRL, &value_l), err, TAG, "read EPDRL failed");
485 *reg_value = (value_h << 8) | value_l;
486 return ESP_OK;
487 err:
488 return ret;
489 }
490
emac_dm9051_set_addr(esp_eth_mac_t * mac,uint8_t * addr)491 static esp_err_t emac_dm9051_set_addr(esp_eth_mac_t *mac, uint8_t *addr)
492 {
493 esp_err_t ret = ESP_OK;
494 ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null");
495 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
496 memcpy(emac->addr, addr, 6);
497 ESP_GOTO_ON_ERROR(dm9051_set_mac_addr(emac), err, TAG, "set mac address failed");
498 return ESP_OK;
499 err:
500 return ret;
501 }
502
emac_dm9051_get_addr(esp_eth_mac_t * mac,uint8_t * addr)503 static esp_err_t emac_dm9051_get_addr(esp_eth_mac_t *mac, uint8_t *addr)
504 {
505 esp_err_t ret = ESP_OK;
506 ESP_GOTO_ON_FALSE(addr, ESP_ERR_INVALID_ARG, err, TAG, "can't set mac addr to null");
507 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
508 memcpy(addr, emac->addr, 6);
509 return ESP_OK;
510 err:
511 return ret;
512 }
513
emac_dm9051_set_link(esp_eth_mac_t * mac,eth_link_t link)514 static esp_err_t emac_dm9051_set_link(esp_eth_mac_t *mac, eth_link_t link)
515 {
516 esp_err_t ret = ESP_OK;
517 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
518 uint8_t nsr = 0;
519 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_NSR, &nsr), err, TAG, "read NSR failed");
520 switch (link) {
521 case ETH_LINK_UP:
522 ESP_GOTO_ON_FALSE(nsr & NSR_LINKST, ESP_ERR_INVALID_STATE, err, TAG, "phy is not link up");
523 ESP_GOTO_ON_ERROR(mac->start(mac), err, TAG, "dm9051 start failed");
524 break;
525 case ETH_LINK_DOWN:
526 ESP_GOTO_ON_FALSE(!(nsr & NSR_LINKST), ESP_ERR_INVALID_STATE, err, TAG, "phy is not link down");
527 ESP_GOTO_ON_ERROR(mac->stop(mac), err, TAG, "dm9051 stop failed");
528 break;
529 default:
530 ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "unknown link status");
531 break;
532 }
533 return ESP_OK;
534 err:
535 return ret;
536 }
537
emac_dm9051_set_speed(esp_eth_mac_t * mac,eth_speed_t speed)538 static esp_err_t emac_dm9051_set_speed(esp_eth_mac_t *mac, eth_speed_t speed)
539 {
540 esp_err_t ret = ESP_OK;
541 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
542 uint8_t nsr = 0;
543 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_NSR, &nsr), err, TAG, "read NSR failed");
544 switch (speed) {
545 case ETH_SPEED_10M:
546 ESP_GOTO_ON_FALSE(nsr & NSR_SPEED, ESP_ERR_INVALID_STATE, err, TAG, "phy speed is not at 10Mbps");
547 ESP_LOGD(TAG, "working in 10Mbps");
548 break;
549 case ETH_SPEED_100M:
550 ESP_GOTO_ON_FALSE(!(nsr & NSR_SPEED), ESP_ERR_INVALID_STATE, err, TAG, "phy speed is not at 100Mbps");
551 ESP_LOGD(TAG, "working in 100Mbps");
552 break;
553 default:
554 ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "unknown speed");
555 break;
556 }
557 return ESP_OK;
558 err:
559 return ret;
560 }
561
emac_dm9051_set_duplex(esp_eth_mac_t * mac,eth_duplex_t duplex)562 static esp_err_t emac_dm9051_set_duplex(esp_eth_mac_t *mac, eth_duplex_t duplex)
563 {
564 esp_err_t ret = ESP_OK;
565 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
566 uint8_t ncr = 0;
567 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_NCR, &ncr), err, TAG, "read NCR failed");
568 switch (duplex) {
569 case ETH_DUPLEX_HALF:
570 ESP_LOGD(TAG, "working in half duplex");
571 ESP_GOTO_ON_FALSE(!(ncr & NCR_FDX), ESP_ERR_INVALID_STATE, err, TAG, "phy is not at half duplex");
572 break;
573 case ETH_DUPLEX_FULL:
574 ESP_LOGD(TAG, "working in full duplex");
575 ESP_GOTO_ON_FALSE(ncr & NCR_FDX, ESP_ERR_INVALID_STATE, err, TAG, "phy is not at full duplex");
576 break;
577 default:
578 ESP_GOTO_ON_FALSE(false, ESP_ERR_INVALID_ARG, err, TAG, "unknown duplex");
579 break;
580 }
581 return ESP_OK;
582 err:
583 return ret;
584 }
585
emac_dm9051_set_promiscuous(esp_eth_mac_t * mac,bool enable)586 static esp_err_t emac_dm9051_set_promiscuous(esp_eth_mac_t *mac, bool enable)
587 {
588 esp_err_t ret = ESP_OK;
589 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
590 uint8_t rcr = 0;
591 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_EPDRL, &rcr), err, TAG, "read RCR failed");
592 if (enable) {
593 rcr |= RCR_PRMSC;
594 } else {
595 rcr &= ~RCR_PRMSC;
596 }
597 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RCR, rcr), err, TAG, "write RCR failed");
598 return ESP_OK;
599 err:
600 return ret;
601 }
602
emac_dm9051_enable_flow_ctrl(esp_eth_mac_t * mac,bool enable)603 static esp_err_t emac_dm9051_enable_flow_ctrl(esp_eth_mac_t *mac, bool enable)
604 {
605 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
606 emac->flow_ctrl_enabled = enable;
607 return ESP_OK;
608 }
609
emac_dm9051_set_peer_pause_ability(esp_eth_mac_t * mac,uint32_t ability)610 static esp_err_t emac_dm9051_set_peer_pause_ability(esp_eth_mac_t *mac, uint32_t ability)
611 {
612 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
613 // we want to enable flow control, and peer does support pause function
614 // then configure the MAC layer to enable flow control feature
615 if (emac->flow_ctrl_enabled && ability) {
616 dm9051_enable_flow_ctrl(emac, true);
617 } else {
618 dm9051_enable_flow_ctrl(emac, false);
619 ESP_LOGD(TAG, "Flow control not enabled for the link");
620 }
621 return ESP_OK;
622 }
623
emac_dm9051_transmit(esp_eth_mac_t * mac,uint8_t * buf,uint32_t length)624 static esp_err_t emac_dm9051_transmit(esp_eth_mac_t *mac, uint8_t *buf, uint32_t length)
625 {
626 esp_err_t ret = ESP_OK;
627 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
628 /* Check if last transmit complete */
629 uint8_t tcr = 0;
630
631 int64_t wait_time = esp_timer_get_time();
632 do {
633 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_TCR, &tcr), err, TAG, "read TCR failed");
634 } while((tcr & TCR_TXREQ) && ((esp_timer_get_time() - wait_time) < 100));
635
636 if (tcr & TCR_TXREQ) {
637 ESP_LOGE(TAG, "last transmit still in progress, cannot send.");
638 return ESP_ERR_INVALID_STATE;
639 }
640
641 /* set tx length */
642 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TXPLL, length & 0xFF), err, TAG, "write TXPLL failed");
643 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TXPLH, (length >> 8) & 0xFF), err, TAG, "write TXPLH failed");
644 /* copy data to tx memory */
645 ESP_GOTO_ON_ERROR(dm9051_memory_write(emac, buf, length), err, TAG, "write memory failed");
646 /* issue tx polling command */
647 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TCR, TCR_TXREQ), err, TAG, "write TCR failed");
648 return ESP_OK;
649 err:
650 return ret;
651 }
652
emac_dm9051_receive(esp_eth_mac_t * mac,uint8_t * buf,uint32_t * length)653 static esp_err_t emac_dm9051_receive(esp_eth_mac_t *mac, uint8_t *buf, uint32_t *length)
654 {
655 esp_err_t ret = ESP_OK;
656 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
657 uint8_t rxbyte = 0;
658 uint16_t rx_len = 0;
659 __attribute__((aligned(4))) dm9051_rx_header_t header; // SPI driver needs the rx buffer 4 byte align
660 emac->packets_remain = false;
661 /* dummy read, get the most updated data */
662 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_MRCMDX, &rxbyte), err, TAG, "read MRCMDX failed");
663 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_MRCMDX, &rxbyte), err, TAG, "read MRCMDX failed");
664 /* rxbyte must be 0xFF, 0 or 1 */
665 if (rxbyte > 1) {
666 ESP_GOTO_ON_ERROR(mac->stop(mac), err, TAG, "stop dm9051 failed");
667 /* reset rx fifo pointer */
668 ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_MPTRCR, MPTRCR_RST_RX), err, TAG, "write MPTRCR failed");
669 esp_rom_delay_us(10);
670 ESP_GOTO_ON_ERROR(mac->start(mac), err, TAG, "start dm9051 failed");
671 ESP_GOTO_ON_FALSE(false, ESP_FAIL, err, TAG, "reset rx fifo pointer");
672 } else if (rxbyte) {
673 ESP_GOTO_ON_ERROR(dm9051_memory_peek(emac, (uint8_t *)&header, sizeof(header)), err, TAG, "peek rx header failed");
674 rx_len = header.length_low + (header.length_high << 8);
675 /* check if the buffer can hold all the incoming data */
676 if (*length < rx_len - 4) {
677 ESP_LOGE(TAG, "buffer size too small, needs %d", rx_len - 4);
678 /* tell upper layer the size we need */
679 *length = rx_len - 4;
680 ret = ESP_ERR_INVALID_SIZE;
681 goto err;
682 }
683 ESP_GOTO_ON_ERROR(dm9051_memory_read(emac, (uint8_t *)&header, sizeof(header)), err, TAG, "read rx header failed");
684 ESP_GOTO_ON_ERROR(dm9051_memory_read(emac, buf, rx_len), err, TAG, "read rx data failed");
685 ESP_GOTO_ON_FALSE(!(header.status & 0xBF), ESP_FAIL, err, TAG, "receive status error: %xH", header.status);
686 *length = rx_len - 4; // substract the CRC length (4Bytes)
687 /* dummy read, get the most updated data */
688 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_MRCMDX, &rxbyte), err, TAG, "read MRCMDX failed");
689 ESP_GOTO_ON_ERROR(dm9051_register_read(emac, DM9051_MRCMDX, &rxbyte), err, TAG, "read MRCMDX failed");
690 emac->packets_remain = rxbyte > 0;
691 }
692 return ESP_OK;
693 err:
694 return ret;
695 }
696
emac_dm9051_init(esp_eth_mac_t * mac)697 static esp_err_t emac_dm9051_init(esp_eth_mac_t *mac)
698 {
699 esp_err_t ret = ESP_OK;
700 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
701 esp_eth_mediator_t *eth = emac->eth;
702 esp_rom_gpio_pad_select_gpio(emac->int_gpio_num);
703 gpio_set_direction(emac->int_gpio_num, GPIO_MODE_INPUT);
704 gpio_set_pull_mode(emac->int_gpio_num, GPIO_PULLDOWN_ONLY);
705 gpio_set_intr_type(emac->int_gpio_num, GPIO_INTR_POSEDGE);
706 gpio_intr_enable(emac->int_gpio_num);
707 gpio_isr_handler_add(emac->int_gpio_num, dm9051_isr_handler, emac);
708 ESP_GOTO_ON_ERROR(eth->on_state_changed(eth, ETH_STATE_LLINIT, NULL), err, TAG, "lowlevel init failed");
709 /* reset dm9051 */
710 ESP_GOTO_ON_ERROR(dm9051_reset(emac), err, TAG, "reset dm9051 failed");
711 /* verify chip id */
712 ESP_GOTO_ON_ERROR(dm9051_verify_id(emac), err, TAG, "vefiry chip ID failed");
713 /* default setup of internal registers */
714 ESP_GOTO_ON_ERROR(dm9051_setup_default(emac), err, TAG, "dm9051 default setup failed");
715 /* clear multicast hash table */
716 ESP_GOTO_ON_ERROR(dm9051_clear_multicast_table(emac), err, TAG, "clear multicast table failed");
717 /* get emac address from eeprom */
718 ESP_GOTO_ON_ERROR(dm9051_get_mac_addr(emac), err, TAG, "fetch ethernet mac address failed");
719 return ESP_OK;
720 err:
721 gpio_isr_handler_remove(emac->int_gpio_num);
722 gpio_reset_pin(emac->int_gpio_num);
723 eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
724 return ret;
725 }
726
emac_dm9051_deinit(esp_eth_mac_t * mac)727 static esp_err_t emac_dm9051_deinit(esp_eth_mac_t *mac)
728 {
729 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
730 esp_eth_mediator_t *eth = emac->eth;
731 mac->stop(mac);
732 gpio_isr_handler_remove(emac->int_gpio_num);
733 gpio_reset_pin(emac->int_gpio_num);
734 eth->on_state_changed(eth, ETH_STATE_DEINIT, NULL);
735 return ESP_OK;
736 }
737
emac_dm9051_del(esp_eth_mac_t * mac)738 static esp_err_t emac_dm9051_del(esp_eth_mac_t *mac)
739 {
740 emac_dm9051_t *emac = __containerof(mac, emac_dm9051_t, parent);
741 vTaskDelete(emac->rx_task_hdl);
742 vSemaphoreDelete(emac->spi_lock);
743 free(emac);
744 return ESP_OK;
745 }
746
esp_eth_mac_new_dm9051(const eth_dm9051_config_t * dm9051_config,const eth_mac_config_t * mac_config)747 esp_eth_mac_t *esp_eth_mac_new_dm9051(const eth_dm9051_config_t *dm9051_config, const eth_mac_config_t *mac_config)
748 {
749 esp_eth_mac_t *ret = NULL;
750 emac_dm9051_t *emac = NULL;
751 ESP_GOTO_ON_FALSE(dm9051_config, NULL, err, TAG, "can't set dm9051 specific config to null");
752 ESP_GOTO_ON_FALSE(mac_config, NULL, err, TAG, "can't set mac config to null");
753 emac = calloc(1, sizeof(emac_dm9051_t));
754 ESP_GOTO_ON_FALSE(emac, NULL, err, TAG, "calloc emac failed");
755 /* dm9051 receive is driven by interrupt only for now*/
756 ESP_GOTO_ON_FALSE(dm9051_config->int_gpio_num >= 0, NULL, err, TAG, "error interrupt gpio number");
757 /* bind methods and attributes */
758 emac->sw_reset_timeout_ms = mac_config->sw_reset_timeout_ms;
759 emac->int_gpio_num = dm9051_config->int_gpio_num;
760 emac->spi_hdl = dm9051_config->spi_hdl;
761 emac->parent.set_mediator = emac_dm9051_set_mediator;
762 emac->parent.init = emac_dm9051_init;
763 emac->parent.deinit = emac_dm9051_deinit;
764 emac->parent.start = emac_dm9051_start;
765 emac->parent.stop = emac_dm9051_stop;
766 emac->parent.del = emac_dm9051_del;
767 emac->parent.write_phy_reg = emac_dm9051_write_phy_reg;
768 emac->parent.read_phy_reg = emac_dm9051_read_phy_reg;
769 emac->parent.set_addr = emac_dm9051_set_addr;
770 emac->parent.get_addr = emac_dm9051_get_addr;
771 emac->parent.set_speed = emac_dm9051_set_speed;
772 emac->parent.set_duplex = emac_dm9051_set_duplex;
773 emac->parent.set_link = emac_dm9051_set_link;
774 emac->parent.set_promiscuous = emac_dm9051_set_promiscuous;
775 emac->parent.set_peer_pause_ability = emac_dm9051_set_peer_pause_ability;
776 emac->parent.enable_flow_ctrl = emac_dm9051_enable_flow_ctrl;
777 emac->parent.transmit = emac_dm9051_transmit;
778 emac->parent.receive = emac_dm9051_receive;
779 /* create mutex */
780 emac->spi_lock = xSemaphoreCreateMutex();
781 ESP_GOTO_ON_FALSE(emac->spi_lock, NULL, err, TAG, "create lock failed");
782 /* create dm9051 task */
783 BaseType_t core_num = tskNO_AFFINITY;
784 if (mac_config->flags & ETH_MAC_FLAG_PIN_TO_CORE) {
785 core_num = cpu_hal_get_core_id();
786 }
787 BaseType_t xReturned = xTaskCreatePinnedToCore(emac_dm9051_task, "dm9051_tsk", mac_config->rx_task_stack_size, emac,
788 mac_config->rx_task_prio, &emac->rx_task_hdl, core_num);
789 ESP_GOTO_ON_FALSE(xReturned == pdPASS, NULL, err, TAG, "create dm9051 task failed");
790 return &(emac->parent);
791
792 err:
793 if (emac) {
794 if (emac->rx_task_hdl) {
795 vTaskDelete(emac->rx_task_hdl);
796 }
797 if (emac->spi_lock) {
798 vSemaphoreDelete(emac->spi_lock);
799 }
800 free(emac);
801 }
802 return ret;
803 }
804
